[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:13:01 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit f80589101062062e9f8f756abb04f763009f322f
Author: Török Edvin <edwin at clamav.net>
Date: Wed Dec 16 19:14:43 2009 +0200
Run tblgen only in maintainer-mode.
And ship prebuilt .inc files instead.
This should improve build times a bit.
diff --git a/.gitignore b/.gitignore
index 5033216..f799fe9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,7 +21,6 @@ TAGS
libclamav/c++/autom4te.cache/*
libclamav/c++/FileCheck
libclamav/c++/count
-libclamav/c++/*.inc
libclamav/c++/clamavcxx-config.h
libclamav/c++/llc
libclamav/c++/lli
@@ -33,7 +32,6 @@ libclamav/c++/llvm/Release
libclamav/c++/llvm/docs/doxygen.cfg
libclamav/c++/llvm/include/llvm/Config/*.def
libclamav/c++/llvm/include/llvm/Config/config.h
-libclamav/c++/llvm/include/llvm/Intrinsics.gen
libclamav/c++/llvm/include/llvm/System/DataTypes.h
libclamav/c++/llvm/llvm.spec
libclamav/c++/llvm/mklib
diff --git a/libclamav/c++/ARMGenAsmWriter.inc b/libclamav/c++/ARMGenAsmWriter.inc
new file mode 100644
index 0000000..0626d07
--- /dev/null
+++ b/libclamav/c++/ARMGenAsmWriter.inc
@@ -0,0 +1,5261 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Assembly Writer Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
+ static const unsigned OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // DBG_LABEL
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 1U, // ADCSSri
+ 7U, // ADCSSrr
+ 7U, // ADCSSrs
+ 135299085U, // ADCri
+ 135331853U, // ADCrr
+ 270532621U, // ADCrs
+ 137461777U, // ADDSri
+ 137461777U, // ADDSrr
+ 271679505U, // ADDSrs
+ 135299094U, // ADDri
+ 135331862U, // ADDrr
+ 270532630U, // ADDrs
+ 4194330U, // ADJCALLSTACKDOWN
+ 4194350U, // ADJCALLSTACKUP
+ 135299136U, // ANDri
+ 135331904U, // ANDrr
+ 270532672U, // ANDrs
+ 407896132U, // ATOMIC_CMP_SWAP_I16
+ 408944708U, // ATOMIC_CMP_SWAP_I32
+ 409993284U, // ATOMIC_CMP_SWAP_I8
+ 411041860U, // ATOMIC_LOAD_ADD_I16
+ 412090436U, // ATOMIC_LOAD_ADD_I32
+ 413139012U, // ATOMIC_LOAD_ADD_I8
+ 414187588U, // ATOMIC_LOAD_AND_I16
+ 415236164U, // ATOMIC_LOAD_AND_I32
+ 416284740U, // ATOMIC_LOAD_AND_I8
+ 417333316U, // ATOMIC_LOAD_NAND_I16
+ 418381892U, // ATOMIC_LOAD_NAND_I32
+ 419430468U, // ATOMIC_LOAD_NAND_I8
+ 420479044U, // ATOMIC_LOAD_OR_I16
+ 421527620U, // ATOMIC_LOAD_OR_I32
+ 422576196U, // ATOMIC_LOAD_OR_I8
+ 423624772U, // ATOMIC_LOAD_SUB_I16
+ 424673348U, // ATOMIC_LOAD_SUB_I32
+ 425721924U, // ATOMIC_LOAD_SUB_I8
+ 426770500U, // ATOMIC_LOAD_XOR_I16
+ 427819076U, // ATOMIC_LOAD_XOR_I32
+ 428867652U, // ATOMIC_LOAD_XOR_I8
+ 429916228U, // ATOMIC_SWAP_I16
+ 430964804U, // ATOMIC_SWAP_I32
+ 432013380U, // ATOMIC_SWAP_I8
+ 4194373U, // B
+ 137461832U, // BFC
+ 135299148U, // BICri
+ 135331916U, // BICrr
+ 270532684U, // BICrs
+ 536870992U, // BL
+ 4194388U, // BLX
+ 4194388U, // BLXr9
+ 674365529U, // BL_pred
+ 536870992U, // BLr9
+ 674365529U, // BLr9_pred
+ 4194396U, // BRIND
+ 96U, // BR_JTadd
+ 805306473U, // BR_JTm
+ 30408818U, // BR_JTr
+ 4194427U, // BX
+ 970981515U, // BX_RET
+ 4194427U, // BXr9
+ 674332814U, // Bcc
+ 1076986000U, // CLZ
+ 1076986004U, // CMNri
+ 1076986004U, // CMNrr
+ 1211203732U, // CMNrs
+ 1076986004U, // CMNzri
+ 1076986004U, // CMNzrr
+ 1211203732U, // CMNzrs
+ 1076986008U, // CMPri
+ 1076986008U, // CMPrr
+ 1211203736U, // CMPrs
+ 1076986008U, // CMPzri
+ 1076986008U, // CMPzrr
+ 1211203736U, // CMPzrs
+ 1342177348U, // CONSTPOOL_ENTRY
+ 135299228U, // EORri
+ 135331996U, // EORrr
+ 270532764U, // EORrs
+ 1106411680U, // FCONSTD
+ 1107460256U, // FCONSTS
+ 974127269U, // FMSTAT
+ 35651754U, // Int_MemBarrierV6
+ 1476395191U, // Int_MemBarrierV7
+ 36700330U, // Int_SyncBarrierV6
+ 1476395195U, // Int_SyncBarrierV7
+ 37748927U, // Int_eh_sjlj_setjmp
+ 1613955273U, // LDM
+ 1613955273U, // LDM_RET
+ 1211203789U, // LDR
+ 1211203793U, // LDRB
+ 271679697U, // LDRB_POST
+ 271679697U, // LDRB_PRE
+ 271679702U, // LDRD
+ 1076986075U, // LDREX
+ 1076986081U, // LDREXB
+ 137461992U, // LDREXD
+ 1076986095U, // LDREXH
+ 1211203830U, // LDRH
+ 271679734U, // LDRH_POST
+ 271679734U, // LDRH_PRE
+ 1211203835U, // LDRSB
+ 271679739U, // LDRSB_POST
+ 271679739U, // LDRSB_PRE
+ 1211203841U, // LDRSH
+ 271679745U, // LDRSH_POST
+ 271679745U, // LDRSH_PRE
+ 271679693U, // LDR_POST
+ 271679693U, // LDR_PRE
+ 1211203789U, // LDRcp
+ 1783628039U, // LEApcrel
+ 1784676615U, // LEApcrelJT
+ 1248854285U, // MLA
+ 1211203857U, // MLS
+ 137462037U, // MOVCCi
+ 137462037U, // MOVCCr
+ 271679765U, // MOVCCs
+ 137462041U, // MOVTi16
+ 1115914517U, // MOVi
+ 1076986142U, // MOVi16
+ 1076986133U, // MOVi2pieces
+ 1076986142U, // MOVi32imm
+ 1115685141U, // MOVr
+ 1115685141U, // MOVrx
+ 1249116437U, // MOVs
+ 1076986147U, // MOVsra_flag
+ 1076986147U, // MOVsrl_flag
+ 135332136U, // MUL
+ 1115914540U, // MVNi
+ 1115685164U, // MVNr
+ 1249116460U, // MVNs
+ 135299376U, // ORRri
+ 135332144U, // ORRrr
+ 270532912U, // ORRrs
+ 1922040116U, // PICADD
+ 2057306420U, // PICLDR
+ 2058354996U, // PICLDRB
+ 2059403572U, // PICLDRH
+ 2060452148U, // PICLDRSB
+ 2061500724U, // PICLDRSH
+ 2062549300U, // PICSTR
+ 2063597876U, // PICSTRB
+ 2064646452U, // PICSTRH
+ 1211203894U, // PKHBT
+ 1211203900U, // PKHTB
+ 1076986178U, // REV
+ 1076986182U, // REV16
+ 1076986188U, // REVSH
+ 137462098U, // RSBSri
+ 271679826U, // RSBSrs
+ 135299415U, // RSBri
+ 270532951U, // RSBrs
+ 347U, // RSCSri
+ 347U, // RSCSrs
+ 135299425U, // RSCri
+ 270532961U, // RSCrs
+ 357U, // SBCSSri
+ 357U, // SBCSSrr
+ 357U, // SBCSSrs
+ 135299435U, // SBCri
+ 135332203U, // SBCrr
+ 270532971U, // SBCrs
+ 1211203951U, // SBFX
+ 1211203956U, // SMLABB
+ 1211203963U, // SMLABT
+ 1248854402U, // SMLAL
+ 1211203976U, // SMLATB
+ 1211203983U, // SMLATT
+ 1211203990U, // SMLAWB
+ 1211203997U, // SMLAWT
+ 1211204004U, // SMMLA
+ 1211204010U, // SMMLS
+ 137462192U, // SMMUL
+ 137462198U, // SMULBB
+ 137462205U, // SMULBT
+ 1248854468U, // SMULL
+ 137462218U, // SMULTB
+ 137462225U, // SMULTT
+ 137462232U, // SMULWB
+ 137462239U, // SMULWT
+ 1613955558U, // STM
+ 1211204074U, // STR
+ 1211204078U, // STRB
+ 271581678U, // STRB_POST
+ 271581678U, // STRB_PRE
+ 271679987U, // STRD
+ 137462264U, // STREX
+ 137462270U, // STREXB
+ 1211204101U, // STREXD
+ 137462284U, // STREXH
+ 1211204115U, // STRH
+ 271581715U, // STRH_POST
+ 271581715U, // STRH_PRE
+ 271581674U, // STR_POST
+ 271581674U, // STR_PRE
+ 137462296U, // SUBSri
+ 137462296U, // SUBSrr
+ 271680024U, // SUBSrs
+ 135299613U, // SUBri
+ 135332381U, // SUBrr
+ 270533149U, // SUBrs
+ 137462305U, // SXTABrr
+ 1211204129U, // SXTABrr_rot
+ 137462311U, // SXTAHrr
+ 1211204135U, // SXTAHrr_rot
+ 1076986413U, // SXTBr
+ 137462317U, // SXTBr_rot
+ 1076986418U, // SXTHr
+ 137462322U, // SXTHr_rot
+ 1076986423U, // TEQri
+ 1076986423U, // TEQrr
+ 1211204151U, // TEQrs
+ 1476395579U, // TPsoft
+ 1076986446U, // TSTri
+ 1076986446U, // TSTrr
+ 1211204174U, // TSTrs
+ 1211204178U, // UBFX
+ 1211204183U, // UMAAL
+ 1248854621U, // UMLAL
+ 1248854627U, // UMULL
+ 137462377U, // UXTABrr
+ 1211204201U, // UXTABrr_rot
+ 137462383U, // UXTAHrr
+ 1211204207U, // UXTAHrr_rot
+ 1076986485U, // UXTB16r
+ 137462389U, // UXTB16r_rot
+ 1076986492U, // UXTBr
+ 137462396U, // UXTBr_rot
+ 1076986497U, // UXTHr
+ 137462401U, // UXTHr_rot
+ 1260454534U, // VABALsv2i64
+ 1261503110U, // VABALsv4i32
+ 1262551686U, // VABALsv8i16
+ 1263600262U, // VABALuv2i64
+ 1264648838U, // VABALuv4i32
+ 1265697414U, // VABALuv8i16
+ 1262551692U, // VABAsv16i8
+ 1260454540U, // VABAsv2i32
+ 1261503116U, // VABAsv4i16
+ 1260454540U, // VABAsv4i32
+ 1261503116U, // VABAsv8i16
+ 1262551692U, // VABAsv8i8
+ 1265697420U, // VABAuv16i8
+ 1263600268U, // VABAuv2i32
+ 1264648844U, // VABAuv4i16
+ 1263600268U, // VABAuv4i32
+ 1264648844U, // VABAuv8i16
+ 1265697420U, // VABAuv8i8
+ 186647185U, // VABDLsv2i64
+ 187695761U, // VABDLsv4i32
+ 188744337U, // VABDLsv8i16
+ 189792913U, // VABDLuv2i64
+ 190841489U, // VABDLuv4i32
+ 191890065U, // VABDLuv8i16
+ 167936663U, // VABDfd
+ 167936663U, // VABDfq
+ 188744343U, // VABDsv16i8
+ 186647191U, // VABDsv2i32
+ 187695767U, // VABDsv4i16
+ 186647191U, // VABDsv4i32
+ 187695767U, // VABDsv8i16
+ 188744343U, // VABDsv8i8
+ 191890071U, // VABDuv16i8
+ 189792919U, // VABDuv2i32
+ 190841495U, // VABDuv4i16
+ 189792919U, // VABDuv4i32
+ 190841495U, // VABDuv8i16
+ 191890071U, // VABDuv8i8
+ 1106412188U, // VABSD
+ 1107460764U, // VABSS
+ 1107460764U, // VABSfd
+ 1107460764U, // VABSfd_sfp
+ 1107460764U, // VABSfq
+ 1128268444U, // VABSv16i8
+ 1126171292U, // VABSv2i32
+ 1127219868U, // VABSv4i16
+ 1126171292U, // VABSv4i32
+ 1127219868U, // VABSv8i16
+ 1128268444U, // VABSv8i8
+ 167936673U, // VACGEd
+ 167936673U, // VACGEq
+ 167936679U, // VACGTd
+ 167936679U, // VACGTq
+ 166888109U, // VADDD
+ 192938674U, // VADDHNv2i32
+ 193987250U, // VADDHNv4i16
+ 195035826U, // VADDHNv8i8
+ 186647225U, // VADDLsv2i64
+ 187695801U, // VADDLsv4i32
+ 188744377U, // VADDLsv8i16
+ 189792953U, // VADDLuv2i64
+ 190841529U, // VADDLuv4i32
+ 191890105U, // VADDLuv8i16
+ 167936685U, // VADDS
+ 186647231U, // VADDWsv2i64
+ 187695807U, // VADDWsv4i32
+ 188744383U, // VADDWsv8i16
+ 189792959U, // VADDWuv2i64
+ 190841535U, // VADDWuv4i32
+ 191890111U, // VADDWuv8i16
+ 167936685U, // VADDfd
+ 167936685U, // VADDfd_sfp
+ 167936685U, // VADDfq
+ 196084397U, // VADDv16i8
+ 192938669U, // VADDv1i64
+ 193987245U, // VADDv2i32
+ 192938669U, // VADDv2i64
+ 195035821U, // VADDv4i16
+ 193987245U, // VADDv4i32
+ 195035821U, // VADDv8i16
+ 196084397U, // VADDv8i8
+ 137462469U, // VANDd
+ 137462469U, // VANDq
+ 137462474U, // VBICd
+ 137462474U, // VBICq
+ 1211204303U, // VBSLd
+ 1211204303U, // VBSLq
+ 167936724U, // VCEQfd
+ 167936724U, // VCEQfq
+ 196084436U, // VCEQv16i8
+ 193987284U, // VCEQv2i32
+ 195035860U, // VCEQv4i16
+ 193987284U, // VCEQv4i32
+ 195035860U, // VCEQv8i16
+ 196084436U, // VCEQv8i8
+ 167936729U, // VCGEfd
+ 167936729U, // VCGEfq
+ 188744409U, // VCGEsv16i8
+ 186647257U, // VCGEsv2i32
+ 187695833U, // VCGEsv4i16
+ 186647257U, // VCGEsv4i32
+ 187695833U, // VCGEsv8i16
+ 188744409U, // VCGEsv8i8
+ 191890137U, // VCGEuv16i8
+ 189792985U, // VCGEuv2i32
+ 190841561U, // VCGEuv4i16
+ 189792985U, // VCGEuv4i32
+ 190841561U, // VCGEuv8i16
+ 191890137U, // VCGEuv8i8
+ 167936734U, // VCGTfd
+ 167936734U, // VCGTfq
+ 188744414U, // VCGTsv16i8
+ 186647262U, // VCGTsv2i32
+ 187695838U, // VCGTsv4i16
+ 186647262U, // VCGTsv4i32
+ 187695838U, // VCGTsv8i16
+ 188744414U, // VCGTsv8i8
+ 191890142U, // VCGTuv16i8
+ 189792990U, // VCGTuv2i32
+ 190841566U, // VCGTuv4i16
+ 189792990U, // VCGTuv4i32
+ 190841566U, // VCGTuv8i16
+ 191890142U, // VCGTuv8i8
+ 1128268515U, // VCLSv16i8
+ 1126171363U, // VCLSv2i32
+ 1127219939U, // VCLSv4i16
+ 1126171363U, // VCLSv4i32
+ 1127219939U, // VCLSv8i16
+ 1128268515U, // VCLSv8i8
+ 1135608552U, // VCLZv16i8
+ 1133511400U, // VCLZv2i32
+ 1134559976U, // VCLZv4i16
+ 1133511400U, // VCLZv4i32
+ 1134559976U, // VCLZv8i16
+ 1135608552U, // VCLZv8i8
+ 1106412269U, // VCMPED
+ 1107460845U, // VCMPES
+ 703890157U, // VCMPEZD
+ 704938733U, // VCMPEZS
+ 1136755443U, // VCNTd
+ 1136755443U, // VCNTq
+ 1137705720U, // VCVTDS
+ 1138754296U, // VCVTSD
+ 1140130552U, // VCVTf2sd
+ 1140130552U, // VCVTf2sd_sfp
+ 1140130552U, // VCVTf2sq
+ 1141179128U, // VCVTf2ud
+ 1141179128U, // VCVTf2ud_sfp
+ 1141179128U, // VCVTf2uq
+ 200442616U, // VCVTf2xsd
+ 200442616U, // VCVTf2xsq
+ 201491192U, // VCVTf2xud
+ 201491192U, // VCVTf2xuq
+ 1142227704U, // VCVTs2fd
+ 1142227704U, // VCVTs2fd_sfp
+ 1142227704U, // VCVTs2fq
+ 1143276280U, // VCVTu2fd
+ 1143276280U, // VCVTu2fd_sfp
+ 1143276280U, // VCVTu2fq
+ 202539768U, // VCVTxs2fd
+ 202539768U, // VCVTxs2fq
+ 203588344U, // VCVTxu2fd
+ 203588344U, // VCVTxu2fq
+ 166888189U, // VDIVD
+ 167936765U, // VDIVS
+ 1144095490U, // VDUP16d
+ 1144095490U, // VDUP16q
+ 1145144066U, // VDUP32d
+ 1145144066U, // VDUP32q
+ 1136755458U, // VDUP8d
+ 1136755458U, // VDUP8q
+ 204571394U, // VDUPLN16d
+ 204571394U, // VDUPLN16q
+ 205619970U, // VDUPLN32d
+ 205619970U, // VDUPLN32q
+ 197231362U, // VDUPLN8d
+ 197231362U, // VDUPLN8q
+ 205619970U, // VDUPLNfd
+ 205619970U, // VDUPLNfq
+ 1145144066U, // VDUPfd
+ 1145144066U, // VDUPfdf
+ 1145144066U, // VDUPfq
+ 1145144066U, // VDUPfqf
+ 137462535U, // VEORd
+ 137462535U, // VEORq
+ 1278313228U, // VEXTd16
+ 1279361804U, // VEXTd32
+ 1270973196U, // VEXTd8
+ 1279361804U, // VEXTdf
+ 1278313228U, // VEXTq16
+ 1279361804U, // VEXTq32
+ 1270973196U, // VEXTq8
+ 1279361804U, // VEXTqf
+ 205619360U, // VGETLNi32
+ 187695264U, // VGETLNs16
+ 188743840U, // VGETLNs8
+ 190840992U, // VGETLNu16
+ 191889568U, // VGETLNu8
+ 188744465U, // VHADDsv16i8
+ 186647313U, // VHADDsv2i32
+ 187695889U, // VHADDsv4i16
+ 186647313U, // VHADDsv4i32
+ 187695889U, // VHADDsv8i16
+ 188744465U, // VHADDsv8i8
+ 191890193U, // VHADDuv16i8
+ 189793041U, // VHADDuv2i32
+ 190841617U, // VHADDuv4i16
+ 189793041U, // VHADDuv4i32
+ 190841617U, // VHADDuv8i16
+ 191890193U, // VHADDuv8i8
+ 188744471U, // VHSUBsv16i8
+ 186647319U, // VHSUBsv2i32
+ 187695895U, // VHSUBsv4i16
+ 186647319U, // VHSUBsv4i32
+ 187695895U, // VHSUBsv8i16
+ 188744471U, // VHSUBsv8i8
+ 191890199U, // VHSUBuv16i8
+ 189793047U, // VHSUBuv2i32
+ 190841623U, // VHSUBuv4i16
+ 189793047U, // VHSUBuv4i32
+ 190841623U, // VHSUBuv8i16
+ 191890199U, // VHSUBuv8i8
+ 340886301U, // VLD1d16
+ 341934877U, // VLD1d32
+ 342983453U, // VLD1d64
+ 344032029U, // VLD1d8
+ 341934877U, // VLD1df
+ 339051293U, // VLD1q16
+ 340099869U, // VLD1q32
+ 345342749U, // VLD1q64
+ 331711261U, // VLD1q8
+ 340099869U, // VLD1qf
+ 2219934498U, // VLD2LNd16
+ 2220983074U, // VLD2LNd32
+ 2223080226U, // VLD2LNd8
+ 2219934498U, // VLD2LNq16a
+ 2219934498U, // VLD2LNq16b
+ 2220983074U, // VLD2LNq32a
+ 2220983074U, // VLD2LNq32b
+ 2354152226U, // VLD2d16
+ 2355200802U, // VLD2d32
+ 2356249373U, // VLD2d64
+ 2357297954U, // VLD2d8
+ 2488369954U, // VLD2q16
+ 2489418530U, // VLD2q32
+ 2491515682U, // VLD2q8
+ 2622587687U, // VLD3LNd16
+ 2623636263U, // VLD3LNd32
+ 2625733415U, // VLD3LNd8
+ 2622587687U, // VLD3LNq16a
+ 2622587687U, // VLD3LNq16b
+ 2623636263U, // VLD3LNq32a
+ 2623636263U, // VLD3LNq32b
+ 2756805415U, // VLD3d16
+ 2757853991U, // VLD3d32
+ 2758902557U, // VLD3d64
+ 2759951143U, // VLD3d8
+ 2488369959U, // VLD3q16a
+ 2488369959U, // VLD3q16b
+ 2489418535U, // VLD3q32a
+ 2489418535U, // VLD3q32b
+ 2491515687U, // VLD3q8a
+ 2491515687U, // VLD3q8b
+ 2891023148U, // VLD4LNd16
+ 2892071724U, // VLD4LNd32
+ 2894168876U, // VLD4LNd8
+ 2891023148U, // VLD4LNq16a
+ 2891023148U, // VLD4LNq16b
+ 2892071724U, // VLD4LNq32a
+ 2892071724U, // VLD4LNq32b
+ 2488369964U, // VLD4d16
+ 2489418540U, // VLD4d32
+ 2490467101U, // VLD4d64
+ 2491515692U, // VLD4d8
+ 2219934508U, // VLD4q16a
+ 2219934508U, // VLD4q16b
+ 2220983084U, // VLD4q32a
+ 2220983084U, // VLD4q32b
+ 2223080236U, // VLD4q8a
+ 2223080236U, // VLD4q8b
+ 2952790833U, // VLDMD
+ 2952790833U, // VLDMS
+ 210862902U, // VLDRD
+ 137757499U, // VLDRQ
+ 205620022U, // VLDRS
+ 167936834U, // VMAXfd
+ 167936834U, // VMAXfq
+ 188744514U, // VMAXsv16i8
+ 186647362U, // VMAXsv2i32
+ 187695938U, // VMAXsv4i16
+ 186647362U, // VMAXsv4i32
+ 187695938U, // VMAXsv8i16
+ 188744514U, // VMAXsv8i8
+ 191890242U, // VMAXuv16i8
+ 189793090U, // VMAXuv2i32
+ 190841666U, // VMAXuv4i16
+ 189793090U, // VMAXuv4i32
+ 190841666U, // VMAXuv8i16
+ 191890242U, // VMAXuv8i8
+ 167936839U, // VMINfd
+ 167936839U, // VMINfq
+ 188744519U, // VMINsv16i8
+ 186647367U, // VMINsv2i32
+ 187695943U, // VMINsv4i16
+ 186647367U, // VMINsv4i32
+ 187695943U, // VMINsv8i16
+ 188744519U, // VMINsv8i8
+ 191890247U, // VMINuv16i8
+ 189793095U, // VMINuv2i32
+ 190841671U, // VMINuv4i16
+ 189793095U, // VMINuv4i32
+ 190841671U, // VMINuv8i16
+ 191890247U, // VMINuv8i8
+ 1240630092U, // VMLAD
+ 320930641U, // VMLALslsv2i32
+ 321979217U, // VMLALslsv4i16
+ 324076369U, // VMLALsluv2i32
+ 325124945U, // VMLALsluv4i16
+ 1260454737U, // VMLALsv2i64
+ 1261503313U, // VMLALsv4i32
+ 1262551889U, // VMLALsv8i16
+ 1263600465U, // VMLALuv2i64
+ 1264649041U, // VMLALuv4i32
+ 1265697617U, // VMLALuv8i16
+ 1241678668U, // VMLAS
+ 1241678668U, // VMLAfd
+ 1241678668U, // VMLAfq
+ 302154572U, // VMLAslfd
+ 302154572U, // VMLAslfq
+ 328270668U, // VMLAslv2i32
+ 329319244U, // VMLAslv4i16
+ 328270668U, // VMLAslv4i32
+ 329319244U, // VMLAslv8i16
+ 1269891916U, // VMLAv16i8
+ 1267794764U, // VMLAv2i32
+ 1268843340U, // VMLAv4i16
+ 1267794764U, // VMLAv4i32
+ 1268843340U, // VMLAv8i16
+ 1269891916U, // VMLAv8i8
+ 1240630103U, // VMLSD
+ 320930652U, // VMLSLslsv2i32
+ 321979228U, // VMLSLslsv4i16
+ 324076380U, // VMLSLsluv2i32
+ 325124956U, // VMLSLsluv4i16
+ 1260454748U, // VMLSLsv2i64
+ 1261503324U, // VMLSLsv4i32
+ 1262551900U, // VMLSLsv8i16
+ 1263600476U, // VMLSLuv2i64
+ 1264649052U, // VMLSLuv4i32
+ 1265697628U, // VMLSLuv8i16
+ 1241678679U, // VMLSS
+ 1241678679U, // VMLSfd
+ 1241678679U, // VMLSfq
+ 302154583U, // VMLSslfd
+ 302154583U, // VMLSslfq
+ 328270679U, // VMLSslv2i32
+ 329319255U, // VMLSslv4i16
+ 328270679U, // VMLSslv4i32
+ 329319255U, // VMLSslv8i16
+ 1269891927U, // VMLSv16i8
+ 1267794775U, // VMLSv2i32
+ 1268843351U, // VMLSv4i16
+ 1267794775U, // VMLSv4i32
+ 1268843351U, // VMLSv8i16
+ 1269891927U, // VMLSv8i8
+ 1106411680U, // VMOVD
+ 137461920U, // VMOVDRR
+ 166887584U, // VMOVDcc
+ 1076986016U, // VMOVDneon
+ 1126171490U, // VMOVLsv2i64
+ 1127220066U, // VMOVLsv4i32
+ 1128268642U, // VMOVLsv8i16
+ 1129317218U, // VMOVLuv2i64
+ 1130365794U, // VMOVLuv4i32
+ 1131414370U, // VMOVLuv8i16
+ 1132462952U, // VMOVNv2i32
+ 1133511528U, // VMOVNv4i16
+ 1134560104U, // VMOVNv8i8
+ 1076986016U, // VMOVQ
+ 137461920U, // VMOVRRD
+ 1076986016U, // VMOVRS
+ 1107460256U, // VMOVS
+ 1076986016U, // VMOVSR
+ 167936160U, // VMOVScc
+ 1136033952U, // VMOVv16i8
+ 1132920992U, // VMOVv1i64
+ 1134002336U, // VMOVv2i32
+ 1132920992U, // VMOVv2i64
+ 1135083680U, // VMOVv4i16
+ 1134002336U, // VMOVv4i32
+ 1135083680U, // VMOVv8i16
+ 1136033952U, // VMOVv8i8
+ 166888302U, // VMULD
+ 211813235U, // VMULLp
+ 1260389235U, // VMULLslsv2i32
+ 1261437811U, // VMULLslsv4i16
+ 1263534963U, // VMULLsluv2i32
+ 1264583539U, // VMULLsluv4i16
+ 186647411U, // VMULLsv2i64
+ 187695987U, // VMULLsv4i32
+ 188744563U, // VMULLsv8i16
+ 189793139U, // VMULLuv2i64
+ 190841715U, // VMULLuv4i32
+ 191890291U, // VMULLuv8i16
+ 167936878U, // VMULS
+ 167936878U, // VMULfd
+ 167936878U, // VMULfd_sfp
+ 167936878U, // VMULfq
+ 211813230U, // VMULpd
+ 211813230U, // VMULpq
+ 1241678702U, // VMULslfd
+ 1241678702U, // VMULslfq
+ 1267729262U, // VMULslv2i32
+ 1268777838U, // VMULslv4i16
+ 1267729262U, // VMULslv4i32
+ 1268777838U, // VMULslv8i16
+ 196084590U, // VMULv16i8
+ 193987438U, // VMULv2i32
+ 195036014U, // VMULv4i16
+ 193987438U, // VMULv4i32
+ 195036014U, // VMULv8i16
+ 196084590U, // VMULv8i8
+ 1076986745U, // VMVNd
+ 1076986745U, // VMVNq
+ 1106412414U, // VNEGD
+ 166888318U, // VNEGDcc
+ 1107460990U, // VNEGS
+ 167936894U, // VNEGScc
+ 1107460990U, // VNEGf32d
+ 1107460990U, // VNEGf32d_sfp
+ 1107460990U, // VNEGf32q
+ 1127220094U, // VNEGs16d
+ 1127220094U, // VNEGs16q
+ 1126171518U, // VNEGs32d
+ 1126171518U, // VNEGs32q
+ 1128268670U, // VNEGs8d
+ 1128268670U, // VNEGs8q
+ 1240630147U, // VNMLAD
+ 1241678723U, // VNMLAS
+ 1240630153U, // VNMLSD
+ 1241678729U, // VNMLSS
+ 166888335U, // VNMULD
+ 167936911U, // VNMULS
+ 137462677U, // VORNd
+ 137462677U, // VORNq
+ 137462682U, // VORRd
+ 137462682U, // VORRq
+ 188810143U, // VPADALsv16i8
+ 186712991U, // VPADALsv2i32
+ 187761567U, // VPADALsv4i16
+ 186712991U, // VPADALsv4i32
+ 187761567U, // VPADALsv8i16
+ 188810143U, // VPADALsv8i8
+ 191955871U, // VPADALuv16i8
+ 189858719U, // VPADALuv2i32
+ 190907295U, // VPADALuv4i16
+ 189858719U, // VPADALuv4i32
+ 190907295U, // VPADALuv8i16
+ 191955871U, // VPADALuv8i8
+ 1128268710U, // VPADDLsv16i8
+ 1126171558U, // VPADDLsv2i32
+ 1127220134U, // VPADDLsv4i16
+ 1126171558U, // VPADDLsv4i32
+ 1127220134U, // VPADDLsv8i16
+ 1128268710U, // VPADDLsv8i8
+ 1131414438U, // VPADDLuv16i8
+ 1129317286U, // VPADDLuv2i32
+ 1130365862U, // VPADDLuv4i16
+ 1129317286U, // VPADDLuv4i32
+ 1130365862U, // VPADDLuv8i16
+ 1131414438U, // VPADDLuv8i8
+ 167936941U, // VPADDf
+ 195036077U, // VPADDi16
+ 193987501U, // VPADDi32
+ 196084653U, // VPADDi8
+ 167936947U, // VPMAXf
+ 187696051U, // VPMAXs16
+ 186647475U, // VPMAXs32
+ 188744627U, // VPMAXs8
+ 190841779U, // VPMAXu16
+ 189793203U, // VPMAXu32
+ 191890355U, // VPMAXu8
+ 167936953U, // VPMINf
+ 187696057U, // VPMINs16
+ 186647481U, // VPMINs32
+ 188744633U, // VPMINs8
+ 190841785U, // VPMINu16
+ 189793209U, // VPMINu32
+ 191890361U, // VPMINu8
+ 1128268735U, // VQABSv16i8
+ 1126171583U, // VQABSv2i32
+ 1127220159U, // VQABSv4i16
+ 1126171583U, // VQABSv4i32
+ 1127220159U, // VQABSv8i16
+ 1128268735U, // VQABSv8i8
+ 188744645U, // VQADDsv16i8
+ 212861893U, // VQADDsv1i64
+ 186647493U, // VQADDsv2i32
+ 212861893U, // VQADDsv2i64
+ 187696069U, // VQADDsv4i16
+ 186647493U, // VQADDsv4i32
+ 187696069U, // VQADDsv8i16
+ 188744645U, // VQADDsv8i8
+ 191890373U, // VQADDuv16i8
+ 213910469U, // VQADDuv1i64
+ 189793221U, // VQADDuv2i32
+ 213910469U, // VQADDuv2i64
+ 190841797U, // VQADDuv4i16
+ 189793221U, // VQADDuv4i32
+ 190841797U, // VQADDuv8i16
+ 191890373U, // VQADDuv8i8
+ 320930763U, // VQDMLALslv2i32
+ 321979339U, // VQDMLALslv4i16
+ 1260454859U, // VQDMLALv2i64
+ 1261503435U, // VQDMLALv4i32
+ 320930771U, // VQDMLSLslv2i32
+ 321979347U, // VQDMLSLslv4i16
+ 1260454867U, // VQDMLSLv2i64
+ 1261503443U, // VQDMLSLv4i32
+ 1260389339U, // VQDMULHslv2i32
+ 1261437915U, // VQDMULHslv4i16
+ 1260389339U, // VQDMULHslv4i32
+ 1261437915U, // VQDMULHslv8i16
+ 186647515U, // VQDMULHv2i32
+ 187696091U, // VQDMULHv4i16
+ 186647515U, // VQDMULHv4i32
+ 187696091U, // VQDMULHv8i16
+ 1260389347U, // VQDMULLslv2i32
+ 1261437923U, // VQDMULLslv4i16
+ 186647523U, // VQDMULLv2i64
+ 187696099U, // VQDMULLv4i32
+ 1152386027U, // VQMOVNsuv2i32
+ 1126171627U, // VQMOVNsuv4i16
+ 1127220203U, // VQMOVNsuv8i8
+ 1152386035U, // VQMOVNsv2i32
+ 1126171635U, // VQMOVNsv4i16
+ 1127220211U, // VQMOVNsv8i8
+ 1153434611U, // VQMOVNuv2i32
+ 1129317363U, // VQMOVNuv4i16
+ 1130365939U, // VQMOVNuv8i8
+ 1128268794U, // VQNEGv16i8
+ 1126171642U, // VQNEGv2i32
+ 1127220218U, // VQNEGv4i16
+ 1126171642U, // VQNEGv4i32
+ 1127220218U, // VQNEGv8i16
+ 1128268794U, // VQNEGv8i8
+ 1260389376U, // VQRDMULHslv2i32
+ 1261437952U, // VQRDMULHslv4i16
+ 1260389376U, // VQRDMULHslv4i32
+ 1261437952U, // VQRDMULHslv8i16
+ 186647552U, // VQRDMULHv2i32
+ 187696128U, // VQRDMULHv4i16
+ 186647552U, // VQRDMULHv4i32
+ 187696128U, // VQRDMULHv8i16
+ 188744713U, // VQRSHLsv16i8
+ 212861961U, // VQRSHLsv1i64
+ 186647561U, // VQRSHLsv2i32
+ 212861961U, // VQRSHLsv2i64
+ 187696137U, // VQRSHLsv4i16
+ 186647561U, // VQRSHLsv4i32
+ 187696137U, // VQRSHLsv8i16
+ 188744713U, // VQRSHLsv8i8
+ 191890441U, // VQRSHLuv16i8
+ 213910537U, // VQRSHLuv1i64
+ 189793289U, // VQRSHLuv2i32
+ 213910537U, // VQRSHLuv2i64
+ 190841865U, // VQRSHLuv4i16
+ 189793289U, // VQRSHLuv4i32
+ 190841865U, // VQRSHLuv8i16
+ 191890441U, // VQRSHLuv8i8
+ 212861968U, // VQRSHRNsv2i32
+ 186647568U, // VQRSHRNsv4i16
+ 187696144U, // VQRSHRNsv8i8
+ 213910544U, // VQRSHRNuv2i32
+ 189793296U, // VQRSHRNuv4i16
+ 190841872U, // VQRSHRNuv8i8
+ 212861976U, // VQRSHRUNv2i32
+ 186647576U, // VQRSHRUNv4i16
+ 187696152U, // VQRSHRUNv8i8
+ 188744737U, // VQSHLsiv16i8
+ 212861985U, // VQSHLsiv1i64
+ 186647585U, // VQSHLsiv2i32
+ 212861985U, // VQSHLsiv2i64
+ 187696161U, // VQSHLsiv4i16
+ 186647585U, // VQSHLsiv4i32
+ 187696161U, // VQSHLsiv8i16
+ 188744737U, // VQSHLsiv8i8
+ 188744743U, // VQSHLsuv16i8
+ 212861991U, // VQSHLsuv1i64
+ 186647591U, // VQSHLsuv2i32
+ 212861991U, // VQSHLsuv2i64
+ 187696167U, // VQSHLsuv4i16
+ 186647591U, // VQSHLsuv4i32
+ 187696167U, // VQSHLsuv8i16
+ 188744743U, // VQSHLsuv8i8
+ 188744737U, // VQSHLsv16i8
+ 212861985U, // VQSHLsv1i64
+ 186647585U, // VQSHLsv2i32
+ 212861985U, // VQSHLsv2i64
+ 187696161U, // VQSHLsv4i16
+ 186647585U, // VQSHLsv4i32
+ 187696161U, // VQSHLsv8i16
+ 188744737U, // VQSHLsv8i8
+ 191890465U, // VQSHLuiv16i8
+ 213910561U, // VQSHLuiv1i64
+ 189793313U, // VQSHLuiv2i32
+ 213910561U, // VQSHLuiv2i64
+ 190841889U, // VQSHLuiv4i16
+ 189793313U, // VQSHLuiv4i32
+ 190841889U, // VQSHLuiv8i16
+ 191890465U, // VQSHLuiv8i8
+ 191890465U, // VQSHLuv16i8
+ 213910561U, // VQSHLuv1i64
+ 189793313U, // VQSHLuv2i32
+ 213910561U, // VQSHLuv2i64
+ 190841889U, // VQSHLuv4i16
+ 189793313U, // VQSHLuv4i32
+ 190841889U, // VQSHLuv8i16
+ 191890465U, // VQSHLuv8i8
+ 212861998U, // VQSHRNsv2i32
+ 186647598U, // VQSHRNsv4i16
+ 187696174U, // VQSHRNsv8i8
+ 213910574U, // VQSHRNuv2i32
+ 189793326U, // VQSHRNuv4i16
+ 190841902U, // VQSHRNuv8i8
+ 212862005U, // VQSHRUNv2i32
+ 186647605U, // VQSHRUNv4i16
+ 187696181U, // VQSHRUNv8i8
+ 188744765U, // VQSUBsv16i8
+ 212862013U, // VQSUBsv1i64
+ 186647613U, // VQSUBsv2i32
+ 212862013U, // VQSUBsv2i64
+ 187696189U, // VQSUBsv4i16
+ 186647613U, // VQSUBsv4i32
+ 187696189U, // VQSUBsv8i16
+ 188744765U, // VQSUBsv8i8
+ 191890493U, // VQSUBuv16i8
+ 213910589U, // VQSUBuv1i64
+ 189793341U, // VQSUBuv2i32
+ 213910589U, // VQSUBuv2i64
+ 190841917U, // VQSUBuv4i16
+ 189793341U, // VQSUBuv4i32
+ 190841917U, // VQSUBuv8i16
+ 191890493U, // VQSUBuv8i8
+ 192939075U, // VRADDHNv2i32
+ 193987651U, // VRADDHNv4i16
+ 195036227U, // VRADDHNv8i8
+ 1129317451U, // VRECPEd
+ 1107461195U, // VRECPEfd
+ 1107461195U, // VRECPEfq
+ 1129317451U, // VRECPEq
+ 167937106U, // VRECPSfd
+ 167937106U, // VRECPSfq
+ 1136755801U, // VREV16d8
+ 1136755801U, // VREV16q8
+ 1144095840U, // VREV32d16
+ 1136755808U, // VREV32d8
+ 1144095840U, // VREV32q16
+ 1136755808U, // VREV32q8
+ 1144095847U, // VREV64d16
+ 1145144423U, // VREV64d32
+ 1136755815U, // VREV64d8
+ 1145144423U, // VREV64df
+ 1144095847U, // VREV64q16
+ 1145144423U, // VREV64q32
+ 1136755815U, // VREV64q8
+ 1145144423U, // VREV64qf
+ 188744814U, // VRHADDsv16i8
+ 186647662U, // VRHADDsv2i32
+ 187696238U, // VRHADDsv4i16
+ 186647662U, // VRHADDsv4i32
+ 187696238U, // VRHADDsv8i16
+ 188744814U, // VRHADDsv8i8
+ 191890542U, // VRHADDuv16i8
+ 189793390U, // VRHADDuv2i32
+ 190841966U, // VRHADDuv4i16
+ 189793390U, // VRHADDuv4i32
+ 190841966U, // VRHADDuv8i16
+ 191890542U, // VRHADDuv8i8
+ 188744821U, // VRSHLsv16i8
+ 212862069U, // VRSHLsv1i64
+ 186647669U, // VRSHLsv2i32
+ 212862069U, // VRSHLsv2i64
+ 187696245U, // VRSHLsv4i16
+ 186647669U, // VRSHLsv4i32
+ 187696245U, // VRSHLsv8i16
+ 188744821U, // VRSHLsv8i8
+ 191890549U, // VRSHLuv16i8
+ 213910645U, // VRSHLuv1i64
+ 189793397U, // VRSHLuv2i32
+ 213910645U, // VRSHLuv2i64
+ 190841973U, // VRSHLuv4i16
+ 189793397U, // VRSHLuv4i32
+ 190841973U, // VRSHLuv8i16
+ 191890549U, // VRSHLuv8i8
+ 192939131U, // VRSHRNv2i32
+ 193987707U, // VRSHRNv4i16
+ 195036283U, // VRSHRNv8i8
+ 188744834U, // VRSHRsv16i8
+ 212862082U, // VRSHRsv1i64
+ 186647682U, // VRSHRsv2i32
+ 212862082U, // VRSHRsv2i64
+ 187696258U, // VRSHRsv4i16
+ 186647682U, // VRSHRsv4i32
+ 187696258U, // VRSHRsv8i16
+ 188744834U, // VRSHRsv8i8
+ 191890562U, // VRSHRuv16i8
+ 213910658U, // VRSHRuv1i64
+ 189793410U, // VRSHRuv2i32
+ 213910658U, // VRSHRuv2i64
+ 190841986U, // VRSHRuv4i16
+ 189793410U, // VRSHRuv4i32
+ 190841986U, // VRSHRuv8i16
+ 191890562U, // VRSHRuv8i8
+ 1129317512U, // VRSQRTEd
+ 1107461256U, // VRSQRTEfd
+ 1107461256U, // VRSQRTEfq
+ 1129317512U, // VRSQRTEq
+ 167937168U, // VRSQRTSfd
+ 167937168U, // VRSQRTSfq
+ 1262552216U, // VRSRAsv16i8
+ 1286669464U, // VRSRAsv1i64
+ 1260455064U, // VRSRAsv2i32
+ 1286669464U, // VRSRAsv2i64
+ 1261503640U, // VRSRAsv4i16
+ 1260455064U, // VRSRAsv4i32
+ 1261503640U, // VRSRAsv8i16
+ 1262552216U, // VRSRAsv8i8
+ 1265697944U, // VRSRAuv16i8
+ 1287718040U, // VRSRAuv1i64
+ 1263600792U, // VRSRAuv2i32
+ 1287718040U, // VRSRAuv2i64
+ 1264649368U, // VRSRAuv4i16
+ 1263600792U, // VRSRAuv4i32
+ 1264649368U, // VRSRAuv8i16
+ 1265697944U, // VRSRAuv8i8
+ 192939166U, // VRSUBHNv2i32
+ 193987742U, // VRSUBHNv4i16
+ 195036318U, // VRSUBHNv8i8
+ 1278312608U, // VSETLNi16
+ 1279361184U, // VSETLNi32
+ 1270972576U, // VSETLNi8
+ 195036326U, // VSHLLi16
+ 193987750U, // VSHLLi32
+ 196084902U, // VSHLLi8
+ 186647718U, // VSHLLsv2i64
+ 187696294U, // VSHLLsv4i32
+ 188744870U, // VSHLLsv8i16
+ 189793446U, // VSHLLuv2i64
+ 190842022U, // VSHLLuv4i32
+ 191890598U, // VSHLLuv8i16
+ 196084908U, // VSHLiv16i8
+ 192939180U, // VSHLiv1i64
+ 193987756U, // VSHLiv2i32
+ 192939180U, // VSHLiv2i64
+ 195036332U, // VSHLiv4i16
+ 193987756U, // VSHLiv4i32
+ 195036332U, // VSHLiv8i16
+ 196084908U, // VSHLiv8i8
+ 188744876U, // VSHLsv16i8
+ 212862124U, // VSHLsv1i64
+ 186647724U, // VSHLsv2i32
+ 212862124U, // VSHLsv2i64
+ 187696300U, // VSHLsv4i16
+ 186647724U, // VSHLsv4i32
+ 187696300U, // VSHLsv8i16
+ 188744876U, // VSHLsv8i8
+ 191890604U, // VSHLuv16i8
+ 213910700U, // VSHLuv1i64
+ 189793452U, // VSHLuv2i32
+ 213910700U, // VSHLuv2i64
+ 190842028U, // VSHLuv4i16
+ 189793452U, // VSHLuv4i32
+ 190842028U, // VSHLuv8i16
+ 191890604U, // VSHLuv8i8
+ 192939185U, // VSHRNv2i32
+ 193987761U, // VSHRNv4i16
+ 195036337U, // VSHRNv8i8
+ 188744887U, // VSHRsv16i8
+ 212862135U, // VSHRsv1i64
+ 186647735U, // VSHRsv2i32
+ 212862135U, // VSHRsv2i64
+ 187696311U, // VSHRsv4i16
+ 186647735U, // VSHRsv4i32
+ 187696311U, // VSHRsv8i16
+ 188744887U, // VSHRsv8i8
+ 191890615U, // VSHRuv16i8
+ 213910711U, // VSHRuv1i64
+ 189793463U, // VSHRuv2i32
+ 213910711U, // VSHRuv2i64
+ 190842039U, // VSHRuv4i16
+ 189793463U, // VSHRuv4i32
+ 190842039U, // VSHRuv8i16
+ 191890615U, // VSHRuv8i8
+ 1154482936U, // VSITOD
+ 1142227704U, // VSITOS
+ 1270973628U, // VSLIv16i8
+ 1284605116U, // VSLIv1i64
+ 1279362236U, // VSLIv2i32
+ 1284605116U, // VSLIv2i64
+ 1278313660U, // VSLIv4i16
+ 1279362236U, // VSLIv4i32
+ 1278313660U, // VSLIv8i16
+ 1270973628U, // VSLIv8i8
+ 1106412737U, // VSQRTD
+ 1107461313U, // VSQRTS
+ 1262552263U, // VSRAsv16i8
+ 1286669511U, // VSRAsv1i64
+ 1260455111U, // VSRAsv2i32
+ 1286669511U, // VSRAsv2i64
+ 1261503687U, // VSRAsv4i16
+ 1260455111U, // VSRAsv4i32
+ 1261503687U, // VSRAsv8i16
+ 1262552263U, // VSRAsv8i8
+ 1265697991U, // VSRAuv16i8
+ 1287718087U, // VSRAuv1i64
+ 1263600839U, // VSRAuv2i32
+ 1287718087U, // VSRAuv2i64
+ 1264649415U, // VSRAuv4i16
+ 1263600839U, // VSRAuv4i32
+ 1264649415U, // VSRAuv8i16
+ 1265697991U, // VSRAuv8i8
+ 1270973644U, // VSRIv16i8
+ 1284605132U, // VSRIv1i64
+ 1279362252U, // VSRIv2i32
+ 1284605132U, // VSRIv2i64
+ 1278313676U, // VSRIv4i16
+ 1279362252U, // VSRIv4i32
+ 1278313676U, // VSRIv8i16
+ 1270973644U, // VSRIv8i8
+ 341345489U, // VST1d16
+ 342394065U, // VST1d32
+ 343442641U, // VST1d64
+ 344491217U, // VST1d8
+ 342394065U, // VST1df
+ 339281105U, // VST1q16
+ 340329681U, // VST1q32
+ 345572561U, // VST1q64
+ 331941073U, // VST1q8
+ 340329681U, // VST1qf
+ 2757264598U, // VST2LNd16
+ 2758313174U, // VST2LNd32
+ 2760410326U, // VST2LNd8
+ 2757264598U, // VST2LNq16a
+ 2757264598U, // VST2LNq16b
+ 2758313174U, // VST2LNq32a
+ 2758313174U, // VST2LNq32b
+ 2354611414U, // VST2d16
+ 2355659990U, // VST2d32
+ 2356708561U, // VST2d64
+ 2357757142U, // VST2d8
+ 2488829142U, // VST2q16
+ 2489877718U, // VST2q32
+ 2491974870U, // VST2q8
+ 2488829147U, // VST3LNd16
+ 2489877723U, // VST3LNd32
+ 2491974875U, // VST3LNd8
+ 2488829147U, // VST3LNq16a
+ 2488829147U, // VST3LNq16b
+ 2489877723U, // VST3LNq32a
+ 2489877723U, // VST3LNq32b
+ 2757264603U, // VST3d16
+ 2758313179U, // VST3d32
+ 2759361745U, // VST3d64
+ 2760410331U, // VST3d8
+ 2488894683U, // VST3q16a
+ 2488894683U, // VST3q16b
+ 2489943259U, // VST3q32a
+ 2489943259U, // VST3q32b
+ 2492040411U, // VST3q8a
+ 2492040411U, // VST3q8b
+ 2220393696U, // VST4LNd16
+ 2221442272U, // VST4LNd32
+ 2223539424U, // VST4LNd8
+ 2220393696U, // VST4LNq16a
+ 2220393696U, // VST4LNq16b
+ 2221442272U, // VST4LNq32a
+ 2221442272U, // VST4LNq32b
+ 2488829152U, // VST4d16
+ 2489877728U, // VST4d32
+ 2490926289U, // VST4d64
+ 2491974880U, // VST4d8
+ 2220459232U, // VST4q16a
+ 2220459232U, // VST4q16b
+ 2221507808U, // VST4q32a
+ 2221507808U, // VST4q32b
+ 2223604960U, // VST4q8a
+ 2223604960U, // VST4q8b
+ 2952791269U, // VSTMD
+ 2952791269U, // VSTMS
+ 210863338U, // VSTRD
+ 137757935U, // VSTRQ
+ 205620458U, // VSTRS
+ 166888694U, // VSUBD
+ 192939259U, // VSUBHNv2i32
+ 193987835U, // VSUBHNv4i16
+ 195036411U, // VSUBHNv8i8
+ 186647810U, // VSUBLsv2i64
+ 187696386U, // VSUBLsv4i32
+ 188744962U, // VSUBLsv8i16
+ 189793538U, // VSUBLuv2i64
+ 190842114U, // VSUBLuv4i32
+ 191890690U, // VSUBLuv8i16
+ 167937270U, // VSUBS
+ 186647816U, // VSUBWsv2i64
+ 187696392U, // VSUBWsv4i32
+ 188744968U, // VSUBWsv8i16
+ 189793544U, // VSUBWuv2i64
+ 190842120U, // VSUBWuv4i32
+ 191890696U, // VSUBWuv8i16
+ 167937270U, // VSUBfd
+ 167937270U, // VSUBfd_sfp
+ 167937270U, // VSUBfq
+ 196084982U, // VSUBv16i8
+ 192939254U, // VSUBv1i64
+ 193987830U, // VSUBv2i32
+ 192939254U, // VSUBv2i64
+ 195036406U, // VSUBv4i16
+ 193987830U, // VSUBv4i32
+ 195036406U, // VSUBv8i16
+ 196084982U, // VSUBv8i8
+ 197231886U, // VTBL1
+ 1270973710U, // VTBL2
+ 331449614U, // VTBL3
+ 2344715534U, // VTBL4
+ 1270973715U, // VTBX1
+ 331449619U, // VTBX2
+ 2344715539U, // VTBX3
+ 2747368723U, // VTBX4
+ 1155531512U, // VTOSIZD
+ 1140130552U, // VTOSIZS
+ 1156580088U, // VTOUIZD
+ 1141179128U, // VTOUIZS
+ 1278313752U, // VTRNd16
+ 1279362328U, // VTRNd32
+ 1270973720U, // VTRNd8
+ 1278313752U, // VTRNq16
+ 1279362328U, // VTRNq32
+ 1270973720U, // VTRNq8
+ 196085021U, // VTSTv16i8
+ 193987869U, // VTSTv2i32
+ 195036445U, // VTSTv4i16
+ 193987869U, // VTSTv4i32
+ 195036445U, // VTSTv8i16
+ 196085021U, // VTSTv8i8
+ 1157628664U, // VUITOD
+ 1143276280U, // VUITOS
+ 1278313762U, // VUZPd16
+ 1279362338U, // VUZPd32
+ 1270973730U, // VUZPd8
+ 1278313762U, // VUZPq16
+ 1279362338U, // VUZPq32
+ 1270973730U, // VUZPq8
+ 1278313767U, // VZIPd16
+ 1279362343U, // VZIPd32
+ 1270973735U, // VZIPd8
+ 1278313767U, // VZIPq16
+ 1279362343U, // VZIPq32
+ 1270973735U, // VZIPq8
+ 7U, // t2ADCSri
+ 1324U, // t2ADCSrr
+ 1324U, // t2ADCSrs
+ 3090251789U, // t2ADCri
+ 3172106253U, // t2ADCrr
+ 3306323981U, // t2ADCrs
+ 219316241U, // t2ADDSri
+ 219316241U, // t2ADDSrr
+ 1293058065U, // t2ADDSrs
+ 3172106262U, // t2ADDrSPi
+ 137463092U, // t2ADDrSPi12
+ 3306323990U, // t2ADDrSPs
+ 3172106262U, // t2ADDri
+ 3090253108U, // t2ADDri12
+ 3172106262U, // t2ADDrr
+ 3306323990U, // t2ADDrs
+ 3090251840U, // t2ANDri
+ 3172106304U, // t2ANDrr
+ 3306324032U, // t2ANDrs
+ 3172107577U, // t2ASRri
+ 3172107577U, // t2ASRrr
+ 4195645U, // t2B
+ 137461832U, // t2BFC
+ 3090251852U, // t2BICri
+ 3172106316U, // t2BICrr
+ 3306324044U, // t2BICrs
+ 85983346U, // t2BR_JT
+ 756351118U, // t2Bcc
+ 1076986000U, // t2CLZ
+ 1158840468U, // t2CMNri
+ 1158840468U, // t2CMNrr
+ 219316372U, // t2CMNrs
+ 1158840468U, // t2CMNzri
+ 1158840468U, // t2CMNzrr
+ 219316372U, // t2CMNzrs
+ 1158840472U, // t2CMPri
+ 1158840472U, // t2CMPrr
+ 219316376U, // t2CMPrs
+ 1158840472U, // t2CMPzri
+ 1158840472U, // t2CMPzrr
+ 219316376U, // t2CMPzrs
+ 3090251932U, // t2EORri
+ 3172106396U, // t2EORrr
+ 3306324124U, // t2EORrs
+ 3355444546U, // t2IT
+ 1476395191U, // t2Int_MemBarrierV7
+ 1476395195U, // t2Int_SyncBarrierV7
+ 87033157U, // t2Int_eh_sjlj_setjmp
+ 1698693321U, // t2LDM
+ 1698693321U, // t2LDM_RET
+ 1211203793U, // t2LDRB_POST
+ 1211203793U, // t2LDRB_PRE
+ 219316433U, // t2LDRBi12
+ 137461969U, // t2LDRBi8
+ 1158840529U, // t2LDRBpci
+ 1293058257U, // t2LDRBs
+ 1211203798U, // t2LDRDi8
+ 137461974U, // t2LDRDpci
+ 1076986075U, // t2LDREX
+ 1076986081U, // t2LDREXB
+ 137461992U, // t2LDREXD
+ 1076986095U, // t2LDREXH
+ 1211203830U, // t2LDRH_POST
+ 1211203830U, // t2LDRH_PRE
+ 219316470U, // t2LDRHi12
+ 137462006U, // t2LDRHi8
+ 1158840566U, // t2LDRHpci
+ 1293058294U, // t2LDRHs
+ 1211203835U, // t2LDRSB_POST
+ 1211203835U, // t2LDRSB_PRE
+ 219316475U, // t2LDRSBi12
+ 137462011U, // t2LDRSBi8
+ 1158840571U, // t2LDRSBpci
+ 1293058299U, // t2LDRSBs
+ 1211203841U, // t2LDRSH_POST
+ 1211203841U, // t2LDRSH_PRE
+ 219316481U, // t2LDRSHi12
+ 137462017U, // t2LDRSHi8
+ 1158840577U, // t2LDRSHpci
+ 1293058305U, // t2LDRSHs
+ 1211203789U, // t2LDR_POST
+ 1211203789U, // t2LDR_PRE
+ 219316429U, // t2LDRi12
+ 137461965U, // t2LDRi8
+ 1158840525U, // t2LDRpci
+ 1361U, // t2LDRpci_pic
+ 1293058253U, // t2LDRs
+ 1159333210U, // t2LEApcrel
+ 219809114U, // t2LEApcrelJT
+ 3172107614U, // t2LSLri
+ 3172107614U, // t2LSLrr
+ 3172107618U, // t2LSRri
+ 3172107618U, // t2LSRrr
+ 1211203853U, // t2MLA
+ 1211203857U, // t2MLS
+ 1293059385U, // t2MOVCCasr
+ 219316501U, // t2MOVCCi
+ 1293059422U, // t2MOVCClsl
+ 1293059426U, // t2MOVCClsr
+ 219316501U, // t2MOVCCr
+ 1293059430U, // t2MOVCCror
+ 137462041U, // t2MOVTi16
+ 3579478293U, // t2MOVi
+ 1076986142U, // t2MOVi16
+ 1076986142U, // t2MOVi32imm
+ 3579478293U, // t2MOVr
+ 3579512170U, // t2MOVrx
+ 1390U, // t2MOVsra_flag
+ 1398U, // t2MOVsrl_flag
+ 137462056U, // t2MUL
+ 3579511084U, // t2MVNi
+ 1158840620U, // t2MVNr
+ 219316524U, // t2MVNs
+ 3090253182U, // t2ORNri
+ 3090253182U, // t2ORNrr
+ 3224470910U, // t2ORNrs
+ 3090252080U, // t2ORRri
+ 3172106544U, // t2ORRrr
+ 3306324272U, // t2ORRrs
+ 1211203894U, // t2PKHBT
+ 1211203900U, // t2PKHTB
+ 1158840642U, // t2REV
+ 1158840646U, // t2REV16
+ 1158840652U, // t2REVSH
+ 3172107622U, // t2RORri
+ 3172107622U, // t2RORrr
+ 3623878999U, // t2RSBSri
+ 3492905303U, // t2RSBSrs
+ 219316567U, // t2RSBri
+ 1211203927U, // t2RSBrs
+ 357U, // t2SBCSri
+ 1410U, // t2SBCSrr
+ 1410U, // t2SBCSrs
+ 3090252139U, // t2SBCri
+ 3172106603U, // t2SBCrr
+ 3306324331U, // t2SBCrs
+ 1211203951U, // t2SBFX
+ 1211203956U, // t2SMLABB
+ 1211203963U, // t2SMLABT
+ 1211203970U, // t2SMLAL
+ 1211203976U, // t2SMLATB
+ 1211203983U, // t2SMLATT
+ 1211203990U, // t2SMLAWB
+ 1211203997U, // t2SMLAWT
+ 1211204004U, // t2SMMLA
+ 1211204010U, // t2SMMLS
+ 137462192U, // t2SMMUL
+ 137462198U, // t2SMULBB
+ 137462205U, // t2SMULBT
+ 1211204036U, // t2SMULL
+ 137462218U, // t2SMULTB
+ 137462225U, // t2SMULTT
+ 137462232U, // t2SMULWB
+ 137462239U, // t2SMULWT
+ 1698693606U, // t2STM
+ 1211105774U, // t2STRB_POST
+ 1211105774U, // t2STRB_PRE
+ 219316718U, // t2STRBi12
+ 137462254U, // t2STRBi8
+ 1293058542U, // t2STRBs
+ 1211204083U, // t2STRDi8
+ 137462264U, // t2STREX
+ 137462270U, // t2STREXB
+ 1211204101U, // t2STREXD
+ 137462284U, // t2STREXH
+ 1211105811U, // t2STRH_POST
+ 1211105811U, // t2STRH_PRE
+ 219316755U, // t2STRHi12
+ 137462291U, // t2STRHi8
+ 1293058579U, // t2STRHs
+ 1211105770U, // t2STR_POST
+ 1211105770U, // t2STR_PRE
+ 219316714U, // t2STRi12
+ 137462250U, // t2STRi8
+ 1293058538U, // t2STRs
+ 219316760U, // t2SUBSri
+ 219316760U, // t2SUBSrr
+ 1293058584U, // t2SUBSrs
+ 3172106781U, // t2SUBrSPi
+ 137463178U, // t2SUBrSPi12
+ 1423U, // t2SUBrSPi12_
+ 1431U, // t2SUBrSPi_
+ 3224470045U, // t2SUBrSPs
+ 1440U, // t2SUBrSPs_
+ 3172106781U, // t2SUBri
+ 3090253194U, // t2SUBri12
+ 3172106781U, // t2SUBrr
+ 3306324509U, // t2SUBrs
+ 137462305U, // t2SXTABrr
+ 1211204129U, // t2SXTABrr_rot
+ 137462311U, // t2SXTAHrr
+ 1211204135U, // t2SXTAHrr_rot
+ 1158840877U, // t2SXTBr
+ 219316781U, // t2SXTBr_rot
+ 1158840882U, // t2SXTHr
+ 219316786U, // t2SXTHr_rot
+ 3758097831U, // t2TBB
+ 3758097836U, // t2TBH
+ 1158840887U, // t2TEQri
+ 1158840887U, // t2TEQrr
+ 219316791U, // t2TEQrs
+ 1476395579U, // t2TPsoft
+ 1158840910U, // t2TSTri
+ 1158840910U, // t2TSTrr
+ 219316814U, // t2TSTrs
+ 1211204178U, // t2UBFX
+ 1211204183U, // t2UMAAL
+ 1211204189U, // t2UMLAL
+ 1211204195U, // t2UMULL
+ 137462377U, // t2UXTABrr
+ 1211204201U, // t2UXTABrr_rot
+ 137462383U, // t2UXTAHrr
+ 1211204207U, // t2UXTAHrr_rot
+ 1158840949U, // t2UXTB16r
+ 219316853U, // t2UXTB16r_rot
+ 1158840956U, // t2UXTBr
+ 219316860U, // t2UXTBr_rot
+ 1158840961U, // t2UXTHr
+ 219316865U, // t2UXTHr_rot
+ 3983245325U, // tADC
+ 137461782U, // tADDhirr
+ 3982557206U, // tADDi3
+ 3983245334U, // tADDi8
+ 91227569U, // tADDrPCi
+ 66993U, // tADDrSP
+ 1457U, // tADDrSPi
+ 3982557206U, // tADDrr
+ 787889U, // tADDspi
+ 66993U, // tADDspr
+ 66998U, // tADDspr_
+ 4195773U, // tADJCALLSTACKDOWN
+ 4195794U, // tADJCALLSTACKUP
+ 3983245376U, // tAND
+ 67045U, // tANDsp
+ 3982558521U, // tASRri
+ 3983246649U, // tASRrr
+ 4194373U, // tB
+ 3983245388U, // tBIC
+ 536870992U, // tBL
+ 536870996U, // tBLXi
+ 536870996U, // tBLXi_r9
+ 4194388U, // tBLXr
+ 4194388U, // tBLXr_r9
+ 536870992U, // tBLr9
+ 4194418U, // tBRIND
+ 92274802U, // tBR_JTr
+ 4194427U, // tBX
+ 1476396524U, // tBX_RET
+ 4194396U, // tBX_RET_vararg
+ 4194427U, // tBXr9
+ 674332814U, // tBcc
+ 93323344U, // tBfar
+ 1522U, // tCBNZ
+ 1528U, // tCBZ
+ 1076986004U, // tCMN
+ 1076986004U, // tCMNZ
+ 1076986008U, // tCMPhir
+ 1076986008U, // tCMPi8
+ 1076986008U, // tCMPr
+ 1076986008U, // tCMPzhir
+ 1076986008U, // tCMPzi8
+ 1076986008U, // tCMPzr
+ 3983245468U, // tEOR
+ 94373373U, // tInt_eh_sjlj_setjmp
+ 1613955273U, // tLDM
+ 1211203789U, // tLDR
+ 1211203793U, // tLDRB
+ 1211203830U, // tLDRH
+ 137462011U, // tLDRSB
+ 137462017U, // tLDRSH
+ 1076986061U, // tLDRcp
+ 1169162445U, // tLDRpci
+ 1586U, // tLDRpci_pic
+ 137461965U, // tLDRspi
+ 1076987226U, // tLEApcrel
+ 137463130U, // tLEApcrelJT
+ 3982558558U, // tLSLri
+ 3983246686U, // tLSLrr
+ 3982558562U, // tLSRri
+ 3983246690U, // tLSRrr
+ 137462037U, // tMOVCCi
+ 137462037U, // tMOVCCr
+ 138413627U, // tMOVCCr_pseudo
+ 1606U, // tMOVSr
+ 1612U, // tMOVgpr2gpr
+ 1612U, // tMOVgpr2tgpr
+ 3989111061U, // tMOVi8
+ 1612U, // tMOVr
+ 1612U, // tMOVtgpr2gpr
+ 3983245608U, // tMUL
+ 3989111084U, // tMVN
+ 3983245616U, // tORR
+ 1976566068U, // tPICADD
+ 943490641U, // tPOP
+ 943490641U, // tPOP_RET
+ 943490645U, // tPUSH
+ 1076986178U, // tREV
+ 1076986182U, // tREV16
+ 1076986188U, // tREVSH
+ 3983246694U, // tROR
+ 3989078359U, // tRSB
+ 137461965U, // tRestore
+ 3983245675U, // tSBC
+ 1613955558U, // tSTM
+ 1211204074U, // tSTR
+ 1211204078U, // tSTRB
+ 1211204115U, // tSTRH
+ 137462250U, // tSTRspi
+ 3982557725U, // tSUBi3
+ 3983245853U, // tSUBi8
+ 3982557725U, // tSUBrr
+ 788058U, // tSUBspi
+ 787872U, // tSUBspi_
+ 1076986413U, // tSXTB
+ 1076986418U, // tSXTH
+ 137462250U, // tSpill
+ 1476395579U, // tTPsoft
+ 1076986446U, // tTST
+ 1076986492U, // tUXTB
+ 1076986497U, // tUXTH
+ 0U
+ };
+
+ const char *AsmStrs =
+ "adcs\t\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ ADJC"
+ "ALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bl\t\000blx\t\000bl\000b"
+ "x\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000bx"
+ "\000b\000clz\000cmn\000cmp\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000d"
+ "mb\000dsb\000str\tsp, [\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldrex"
+ "b\000ldrexd\000ldrexh\000ldrh\000ldrsb\000ldrsh\000.set \000mla\000mls\000"
+ "mov\000movt\000movw\000movs\000mul\000mvn\000orr\000\n\000pkhbt\000pkht"
+ "b\000rev\000rev16\000revsh\000rsbs\000rsb\000rscs\t\000rsc\000sbcs\t\000"
+ "sbc\000sbfx\000smlabb\000smlabt\000smlal\000smlatb\000smlatt\000smlawb\000"
+ "smlawt\000smmla\000smmls\000smmul\000smulbb\000smulbt\000smull\000smult"
+ "b\000smultt\000smulwb\000smulwt\000stm\000str\000strb\000strd\000strex\000"
+ "strexb\000strexd\000strexh\000strh\000subs\000sub\000sxtab\000sxtah\000"
+ "sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000tst\000ubfx\000umaal\000u"
+ "mlal\000umull\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000vabal\000v"
+ "aba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vaddhn\000vad"
+ "dl\000vaddw\000vand\000vbic\000vbsl\000vceq\000vcge\000vcgt\000vcls\000"
+ "vclz\000vcmpe\000vcnt\000vcvt\000vdiv\000vdup\000veor\000vext\000vhadd\000"
+ "vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmia\000vmax"
+ "\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000vmul\000"
+ "vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000vpa"
+ "dal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmlal\000"
+ "vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqrdmulh"
+ "\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000vqshr"
+ "un\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000vrev6"
+ "4\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000vrsra\000"
+ "vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000vsra\000v"
+ "sri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000vsub\000"
+ "vsubhn\000vsubl\000vsubw\000vtbl\000vtbx\000vtrn\000vtst\000vuzp\000vzi"
+ "p\000adcs.w\t\000addw\000asr\000b.w\t\000it\000str.w\tsp, [\000@ ldr.w\t"
+ "\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000s"
+ "bcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000tbb\t\000tbh\t\000"
+ "add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and"
+ "\t\000bx\tlr\000cbnz\t\000cbz\t\000mov\tr12, r1\t@ begin eh.setjmp\n\tm"
+ "ov\tr1, sp\n\tstr\tr1, [\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000mov\t\000"
+ "pop\000push\000sub\t\000";
+
+
+#ifndef NO_ASM_WRITER_BOILERPLATE
+ if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+ printInlineAsm(MI);
+ return;
+ } else if (MI->isLabel()) {
+ printLabel(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ printImplicitDef(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
+ printKill(MI);
+ return;
+ }
+
+
+#endif
+ O << "\t";
+
+ // Emit the opcode for the instruction.
+ unsigned Bits = OpInfo[MI->getOpcode()];
+ assert(Bits != 0 && "Cannot print this instruction.");
+ O << AsmStrs+(Bits & 2047)-1;
+
+
+ // Fragment 0 encoded into 5 bits for 30 unique commands.
+ switch ((Bits >> 27) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
+ printOperand(MI, 0);
+ break;
+ case 1:
+ // ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BICri, ...
+ printPredicateOperand(MI, 3);
+ break;
+ case 2:
+ // ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRB_POST, LDRB_PRE, LDRD, ...
+ printPredicateOperand(MI, 5);
+ break;
+ case 3:
+ // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
+ PrintSpecial(MI, "comment");
+ break;
+ case 4:
+ // BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
+ printOperand(MI, 0, "call");
+ return;
+ break;
+ case 5:
+ // BL_pred, BLr9_pred, Bcc, VCMPEZD, VCMPEZS, t2Bcc, tBcc
+ printPredicateOperand(MI, 1);
+ break;
+ case 6:
+ // BR_JTm
+ printAddrMode2Operand(MI, 0);
+ O << " \n";
+ printJTBlockOperand(MI, 3);
+ return;
+ break;
+ case 7:
+ // BX_RET, FMSTAT, tPOP, tPOP_RET, tPUSH
+ printPredicateOperand(MI, 0);
+ break;
+ case 8:
+ // CLZ, CMNri, CMNrr, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONS...
+ printPredicateOperand(MI, 2);
+ break;
+ case 9:
+ // CMNrs, CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, ML...
+ printPredicateOperand(MI, 4);
+ break;
+ case 10:
+ // CONSTPOOL_ENTRY
+ printCPInstOperand(MI, 0, "label");
+ O << ' ';
+ printCPInstOperand(MI, 1, "cpentry");
+ return;
+ break;
+ case 11:
+ // Int_MemBarrierV7, Int_SyncBarrierV7, TPsoft, t2Int_MemBarrierV7, t2Int...
+ return;
+ break;
+ case 12:
+ // LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2STM, tLDM, tSTM
+ printAddrMode4Operand(MI, 0, "submode");
+ printPredicateOperand(MI, 2);
+ break;
+ case 13:
+ // LEApcrel, LEApcrelJT
+ PrintSpecial(MI, "private");
+ O << "PCRELV";
+ PrintSpecial(MI, "uid");
+ O << ", (";
+ printOperand(MI, 1);
+ break;
+ case 14:
+ // PICADD, tPICADD
+ printPCLabel(MI, 2);
+ break;
+ case 15:
+ // PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
+ printAddrModePCOperand(MI, 1, "label");
+ break;
+ case 16:
+ // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
+ printPredicateOperand(MI, 9);
+ break;
+ case 17:
+ // VLD2d16, VLD2d32, VLD2d64, VLD2d8, VST2d16, VST2d32, VST2d64, VST2d8, ...
+ printPredicateOperand(MI, 6);
+ break;
+ case 18:
+ // VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q16b, VLD3q32a, VLD3q32b, VLD3...
+ printPredicateOperand(MI, 8);
+ break;
+ case 19:
+ // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
+ printPredicateOperand(MI, 11);
+ break;
+ case 20:
+ // VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST2LNd16, VST2LNd32, VST2LNd8, VST...
+ printPredicateOperand(MI, 7);
+ break;
+ case 21:
+ // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
+ printPredicateOperand(MI, 13);
+ break;
+ case 22:
+ // VLDMD, VLDMS, VSTMD, VSTMS
+ printAddrMode5Operand(MI, 0, "submode");
+ printPredicateOperand(MI, 2);
+ O << "\t";
+ printAddrMode5Operand(MI, 0, "base");
+ O << ", ";
+ printRegisterList(MI, 4);
+ return;
+ break;
+ case 23:
+ // t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t2ADDrr, t2ANDri, t2A...
+ printSBitModifierOperand(MI, 5);
+ printPredicateOperand(MI, 3);
+ break;
+ case 24:
+ // t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORR...
+ printSBitModifierOperand(MI, 6);
+ printPredicateOperand(MI, 4);
+ break;
+ case 25:
+ // t2IT
+ printThumbITMask(MI, 1);
+ O << "\t";
+ printPredicateOperand(MI, 0);
+ return;
+ break;
+ case 26:
+ // t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
+ printSBitModifierOperand(MI, 4);
+ break;
+ case 27:
+ // t2RSBSri
+ printSBitModifierOperand(MI, 3);
+ O << ".w\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case 28:
+ // t2TBB, t2TBH
+ printTBAddrMode(MI, 0);
+ O << "\n";
+ printJT2BlockOperand(MI, 1);
+ return;
+ break;
+ case 29:
+ // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
+ printSBitModifierOperand(MI, 1);
+ break;
+ }
+
+
+ // Fragment 1 encoded into 7 bits for 94 unique commands.
+ switch ((Bits >> 20) & 127) {
+ default: // unreachable.
+ case 0:
+ // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, RSCSri, RSCSrs, SBCSSri, SBCSSrr,...
+ O << ", ";
+ break;
+ case 1:
+ // ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, BICri, BICrr, EORri, EORrr, ...
+ printSBitModifierOperand(MI, 5);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ break;
+ case 2:
+ // ADCrs, ADDrs, ANDrs, BICrs, EORrs, ORRrs, RSBrs, RSCrs, SBCrs, SUBrs
+ printSBitModifierOperand(MI, 7);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printSORegOperand(MI, 2);
+ return;
+ break;
+ case 3:
+ // ADDSri, ADDSrr, ADDSrs, BFC, BL_pred, BLr9_pred, Bcc, CLZ, CMNri, CMNr...
+ O << "\t";
+ break;
+ case 4:
+ // ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, t2B,...
+ return;
+ break;
+ case 5:
+ // ATOMIC_CMP_SWAP_I16
+ O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
+ return;
+ break;
+ case 6:
+ // ATOMIC_CMP_SWAP_I32
+ O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
+ return;
+ break;
+ case 7:
+ // ATOMIC_CMP_SWAP_I8
+ O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
+ return;
+ break;
+ case 8:
+ // ATOMIC_LOAD_ADD_I16
+ O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
+ return;
+ break;
+ case 9:
+ // ATOMIC_LOAD_ADD_I32
+ O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
+ return;
+ break;
+ case 10:
+ // ATOMIC_LOAD_ADD_I8
+ O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
+ return;
+ break;
+ case 11:
+ // ATOMIC_LOAD_AND_I16
+ O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
+ return;
+ break;
+ case 12:
+ // ATOMIC_LOAD_AND_I32
+ O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
+ return;
+ break;
+ case 13:
+ // ATOMIC_LOAD_AND_I8
+ O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
+ return;
+ break;
+ case 14:
+ // ATOMIC_LOAD_NAND_I16
+ O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
+ return;
+ break;
+ case 15:
+ // ATOMIC_LOAD_NAND_I32
+ O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
+ return;
+ break;
+ case 16:
+ // ATOMIC_LOAD_NAND_I8
+ O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
+ return;
+ break;
+ case 17:
+ // ATOMIC_LOAD_OR_I16
+ O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
+ return;
+ break;
+ case 18:
+ // ATOMIC_LOAD_OR_I32
+ O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
+ return;
+ break;
+ case 19:
+ // ATOMIC_LOAD_OR_I8
+ O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
+ return;
+ break;
+ case 20:
+ // ATOMIC_LOAD_SUB_I16
+ O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
+ return;
+ break;
+ case 21:
+ // ATOMIC_LOAD_SUB_I32
+ O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
+ return;
+ break;
+ case 22:
+ // ATOMIC_LOAD_SUB_I8
+ O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
+ return;
+ break;
+ case 23:
+ // ATOMIC_LOAD_XOR_I16
+ O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
+ return;
+ break;
+ case 24:
+ // ATOMIC_LOAD_XOR_I32
+ O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
+ return;
+ break;
+ case 25:
+ // ATOMIC_LOAD_XOR_I8
+ O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
+ return;
+ break;
+ case 26:
+ // ATOMIC_SWAP_I16
+ O << " ATOMIC_SWAP_I16 PSEUDO!";
+ return;
+ break;
+ case 27:
+ // ATOMIC_SWAP_I32
+ O << " ATOMIC_SWAP_I32 PSEUDO!";
+ return;
+ break;
+ case 28:
+ // ATOMIC_SWAP_I8
+ O << " ATOMIC_SWAP_I8 PSEUDO!";
+ return;
+ break;
+ case 29:
+ // BR_JTr
+ O << " \n";
+ printJTBlockOperand(MI, 1);
+ return;
+ break;
+ case 30:
+ // BX_RET
+ O << "\tlr";
+ return;
+ break;
+ case 31:
+ // FCONSTD, VABSD, VADDD, VCMPED, VCMPEZD, VDIVD, VMLAD, VMLSD, VMOVD, VM...
+ O << ".f64\t";
+ printOperand(MI, 0);
+ break;
+ case 32:
+ // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
+ O << ".f32\t";
+ printOperand(MI, 0);
+ break;
+ case 33:
+ // FMSTAT
+ O << "\tapsr_nzcv, fpscr";
+ return;
+ break;
+ case 34:
+ // Int_MemBarrierV6
+ O << ", c7, c10, 5";
+ return;
+ break;
+ case 35:
+ // Int_SyncBarrierV6
+ O << ", c7, c10, 4";
+ return;
+ break;
+ case 36:
+ // Int_eh_sjlj_setjmp
+ O << ", #+8] @ eh_setjmp begin\n\tadd\tr12, pc, #8\n\tstr\tr12, [";
+ printOperand(MI, 0);
+ O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
+ return;
+ break;
+ case 37:
+ // LEApcrel
+ O << "-(";
+ PrintSpecial(MI, "private");
+ O << "PCRELL";
+ PrintSpecial(MI, "uid");
+ O << "+8))\n";
+ PrintSpecial(MI, "private");
+ O << "PCRELL";
+ PrintSpecial(MI, "uid");
+ O << ":\n\tadd";
+ printPredicateOperand(MI, 2);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", pc, #";
+ PrintSpecial(MI, "private");
+ O << "PCRELV";
+ PrintSpecial(MI, "uid");
+ return;
+ break;
+ case 38:
+ // LEApcrelJT
+ O << '_';
+ printNoHashImmediate(MI, 2);
+ O << "-(";
+ PrintSpecial(MI, "private");
+ O << "PCRELL";
+ PrintSpecial(MI, "uid");
+ O << "+8))\n";
+ PrintSpecial(MI, "private");
+ O << "PCRELL";
+ PrintSpecial(MI, "uid");
+ O << ":\n\tadd";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", pc, #";
+ PrintSpecial(MI, "private");
+ O << "PCRELV";
+ PrintSpecial(MI, "uid");
+ return;
+ break;
+ case 39:
+ // MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
+ printSBitModifierOperand(MI, 6);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 40:
+ // MOVi, MOVr, MOVrx, MVNi, MVNr
+ printSBitModifierOperand(MI, 4);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 41:
+ // PICADD
+ O << ":\n\tadd";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", pc, ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 42:
+ // PICLDR
+ O << ":\n\tldr";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 43:
+ // PICLDRB
+ O << ":\n\tldrb";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 44:
+ // PICLDRH
+ O << ":\n\tldrh";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 45:
+ // PICLDRSB
+ O << ":\n\tldrsb";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 46:
+ // PICLDRSH
+ O << ":\n\tldrsh";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 47:
+ // PICSTR
+ O << ":\n\tstr";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 48:
+ // PICSTRB
+ O << ":\n\tstrb";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 49:
+ // PICSTRH
+ O << ":\n\tstrh";
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printAddrModePCOperand(MI, 1);
+ return;
+ break;
+ case 50:
+ // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
+ O << ".s32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 51:
+ // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
+ O << ".s16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 52:
+ // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
+ O << ".s8\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 53:
+ // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
+ O << ".u32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 54:
+ // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
+ O << ".u16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 55:
+ // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
+ O << ".u8\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 56:
+ // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
+ O << ".i64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 57:
+ // VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCLZv2i32, VC...
+ O << ".i32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 58:
+ // VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCLZv4i16, VCL...
+ O << ".i16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 59:
+ // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCLZv16i8, VCLZv8i8, VMLAv16...
+ O << ".i8\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 60:
+ // VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
+ O << ".8\t";
+ break;
+ case 61:
+ // VCVTDS
+ O << ".f64.f32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 62:
+ // VCVTSD
+ O << ".f32.f64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 63:
+ // VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIZS
+ O << ".s32.f32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 64:
+ // VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIZS
+ O << ".u32.f32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 65:
+ // VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS
+ O << ".f32.s32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 66:
+ // VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS
+ O << ".f32.u32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 67:
+ // VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
+ O << ".16\t";
+ break;
+ case 68:
+ // VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
+ O << ".32\t";
+ break;
+ case 69:
+ // VLD1d16, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d16, VLD2q16, VLD3LNd1...
+ O << ".16\t{";
+ break;
+ case 70:
+ // VLD1d32, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b, VLD2d32, VLD2q32, ...
+ O << ".32\t{";
+ break;
+ case 71:
+ // VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
+ O << ".64\t{";
+ break;
+ case 72:
+ // VLD1d8, VLD2LNd8, VLD2d8, VLD2q8, VLD3LNd8, VLD3d8, VLD3q8a, VLD3q8b, ...
+ O << ".8\t{";
+ break;
+ case 73:
+ // VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
+ O << ".64\t";
+ break;
+ case 74:
+ // VMULLp, VMULpd, VMULpq
+ O << ".p8\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case 75:
+ // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
+ O << ".s64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 76:
+ // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
+ O << ".u64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 77:
+ // VSITOD
+ O << ".f64.s32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 78:
+ // VTOSIZD
+ O << ".s32.f64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 79:
+ // VTOUIZD
+ O << ".u32.f64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 80:
+ // VUITOD
+ O << ".f64.u32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 81:
+ // t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2ADDrSPi, t2ADDrSPs, ...
+ O << ".w\t";
+ printOperand(MI, 0);
+ break;
+ case 82:
+ // t2BR_JT
+ O << "\n";
+ printJT2BlockOperand(MI, 2);
+ return;
+ break;
+ case 83:
+ // t2Int_eh_sjlj_setjmp
+ O << ", #+8] @ eh_setjmp begin\n\tadr\tr12, 0f\n\torr.w\tr12, r12, #1\n\tstr.w\tr12, [";
+ printOperand(MI, 0);
+ O << ", #+4]\n\tmovs\tr0, #0\n\tb\t1f\n0:\tmovs\tr0, #1 @ eh_setjmp end\n1:";
+ return;
+ break;
+ case 84:
+ // t2LDM, t2LDM_RET, t2STM
+ printAddrMode4Operand(MI, 0, "wide");
+ O << "\t";
+ printAddrMode4Operand(MI, 0);
+ O << ", ";
+ printRegisterList(MI, 4);
+ return;
+ break;
+ case 85:
+ // t2MOVi, t2MOVr, t2MOVrx, t2MVNi
+ printPredicateOperand(MI, 2);
+ break;
+ case 86:
+ // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
+ printPredicateOperand(MI, 4);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 87:
+ // tADDrPCi
+ O << ", pc, ";
+ printThumbS4ImmOperand(MI, 1);
+ return;
+ break;
+ case 88:
+ // tBR_JTr
+ O << "\n\t.align\t2\n";
+ printJTBlockOperand(MI, 1);
+ return;
+ break;
+ case 89:
+ // tBfar
+ O << "\t@ far jump";
+ return;
+ break;
+ case 90:
+ // tInt_eh_sjlj_setjmp
+ O << ", #8]\n\tadr\tr1, 0f\n\tadds\tr1, #1\n\tstr\tr1, [";
+ printOperand(MI, 0);
+ O << ", #4]\n\tmov\tr1, r12\n\tmovs\tr0, #0\n\tb\t1f\n.align 2\n0:\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
+ return;
+ break;
+ case 91:
+ // tLDRpci
+ O << ".n\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 92:
+ // tMOVi8, tMVN, tRSB
+ printPredicateOperand(MI, 3);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 2);
+ break;
+ case 93:
+ // tPICADD
+ O << ":\n\tadd\t";
+ printOperand(MI, 0);
+ O << ", pc";
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 5 bits for 26 unique commands.
+ switch ((Bits >> 15) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, RSCSri, R...
+ printOperand(MI, 1);
+ break;
+ case 1:
+ // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
+ printSOImmOperand(MI, 2);
+ return;
+ break;
+ case 2:
+ // ADCrr, ADDrr, ANDrr, BICrr, EORrr, MUL, ORRrr, SBCrr, SUBrr, VABALsv2i...
+ printOperand(MI, 2);
+ break;
+ case 3:
+ // ADDSri, ADDSrr, ADDSrs, BFC, Bcc, CLZ, CMNri, CMNrr, CMNrs, CMNzri, CM...
+ printOperand(MI, 0);
+ break;
+ case 4:
+ // BL_pred, BLr9_pred
+ printOperand(MI, 0, "call");
+ return;
+ break;
+ case 5:
+ // FCONSTD, FCONSTS, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSfd_sfp, VA...
+ O << ", ";
+ break;
+ case 6:
+ // LDM, LDM_RET, STM, tLDM, tSTM
+ printAddrMode4Operand(MI, 0);
+ O << ", ";
+ printRegisterList(MI, 4);
+ return;
+ break;
+ case 7:
+ // MOVi, MVNi
+ printSOImmOperand(MI, 1);
+ return;
+ break;
+ case 8:
+ // MOVs, MVNs
+ printSORegOperand(MI, 1);
+ return;
+ break;
+ case 9:
+ // VCMPEZD, VCMPEZS, tRSB
+ O << ", #0";
+ return;
+ break;
+ case 10:
+ // VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
+ return;
+ break;
+ case 11:
+ // VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
+ printOperand(MI, 0, "dregpair");
+ O << ", ";
+ printAddrMode6Operand(MI, 1);
+ return;
+ break;
+ case 12:
+ // VLDRQ, VSTRQ
+ printAddrMode4Operand(MI, 1);
+ O << ", ";
+ printOperand(MI, 0, "dregpair");
+ return;
+ break;
+ case 13:
+ // VMOVv16i8, VMOVv8i8
+ printHex8ImmOperand(MI, 1);
+ return;
+ break;
+ case 14:
+ // VMOVv1i64, VMOVv2i64
+ printHex64ImmOperand(MI, 1);
+ return;
+ break;
+ case 15:
+ // VMOVv2i32, VMOVv4i32
+ printHex32ImmOperand(MI, 1);
+ return;
+ break;
+ case 16:
+ // VMOVv4i16, VMOVv8i16
+ printHex16ImmOperand(MI, 1);
+ return;
+ break;
+ case 17:
+ // VST1d16, VST1d32, VST1d64, VST1d8, VST1df, VST2LNd16, VST2LNd32, VST2L...
+ printOperand(MI, 4);
+ break;
+ case 18:
+ // VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
+ printOperand(MI, 4, "dregpair");
+ O << ", ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case 19:
+ // VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
+ printOperand(MI, 5);
+ O << ',';
+ printOperand(MI, 6);
+ O << ',';
+ printOperand(MI, 7);
+ break;
+ case 20:
+ // t2LEApcrel, t2LEApcrelJT
+ O << ", #";
+ printOperand(MI, 1);
+ break;
+ case 21:
+ // t2MOVi, t2MOVr
+ O << ".w\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 22:
+ // t2MOVrx, t2MVNi
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 23:
+ // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
+ printOperand(MI, 3);
+ return;
+ break;
+ case 24:
+ // tADDspi, tSUBspi, tSUBspi_
+ printThumbS4ImmOperand(MI, 2);
+ return;
+ break;
+ case 25:
+ // tPOP, tPOP_RET, tPUSH
+ printRegisterList(MI, 2);
+ return;
+ break;
+ }
+
+ switch (MI->getOpcode()) {
+ case ARM::ADCSSri:
+ case ARM::ADCSSrr:
+ case ARM::ADCSSrs:
+ case ARM::BFC:
+ case ARM::CLZ:
+ case ARM::CMNri:
+ case ARM::CMNrr:
+ case ARM::CMNrs:
+ case ARM::CMNzri:
+ case ARM::CMNzrr:
+ case ARM::CMNzrs:
+ case ARM::CMPri:
+ case ARM::CMPrr:
+ case ARM::CMPrs:
+ case ARM::CMPzri:
+ case ARM::CMPzrr:
+ case ARM::CMPzrs:
+ case ARM::LDR:
+ case ARM::LDRB:
+ case ARM::LDRD:
+ case ARM::LDRH:
+ case ARM::LDRSB:
+ case ARM::LDRSH:
+ case ARM::LDRcp:
+ case ARM::MOVCCi:
+ case ARM::MOVCCr:
+ case ARM::MOVCCs:
+ case ARM::MOVTi16:
+ case ARM::MOVi16:
+ case ARM::MOVi2pieces:
+ case ARM::REV:
+ case ARM::REV16:
+ case ARM::REVSH:
+ case ARM::RSCSri:
+ case ARM::RSCSrs:
+ case ARM::SBCSSri:
+ case ARM::SBCSSrr:
+ case ARM::SBCSSrs:
+ case ARM::STR:
+ case ARM::STRB:
+ case ARM::STRD:
+ case ARM::STRH:
+ case ARM::SXTBr:
+ case ARM::SXTHr:
+ case ARM::TEQri:
+ case ARM::TEQrr:
+ case ARM::TEQrs:
+ case ARM::TSTri:
+ case ARM::TSTrr:
+ case ARM::TSTrs:
+ case ARM::UXTB16r:
+ case ARM::UXTBr:
+ case ARM::UXTHr:
+ case ARM::VABALsv2i64:
+ case ARM::VABALsv4i32:
+ case ARM::VABALsv8i16:
+ case ARM::VABALuv2i64:
+ case ARM::VABALuv4i32:
+ case ARM::VABALuv8i16:
+ case ARM::VABAsv16i8:
+ case ARM::VABAsv2i32:
+ case ARM::VABAsv4i16:
+ case ARM::VABAsv4i32:
+ case ARM::VABAsv8i16:
+ case ARM::VABAsv8i8:
+ case ARM::VABAuv16i8:
+ case ARM::VABAuv2i32:
+ case ARM::VABAuv4i16:
+ case ARM::VABAuv4i32:
+ case ARM::VABAuv8i16:
+ case ARM::VABAuv8i8:
+ case ARM::VABDLsv2i64:
+ case ARM::VABDLsv4i32:
+ case ARM::VABDLsv8i16:
+ case ARM::VABDLuv2i64:
+ case ARM::VABDLuv4i32:
+ case ARM::VABDLuv8i16:
+ case ARM::VABDsv16i8:
+ case ARM::VABDsv2i32:
+ case ARM::VABDsv4i16:
+ case ARM::VABDsv4i32:
+ case ARM::VABDsv8i16:
+ case ARM::VABDsv8i8:
+ case ARM::VABDuv16i8:
+ case ARM::VABDuv2i32:
+ case ARM::VABDuv4i16:
+ case ARM::VABDuv4i32:
+ case ARM::VABDuv8i16:
+ case ARM::VABDuv8i8:
+ case ARM::VADDHNv2i32:
+ case ARM::VADDHNv4i16:
+ case ARM::VADDHNv8i8:
+ case ARM::VADDLsv2i64:
+ case ARM::VADDLsv4i32:
+ case ARM::VADDLsv8i16:
+ case ARM::VADDLuv2i64:
+ case ARM::VADDLuv4i32:
+ case ARM::VADDLuv8i16:
+ case ARM::VADDWsv2i64:
+ case ARM::VADDWsv4i32:
+ case ARM::VADDWsv8i16:
+ case ARM::VADDWuv2i64:
+ case ARM::VADDWuv4i32:
+ case ARM::VADDWuv8i16:
+ case ARM::VADDv16i8:
+ case ARM::VADDv1i64:
+ case ARM::VADDv2i32:
+ case ARM::VADDv2i64:
+ case ARM::VADDv4i16:
+ case ARM::VADDv4i32:
+ case ARM::VADDv8i16:
+ case ARM::VADDv8i8:
+ case ARM::VCEQv16i8:
+ case ARM::VCEQv2i32:
+ case ARM::VCEQv4i16:
+ case ARM::VCEQv4i32:
+ case ARM::VCEQv8i16:
+ case ARM::VCEQv8i8:
+ case ARM::VCGEsv16i8:
+ case ARM::VCGEsv2i32:
+ case ARM::VCGEsv4i16:
+ case ARM::VCGEsv4i32:
+ case ARM::VCGEsv8i16:
+ case ARM::VCGEsv8i8:
+ case ARM::VCGEuv16i8:
+ case ARM::VCGEuv2i32:
+ case ARM::VCGEuv4i16:
+ case ARM::VCGEuv4i32:
+ case ARM::VCGEuv8i16:
+ case ARM::VCGEuv8i8:
+ case ARM::VCGTsv16i8:
+ case ARM::VCGTsv2i32:
+ case ARM::VCGTsv4i16:
+ case ARM::VCGTsv4i32:
+ case ARM::VCGTsv8i16:
+ case ARM::VCGTsv8i8:
+ case ARM::VCGTuv16i8:
+ case ARM::VCGTuv2i32:
+ case ARM::VCGTuv4i16:
+ case ARM::VCGTuv4i32:
+ case ARM::VCGTuv8i16:
+ case ARM::VCGTuv8i8:
+ case ARM::VCNTd:
+ case ARM::VCNTq:
+ case ARM::VDUP16d:
+ case ARM::VDUP16q:
+ case ARM::VDUP32d:
+ case ARM::VDUP32q:
+ case ARM::VDUP8d:
+ case ARM::VDUP8q:
+ case ARM::VDUPfd:
+ case ARM::VDUPfdf:
+ case ARM::VDUPfq:
+ case ARM::VDUPfqf:
+ case ARM::VHADDsv16i8:
+ case ARM::VHADDsv2i32:
+ case ARM::VHADDsv4i16:
+ case ARM::VHADDsv4i32:
+ case ARM::VHADDsv8i16:
+ case ARM::VHADDsv8i8:
+ case ARM::VHADDuv16i8:
+ case ARM::VHADDuv2i32:
+ case ARM::VHADDuv4i16:
+ case ARM::VHADDuv4i32:
+ case ARM::VHADDuv8i16:
+ case ARM::VHADDuv8i8:
+ case ARM::VHSUBsv16i8:
+ case ARM::VHSUBsv2i32:
+ case ARM::VHSUBsv4i16:
+ case ARM::VHSUBsv4i32:
+ case ARM::VHSUBsv8i16:
+ case ARM::VHSUBsv8i8:
+ case ARM::VHSUBuv16i8:
+ case ARM::VHSUBuv2i32:
+ case ARM::VHSUBuv4i16:
+ case ARM::VHSUBuv4i32:
+ case ARM::VHSUBuv8i16:
+ case ARM::VHSUBuv8i8:
+ case ARM::VLDRD:
+ case ARM::VLDRS:
+ case ARM::VMAXsv16i8:
+ case ARM::VMAXsv2i32:
+ case ARM::VMAXsv4i16:
+ case ARM::VMAXsv4i32:
+ case ARM::VMAXsv8i16:
+ case ARM::VMAXsv8i8:
+ case ARM::VMAXuv16i8:
+ case ARM::VMAXuv2i32:
+ case ARM::VMAXuv4i16:
+ case ARM::VMAXuv4i32:
+ case ARM::VMAXuv8i16:
+ case ARM::VMAXuv8i8:
+ case ARM::VMINsv16i8:
+ case ARM::VMINsv2i32:
+ case ARM::VMINsv4i16:
+ case ARM::VMINsv4i32:
+ case ARM::VMINsv8i16:
+ case ARM::VMINsv8i8:
+ case ARM::VMINuv16i8:
+ case ARM::VMINuv2i32:
+ case ARM::VMINuv4i16:
+ case ARM::VMINuv4i32:
+ case ARM::VMINuv8i16:
+ case ARM::VMINuv8i8:
+ case ARM::VMLALsv2i64:
+ case ARM::VMLALsv4i32:
+ case ARM::VMLALsv8i16:
+ case ARM::VMLALuv2i64:
+ case ARM::VMLALuv4i32:
+ case ARM::VMLALuv8i16:
+ case ARM::VMLAv16i8:
+ case ARM::VMLAv2i32:
+ case ARM::VMLAv4i16:
+ case ARM::VMLAv4i32:
+ case ARM::VMLAv8i16:
+ case ARM::VMLAv8i8:
+ case ARM::VMLSLsv2i64:
+ case ARM::VMLSLsv4i32:
+ case ARM::VMLSLsv8i16:
+ case ARM::VMLSLuv2i64:
+ case ARM::VMLSLuv4i32:
+ case ARM::VMLSLuv8i16:
+ case ARM::VMLSv16i8:
+ case ARM::VMLSv2i32:
+ case ARM::VMLSv4i16:
+ case ARM::VMLSv4i32:
+ case ARM::VMLSv8i16:
+ case ARM::VMLSv8i8:
+ case ARM::VMOVDneon:
+ case ARM::VMOVQ:
+ case ARM::VMOVRS:
+ case ARM::VMOVSR:
+ case ARM::VMULLsv2i64:
+ case ARM::VMULLsv4i32:
+ case ARM::VMULLsv8i16:
+ case ARM::VMULLuv2i64:
+ case ARM::VMULLuv4i32:
+ case ARM::VMULLuv8i16:
+ case ARM::VMULv16i8:
+ case ARM::VMULv2i32:
+ case ARM::VMULv4i16:
+ case ARM::VMULv4i32:
+ case ARM::VMULv8i16:
+ case ARM::VMULv8i8:
+ case ARM::VMVNd:
+ case ARM::VMVNq:
+ case ARM::VPADDi16:
+ case ARM::VPADDi32:
+ case ARM::VPADDi8:
+ case ARM::VPMAXs16:
+ case ARM::VPMAXs32:
+ case ARM::VPMAXs8:
+ case ARM::VPMAXu16:
+ case ARM::VPMAXu32:
+ case ARM::VPMAXu8:
+ case ARM::VPMINs16:
+ case ARM::VPMINs32:
+ case ARM::VPMINs8:
+ case ARM::VPMINu16:
+ case ARM::VPMINu32:
+ case ARM::VPMINu8:
+ case ARM::VQADDsv16i8:
+ case ARM::VQADDsv1i64:
+ case ARM::VQADDsv2i32:
+ case ARM::VQADDsv2i64:
+ case ARM::VQADDsv4i16:
+ case ARM::VQADDsv4i32:
+ case ARM::VQADDsv8i16:
+ case ARM::VQADDsv8i8:
+ case ARM::VQADDuv16i8:
+ case ARM::VQADDuv1i64:
+ case ARM::VQADDuv2i32:
+ case ARM::VQADDuv2i64:
+ case ARM::VQADDuv4i16:
+ case ARM::VQADDuv4i32:
+ case ARM::VQADDuv8i16:
+ case ARM::VQADDuv8i8:
+ case ARM::VQDMLALv2i64:
+ case ARM::VQDMLALv4i32:
+ case ARM::VQDMLSLv2i64:
+ case ARM::VQDMLSLv4i32:
+ case ARM::VQDMULHv2i32:
+ case ARM::VQDMULHv4i16:
+ case ARM::VQDMULHv4i32:
+ case ARM::VQDMULHv8i16:
+ case ARM::VQDMULLv2i64:
+ case ARM::VQDMULLv4i32:
+ case ARM::VQRDMULHv2i32:
+ case ARM::VQRDMULHv4i16:
+ case ARM::VQRDMULHv4i32:
+ case ARM::VQRDMULHv8i16:
+ case ARM::VQRSHLsv16i8:
+ case ARM::VQRSHLsv1i64:
+ case ARM::VQRSHLsv2i32:
+ case ARM::VQRSHLsv2i64:
+ case ARM::VQRSHLsv4i16:
+ case ARM::VQRSHLsv4i32:
+ case ARM::VQRSHLsv8i16:
+ case ARM::VQRSHLsv8i8:
+ case ARM::VQRSHLuv16i8:
+ case ARM::VQRSHLuv1i64:
+ case ARM::VQRSHLuv2i32:
+ case ARM::VQRSHLuv2i64:
+ case ARM::VQRSHLuv4i16:
+ case ARM::VQRSHLuv4i32:
+ case ARM::VQRSHLuv8i16:
+ case ARM::VQRSHLuv8i8:
+ case ARM::VQRSHRNsv2i32:
+ case ARM::VQRSHRNsv4i16:
+ case ARM::VQRSHRNsv8i8:
+ case ARM::VQRSHRNuv2i32:
+ case ARM::VQRSHRNuv4i16:
+ case ARM::VQRSHRNuv8i8:
+ case ARM::VQRSHRUNv2i32:
+ case ARM::VQRSHRUNv4i16:
+ case ARM::VQRSHRUNv8i8:
+ case ARM::VQSHLsiv16i8:
+ case ARM::VQSHLsiv1i64:
+ case ARM::VQSHLsiv2i32:
+ case ARM::VQSHLsiv2i64:
+ case ARM::VQSHLsiv4i16:
+ case ARM::VQSHLsiv4i32:
+ case ARM::VQSHLsiv8i16:
+ case ARM::VQSHLsiv8i8:
+ case ARM::VQSHLsuv16i8:
+ case ARM::VQSHLsuv1i64:
+ case ARM::VQSHLsuv2i32:
+ case ARM::VQSHLsuv2i64:
+ case ARM::VQSHLsuv4i16:
+ case ARM::VQSHLsuv4i32:
+ case ARM::VQSHLsuv8i16:
+ case ARM::VQSHLsuv8i8:
+ case ARM::VQSHLsv16i8:
+ case ARM::VQSHLsv1i64:
+ case ARM::VQSHLsv2i32:
+ case ARM::VQSHLsv2i64:
+ case ARM::VQSHLsv4i16:
+ case ARM::VQSHLsv4i32:
+ case ARM::VQSHLsv8i16:
+ case ARM::VQSHLsv8i8:
+ case ARM::VQSHLuiv16i8:
+ case ARM::VQSHLuiv1i64:
+ case ARM::VQSHLuiv2i32:
+ case ARM::VQSHLuiv2i64:
+ case ARM::VQSHLuiv4i16:
+ case ARM::VQSHLuiv4i32:
+ case ARM::VQSHLuiv8i16:
+ case ARM::VQSHLuiv8i8:
+ case ARM::VQSHLuv16i8:
+ case ARM::VQSHLuv1i64:
+ case ARM::VQSHLuv2i32:
+ case ARM::VQSHLuv2i64:
+ case ARM::VQSHLuv4i16:
+ case ARM::VQSHLuv4i32:
+ case ARM::VQSHLuv8i16:
+ case ARM::VQSHLuv8i8:
+ case ARM::VQSHRNsv2i32:
+ case ARM::VQSHRNsv4i16:
+ case ARM::VQSHRNsv8i8:
+ case ARM::VQSHRNuv2i32:
+ case ARM::VQSHRNuv4i16:
+ case ARM::VQSHRNuv8i8:
+ case ARM::VQSHRUNv2i32:
+ case ARM::VQSHRUNv4i16:
+ case ARM::VQSHRUNv8i8:
+ case ARM::VQSUBsv16i8:
+ case ARM::VQSUBsv1i64:
+ case ARM::VQSUBsv2i32:
+ case ARM::VQSUBsv2i64:
+ case ARM::VQSUBsv4i16:
+ case ARM::VQSUBsv4i32:
+ case ARM::VQSUBsv8i16:
+ case ARM::VQSUBsv8i8:
+ case ARM::VQSUBuv16i8:
+ case ARM::VQSUBuv1i64:
+ case ARM::VQSUBuv2i32:
+ case ARM::VQSUBuv2i64:
+ case ARM::VQSUBuv4i16:
+ case ARM::VQSUBuv4i32:
+ case ARM::VQSUBuv8i16:
+ case ARM::VQSUBuv8i8:
+ case ARM::VRADDHNv2i32:
+ case ARM::VRADDHNv4i16:
+ case ARM::VRADDHNv8i8:
+ case ARM::VREV16d8:
+ case ARM::VREV16q8:
+ case ARM::VREV32d16:
+ case ARM::VREV32d8:
+ case ARM::VREV32q16:
+ case ARM::VREV32q8:
+ case ARM::VREV64d16:
+ case ARM::VREV64d32:
+ case ARM::VREV64d8:
+ case ARM::VREV64df:
+ case ARM::VREV64q16:
+ case ARM::VREV64q32:
+ case ARM::VREV64q8:
+ case ARM::VREV64qf:
+ case ARM::VRHADDsv16i8:
+ case ARM::VRHADDsv2i32:
+ case ARM::VRHADDsv4i16:
+ case ARM::VRHADDsv4i32:
+ case ARM::VRHADDsv8i16:
+ case ARM::VRHADDsv8i8:
+ case ARM::VRHADDuv16i8:
+ case ARM::VRHADDuv2i32:
+ case ARM::VRHADDuv4i16:
+ case ARM::VRHADDuv4i32:
+ case ARM::VRHADDuv8i16:
+ case ARM::VRHADDuv8i8:
+ case ARM::VRSHLsv16i8:
+ case ARM::VRSHLsv1i64:
+ case ARM::VRSHLsv2i32:
+ case ARM::VRSHLsv2i64:
+ case ARM::VRSHLsv4i16:
+ case ARM::VRSHLsv4i32:
+ case ARM::VRSHLsv8i16:
+ case ARM::VRSHLsv8i8:
+ case ARM::VRSHLuv16i8:
+ case ARM::VRSHLuv1i64:
+ case ARM::VRSHLuv2i32:
+ case ARM::VRSHLuv2i64:
+ case ARM::VRSHLuv4i16:
+ case ARM::VRSHLuv4i32:
+ case ARM::VRSHLuv8i16:
+ case ARM::VRSHLuv8i8:
+ case ARM::VRSHRNv2i32:
+ case ARM::VRSHRNv4i16:
+ case ARM::VRSHRNv8i8:
+ case ARM::VRSHRsv16i8:
+ case ARM::VRSHRsv1i64:
+ case ARM::VRSHRsv2i32:
+ case ARM::VRSHRsv2i64:
+ case ARM::VRSHRsv4i16:
+ case ARM::VRSHRsv4i32:
+ case ARM::VRSHRsv8i16:
+ case ARM::VRSHRsv8i8:
+ case ARM::VRSHRuv16i8:
+ case ARM::VRSHRuv1i64:
+ case ARM::VRSHRuv2i32:
+ case ARM::VRSHRuv2i64:
+ case ARM::VRSHRuv4i16:
+ case ARM::VRSHRuv4i32:
+ case ARM::VRSHRuv8i16:
+ case ARM::VRSHRuv8i8:
+ case ARM::VRSRAsv16i8:
+ case ARM::VRSRAsv1i64:
+ case ARM::VRSRAsv2i32:
+ case ARM::VRSRAsv2i64:
+ case ARM::VRSRAsv4i16:
+ case ARM::VRSRAsv4i32:
+ case ARM::VRSRAsv8i16:
+ case ARM::VRSRAsv8i8:
+ case ARM::VRSRAuv16i8:
+ case ARM::VRSRAuv1i64:
+ case ARM::VRSRAuv2i32:
+ case ARM::VRSRAuv2i64:
+ case ARM::VRSRAuv4i16:
+ case ARM::VRSRAuv4i32:
+ case ARM::VRSRAuv8i16:
+ case ARM::VRSRAuv8i8:
+ case ARM::VRSUBHNv2i32:
+ case ARM::VRSUBHNv4i16:
+ case ARM::VRSUBHNv8i8:
+ case ARM::VSHLLi16:
+ case ARM::VSHLLi32:
+ case ARM::VSHLLi8:
+ case ARM::VSHLLsv2i64:
+ case ARM::VSHLLsv4i32:
+ case ARM::VSHLLsv8i16:
+ case ARM::VSHLLuv2i64:
+ case ARM::VSHLLuv4i32:
+ case ARM::VSHLLuv8i16:
+ case ARM::VSHLiv16i8:
+ case ARM::VSHLiv1i64:
+ case ARM::VSHLiv2i32:
+ case ARM::VSHLiv2i64:
+ case ARM::VSHLiv4i16:
+ case ARM::VSHLiv4i32:
+ case ARM::VSHLiv8i16:
+ case ARM::VSHLiv8i8:
+ case ARM::VSHLsv16i8:
+ case ARM::VSHLsv1i64:
+ case ARM::VSHLsv2i32:
+ case ARM::VSHLsv2i64:
+ case ARM::VSHLsv4i16:
+ case ARM::VSHLsv4i32:
+ case ARM::VSHLsv8i16:
+ case ARM::VSHLsv8i8:
+ case ARM::VSHLuv16i8:
+ case ARM::VSHLuv1i64:
+ case ARM::VSHLuv2i32:
+ case ARM::VSHLuv2i64:
+ case ARM::VSHLuv4i16:
+ case ARM::VSHLuv4i32:
+ case ARM::VSHLuv8i16:
+ case ARM::VSHLuv8i8:
+ case ARM::VSHRNv2i32:
+ case ARM::VSHRNv4i16:
+ case ARM::VSHRNv8i8:
+ case ARM::VSHRsv16i8:
+ case ARM::VSHRsv1i64:
+ case ARM::VSHRsv2i32:
+ case ARM::VSHRsv2i64:
+ case ARM::VSHRsv4i16:
+ case ARM::VSHRsv4i32:
+ case ARM::VSHRsv8i16:
+ case ARM::VSHRsv8i8:
+ case ARM::VSHRuv16i8:
+ case ARM::VSHRuv1i64:
+ case ARM::VSHRuv2i32:
+ case ARM::VSHRuv2i64:
+ case ARM::VSHRuv4i16:
+ case ARM::VSHRuv4i32:
+ case ARM::VSHRuv8i16:
+ case ARM::VSHRuv8i8:
+ case ARM::VSRAsv16i8:
+ case ARM::VSRAsv1i64:
+ case ARM::VSRAsv2i32:
+ case ARM::VSRAsv2i64:
+ case ARM::VSRAsv4i16:
+ case ARM::VSRAsv4i32:
+ case ARM::VSRAsv8i16:
+ case ARM::VSRAsv8i8:
+ case ARM::VSRAuv16i8:
+ case ARM::VSRAuv1i64:
+ case ARM::VSRAuv2i32:
+ case ARM::VSRAuv2i64:
+ case ARM::VSRAuv4i16:
+ case ARM::VSRAuv4i32:
+ case ARM::VSRAuv8i16:
+ case ARM::VSRAuv8i8:
+ case ARM::VSTRD:
+ case ARM::VSTRS:
+ case ARM::VSUBHNv2i32:
+ case ARM::VSUBHNv4i16:
+ case ARM::VSUBHNv8i8:
+ case ARM::VSUBLsv2i64:
+ case ARM::VSUBLsv4i32:
+ case ARM::VSUBLsv8i16:
+ case ARM::VSUBLuv2i64:
+ case ARM::VSUBLuv4i32:
+ case ARM::VSUBLuv8i16:
+ case ARM::VSUBWsv2i64:
+ case ARM::VSUBWsv4i32:
+ case ARM::VSUBWsv8i16:
+ case ARM::VSUBWuv2i64:
+ case ARM::VSUBWuv4i32:
+ case ARM::VSUBWuv8i16:
+ case ARM::VSUBv16i8:
+ case ARM::VSUBv1i64:
+ case ARM::VSUBv2i32:
+ case ARM::VSUBv2i64:
+ case ARM::VSUBv4i16:
+ case ARM::VSUBv4i32:
+ case ARM::VSUBv8i16:
+ case ARM::VSUBv8i8:
+ case ARM::VTRNd16:
+ case ARM::VTRNd32:
+ case ARM::VTRNd8:
+ case ARM::VTRNq16:
+ case ARM::VTRNq32:
+ case ARM::VTRNq8:
+ case ARM::VTSTv16i8:
+ case ARM::VTSTv2i32:
+ case ARM::VTSTv4i16:
+ case ARM::VTSTv4i32:
+ case ARM::VTSTv8i16:
+ case ARM::VTSTv8i8:
+ case ARM::VUZPd16:
+ case ARM::VUZPd32:
+ case ARM::VUZPd8:
+ case ARM::VUZPq16:
+ case ARM::VUZPq32:
+ case ARM::VUZPq8:
+ case ARM::VZIPd16:
+ case ARM::VZIPd32:
+ case ARM::VZIPd8:
+ case ARM::VZIPq16:
+ case ARM::VZIPq32:
+ case ARM::VZIPq8:
+ case ARM::t2ADCSri:
+ case ARM::t2ADCSrr:
+ case ARM::t2ADCSrs:
+ case ARM::t2BFC:
+ case ARM::t2CLZ:
+ case ARM::t2LDRBi8:
+ case ARM::t2LDRDi8:
+ case ARM::t2LDRDpci:
+ case ARM::t2LDRHi8:
+ case ARM::t2LDRSBi8:
+ case ARM::t2LDRSHi8:
+ case ARM::t2LDRi8:
+ case ARM::t2MOVTi16:
+ case ARM::t2MOVi16:
+ case ARM::t2SBCSri:
+ case ARM::t2SBCSrr:
+ case ARM::t2SBCSrs:
+ case ARM::t2STRBi8:
+ case ARM::t2STRDi8:
+ case ARM::t2STRHi8:
+ case ARM::t2STRi8:
+ case ARM::t2SUBrSPi12_:
+ case ARM::t2SUBrSPi_:
+ case ARM::t2SUBrSPs_:
+ case ARM::tADDhirr:
+ case ARM::tADDi3:
+ case ARM::tADDrSPi:
+ case ARM::tADDrr:
+ case ARM::tASRri:
+ case ARM::tCMN:
+ case ARM::tCMNZ:
+ case ARM::tCMPhir:
+ case ARM::tCMPi8:
+ case ARM::tCMPr:
+ case ARM::tCMPzhir:
+ case ARM::tCMPzi8:
+ case ARM::tCMPzr:
+ case ARM::tLDR:
+ case ARM::tLDRB:
+ case ARM::tLDRH:
+ case ARM::tLDRSB:
+ case ARM::tLDRSH:
+ case ARM::tLDRcp:
+ case ARM::tLDRspi:
+ case ARM::tLSLri:
+ case ARM::tLSRri:
+ case ARM::tMOVCCi:
+ case ARM::tMOVCCr:
+ case ARM::tREV:
+ case ARM::tREV16:
+ case ARM::tREVSH:
+ case ARM::tRestore:
+ case ARM::tSTR:
+ case ARM::tSTRB:
+ case ARM::tSTRH:
+ case ARM::tSTRspi:
+ case ARM::tSUBi3:
+ case ARM::tSUBrr:
+ case ARM::tSXTB:
+ case ARM::tSXTH:
+ case ARM::tSpill:
+ case ARM::tTST:
+ case ARM::tUXTB:
+ case ARM::tUXTH:
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case ARM::ADCSSri:
+ case ARM::MOVCCi:
+ case ARM::RSCSri:
+ case ARM::SBCSSri: printSOImmOperand(MI, 2); break;
+ case ARM::ADCSSrr:
+ case ARM::MOVCCr:
+ case ARM::MOVTi16:
+ case ARM::SBCSSrr:
+ case ARM::VABDLsv2i64:
+ case ARM::VABDLsv4i32:
+ case ARM::VABDLsv8i16:
+ case ARM::VABDLuv2i64:
+ case ARM::VABDLuv4i32:
+ case ARM::VABDLuv8i16:
+ case ARM::VABDsv16i8:
+ case ARM::VABDsv2i32:
+ case ARM::VABDsv4i16:
+ case ARM::VABDsv4i32:
+ case ARM::VABDsv8i16:
+ case ARM::VABDsv8i8:
+ case ARM::VABDuv16i8:
+ case ARM::VABDuv2i32:
+ case ARM::VABDuv4i16:
+ case ARM::VABDuv4i32:
+ case ARM::VABDuv8i16:
+ case ARM::VABDuv8i8:
+ case ARM::VADDHNv2i32:
+ case ARM::VADDHNv4i16:
+ case ARM::VADDHNv8i8:
+ case ARM::VADDLsv2i64:
+ case ARM::VADDLsv4i32:
+ case ARM::VADDLsv8i16:
+ case ARM::VADDLuv2i64:
+ case ARM::VADDLuv4i32:
+ case ARM::VADDLuv8i16:
+ case ARM::VADDWsv2i64:
+ case ARM::VADDWsv4i32:
+ case ARM::VADDWsv8i16:
+ case ARM::VADDWuv2i64:
+ case ARM::VADDWuv4i32:
+ case ARM::VADDWuv8i16:
+ case ARM::VADDv16i8:
+ case ARM::VADDv1i64:
+ case ARM::VADDv2i32:
+ case ARM::VADDv2i64:
+ case ARM::VADDv4i16:
+ case ARM::VADDv4i32:
+ case ARM::VADDv8i16:
+ case ARM::VADDv8i8:
+ case ARM::VCEQv16i8:
+ case ARM::VCEQv2i32:
+ case ARM::VCEQv4i16:
+ case ARM::VCEQv4i32:
+ case ARM::VCEQv8i16:
+ case ARM::VCEQv8i8:
+ case ARM::VCGEsv16i8:
+ case ARM::VCGEsv2i32:
+ case ARM::VCGEsv4i16:
+ case ARM::VCGEsv4i32:
+ case ARM::VCGEsv8i16:
+ case ARM::VCGEsv8i8:
+ case ARM::VCGEuv16i8:
+ case ARM::VCGEuv2i32:
+ case ARM::VCGEuv4i16:
+ case ARM::VCGEuv4i32:
+ case ARM::VCGEuv8i16:
+ case ARM::VCGEuv8i8:
+ case ARM::VCGTsv16i8:
+ case ARM::VCGTsv2i32:
+ case ARM::VCGTsv4i16:
+ case ARM::VCGTsv4i32:
+ case ARM::VCGTsv8i16:
+ case ARM::VCGTsv8i8:
+ case ARM::VCGTuv16i8:
+ case ARM::VCGTuv2i32:
+ case ARM::VCGTuv4i16:
+ case ARM::VCGTuv4i32:
+ case ARM::VCGTuv8i16:
+ case ARM::VCGTuv8i8:
+ case ARM::VHADDsv16i8:
+ case ARM::VHADDsv2i32:
+ case ARM::VHADDsv4i16:
+ case ARM::VHADDsv4i32:
+ case ARM::VHADDsv8i16:
+ case ARM::VHADDsv8i8:
+ case ARM::VHADDuv16i8:
+ case ARM::VHADDuv2i32:
+ case ARM::VHADDuv4i16:
+ case ARM::VHADDuv4i32:
+ case ARM::VHADDuv8i16:
+ case ARM::VHADDuv8i8:
+ case ARM::VHSUBsv16i8:
+ case ARM::VHSUBsv2i32:
+ case ARM::VHSUBsv4i16:
+ case ARM::VHSUBsv4i32:
+ case ARM::VHSUBsv8i16:
+ case ARM::VHSUBsv8i8:
+ case ARM::VHSUBuv16i8:
+ case ARM::VHSUBuv2i32:
+ case ARM::VHSUBuv4i16:
+ case ARM::VHSUBuv4i32:
+ case ARM::VHSUBuv8i16:
+ case ARM::VHSUBuv8i8:
+ case ARM::VMAXsv16i8:
+ case ARM::VMAXsv2i32:
+ case ARM::VMAXsv4i16:
+ case ARM::VMAXsv4i32:
+ case ARM::VMAXsv8i16:
+ case ARM::VMAXsv8i8:
+ case ARM::VMAXuv16i8:
+ case ARM::VMAXuv2i32:
+ case ARM::VMAXuv4i16:
+ case ARM::VMAXuv4i32:
+ case ARM::VMAXuv8i16:
+ case ARM::VMAXuv8i8:
+ case ARM::VMINsv16i8:
+ case ARM::VMINsv2i32:
+ case ARM::VMINsv4i16:
+ case ARM::VMINsv4i32:
+ case ARM::VMINsv8i16:
+ case ARM::VMINsv8i8:
+ case ARM::VMINuv16i8:
+ case ARM::VMINuv2i32:
+ case ARM::VMINuv4i16:
+ case ARM::VMINuv4i32:
+ case ARM::VMINuv8i16:
+ case ARM::VMINuv8i8:
+ case ARM::VMULLsv2i64:
+ case ARM::VMULLsv4i32:
+ case ARM::VMULLsv8i16:
+ case ARM::VMULLuv2i64:
+ case ARM::VMULLuv4i32:
+ case ARM::VMULLuv8i16:
+ case ARM::VMULv16i8:
+ case ARM::VMULv2i32:
+ case ARM::VMULv4i16:
+ case ARM::VMULv4i32:
+ case ARM::VMULv8i16:
+ case ARM::VMULv8i8:
+ case ARM::VPADDi16:
+ case ARM::VPADDi32:
+ case ARM::VPADDi8:
+ case ARM::VPMAXs16:
+ case ARM::VPMAXs32:
+ case ARM::VPMAXs8:
+ case ARM::VPMAXu16:
+ case ARM::VPMAXu32:
+ case ARM::VPMAXu8:
+ case ARM::VPMINs16:
+ case ARM::VPMINs32:
+ case ARM::VPMINs8:
+ case ARM::VPMINu16:
+ case ARM::VPMINu32:
+ case ARM::VPMINu8:
+ case ARM::VQADDsv16i8:
+ case ARM::VQADDsv1i64:
+ case ARM::VQADDsv2i32:
+ case ARM::VQADDsv2i64:
+ case ARM::VQADDsv4i16:
+ case ARM::VQADDsv4i32:
+ case ARM::VQADDsv8i16:
+ case ARM::VQADDsv8i8:
+ case ARM::VQADDuv16i8:
+ case ARM::VQADDuv1i64:
+ case ARM::VQADDuv2i32:
+ case ARM::VQADDuv2i64:
+ case ARM::VQADDuv4i16:
+ case ARM::VQADDuv4i32:
+ case ARM::VQADDuv8i16:
+ case ARM::VQADDuv8i8:
+ case ARM::VQDMULHv2i32:
+ case ARM::VQDMULHv4i16:
+ case ARM::VQDMULHv4i32:
+ case ARM::VQDMULHv8i16:
+ case ARM::VQDMULLv2i64:
+ case ARM::VQDMULLv4i32:
+ case ARM::VQRDMULHv2i32:
+ case ARM::VQRDMULHv4i16:
+ case ARM::VQRDMULHv4i32:
+ case ARM::VQRDMULHv8i16:
+ case ARM::VQRSHLsv16i8:
+ case ARM::VQRSHLsv1i64:
+ case ARM::VQRSHLsv2i32:
+ case ARM::VQRSHLsv2i64:
+ case ARM::VQRSHLsv4i16:
+ case ARM::VQRSHLsv4i32:
+ case ARM::VQRSHLsv8i16:
+ case ARM::VQRSHLsv8i8:
+ case ARM::VQRSHLuv16i8:
+ case ARM::VQRSHLuv1i64:
+ case ARM::VQRSHLuv2i32:
+ case ARM::VQRSHLuv2i64:
+ case ARM::VQRSHLuv4i16:
+ case ARM::VQRSHLuv4i32:
+ case ARM::VQRSHLuv8i16:
+ case ARM::VQRSHLuv8i8:
+ case ARM::VQRSHRNsv2i32:
+ case ARM::VQRSHRNsv4i16:
+ case ARM::VQRSHRNsv8i8:
+ case ARM::VQRSHRNuv2i32:
+ case ARM::VQRSHRNuv4i16:
+ case ARM::VQRSHRNuv8i8:
+ case ARM::VQRSHRUNv2i32:
+ case ARM::VQRSHRUNv4i16:
+ case ARM::VQRSHRUNv8i8:
+ case ARM::VQSHLsiv16i8:
+ case ARM::VQSHLsiv1i64:
+ case ARM::VQSHLsiv2i32:
+ case ARM::VQSHLsiv2i64:
+ case ARM::VQSHLsiv4i16:
+ case ARM::VQSHLsiv4i32:
+ case ARM::VQSHLsiv8i16:
+ case ARM::VQSHLsiv8i8:
+ case ARM::VQSHLsuv16i8:
+ case ARM::VQSHLsuv1i64:
+ case ARM::VQSHLsuv2i32:
+ case ARM::VQSHLsuv2i64:
+ case ARM::VQSHLsuv4i16:
+ case ARM::VQSHLsuv4i32:
+ case ARM::VQSHLsuv8i16:
+ case ARM::VQSHLsuv8i8:
+ case ARM::VQSHLsv16i8:
+ case ARM::VQSHLsv1i64:
+ case ARM::VQSHLsv2i32:
+ case ARM::VQSHLsv2i64:
+ case ARM::VQSHLsv4i16:
+ case ARM::VQSHLsv4i32:
+ case ARM::VQSHLsv8i16:
+ case ARM::VQSHLsv8i8:
+ case ARM::VQSHLuiv16i8:
+ case ARM::VQSHLuiv1i64:
+ case ARM::VQSHLuiv2i32:
+ case ARM::VQSHLuiv2i64:
+ case ARM::VQSHLuiv4i16:
+ case ARM::VQSHLuiv4i32:
+ case ARM::VQSHLuiv8i16:
+ case ARM::VQSHLuiv8i8:
+ case ARM::VQSHLuv16i8:
+ case ARM::VQSHLuv1i64:
+ case ARM::VQSHLuv2i32:
+ case ARM::VQSHLuv2i64:
+ case ARM::VQSHLuv4i16:
+ case ARM::VQSHLuv4i32:
+ case ARM::VQSHLuv8i16:
+ case ARM::VQSHLuv8i8:
+ case ARM::VQSHRNsv2i32:
+ case ARM::VQSHRNsv4i16:
+ case ARM::VQSHRNsv8i8:
+ case ARM::VQSHRNuv2i32:
+ case ARM::VQSHRNuv4i16:
+ case ARM::VQSHRNuv8i8:
+ case ARM::VQSHRUNv2i32:
+ case ARM::VQSHRUNv4i16:
+ case ARM::VQSHRUNv8i8:
+ case ARM::VQSUBsv16i8:
+ case ARM::VQSUBsv1i64:
+ case ARM::VQSUBsv2i32:
+ case ARM::VQSUBsv2i64:
+ case ARM::VQSUBsv4i16:
+ case ARM::VQSUBsv4i32:
+ case ARM::VQSUBsv8i16:
+ case ARM::VQSUBsv8i8:
+ case ARM::VQSUBuv16i8:
+ case ARM::VQSUBuv1i64:
+ case ARM::VQSUBuv2i32:
+ case ARM::VQSUBuv2i64:
+ case ARM::VQSUBuv4i16:
+ case ARM::VQSUBuv4i32:
+ case ARM::VQSUBuv8i16:
+ case ARM::VQSUBuv8i8:
+ case ARM::VRADDHNv2i32:
+ case ARM::VRADDHNv4i16:
+ case ARM::VRADDHNv8i8:
+ case ARM::VRHADDsv16i8:
+ case ARM::VRHADDsv2i32:
+ case ARM::VRHADDsv4i16:
+ case ARM::VRHADDsv4i32:
+ case ARM::VRHADDsv8i16:
+ case ARM::VRHADDsv8i8:
+ case ARM::VRHADDuv16i8:
+ case ARM::VRHADDuv2i32:
+ case ARM::VRHADDuv4i16:
+ case ARM::VRHADDuv4i32:
+ case ARM::VRHADDuv8i16:
+ case ARM::VRHADDuv8i8:
+ case ARM::VRSHLsv16i8:
+ case ARM::VRSHLsv1i64:
+ case ARM::VRSHLsv2i32:
+ case ARM::VRSHLsv2i64:
+ case ARM::VRSHLsv4i16:
+ case ARM::VRSHLsv4i32:
+ case ARM::VRSHLsv8i16:
+ case ARM::VRSHLsv8i8:
+ case ARM::VRSHLuv16i8:
+ case ARM::VRSHLuv1i64:
+ case ARM::VRSHLuv2i32:
+ case ARM::VRSHLuv2i64:
+ case ARM::VRSHLuv4i16:
+ case ARM::VRSHLuv4i32:
+ case ARM::VRSHLuv8i16:
+ case ARM::VRSHLuv8i8:
+ case ARM::VRSHRNv2i32:
+ case ARM::VRSHRNv4i16:
+ case ARM::VRSHRNv8i8:
+ case ARM::VRSHRsv16i8:
+ case ARM::VRSHRsv1i64:
+ case ARM::VRSHRsv2i32:
+ case ARM::VRSHRsv2i64:
+ case ARM::VRSHRsv4i16:
+ case ARM::VRSHRsv4i32:
+ case ARM::VRSHRsv8i16:
+ case ARM::VRSHRsv8i8:
+ case ARM::VRSHRuv16i8:
+ case ARM::VRSHRuv1i64:
+ case ARM::VRSHRuv2i32:
+ case ARM::VRSHRuv2i64:
+ case ARM::VRSHRuv4i16:
+ case ARM::VRSHRuv4i32:
+ case ARM::VRSHRuv8i16:
+ case ARM::VRSHRuv8i8:
+ case ARM::VRSUBHNv2i32:
+ case ARM::VRSUBHNv4i16:
+ case ARM::VRSUBHNv8i8:
+ case ARM::VSHLLi16:
+ case ARM::VSHLLi32:
+ case ARM::VSHLLi8:
+ case ARM::VSHLLsv2i64:
+ case ARM::VSHLLsv4i32:
+ case ARM::VSHLLsv8i16:
+ case ARM::VSHLLuv2i64:
+ case ARM::VSHLLuv4i32:
+ case ARM::VSHLLuv8i16:
+ case ARM::VSHLiv16i8:
+ case ARM::VSHLiv1i64:
+ case ARM::VSHLiv2i32:
+ case ARM::VSHLiv2i64:
+ case ARM::VSHLiv4i16:
+ case ARM::VSHLiv4i32:
+ case ARM::VSHLiv8i16:
+ case ARM::VSHLiv8i8:
+ case ARM::VSHLsv16i8:
+ case ARM::VSHLsv1i64:
+ case ARM::VSHLsv2i32:
+ case ARM::VSHLsv2i64:
+ case ARM::VSHLsv4i16:
+ case ARM::VSHLsv4i32:
+ case ARM::VSHLsv8i16:
+ case ARM::VSHLsv8i8:
+ case ARM::VSHLuv16i8:
+ case ARM::VSHLuv1i64:
+ case ARM::VSHLuv2i32:
+ case ARM::VSHLuv2i64:
+ case ARM::VSHLuv4i16:
+ case ARM::VSHLuv4i32:
+ case ARM::VSHLuv8i16:
+ case ARM::VSHLuv8i8:
+ case ARM::VSHRNv2i32:
+ case ARM::VSHRNv4i16:
+ case ARM::VSHRNv8i8:
+ case ARM::VSHRsv16i8:
+ case ARM::VSHRsv1i64:
+ case ARM::VSHRsv2i32:
+ case ARM::VSHRsv2i64:
+ case ARM::VSHRsv4i16:
+ case ARM::VSHRsv4i32:
+ case ARM::VSHRsv8i16:
+ case ARM::VSHRsv8i8:
+ case ARM::VSHRuv16i8:
+ case ARM::VSHRuv1i64:
+ case ARM::VSHRuv2i32:
+ case ARM::VSHRuv2i64:
+ case ARM::VSHRuv4i16:
+ case ARM::VSHRuv4i32:
+ case ARM::VSHRuv8i16:
+ case ARM::VSHRuv8i8:
+ case ARM::VSUBHNv2i32:
+ case ARM::VSUBHNv4i16:
+ case ARM::VSUBHNv8i8:
+ case ARM::VSUBLsv2i64:
+ case ARM::VSUBLsv4i32:
+ case ARM::VSUBLsv8i16:
+ case ARM::VSUBLuv2i64:
+ case ARM::VSUBLuv4i32:
+ case ARM::VSUBLuv8i16:
+ case ARM::VSUBWsv2i64:
+ case ARM::VSUBWsv4i32:
+ case ARM::VSUBWsv8i16:
+ case ARM::VSUBWuv2i64:
+ case ARM::VSUBWuv4i32:
+ case ARM::VSUBWuv8i16:
+ case ARM::VSUBv16i8:
+ case ARM::VSUBv1i64:
+ case ARM::VSUBv2i32:
+ case ARM::VSUBv2i64:
+ case ARM::VSUBv4i16:
+ case ARM::VSUBv4i32:
+ case ARM::VSUBv8i16:
+ case ARM::VSUBv8i8:
+ case ARM::VTSTv16i8:
+ case ARM::VTSTv2i32:
+ case ARM::VTSTv4i16:
+ case ARM::VTSTv4i32:
+ case ARM::VTSTv8i16:
+ case ARM::VTSTv8i8:
+ case ARM::t2ADCSri:
+ case ARM::t2ADCSrr:
+ case ARM::t2LDRDpci:
+ case ARM::t2MOVTi16:
+ case ARM::t2SBCSri:
+ case ARM::t2SBCSrr:
+ case ARM::t2SUBrSPi12_:
+ case ARM::t2SUBrSPi_:
+ case ARM::tADDhirr:
+ case ARM::tMOVCCi:
+ case ARM::tMOVCCr: printOperand(MI, 2); break;
+ case ARM::ADCSSrs:
+ case ARM::MOVCCs:
+ case ARM::RSCSrs:
+ case ARM::SBCSSrs: printSORegOperand(MI, 2); break;
+ case ARM::BFC:
+ case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
+ case ARM::CLZ:
+ case ARM::CMNrr:
+ case ARM::CMNzrr:
+ case ARM::CMPrr:
+ case ARM::CMPzrr:
+ case ARM::MOVi16:
+ case ARM::REV:
+ case ARM::REV16:
+ case ARM::REVSH:
+ case ARM::SXTBr:
+ case ARM::SXTHr:
+ case ARM::TEQrr:
+ case ARM::TSTrr:
+ case ARM::UXTB16r:
+ case ARM::UXTBr:
+ case ARM::UXTHr:
+ case ARM::VCNTd:
+ case ARM::VCNTq:
+ case ARM::VDUP16d:
+ case ARM::VDUP16q:
+ case ARM::VDUP32d:
+ case ARM::VDUP32q:
+ case ARM::VDUP8d:
+ case ARM::VDUP8q:
+ case ARM::VDUPfd:
+ case ARM::VDUPfq:
+ case ARM::VMOVDneon:
+ case ARM::VMOVQ:
+ case ARM::VMOVRS:
+ case ARM::VMOVSR:
+ case ARM::VMVNd:
+ case ARM::VMVNq:
+ case ARM::VREV16d8:
+ case ARM::VREV16q8:
+ case ARM::VREV32d16:
+ case ARM::VREV32d8:
+ case ARM::VREV32q16:
+ case ARM::VREV32q8:
+ case ARM::VREV64d16:
+ case ARM::VREV64d32:
+ case ARM::VREV64d8:
+ case ARM::VREV64df:
+ case ARM::VREV64q16:
+ case ARM::VREV64q32:
+ case ARM::VREV64q8:
+ case ARM::VREV64qf:
+ case ARM::VTRNd16:
+ case ARM::VTRNd32:
+ case ARM::VTRNd8:
+ case ARM::VTRNq16:
+ case ARM::VTRNq32:
+ case ARM::VTRNq8:
+ case ARM::VUZPd16:
+ case ARM::VUZPd32:
+ case ARM::VUZPd8:
+ case ARM::VUZPq16:
+ case ARM::VUZPq32:
+ case ARM::VUZPq8:
+ case ARM::VZIPd16:
+ case ARM::VZIPd32:
+ case ARM::VZIPd8:
+ case ARM::VZIPq16:
+ case ARM::VZIPq32:
+ case ARM::VZIPq8:
+ case ARM::t2CLZ:
+ case ARM::t2MOVi16:
+ case ARM::tCMN:
+ case ARM::tCMNZ:
+ case ARM::tCMPhir:
+ case ARM::tCMPi8:
+ case ARM::tCMPr:
+ case ARM::tCMPzhir:
+ case ARM::tCMPzi8:
+ case ARM::tCMPzr:
+ case ARM::tLDRcp:
+ case ARM::tREV:
+ case ARM::tREV16:
+ case ARM::tREVSH:
+ case ARM::tSXTB:
+ case ARM::tSXTH:
+ case ARM::tTST:
+ case ARM::tUXTB:
+ case ARM::tUXTH: printOperand(MI, 1); break;
+ case ARM::CMNri:
+ case ARM::CMNzri:
+ case ARM::CMPri:
+ case ARM::CMPzri:
+ case ARM::TEQri:
+ case ARM::TSTri: printSOImmOperand(MI, 1); break;
+ case ARM::CMNrs:
+ case ARM::CMNzrs:
+ case ARM::CMPrs:
+ case ARM::CMPzrs:
+ case ARM::TEQrs:
+ case ARM::TSTrs: printSORegOperand(MI, 1); break;
+ case ARM::LDR:
+ case ARM::LDRB:
+ case ARM::LDRcp:
+ case ARM::STR:
+ case ARM::STRB: printAddrMode2Operand(MI, 1); break;
+ case ARM::LDRD:
+ case ARM::STRD: printAddrMode3Operand(MI, 2); break;
+ case ARM::LDRH:
+ case ARM::LDRSB:
+ case ARM::LDRSH:
+ case ARM::STRH: printAddrMode3Operand(MI, 1); break;
+ case ARM::MOVi2pieces: printSOImm2PartOperand(MI, 1); break;
+ case ARM::VABALsv2i64:
+ case ARM::VABALsv4i32:
+ case ARM::VABALsv8i16:
+ case ARM::VABALuv2i64:
+ case ARM::VABALuv4i32:
+ case ARM::VABALuv8i16:
+ case ARM::VABAsv16i8:
+ case ARM::VABAsv2i32:
+ case ARM::VABAsv4i16:
+ case ARM::VABAsv4i32:
+ case ARM::VABAsv8i16:
+ case ARM::VABAsv8i8:
+ case ARM::VABAuv16i8:
+ case ARM::VABAuv2i32:
+ case ARM::VABAuv4i16:
+ case ARM::VABAuv4i32:
+ case ARM::VABAuv8i16:
+ case ARM::VABAuv8i8:
+ case ARM::VMLALsv2i64:
+ case ARM::VMLALsv4i32:
+ case ARM::VMLALsv8i16:
+ case ARM::VMLALuv2i64:
+ case ARM::VMLALuv4i32:
+ case ARM::VMLALuv8i16:
+ case ARM::VMLAv16i8:
+ case ARM::VMLAv2i32:
+ case ARM::VMLAv4i16:
+ case ARM::VMLAv4i32:
+ case ARM::VMLAv8i16:
+ case ARM::VMLAv8i8:
+ case ARM::VMLSLsv2i64:
+ case ARM::VMLSLsv4i32:
+ case ARM::VMLSLsv8i16:
+ case ARM::VMLSLuv2i64:
+ case ARM::VMLSLuv4i32:
+ case ARM::VMLSLuv8i16:
+ case ARM::VMLSv16i8:
+ case ARM::VMLSv2i32:
+ case ARM::VMLSv4i16:
+ case ARM::VMLSv4i32:
+ case ARM::VMLSv8i16:
+ case ARM::VMLSv8i8:
+ case ARM::VQDMLALv2i64:
+ case ARM::VQDMLALv4i32:
+ case ARM::VQDMLSLv2i64:
+ case ARM::VQDMLSLv4i32:
+ case ARM::VRSRAsv16i8:
+ case ARM::VRSRAsv1i64:
+ case ARM::VRSRAsv2i32:
+ case ARM::VRSRAsv2i64:
+ case ARM::VRSRAsv4i16:
+ case ARM::VRSRAsv4i32:
+ case ARM::VRSRAsv8i16:
+ case ARM::VRSRAsv8i8:
+ case ARM::VRSRAuv16i8:
+ case ARM::VRSRAuv1i64:
+ case ARM::VRSRAuv2i32:
+ case ARM::VRSRAuv2i64:
+ case ARM::VRSRAuv4i16:
+ case ARM::VRSRAuv4i32:
+ case ARM::VRSRAuv8i16:
+ case ARM::VRSRAuv8i8:
+ case ARM::VSRAsv16i8:
+ case ARM::VSRAsv1i64:
+ case ARM::VSRAsv2i32:
+ case ARM::VSRAsv2i64:
+ case ARM::VSRAsv4i16:
+ case ARM::VSRAsv4i32:
+ case ARM::VSRAsv8i16:
+ case ARM::VSRAsv8i8:
+ case ARM::VSRAuv16i8:
+ case ARM::VSRAuv1i64:
+ case ARM::VSRAuv2i32:
+ case ARM::VSRAuv2i64:
+ case ARM::VSRAuv4i16:
+ case ARM::VSRAuv4i32:
+ case ARM::VSRAuv8i16:
+ case ARM::VSRAuv8i8:
+ case ARM::tADDi3:
+ case ARM::tADDrr:
+ case ARM::tASRri:
+ case ARM::tLSLri:
+ case ARM::tLSRri:
+ case ARM::tSUBi3:
+ case ARM::tSUBrr: printOperand(MI, 3); break;
+ case ARM::VDUPfdf:
+ case ARM::VDUPfqf: printOperand(MI, 1, "lane"); break;
+ case ARM::VLDRD:
+ case ARM::VLDRS:
+ case ARM::VSTRD:
+ case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
+ case ARM::t2ADCSrs:
+ case ARM::t2SBCSrs:
+ case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
+ case ARM::t2LDRBi8:
+ case ARM::t2LDRHi8:
+ case ARM::t2LDRSBi8:
+ case ARM::t2LDRSHi8:
+ case ARM::t2LDRi8:
+ case ARM::t2STRBi8:
+ case ARM::t2STRHi8:
+ case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
+ case ARM::t2LDRDi8:
+ case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
+ case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
+ case ARM::tLDR:
+ case ARM::tSTR: printThumbAddrModeS4Operand(MI, 1); break;
+ case ARM::tLDRB:
+ case ARM::tSTRB: printThumbAddrModeS1Operand(MI, 1); break;
+ case ARM::tLDRH:
+ case ARM::tSTRH: printThumbAddrModeS2Operand(MI, 1); break;
+ case ARM::tLDRSB:
+ case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
+ case ARM::tLDRspi:
+ case ARM::tRestore:
+ case ARM::tSTRspi:
+ case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
+ }
+ return;
+ break;
+ case ARM::ADCrr:
+ case ARM::ADDrr:
+ case ARM::ANDrr:
+ case ARM::BICrr:
+ case ARM::Bcc:
+ case ARM::EORrr:
+ case ARM::MOVr:
+ case ARM::MUL:
+ case ARM::MVNr:
+ case ARM::ORRrr:
+ case ARM::SBCrr:
+ case ARM::SUBrr:
+ case ARM::VABSv16i8:
+ case ARM::VABSv2i32:
+ case ARM::VABSv4i16:
+ case ARM::VABSv4i32:
+ case ARM::VABSv8i16:
+ case ARM::VABSv8i8:
+ case ARM::VCLSv16i8:
+ case ARM::VCLSv2i32:
+ case ARM::VCLSv4i16:
+ case ARM::VCLSv4i32:
+ case ARM::VCLSv8i16:
+ case ARM::VCLSv8i8:
+ case ARM::VCLZv16i8:
+ case ARM::VCLZv2i32:
+ case ARM::VCLZv4i16:
+ case ARM::VCLZv4i32:
+ case ARM::VCLZv8i16:
+ case ARM::VCLZv8i8:
+ case ARM::VMOVLsv2i64:
+ case ARM::VMOVLsv4i32:
+ case ARM::VMOVLsv8i16:
+ case ARM::VMOVLuv2i64:
+ case ARM::VMOVLuv4i32:
+ case ARM::VMOVLuv8i16:
+ case ARM::VMOVNv2i32:
+ case ARM::VMOVNv4i16:
+ case ARM::VMOVNv8i8:
+ case ARM::VNEGs16d:
+ case ARM::VNEGs16q:
+ case ARM::VNEGs32d:
+ case ARM::VNEGs32q:
+ case ARM::VNEGs8d:
+ case ARM::VNEGs8q:
+ case ARM::VPADALsv16i8:
+ case ARM::VPADALsv2i32:
+ case ARM::VPADALsv4i16:
+ case ARM::VPADALsv4i32:
+ case ARM::VPADALsv8i16:
+ case ARM::VPADALsv8i8:
+ case ARM::VPADALuv16i8:
+ case ARM::VPADALuv2i32:
+ case ARM::VPADALuv4i16:
+ case ARM::VPADALuv4i32:
+ case ARM::VPADALuv8i16:
+ case ARM::VPADALuv8i8:
+ case ARM::VPADDLsv16i8:
+ case ARM::VPADDLsv2i32:
+ case ARM::VPADDLsv4i16:
+ case ARM::VPADDLsv4i32:
+ case ARM::VPADDLsv8i16:
+ case ARM::VPADDLsv8i8:
+ case ARM::VPADDLuv16i8:
+ case ARM::VPADDLuv2i32:
+ case ARM::VPADDLuv4i16:
+ case ARM::VPADDLuv4i32:
+ case ARM::VPADDLuv8i16:
+ case ARM::VPADDLuv8i8:
+ case ARM::VQABSv16i8:
+ case ARM::VQABSv2i32:
+ case ARM::VQABSv4i16:
+ case ARM::VQABSv4i32:
+ case ARM::VQABSv8i16:
+ case ARM::VQABSv8i8:
+ case ARM::VQMOVNsuv2i32:
+ case ARM::VQMOVNsuv4i16:
+ case ARM::VQMOVNsuv8i8:
+ case ARM::VQMOVNsv2i32:
+ case ARM::VQMOVNsv4i16:
+ case ARM::VQMOVNsv8i8:
+ case ARM::VQMOVNuv2i32:
+ case ARM::VQMOVNuv4i16:
+ case ARM::VQMOVNuv8i8:
+ case ARM::VQNEGv16i8:
+ case ARM::VQNEGv2i32:
+ case ARM::VQNEGv4i16:
+ case ARM::VQNEGv4i32:
+ case ARM::VQNEGv8i16:
+ case ARM::VQNEGv8i8:
+ case ARM::VRECPEd:
+ case ARM::VRECPEq:
+ case ARM::VRSQRTEd:
+ case ARM::VRSQRTEq:
+ case ARM::t2LEApcrel:
+ case ARM::tADDrSP:
+ case ARM::tADDspr:
+ case ARM::tADDspr_:
+ case ARM::tANDsp:
+ case ARM::tBcc:
+ case ARM::tCBNZ:
+ case ARM::tCBZ:
+ case ARM::tMOVSr:
+ case ARM::tMOVgpr2gpr:
+ case ARM::tMOVgpr2tgpr:
+ case ARM::tMOVr:
+ case ARM::tMOVtgpr2gpr:
+ return;
+ break;
+ case ARM::ADDSri:
+ case ARM::ADDSrr:
+ case ARM::ADDSrs:
+ case ARM::RSBSri:
+ case ARM::RSBSrs:
+ case ARM::SMMUL:
+ case ARM::SMULBB:
+ case ARM::SMULBT:
+ case ARM::SMULTB:
+ case ARM::SMULTT:
+ case ARM::SMULWB:
+ case ARM::SMULWT:
+ case ARM::SUBSri:
+ case ARM::SUBSrr:
+ case ARM::SUBSrs:
+ case ARM::SXTABrr:
+ case ARM::SXTAHrr:
+ case ARM::UXTABrr:
+ case ARM::UXTAHrr:
+ case ARM::VANDd:
+ case ARM::VANDq:
+ case ARM::VBICd:
+ case ARM::VBICq:
+ case ARM::VEORd:
+ case ARM::VEORq:
+ case ARM::VMOVDRR:
+ case ARM::VMOVRRD:
+ case ARM::VORNd:
+ case ARM::VORNq:
+ case ARM::VORRd:
+ case ARM::VORRq:
+ case ARM::t2ADCri:
+ case ARM::t2ADDrSPi12:
+ case ARM::t2ADDri12:
+ case ARM::t2ANDri:
+ case ARM::t2BICri:
+ case ARM::t2EORri:
+ case ARM::t2MUL:
+ case ARM::t2ORNri:
+ case ARM::t2ORNrr:
+ case ARM::t2ORNrs:
+ case ARM::t2ORRri:
+ case ARM::t2RSBSrs:
+ case ARM::t2RSBrs:
+ case ARM::t2SBCri:
+ case ARM::t2SMMUL:
+ case ARM::t2SMULBB:
+ case ARM::t2SMULBT:
+ case ARM::t2SMULTB:
+ case ARM::t2SMULTT:
+ case ARM::t2SMULWB:
+ case ARM::t2SMULWT:
+ case ARM::t2SUBrSPi12:
+ case ARM::t2SUBrSPs:
+ case ARM::t2SUBri12:
+ case ARM::t2SXTABrr:
+ case ARM::t2SXTAHrr:
+ case ARM::t2UXTABrr:
+ case ARM::t2UXTAHrr:
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case ARM::ADDSri:
+ case ARM::RSBSri:
+ case ARM::SUBSri: printSOImmOperand(MI, 2); break;
+ case ARM::ADDSrr:
+ case ARM::SMMUL:
+ case ARM::SMULBB:
+ case ARM::SMULBT:
+ case ARM::SMULTB:
+ case ARM::SMULTT:
+ case ARM::SMULWB:
+ case ARM::SMULWT:
+ case ARM::SUBSrr:
+ case ARM::SXTABrr:
+ case ARM::SXTAHrr:
+ case ARM::UXTABrr:
+ case ARM::UXTAHrr:
+ case ARM::VANDd:
+ case ARM::VANDq:
+ case ARM::VBICd:
+ case ARM::VBICq:
+ case ARM::VEORd:
+ case ARM::VEORq:
+ case ARM::VMOVDRR:
+ case ARM::VMOVRRD:
+ case ARM::VORNd:
+ case ARM::VORNq:
+ case ARM::VORRd:
+ case ARM::VORRq:
+ case ARM::t2ADCri:
+ case ARM::t2ADDrSPi12:
+ case ARM::t2ADDri12:
+ case ARM::t2ANDri:
+ case ARM::t2BICri:
+ case ARM::t2EORri:
+ case ARM::t2MUL:
+ case ARM::t2ORNri:
+ case ARM::t2ORNrr:
+ case ARM::t2ORRri:
+ case ARM::t2SBCri:
+ case ARM::t2SMMUL:
+ case ARM::t2SMULBB:
+ case ARM::t2SMULBT:
+ case ARM::t2SMULTB:
+ case ARM::t2SMULTT:
+ case ARM::t2SMULWB:
+ case ARM::t2SMULWT:
+ case ARM::t2SUBrSPi12:
+ case ARM::t2SUBri12:
+ case ARM::t2SXTABrr:
+ case ARM::t2SXTAHrr:
+ case ARM::t2UXTABrr:
+ case ARM::t2UXTAHrr: printOperand(MI, 2); break;
+ case ARM::ADDSrs:
+ case ARM::RSBSrs:
+ case ARM::SUBSrs: printSORegOperand(MI, 2); break;
+ case ARM::t2ORNrs:
+ case ARM::t2RSBSrs:
+ case ARM::t2RSBrs:
+ case ARM::t2SUBrSPs: printT2SOOperand(MI, 2); break;
+ }
+ return;
+ break;
+ case ARM::BR_JTadd:
+ O << " \n";
+ printJTBlockOperand(MI, 2);
+ return;
+ break;
+ case ARM::FCONSTD:
+ case ARM::FCONSTS:
+ case ARM::MOVrx:
+ case ARM::VABSD:
+ case ARM::VABSS:
+ case ARM::VABSfd:
+ case ARM::VABSfd_sfp:
+ case ARM::VABSfq:
+ case ARM::VCMPED:
+ case ARM::VCMPES:
+ case ARM::VCVTf2xsd:
+ case ARM::VCVTf2xsq:
+ case ARM::VCVTf2xud:
+ case ARM::VCVTf2xuq:
+ case ARM::VCVTxs2fd:
+ case ARM::VCVTxs2fq:
+ case ARM::VCVTxu2fd:
+ case ARM::VCVTxu2fq:
+ case ARM::VMOVD:
+ case ARM::VMOVDcc:
+ case ARM::VMOVS:
+ case ARM::VMOVScc:
+ case ARM::VNEGD:
+ case ARM::VNEGDcc:
+ case ARM::VNEGS:
+ case ARM::VNEGScc:
+ case ARM::VNEGf32d:
+ case ARM::VNEGf32d_sfp:
+ case ARM::VNEGf32q:
+ case ARM::VRECPEfd:
+ case ARM::VRECPEfq:
+ case ARM::VRSQRTEfd:
+ case ARM::VRSQRTEfq:
+ case ARM::VSQRTD:
+ case ARM::VSQRTS:
+ case ARM::t2CMNri:
+ case ARM::t2CMNrr:
+ case ARM::t2CMNrs:
+ case ARM::t2CMNzri:
+ case ARM::t2CMNzrr:
+ case ARM::t2CMNzrs:
+ case ARM::t2CMPri:
+ case ARM::t2CMPrr:
+ case ARM::t2CMPrs:
+ case ARM::t2CMPzri:
+ case ARM::t2CMPzrr:
+ case ARM::t2CMPzrs:
+ case ARM::t2LDRBi12:
+ case ARM::t2LDRBpci:
+ case ARM::t2LDRBs:
+ case ARM::t2LDRHi12:
+ case ARM::t2LDRHpci:
+ case ARM::t2LDRHs:
+ case ARM::t2LDRSBi12:
+ case ARM::t2LDRSBpci:
+ case ARM::t2LDRSBs:
+ case ARM::t2LDRSHi12:
+ case ARM::t2LDRSHpci:
+ case ARM::t2LDRSHs:
+ case ARM::t2LDRi12:
+ case ARM::t2LDRpci:
+ case ARM::t2LDRs:
+ case ARM::t2MOVCCi:
+ case ARM::t2MOVCCr:
+ case ARM::t2MOVsra_flag:
+ case ARM::t2MOVsrl_flag:
+ case ARM::t2MVNr:
+ case ARM::t2MVNs:
+ case ARM::t2REV:
+ case ARM::t2REV16:
+ case ARM::t2REVSH:
+ case ARM::t2STRBi12:
+ case ARM::t2STRBs:
+ case ARM::t2STRHi12:
+ case ARM::t2STRHs:
+ case ARM::t2STRi12:
+ case ARM::t2STRs:
+ case ARM::t2SXTBr:
+ case ARM::t2SXTHr:
+ case ARM::t2TEQri:
+ case ARM::t2TEQrr:
+ case ARM::t2TEQrs:
+ case ARM::t2TSTri:
+ case ARM::t2TSTrr:
+ case ARM::t2TSTrs:
+ case ARM::t2UXTB16r:
+ case ARM::t2UXTBr:
+ case ARM::t2UXTHr:
+ switch (MI->getOpcode()) {
+ case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
+ case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
+ case ARM::MOVrx: O << ", rrx"; break;
+ case ARM::VABSD:
+ case ARM::VABSS:
+ case ARM::VABSfd:
+ case ARM::VABSfd_sfp:
+ case ARM::VABSfq:
+ case ARM::VCMPED:
+ case ARM::VCMPES:
+ case ARM::VMOVD:
+ case ARM::VMOVS:
+ case ARM::VNEGD:
+ case ARM::VNEGS:
+ case ARM::VNEGf32d:
+ case ARM::VNEGf32d_sfp:
+ case ARM::VNEGf32q:
+ case ARM::VRECPEfd:
+ case ARM::VRECPEfq:
+ case ARM::VRSQRTEfd:
+ case ARM::VRSQRTEfq:
+ case ARM::VSQRTD:
+ case ARM::VSQRTS:
+ case ARM::t2CMNri:
+ case ARM::t2CMNrr:
+ case ARM::t2CMNzri:
+ case ARM::t2CMNzrr:
+ case ARM::t2CMPri:
+ case ARM::t2CMPrr:
+ case ARM::t2CMPzri:
+ case ARM::t2CMPzrr:
+ case ARM::t2LDRBpci:
+ case ARM::t2LDRHpci:
+ case ARM::t2LDRSBpci:
+ case ARM::t2LDRSHpci:
+ case ARM::t2LDRpci:
+ case ARM::t2MVNr:
+ case ARM::t2REV:
+ case ARM::t2REV16:
+ case ARM::t2REVSH:
+ case ARM::t2SXTBr:
+ case ARM::t2SXTHr:
+ case ARM::t2TEQri:
+ case ARM::t2TEQrr:
+ case ARM::t2TSTri:
+ case ARM::t2TSTrr:
+ case ARM::t2UXTB16r:
+ case ARM::t2UXTBr:
+ case ARM::t2UXTHr: printOperand(MI, 1); break;
+ case ARM::VCVTf2xsd:
+ case ARM::VCVTf2xsq:
+ case ARM::VCVTf2xud:
+ case ARM::VCVTf2xuq:
+ case ARM::VCVTxs2fd:
+ case ARM::VCVTxs2fq:
+ case ARM::VCVTxu2fd:
+ case ARM::VCVTxu2fq:
+ case ARM::VMOVDcc:
+ case ARM::VMOVScc:
+ case ARM::VNEGDcc:
+ case ARM::VNEGScc:
+ case ARM::t2MOVCCi:
+ case ARM::t2MOVCCr: printOperand(MI, 2); break;
+ case ARM::t2CMNrs:
+ case ARM::t2CMNzrs:
+ case ARM::t2CMPrs:
+ case ARM::t2CMPzrs:
+ case ARM::t2MVNs:
+ case ARM::t2TEQrs:
+ case ARM::t2TSTrs: printT2SOOperand(MI, 1); break;
+ case ARM::t2LDRBi12:
+ case ARM::t2LDRHi12:
+ case ARM::t2LDRSBi12:
+ case ARM::t2LDRSHi12:
+ case ARM::t2LDRi12:
+ case ARM::t2STRBi12:
+ case ARM::t2STRHi12:
+ case ARM::t2STRi12: printT2AddrModeImm12Operand(MI, 1); break;
+ case ARM::t2LDRBs:
+ case ARM::t2LDRHs:
+ case ARM::t2LDRSBs:
+ case ARM::t2LDRSHs:
+ case ARM::t2LDRs:
+ case ARM::t2STRBs:
+ case ARM::t2STRHs:
+ case ARM::t2STRs: printT2AddrModeSoRegOperand(MI, 1); break;
+ case ARM::t2MOVsra_flag:
+ case ARM::t2MOVsrl_flag: O << ", #1"; break;
+ }
+ return;
+ break;
+ case ARM::LDRB_POST:
+ case ARM::LDRH_POST:
+ case ARM::LDRSB_POST:
+ case ARM::LDRSH_POST:
+ case ARM::LDR_POST:
+ case ARM::STRB_POST:
+ case ARM::STRH_POST:
+ case ARM::STR_POST:
+ case ARM::t2LDRB_POST:
+ case ARM::t2LDRH_POST:
+ case ARM::t2LDRSB_POST:
+ case ARM::t2LDRSH_POST:
+ case ARM::t2LDR_POST:
+ case ARM::t2STRB_POST:
+ case ARM::t2STRH_POST:
+ case ARM::t2STR_POST:
+ O << ", [";
+ printOperand(MI, 2);
+ O << "], ";
+ switch (MI->getOpcode()) {
+ case ARM::LDRB_POST:
+ case ARM::LDR_POST:
+ case ARM::STRB_POST:
+ case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
+ case ARM::LDRH_POST:
+ case ARM::LDRSB_POST:
+ case ARM::LDRSH_POST:
+ case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
+ case ARM::t2LDRB_POST:
+ case ARM::t2LDRH_POST:
+ case ARM::t2LDRSB_POST:
+ case ARM::t2LDRSH_POST:
+ case ARM::t2LDR_POST:
+ case ARM::t2STRB_POST:
+ case ARM::t2STRH_POST:
+ case ARM::t2STR_POST: printT2AddrModeImm8OffsetOperand(MI, 3); break;
+ }
+ return;
+ break;
+ case ARM::LDRB_PRE:
+ case ARM::LDRH_PRE:
+ case ARM::LDRSB_PRE:
+ case ARM::LDRSH_PRE:
+ case ARM::LDR_PRE:
+ case ARM::t2LDRB_PRE:
+ case ARM::t2LDRH_PRE:
+ case ARM::t2LDRSB_PRE:
+ case ARM::t2LDRSH_PRE:
+ case ARM::t2LDR_PRE:
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case ARM::LDRB_PRE:
+ case ARM::LDR_PRE: printAddrMode2Operand(MI, 2); break;
+ case ARM::LDRH_PRE:
+ case ARM::LDRSB_PRE:
+ case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
+ case ARM::t2LDRB_PRE:
+ case ARM::t2LDRH_PRE:
+ case ARM::t2LDRSB_PRE:
+ case ARM::t2LDRSH_PRE:
+ case ARM::t2LDR_PRE: printT2AddrModeImm8Operand(MI, 2); break;
+ }
+ O << '!';
+ return;
+ break;
+ case ARM::LDREX:
+ case ARM::LDREXB:
+ case ARM::LDREXH:
+ case ARM::t2LDREX:
+ case ARM::t2LDREXB:
+ case ARM::t2LDREXH:
+ O << ", [";
+ printOperand(MI, 1);
+ O << ']';
+ return;
+ break;
+ case ARM::LDREXD:
+ case ARM::STREX:
+ case ARM::STREXB:
+ case ARM::STREXH:
+ case ARM::t2LDREXD:
+ case ARM::t2STREX:
+ case ARM::t2STREXB:
+ case ARM::t2STREXH:
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", [";
+ printOperand(MI, 2);
+ O << ']';
+ return;
+ break;
+ case ARM::MLA:
+ case ARM::SMLAL:
+ case ARM::SMULL:
+ case ARM::UMLAL:
+ case ARM::UMULL:
+ case ARM::VBSLd:
+ case ARM::VBSLq:
+ case ARM::VSLIv16i8:
+ case ARM::VSLIv1i64:
+ case ARM::VSLIv2i32:
+ case ARM::VSLIv2i64:
+ case ARM::VSLIv4i16:
+ case ARM::VSLIv4i32:
+ case ARM::VSLIv8i16:
+ case ARM::VSLIv8i8:
+ case ARM::VSRIv16i8:
+ case ARM::VSRIv1i64:
+ case ARM::VSRIv2i32:
+ case ARM::VSRIv2i64:
+ case ARM::VSRIv4i16:
+ case ARM::VSRIv4i32:
+ case ARM::VSRIv8i16:
+ case ARM::VSRIv8i8:
+ O << ", ";
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 3);
+ return;
+ break;
+ case ARM::MLS:
+ case ARM::PKHBT:
+ case ARM::PKHTB:
+ case ARM::SBFX:
+ case ARM::SMLABB:
+ case ARM::SMLABT:
+ case ARM::SMLATB:
+ case ARM::SMLATT:
+ case ARM::SMLAWB:
+ case ARM::SMLAWT:
+ case ARM::SMMLA:
+ case ARM::SMMLS:
+ case ARM::SXTABrr_rot:
+ case ARM::SXTAHrr_rot:
+ case ARM::UBFX:
+ case ARM::UMAAL:
+ case ARM::UXTABrr_rot:
+ case ARM::UXTAHrr_rot:
+ case ARM::VEXTd16:
+ case ARM::VEXTd32:
+ case ARM::VEXTd8:
+ case ARM::VEXTdf:
+ case ARM::VEXTq16:
+ case ARM::VEXTq32:
+ case ARM::VEXTq8:
+ case ARM::VEXTqf:
+ case ARM::t2MLA:
+ case ARM::t2MLS:
+ case ARM::t2PKHBT:
+ case ARM::t2PKHTB:
+ case ARM::t2SBFX:
+ case ARM::t2SMLABB:
+ case ARM::t2SMLABT:
+ case ARM::t2SMLAL:
+ case ARM::t2SMLATB:
+ case ARM::t2SMLATT:
+ case ARM::t2SMLAWB:
+ case ARM::t2SMLAWT:
+ case ARM::t2SMMLA:
+ case ARM::t2SMMLS:
+ case ARM::t2SMULL:
+ case ARM::t2SXTABrr_rot:
+ case ARM::t2SXTAHrr_rot:
+ case ARM::t2UBFX:
+ case ARM::t2UMAAL:
+ case ARM::t2UMLAL:
+ case ARM::t2UMULL:
+ case ARM::t2UXTABrr_rot:
+ case ARM::t2UXTAHrr_rot:
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ switch (MI->getOpcode()) {
+ case ARM::MLS:
+ case ARM::SBFX:
+ case ARM::SMLABB:
+ case ARM::SMLABT:
+ case ARM::SMLATB:
+ case ARM::SMLATT:
+ case ARM::SMLAWB:
+ case ARM::SMLAWT:
+ case ARM::SMMLA:
+ case ARM::SMMLS:
+ case ARM::UBFX:
+ case ARM::UMAAL:
+ case ARM::VEXTd16:
+ case ARM::VEXTd32:
+ case ARM::VEXTd8:
+ case ARM::VEXTdf:
+ case ARM::VEXTq16:
+ case ARM::VEXTq32:
+ case ARM::VEXTq8:
+ case ARM::VEXTqf:
+ case ARM::t2MLA:
+ case ARM::t2MLS:
+ case ARM::t2SBFX:
+ case ARM::t2SMLABB:
+ case ARM::t2SMLABT:
+ case ARM::t2SMLAL:
+ case ARM::t2SMLATB:
+ case ARM::t2SMLATT:
+ case ARM::t2SMLAWB:
+ case ARM::t2SMLAWT:
+ case ARM::t2SMMLA:
+ case ARM::t2SMMLS:
+ case ARM::t2SMULL:
+ case ARM::t2UBFX:
+ case ARM::t2UMAAL:
+ case ARM::t2UMLAL:
+ case ARM::t2UMULL: O << ", "; break;
+ case ARM::PKHBT:
+ case ARM::t2PKHBT: O << ", LSL "; break;
+ case ARM::PKHTB:
+ case ARM::t2PKHTB: O << ", ASR "; break;
+ case ARM::SXTABrr_rot:
+ case ARM::SXTAHrr_rot:
+ case ARM::UXTABrr_rot:
+ case ARM::UXTAHrr_rot:
+ case ARM::t2SXTABrr_rot:
+ case ARM::t2SXTAHrr_rot:
+ case ARM::t2UXTABrr_rot:
+ case ARM::t2UXTAHrr_rot: O << ", ror "; break;
+ }
+ printOperand(MI, 3);
+ return;
+ break;
+ case ARM::MOVi32imm:
+ case ARM::t2MOVi32imm:
+ O << ", ";
+ printOperand(MI, 1, "lo16");
+ O << "\n\tmovt";
+ printPredicateOperand(MI, 2);
+ O << "\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1, "hi16");
+ return;
+ break;
+ case ARM::MOVsra_flag:
+ case ARM::MOVsrl_flag:
+ O << ", ";
+ printOperand(MI, 1);
+ switch (MI->getOpcode()) {
+ case ARM::MOVsra_flag: O << ", asr #1"; break;
+ case ARM::MOVsrl_flag: O << ", lsr #1"; break;
+ }
+ return;
+ break;
+ case ARM::STRB_PRE:
+ case ARM::STRH_PRE:
+ case ARM::STR_PRE:
+ case ARM::t2STRB_PRE:
+ case ARM::t2STRH_PRE:
+ case ARM::t2STR_PRE:
+ O << ", [";
+ printOperand(MI, 2);
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case ARM::STRB_PRE:
+ case ARM::STR_PRE: printAddrMode2OffsetOperand(MI, 3); break;
+ case ARM::STRH_PRE: printAddrMode3OffsetOperand(MI, 3); break;
+ case ARM::t2STRB_PRE:
+ case ARM::t2STRH_PRE:
+ case ARM::t2STR_PRE: printT2AddrModeImm8OffsetOperand(MI, 3); break;
+ }
+ O << "]!";
+ return;
+ break;
+ case ARM::STREXD:
+ case ARM::t2STREXD:
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ O << ", [";
+ printOperand(MI, 3);
+ O << ']';
+ return;
+ break;
+ case ARM::SXTBr_rot:
+ case ARM::SXTHr_rot:
+ case ARM::UXTB16r_rot:
+ case ARM::UXTBr_rot:
+ case ARM::UXTHr_rot:
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ror ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case ARM::VABDfd:
+ case ARM::VABDfq:
+ case ARM::VACGEd:
+ case ARM::VACGEq:
+ case ARM::VACGTd:
+ case ARM::VACGTq:
+ case ARM::VADDD:
+ case ARM::VADDS:
+ case ARM::VADDfd:
+ case ARM::VADDfd_sfp:
+ case ARM::VADDfq:
+ case ARM::VCEQfd:
+ case ARM::VCEQfq:
+ case ARM::VCGEfd:
+ case ARM::VCGEfq:
+ case ARM::VCGTfd:
+ case ARM::VCGTfq:
+ case ARM::VDIVD:
+ case ARM::VDIVS:
+ case ARM::VMAXfd:
+ case ARM::VMAXfq:
+ case ARM::VMINfd:
+ case ARM::VMINfq:
+ case ARM::VMULD:
+ case ARM::VMULS:
+ case ARM::VMULfd:
+ case ARM::VMULfd_sfp:
+ case ARM::VMULfq:
+ case ARM::VNMULD:
+ case ARM::VNMULS:
+ case ARM::VPADDf:
+ case ARM::VPMAXf:
+ case ARM::VPMINf:
+ case ARM::VRECPSfd:
+ case ARM::VRECPSfq:
+ case ARM::VRSQRTSfd:
+ case ARM::VRSQRTSfq:
+ case ARM::VSUBD:
+ case ARM::VSUBS:
+ case ARM::VSUBfd:
+ case ARM::VSUBfd_sfp:
+ case ARM::VSUBfq:
+ case ARM::t2ADCrr:
+ case ARM::t2ADCrs:
+ case ARM::t2ADDSri:
+ case ARM::t2ADDSrr:
+ case ARM::t2ADDSrs:
+ case ARM::t2ADDrSPi:
+ case ARM::t2ADDrSPs:
+ case ARM::t2ADDri:
+ case ARM::t2ADDrr:
+ case ARM::t2ADDrs:
+ case ARM::t2ANDrr:
+ case ARM::t2ANDrs:
+ case ARM::t2ASRri:
+ case ARM::t2ASRrr:
+ case ARM::t2BICrr:
+ case ARM::t2BICrs:
+ case ARM::t2EORrr:
+ case ARM::t2EORrs:
+ case ARM::t2LSLri:
+ case ARM::t2LSLrr:
+ case ARM::t2LSRri:
+ case ARM::t2LSRrr:
+ case ARM::t2ORRrr:
+ case ARM::t2ORRrs:
+ case ARM::t2RORri:
+ case ARM::t2RORrr:
+ case ARM::t2RSBri:
+ case ARM::t2SBCrr:
+ case ARM::t2SBCrs:
+ case ARM::t2SUBSri:
+ case ARM::t2SUBSrr:
+ case ARM::t2SUBSrs:
+ case ARM::t2SUBrSPi:
+ case ARM::t2SUBri:
+ case ARM::t2SUBrr:
+ case ARM::t2SUBrs:
+ printOperand(MI, 1);
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case ARM::VABDfd:
+ case ARM::VABDfq:
+ case ARM::VACGEd:
+ case ARM::VACGEq:
+ case ARM::VACGTd:
+ case ARM::VACGTq:
+ case ARM::VADDD:
+ case ARM::VADDS:
+ case ARM::VADDfd:
+ case ARM::VADDfd_sfp:
+ case ARM::VADDfq:
+ case ARM::VCEQfd:
+ case ARM::VCEQfq:
+ case ARM::VCGEfd:
+ case ARM::VCGEfq:
+ case ARM::VCGTfd:
+ case ARM::VCGTfq:
+ case ARM::VDIVD:
+ case ARM::VDIVS:
+ case ARM::VMAXfd:
+ case ARM::VMAXfq:
+ case ARM::VMINfd:
+ case ARM::VMINfq:
+ case ARM::VMULD:
+ case ARM::VMULS:
+ case ARM::VMULfd:
+ case ARM::VMULfd_sfp:
+ case ARM::VMULfq:
+ case ARM::VNMULD:
+ case ARM::VNMULS:
+ case ARM::VPADDf:
+ case ARM::VPMAXf:
+ case ARM::VPMINf:
+ case ARM::VRECPSfd:
+ case ARM::VRECPSfq:
+ case ARM::VRSQRTSfd:
+ case ARM::VRSQRTSfq:
+ case ARM::VSUBD:
+ case ARM::VSUBS:
+ case ARM::VSUBfd:
+ case ARM::VSUBfd_sfp:
+ case ARM::VSUBfq:
+ case ARM::t2ADCrr:
+ case ARM::t2ADDSri:
+ case ARM::t2ADDSrr:
+ case ARM::t2ADDrSPi:
+ case ARM::t2ADDri:
+ case ARM::t2ADDrr:
+ case ARM::t2ANDrr:
+ case ARM::t2ASRri:
+ case ARM::t2ASRrr:
+ case ARM::t2BICrr:
+ case ARM::t2EORrr:
+ case ARM::t2LSLri:
+ case ARM::t2LSLrr:
+ case ARM::t2LSRri:
+ case ARM::t2LSRrr:
+ case ARM::t2ORRrr:
+ case ARM::t2RORri:
+ case ARM::t2RORrr:
+ case ARM::t2RSBri:
+ case ARM::t2SBCrr:
+ case ARM::t2SUBSri:
+ case ARM::t2SUBSrr:
+ case ARM::t2SUBrSPi:
+ case ARM::t2SUBri:
+ case ARM::t2SUBrr: printOperand(MI, 2); break;
+ case ARM::t2ADCrs:
+ case ARM::t2ADDSrs:
+ case ARM::t2ADDrSPs:
+ case ARM::t2ADDrs:
+ case ARM::t2ANDrs:
+ case ARM::t2BICrs:
+ case ARM::t2EORrs:
+ case ARM::t2ORRrs:
+ case ARM::t2SBCrs:
+ case ARM::t2SUBSrs:
+ case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
+ }
+ return;
+ break;
+ case ARM::VDUPLN16d:
+ case ARM::VDUPLN16q:
+ case ARM::VDUPLN32d:
+ case ARM::VDUPLN32q:
+ case ARM::VDUPLN8d:
+ case ARM::VDUPLN8q:
+ case ARM::VDUPLNfd:
+ case ARM::VDUPLNfq:
+ case ARM::VGETLNi32:
+ O << ", ";
+ printOperand(MI, 1);
+ O << '[';
+ printNoHashImmediate(MI, 2);
+ O << ']';
+ return;
+ break;
+ case ARM::VGETLNs16:
+ case ARM::VGETLNs8:
+ case ARM::VGETLNu16:
+ case ARM::VGETLNu8:
+ O << '[';
+ printNoHashImmediate(MI, 2);
+ O << ']';
+ return;
+ break;
+ case ARM::VLD1d16:
+ case ARM::VLD1d32:
+ case ARM::VLD1d64:
+ case ARM::VLD1d8:
+ case ARM::VLD1df:
+ case ARM::VST1d16:
+ case ARM::VST1d32:
+ case ARM::VST1d64:
+ case ARM::VST1d8:
+ case ARM::VST1df:
+ case ARM::VST3q16a:
+ case ARM::VST3q16b:
+ case ARM::VST3q32a:
+ case ARM::VST3q32b:
+ case ARM::VST3q8a:
+ case ARM::VST3q8b:
+ O << "}, ";
+ switch (MI->getOpcode()) {
+ case ARM::VLD1d16:
+ case ARM::VLD1d32:
+ case ARM::VLD1d64:
+ case ARM::VLD1d8:
+ case ARM::VLD1df:
+ case ARM::VST3q16a:
+ case ARM::VST3q16b:
+ case ARM::VST3q32a:
+ case ARM::VST3q32b:
+ case ARM::VST3q8a:
+ case ARM::VST3q8b: printAddrMode6Operand(MI, 1); break;
+ case ARM::VST1d16:
+ case ARM::VST1d32:
+ case ARM::VST1d64:
+ case ARM::VST1d8:
+ case ARM::VST1df: printAddrMode6Operand(MI, 0); break;
+ }
+ return;
+ break;
+ case ARM::VLD2LNd16:
+ case ARM::VLD2LNd32:
+ case ARM::VLD2LNd8:
+ case ARM::VLD2LNq16a:
+ case ARM::VLD2LNq16b:
+ case ARM::VLD2LNq32a:
+ case ARM::VLD2LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "],";
+ printOperand(MI, 1);
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 2);
+ return;
+ break;
+ case ARM::VLD2d16:
+ case ARM::VLD2d32:
+ case ARM::VLD2d64:
+ case ARM::VLD2d8:
+ O << ',';
+ printOperand(MI, 1);
+ O << "}, ";
+ printAddrMode6Operand(MI, 2);
+ return;
+ break;
+ case ARM::VLD2q16:
+ case ARM::VLD2q32:
+ case ARM::VLD2q8:
+ case ARM::VLD4d16:
+ case ARM::VLD4d32:
+ case ARM::VLD4d64:
+ case ARM::VLD4d8:
+ case ARM::VLD4q16a:
+ case ARM::VLD4q16b:
+ case ARM::VLD4q32a:
+ case ARM::VLD4q32b:
+ case ARM::VLD4q8a:
+ case ARM::VLD4q8b:
+ O << ',';
+ printOperand(MI, 1);
+ O << ',';
+ printOperand(MI, 2);
+ O << ',';
+ printOperand(MI, 3);
+ O << "}, ";
+ switch (MI->getOpcode()) {
+ case ARM::VLD2q16:
+ case ARM::VLD2q32:
+ case ARM::VLD2q8:
+ case ARM::VLD4d16:
+ case ARM::VLD4d32:
+ case ARM::VLD4d64:
+ case ARM::VLD4d8: printAddrMode6Operand(MI, 4); break;
+ case ARM::VLD4q16a:
+ case ARM::VLD4q16b:
+ case ARM::VLD4q32a:
+ case ARM::VLD4q32b:
+ case ARM::VLD4q8a:
+ case ARM::VLD4q8b: printAddrMode6Operand(MI, 5); break;
+ }
+ return;
+ break;
+ case ARM::VLD3LNd16:
+ case ARM::VLD3LNd32:
+ case ARM::VLD3LNd8:
+ case ARM::VLD3LNq16a:
+ case ARM::VLD3LNq16b:
+ case ARM::VLD3LNq32a:
+ case ARM::VLD3LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 10);
+ O << "],";
+ printOperand(MI, 1);
+ O << '[';
+ printNoHashImmediate(MI, 10);
+ O << "],";
+ printOperand(MI, 2);
+ O << '[';
+ printNoHashImmediate(MI, 10);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 3);
+ return;
+ break;
+ case ARM::VLD3d16:
+ case ARM::VLD3d32:
+ case ARM::VLD3d64:
+ case ARM::VLD3d8:
+ case ARM::VLD3q16a:
+ case ARM::VLD3q16b:
+ case ARM::VLD3q32a:
+ case ARM::VLD3q32b:
+ case ARM::VLD3q8a:
+ case ARM::VLD3q8b:
+ O << ',';
+ printOperand(MI, 1);
+ O << ',';
+ printOperand(MI, 2);
+ O << "}, ";
+ switch (MI->getOpcode()) {
+ case ARM::VLD3d16:
+ case ARM::VLD3d32:
+ case ARM::VLD3d64:
+ case ARM::VLD3d8: printAddrMode6Operand(MI, 3); break;
+ case ARM::VLD3q16a:
+ case ARM::VLD3q16b:
+ case ARM::VLD3q32a:
+ case ARM::VLD3q32b:
+ case ARM::VLD3q8a:
+ case ARM::VLD3q8b: printAddrMode6Operand(MI, 4); break;
+ }
+ return;
+ break;
+ case ARM::VLD4LNd16:
+ case ARM::VLD4LNd32:
+ case ARM::VLD4LNd8:
+ case ARM::VLD4LNq16a:
+ case ARM::VLD4LNq16b:
+ case ARM::VLD4LNq32a:
+ case ARM::VLD4LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 12);
+ O << "],";
+ printOperand(MI, 1);
+ O << '[';
+ printNoHashImmediate(MI, 12);
+ O << "],";
+ printOperand(MI, 2);
+ O << '[';
+ printNoHashImmediate(MI, 12);
+ O << "],";
+ printOperand(MI, 3);
+ O << '[';
+ printNoHashImmediate(MI, 12);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 4);
+ return;
+ break;
+ case ARM::VMLAD:
+ case ARM::VMLAS:
+ case ARM::VMLAfd:
+ case ARM::VMLAfq:
+ case ARM::VMLSD:
+ case ARM::VMLSS:
+ case ARM::VMLSfd:
+ case ARM::VMLSfq:
+ case ARM::VNMLAD:
+ case ARM::VNMLAS:
+ case ARM::VNMLSD:
+ case ARM::VNMLSS:
+ case ARM::t2MOVCCasr:
+ case ARM::t2MOVCClsl:
+ case ARM::t2MOVCClsr:
+ case ARM::t2MOVCCror:
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 3);
+ return;
+ break;
+ case ARM::VMLALslsv2i32:
+ case ARM::VMLALslsv4i16:
+ case ARM::VMLALsluv2i32:
+ case ARM::VMLALsluv4i16:
+ case ARM::VMLAslv2i32:
+ case ARM::VMLAslv4i16:
+ case ARM::VMLAslv4i32:
+ case ARM::VMLAslv8i16:
+ case ARM::VMLSLslsv2i32:
+ case ARM::VMLSLslsv4i16:
+ case ARM::VMLSLsluv2i32:
+ case ARM::VMLSLsluv4i16:
+ case ARM::VMLSslv2i32:
+ case ARM::VMLSslv4i16:
+ case ARM::VMLSslv4i32:
+ case ARM::VMLSslv8i16:
+ case ARM::VQDMLALslv2i32:
+ case ARM::VQDMLALslv4i16:
+ case ARM::VQDMLSLslv2i32:
+ case ARM::VQDMLSLslv4i16:
+ O << ", ";
+ printOperand(MI, 3);
+ O << '[';
+ printNoHashImmediate(MI, 4);
+ O << ']';
+ return;
+ break;
+ case ARM::VMLAslfd:
+ case ARM::VMLAslfq:
+ case ARM::VMLSslfd:
+ case ARM::VMLSslfq:
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 3);
+ O << '[';
+ printNoHashImmediate(MI, 4);
+ O << ']';
+ return;
+ break;
+ case ARM::VMULLslsv2i32:
+ case ARM::VMULLslsv4i16:
+ case ARM::VMULLsluv2i32:
+ case ARM::VMULLsluv4i16:
+ case ARM::VMULslv2i32:
+ case ARM::VMULslv4i16:
+ case ARM::VMULslv4i32:
+ case ARM::VMULslv8i16:
+ case ARM::VQDMULHslv2i32:
+ case ARM::VQDMULHslv4i16:
+ case ARM::VQDMULHslv4i32:
+ case ARM::VQDMULHslv8i16:
+ case ARM::VQDMULLslv2i32:
+ case ARM::VQDMULLslv4i16:
+ case ARM::VQRDMULHslv2i32:
+ case ARM::VQRDMULHslv4i16:
+ case ARM::VQRDMULHslv4i32:
+ case ARM::VQRDMULHslv8i16:
+ O << ", ";
+ printOperand(MI, 2);
+ O << '[';
+ printNoHashImmediate(MI, 3);
+ O << ']';
+ return;
+ break;
+ case ARM::VMULslfd:
+ case ARM::VMULslfq:
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ O << '[';
+ printNoHashImmediate(MI, 3);
+ O << ']';
+ return;
+ break;
+ case ARM::VSETLNi16:
+ case ARM::VSETLNi32:
+ case ARM::VSETLNi8:
+ O << '[';
+ printNoHashImmediate(MI, 3);
+ O << "], ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case ARM::VST2LNd16:
+ case ARM::VST2LNd32:
+ case ARM::VST2LNd8:
+ case ARM::VST2LNq16a:
+ case ARM::VST2LNq16b:
+ case ARM::VST2LNq32a:
+ case ARM::VST2LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 6);
+ O << "],";
+ printOperand(MI, 5);
+ O << '[';
+ printNoHashImmediate(MI, 6);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST2d16:
+ case ARM::VST2d32:
+ case ARM::VST2d64:
+ case ARM::VST2d8:
+ O << ',';
+ printOperand(MI, 5);
+ O << "}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST2q16:
+ case ARM::VST2q32:
+ case ARM::VST2q8:
+ case ARM::VST4d16:
+ case ARM::VST4d32:
+ case ARM::VST4d64:
+ case ARM::VST4d8:
+ O << ',';
+ printOperand(MI, 5);
+ O << ',';
+ printOperand(MI, 6);
+ O << ',';
+ printOperand(MI, 7);
+ O << "}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST3LNd16:
+ case ARM::VST3LNd32:
+ case ARM::VST3LNd8:
+ case ARM::VST3LNq16a:
+ case ARM::VST3LNq16b:
+ case ARM::VST3LNq32a:
+ case ARM::VST3LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 7);
+ O << "],";
+ printOperand(MI, 5);
+ O << '[';
+ printNoHashImmediate(MI, 7);
+ O << "],";
+ printOperand(MI, 6);
+ O << '[';
+ printNoHashImmediate(MI, 7);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST3d16:
+ case ARM::VST3d32:
+ case ARM::VST3d64:
+ case ARM::VST3d8:
+ O << ',';
+ printOperand(MI, 5);
+ O << ',';
+ printOperand(MI, 6);
+ O << "}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST4LNd16:
+ case ARM::VST4LNd32:
+ case ARM::VST4LNd8:
+ case ARM::VST4LNq16a:
+ case ARM::VST4LNq16b:
+ case ARM::VST4LNq32a:
+ case ARM::VST4LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "],";
+ printOperand(MI, 5);
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "],";
+ printOperand(MI, 6);
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "],";
+ printOperand(MI, 7);
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST4q16a:
+ case ARM::VST4q16b:
+ case ARM::VST4q32a:
+ case ARM::VST4q32b:
+ case ARM::VST4q8a:
+ case ARM::VST4q8b:
+ O << ',';
+ printOperand(MI, 8);
+ O << "}, ";
+ printAddrMode6Operand(MI, 1);
+ return;
+ break;
+ case ARM::VTBL1:
+ O << ", {";
+ printOperand(MI, 1);
+ O << "}, ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case ARM::VTBL2:
+ O << ", {";
+ printOperand(MI, 1);
+ O << ',';
+ printOperand(MI, 2);
+ O << "}, ";
+ printOperand(MI, 3);
+ return;
+ break;
+ case ARM::VTBL3:
+ O << ", {";
+ printOperand(MI, 1);
+ O << ',';
+ printOperand(MI, 2);
+ O << ',';
+ printOperand(MI, 3);
+ O << "}, ";
+ printOperand(MI, 4);
+ return;
+ break;
+ case ARM::VTBL4:
+ O << ", {";
+ printOperand(MI, 1);
+ O << ',';
+ printOperand(MI, 2);
+ O << ',';
+ printOperand(MI, 3);
+ O << ',';
+ printOperand(MI, 4);
+ O << "}, ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case ARM::VTBX1:
+ O << ", {";
+ printOperand(MI, 2);
+ O << "}, ";
+ printOperand(MI, 3);
+ return;
+ break;
+ case ARM::VTBX2:
+ O << ", {";
+ printOperand(MI, 2);
+ O << ',';
+ printOperand(MI, 3);
+ O << "}, ";
+ printOperand(MI, 4);
+ return;
+ break;
+ case ARM::VTBX3:
+ O << ", {";
+ printOperand(MI, 2);
+ O << ',';
+ printOperand(MI, 3);
+ O << ',';
+ printOperand(MI, 4);
+ O << "}, ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case ARM::VTBX4:
+ O << ", {";
+ printOperand(MI, 2);
+ O << ',';
+ printOperand(MI, 3);
+ O << ',';
+ printOperand(MI, 4);
+ O << ',';
+ printOperand(MI, 5);
+ O << "}, ";
+ printOperand(MI, 6);
+ return;
+ break;
+ case ARM::t2LDRpci_pic:
+ case ARM::tLDRpci_pic:
+ O << "\n";
+ printPCLabel(MI, 2);
+ O << ":\n\tadd\t";
+ printOperand(MI, 0);
+ O << ", pc";
+ return;
+ break;
+ case ARM::t2LEApcrelJT:
+ O << '_';
+ printNoHashImmediate(MI, 2);
+ return;
+ break;
+ case ARM::t2SXTBr_rot:
+ case ARM::t2SXTHr_rot:
+ case ARM::t2UXTB16r_rot:
+ case ARM::t2UXTBr_rot:
+ case ARM::t2UXTHr_rot:
+ printOperand(MI, 1);
+ O << ", ror ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case ARM::tLEApcrel:
+ O << ", #";
+ printOperand(MI, 1);
+ return;
+ break;
+ case ARM::tLEApcrelJT:
+ O << ", #";
+ printOperand(MI, 1);
+ O << '_';
+ printNoHashImmediate(MI, 2);
+ return;
+ break;
+ }
+ return;
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
+ assert(RegNo && RegNo < 100 && "Invalid register number!");
+
+ static const unsigned RegAsmOffset[] = {
+ 0, 5, 8, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,
+ 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 97, 101, 105,
+ 108, 111, 114, 117, 120, 123, 129, 132, 135, 138, 141, 145, 149, 153,
+ 157, 161, 165, 168, 171, 174, 177, 180, 183, 186, 189, 192, 195, 199,
+ 203, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237, 241, 245,
+ 249, 253, 257, 261, 265, 269, 273, 277, 280, 284, 288, 292, 296, 300,
+ 304, 308, 312, 316, 320, 323, 327, 331, 334, 337, 340, 343, 346, 349,
+ 358, 0
+ };
+
+ const char *AsmStrs =
+ "cpsr\000d0\000d1\000d10\000d11\000d12\000d13\000d14\000d15\000d16\000d1"
+ "7\000d18\000d19\000d2\000d20\000d21\000d22\000d23\000d24\000d25\000d26\000"
+ "d27\000d28\000d29\000d3\000d30\000d31\000d4\000d5\000d6\000d7\000d8\000"
+ "d9\000fpscr\000lr\000pc\000q0\000q1\000q10\000q11\000q12\000q13\000q14\000"
+ "q15\000q2\000q3\000q4\000q5\000q6\000q7\000q8\000q9\000r0\000r1\000r10\000"
+ "r11\000r12\000r2\000r3\000r4\000r5\000r6\000r7\000r8\000r9\000s0\000s1\000"
+ "s10\000s11\000s12\000s13\000s14\000s15\000s16\000s17\000s18\000s19\000s"
+ "2\000s20\000s21\000s22\000s23\000s24\000s25\000s26\000s27\000s28\000s29"
+ "\000s3\000s30\000s31\000s4\000s5\000s6\000s7\000s8\000s9\000sINVALID\000"
+ "sp\000";
+ return AsmStrs+RegAsmOffset[RegNo-1];
+}
diff --git a/libclamav/c++/ARMGenCallingConv.inc b/libclamav/c++/ARMGenCallingConv.inc
new file mode 100644
index 0000000..0845027
--- /dev/null
+++ b/libclamav/c++/ARMGenCallingConv.inc
@@ -0,0 +1,470 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Calling Convention Implementation Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+static bool CC_ARM_AAPCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_ARM_AAPCS_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_ARM_AAPCS_VFP(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_ARM_APCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_ARM_AAPCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_ARM_APCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+
+
+static bool CC_ARM_AAPCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v8i8 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v4f32) {
+ LocVT = MVT::v2f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::f64 ||
+ LocVT == MVT::v2f64) {
+ if (CC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (LocVT == MVT::f32) {
+ LocVT = MVT::i32;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_ARM_AAPCS_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::i32) {
+ if (ArgFlags.getOrigAlign() == 8) {
+ static const unsigned RegList1[] = {
+ ARM::R0, ARM::R2
+ };
+ static const unsigned RegList2[] = {
+ ARM::R0, ARM::R1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ if (State.getNextStackOffset() == 0 &&ArgFlags.getOrigAlign() != 8) {
+ static const unsigned RegList3[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ if (ArgFlags.getOrigAlign() == 8) {
+ unsigned Offset4 = State.AllocateStack(4, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32 ||
+ LocVT == MVT::f32) {
+ unsigned Offset5 = State.AllocateStack(4, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f64) {
+ unsigned Offset6 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v2f64) {
+ unsigned Offset7 = State.AllocateStack(16, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_ARM_AAPCS_VFP(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v8i8 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v4f32) {
+ LocVT = MVT::v2f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2f64) {
+ static const unsigned RegList1[] = {
+ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const unsigned RegList2[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ static const unsigned RegList3[] = {
+ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 16)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!CC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_ARM_APCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v8i8 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v4f32) {
+ LocVT = MVT::v2f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::f64 ||
+ LocVT == MVT::v2f64) {
+ if (CC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (LocVT == MVT::f32) {
+ LocVT = MVT::i32;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ unsigned Offset2 = State.AllocateStack(4, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f64) {
+ unsigned Offset3 = State.AllocateStack(8, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v2f64) {
+ unsigned Offset4 = State.AllocateStack(16, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_ARM_AAPCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v8i8 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v4f32) {
+ LocVT = MVT::v2f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::f64 ||
+ LocVT == MVT::v2f64) {
+ if (RetCC_ARM_AAPCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (LocVT == MVT::f32) {
+ LocVT = MVT::i32;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_ARM_AAPCS_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList2[] = {
+ ARM::R0, ARM::R2
+ };
+ static const unsigned RegList3[] = {
+ ARM::R1, ARM::R3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, RegList3, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v8i8 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v4f32) {
+ LocVT = MVT::v2f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2f64) {
+ static const unsigned RegList1[] = {
+ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const unsigned RegList2[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ static const unsigned RegList3[] = {
+ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 16)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!RetCC_ARM_AAPCS_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_ARM_APCS(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::f32) {
+ LocVT = MVT::i32;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v8i8 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v4f32) {
+ LocVT = MVT::v2f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::f64 ||
+ LocVT == MVT::v2f64) {
+ if (RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList2[] = {
+ ARM::R0, ARM::R2
+ };
+ static const unsigned RegList3[] = {
+ ARM::R1, ARM::R3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, RegList3, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
diff --git a/libclamav/c++/ARMGenCodeEmitter.inc b/libclamav/c++/ARMGenCodeEmitter.inc
new file mode 100644
index 0000000..121e782
--- /dev/null
+++ b/libclamav/c++/ARMGenCodeEmitter.inc
@@ -0,0 +1,3053 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Machine Code Emitter
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
+ static const unsigned InstBits[] = {
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 45088768U, // ADCSSri
+ 11534336U, // ADCSSrr
+ 11534336U, // ADCSSrs
+ 44040192U, // ADCri
+ 10485760U, // ADCrr
+ 10485760U, // ADCrs
+ 42991616U, // ADDSri
+ 9437184U, // ADDSrr
+ 9437184U, // ADDSrs
+ 41943040U, // ADDri
+ 8388608U, // ADDrr
+ 8388608U, // ADDrs
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 33554432U, // ANDri
+ 0U, // ANDrr
+ 0U, // ANDrs
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I8
+ 167772160U, // B
+ 130023455U, // BFC
+ 62914560U, // BICri
+ 29360128U, // BICrr
+ 29360128U, // BICrs
+ 3942645760U, // BL
+ 19922736U, // BLX
+ 19922736U, // BLXr9
+ 184549376U, // BL_pred
+ 3942645760U, // BLr9
+ 184549376U, // BLr9_pred
+ 3778019088U, // BRIND
+ 8450048U, // BR_JTadd
+ 118550528U, // BR_JTm
+ 27324416U, // BR_JTr
+ 19922704U, // BX
+ 19922718U, // BX_RET
+ 19922704U, // BXr9
+ 167772160U, // Bcc
+ 24055568U, // CLZ
+ 57671680U, // CMNri
+ 24117248U, // CMNrr
+ 24117248U, // CMNrs
+ 57671680U, // CMNzri
+ 24117248U, // CMNzrr
+ 24117248U, // CMNzrs
+ 55574528U, // CMPri
+ 22020096U, // CMPrr
+ 22020096U, // CMPrs
+ 55574528U, // CMPzri
+ 22020096U, // CMPzrr
+ 22020096U, // CMPzrs
+ 0U, // CONSTPOOL_ENTRY
+ 35651584U, // EORri
+ 2097152U, // EORrr
+ 2097152U, // EORrs
+ 246418176U, // FCONSTD
+ 246417920U, // FCONSTS
+ 250739216U, // FMSTAT
+ 0U, // Int_MemBarrierV6
+ 4118802527U, // Int_MemBarrierV7
+ 0U, // Int_SyncBarrierV6
+ 4118802511U, // Int_SyncBarrierV7
+ 0U, // Int_eh_sjlj_setjmp
+ 135266304U, // LDM
+ 135266304U, // LDM_RET
+ 84934656U, // LDR
+ 89128960U, // LDRB
+ 72351744U, // LDRB_POST
+ 91226112U, // LDRB_PRE
+ 16777424U, // LDRD
+ 26218399U, // LDREX
+ 30412703U, // LDREXB
+ 28315551U, // LDREXD
+ 32509855U, // LDREXH
+ 17825968U, // LDRH
+ 3145904U, // LDRH_POST
+ 19923120U, // LDRH_PRE
+ 17826000U, // LDRSB
+ 3145936U, // LDRSB_POST
+ 19923152U, // LDRSB_PRE
+ 17826032U, // LDRSH
+ 3145968U, // LDRSH_POST
+ 19923184U, // LDRSH_PRE
+ 68157440U, // LDR_POST
+ 87031808U, // LDR_PRE
+ 84934656U, // LDRcp
+ 0U, // LEApcrel
+ 33554432U, // LEApcrelJT
+ 2097296U, // MLA
+ 6291600U, // MLS
+ 60817408U, // MOVCCi
+ 27262976U, // MOVCCr
+ 27262976U, // MOVCCs
+ 54525952U, // MOVTi16
+ 60817408U, // MOVi
+ 50331648U, // MOVi16
+ 0U, // MOVi2pieces
+ 0U, // MOVi32imm
+ 27262976U, // MOVr
+ 27262976U, // MOVrx
+ 27262976U, // MOVs
+ 27262976U, // MOVsra_flag
+ 27262976U, // MOVsrl_flag
+ 144U, // MUL
+ 65011712U, // MVNi
+ 31457280U, // MVNr
+ 31457280U, // MVNs
+ 58720256U, // ORRri
+ 25165824U, // ORRrr
+ 25165824U, // ORRrs
+ 8388608U, // PICADD
+ 84934656U, // PICLDR
+ 89128960U, // PICLDRB
+ 17825968U, // PICLDRH
+ 17826000U, // PICLDRSB
+ 17826032U, // PICLDRSH
+ 83886080U, // PICSTR
+ 88080384U, // PICSTRB
+ 16777392U, // PICSTRH
+ 109051920U, // PKHBT
+ 109051984U, // PKHTB
+ 113184560U, // REV
+ 113184688U, // REV16
+ 117378992U, // REVSH
+ 40894464U, // RSBSri
+ 7340032U, // RSBSrs
+ 39845888U, // RSBri
+ 6291456U, // RSBrs
+ 49283072U, // RSCSri
+ 15728640U, // RSCSrs
+ 48234496U, // RSCri
+ 14680064U, // RSCrs
+ 47185920U, // SBCSSri
+ 13631488U, // SBCSSrr
+ 13631488U, // SBCSSrs
+ 46137344U, // SBCri
+ 12582912U, // SBCrr
+ 12582912U, // SBCrs
+ 127926352U, // SBFX
+ 16777344U, // SMLABB
+ 16777408U, // SMLABT
+ 14680208U, // SMLAL
+ 16777376U, // SMLATB
+ 16777440U, // SMLATT
+ 18874496U, // SMLAWB
+ 18874560U, // SMLAWT
+ 122683408U, // SMMLA
+ 122683600U, // SMMLS
+ 122744848U, // SMMUL
+ 23068800U, // SMULBB
+ 23068864U, // SMULBT
+ 12583056U, // SMULL
+ 23068832U, // SMULTB
+ 23068896U, // SMULTT
+ 18874528U, // SMULWB
+ 18874592U, // SMULWT
+ 134217728U, // STM
+ 83886080U, // STR
+ 88080384U, // STRB
+ 71303168U, // STRB_POST
+ 90177536U, // STRB_PRE
+ 16777456U, // STRD
+ 25169808U, // STREX
+ 29364112U, // STREXB
+ 27266960U, // STREXD
+ 31461264U, // STREXH
+ 16777392U, // STRH
+ 2097328U, // STRH_POST
+ 18874544U, // STRH_PRE
+ 67108864U, // STR_POST
+ 85983232U, // STR_PRE
+ 38797312U, // SUBSri
+ 5242880U, // SUBSrr
+ 5242880U, // SUBSrs
+ 37748736U, // SUBri
+ 4194304U, // SUBrr
+ 4194304U, // SUBrs
+ 111149168U, // SXTABrr
+ 111149168U, // SXTABrr_rot
+ 112197744U, // SXTAHrr
+ 112197744U, // SXTAHrr_rot
+ 112132208U, // SXTBr
+ 112132208U, // SXTBr_rot
+ 113180784U, // SXTHr
+ 113180784U, // SXTHr_rot
+ 53477376U, // TEQri
+ 19922944U, // TEQrr
+ 19922944U, // TEQrs
+ 184549376U, // TPsoft
+ 51380224U, // TSTri
+ 17825792U, // TSTrr
+ 17825792U, // TSTrs
+ 132120656U, // UBFX
+ 4194448U, // UMAAL
+ 10485904U, // UMLAL
+ 8388752U, // UMULL
+ 115343472U, // UXTABrr
+ 115343472U, // UXTABrr_rot
+ 116392048U, // UXTAHrr
+ 116392048U, // UXTAHrr_rot
+ 114229360U, // UXTB16r
+ 114229360U, // UXTB16r_rot
+ 116326512U, // UXTBr
+ 116326512U, // UXTBr_rot
+ 117375088U, // UXTHr
+ 117375088U, // UXTHr_rot
+ 4070573312U, // VABALsv2i64
+ 4069524736U, // VABALsv4i32
+ 4068476160U, // VABALsv8i16
+ 4087350528U, // VABALuv2i64
+ 4086301952U, // VABALuv4i32
+ 4085253376U, // VABALuv8i16
+ 4060088144U, // VABAsv16i8
+ 4062185232U, // VABAsv2i32
+ 4061136656U, // VABAsv4i16
+ 4062185296U, // VABAsv4i32
+ 4061136720U, // VABAsv8i16
+ 4060088080U, // VABAsv8i8
+ 4076865360U, // VABAuv16i8
+ 4078962448U, // VABAuv2i32
+ 4077913872U, // VABAuv4i16
+ 4078962512U, // VABAuv4i32
+ 4077913936U, // VABAuv8i16
+ 4076865296U, // VABAuv8i8
+ 4070573824U, // VABDLsv2i64
+ 4069525248U, // VABDLsv4i32
+ 4068476672U, // VABDLsv8i16
+ 4087351040U, // VABDLuv2i64
+ 4086302464U, // VABDLuv4i32
+ 4085253888U, // VABDLuv8i16
+ 4078963968U, // VABDfd
+ 4078964032U, // VABDfq
+ 4060088128U, // VABDsv16i8
+ 4062185216U, // VABDsv2i32
+ 4061136640U, // VABDsv4i16
+ 4062185280U, // VABDsv4i32
+ 4061136704U, // VABDsv8i16
+ 4060088064U, // VABDsv8i8
+ 4076865344U, // VABDuv16i8
+ 4078962432U, // VABDuv2i32
+ 4077913856U, // VABDuv4i16
+ 4078962496U, // VABDuv4i32
+ 4077913920U, // VABDuv8i16
+ 4076865280U, // VABDuv8i8
+ 246418368U, // VABSD
+ 246418112U, // VABSS
+ 4088989440U, // VABSfd
+ 4088989440U, // VABSfd_sfp
+ 4088989504U, // VABSfq
+ 4088464192U, // VABSv16i8
+ 4088988416U, // VABSv2i32
+ 4088726272U, // VABSv4i16
+ 4088988480U, // VABSv4i32
+ 4088726336U, // VABSv8i16
+ 4088464128U, // VABSv8i8
+ 4076867088U, // VACGEd
+ 4076867152U, // VACGEq
+ 4078964240U, // VACGTd
+ 4078964304U, // VACGTq
+ 238029568U, // VADDD
+ 4070573056U, // VADDHNv2i32
+ 4069524480U, // VADDHNv4i16
+ 4068475904U, // VADDHNv8i8
+ 4070572032U, // VADDLsv2i64
+ 4069523456U, // VADDLsv4i32
+ 4068474880U, // VADDLsv8i16
+ 4087349248U, // VADDLuv2i64
+ 4086300672U, // VADDLuv4i32
+ 4085252096U, // VADDLuv8i16
+ 238029312U, // VADDS
+ 4070572288U, // VADDWsv2i64
+ 4069523712U, // VADDWsv4i32
+ 4068475136U, // VADDWsv8i16
+ 4087349504U, // VADDWuv2i64
+ 4086300928U, // VADDWuv4i32
+ 4085252352U, // VADDWuv8i16
+ 4060089600U, // VADDfd
+ 4060089600U, // VADDfd_sfp
+ 4060089664U, // VADDfq
+ 4060088384U, // VADDv16i8
+ 4063234048U, // VADDv1i64
+ 4062185472U, // VADDv2i32
+ 4063234112U, // VADDv2i64
+ 4061136896U, // VADDv4i16
+ 4062185536U, // VADDv4i32
+ 4061136960U, // VADDv8i16
+ 4060088320U, // VADDv8i8
+ 4060086544U, // VANDd
+ 4060086608U, // VANDq
+ 4061135120U, // VBICd
+ 4061135184U, // VBICq
+ 4077912336U, // VBSLd
+ 4077912400U, // VBSLq
+ 4060089856U, // VCEQfd
+ 4060089920U, // VCEQfq
+ 4076865616U, // VCEQv16i8
+ 4078962704U, // VCEQv2i32
+ 4077914128U, // VCEQv4i16
+ 4078962768U, // VCEQv4i32
+ 4077914192U, // VCEQv8i16
+ 4076865552U, // VCEQv8i8
+ 4076867072U, // VCGEfd
+ 4076867136U, // VCGEfq
+ 4060087120U, // VCGEsv16i8
+ 4062184208U, // VCGEsv2i32
+ 4061135632U, // VCGEsv4i16
+ 4062184272U, // VCGEsv4i32
+ 4061135696U, // VCGEsv8i16
+ 4060087056U, // VCGEsv8i8
+ 4076864336U, // VCGEuv16i8
+ 4078961424U, // VCGEuv2i32
+ 4077912848U, // VCGEuv4i16
+ 4078961488U, // VCGEuv4i32
+ 4077912912U, // VCGEuv8i16
+ 4076864272U, // VCGEuv8i8
+ 4078964224U, // VCGTfd
+ 4078964288U, // VCGTfq
+ 4060087104U, // VCGTsv16i8
+ 4062184192U, // VCGTsv2i32
+ 4061135616U, // VCGTsv4i16
+ 4062184256U, // VCGTsv4i32
+ 4061135680U, // VCGTsv8i16
+ 4060087040U, // VCGTsv8i8
+ 4076864320U, // VCGTuv16i8
+ 4078961408U, // VCGTuv2i32
+ 4077912832U, // VCGTuv4i16
+ 4078961472U, // VCGTuv4i32
+ 4077912896U, // VCGTuv8i16
+ 4076864256U, // VCGTuv8i8
+ 4088398912U, // VCLSv16i8
+ 4088923136U, // VCLSv2i32
+ 4088660992U, // VCLSv4i16
+ 4088923200U, // VCLSv4i32
+ 4088661056U, // VCLSv8i16
+ 4088398848U, // VCLSv8i8
+ 4088399040U, // VCLZv16i8
+ 4088923264U, // VCLZv2i32
+ 4088661120U, // VCLZv4i16
+ 4088923328U, // VCLZv4i32
+ 4088661184U, // VCLZv8i16
+ 4088398976U, // VCLZv8i8
+ 246680512U, // VCMPED
+ 246680256U, // VCMPES
+ 246746048U, // VCMPEZD
+ 246745792U, // VCMPEZS
+ 4088399104U, // VCNTd
+ 4088399168U, // VCNTq
+ 246876864U, // VCVTDS
+ 246877120U, // VCVTSD
+ 4089120512U, // VCVTf2sd
+ 4089120512U, // VCVTf2sd_sfp
+ 4089120576U, // VCVTf2sq
+ 4089120640U, // VCVTf2ud
+ 4089120640U, // VCVTf2ud_sfp
+ 4089120704U, // VCVTf2uq
+ 4068478736U, // VCVTf2xsd
+ 4068478800U, // VCVTf2xsq
+ 4085255952U, // VCVTf2xud
+ 4085256016U, // VCVTf2xuq
+ 4089120256U, // VCVTs2fd
+ 4089120256U, // VCVTs2fd_sfp
+ 4089120320U, // VCVTs2fq
+ 4089120384U, // VCVTu2fd
+ 4089120384U, // VCVTu2fd_sfp
+ 4089120448U, // VCVTu2fq
+ 4068478480U, // VCVTxs2fd
+ 4068478544U, // VCVTxs2fq
+ 4085255696U, // VCVTxu2fd
+ 4085255760U, // VCVTxu2fq
+ 243272448U, // VDIVD
+ 243272192U, // VDIVS
+ 243272496U, // VDUP16d
+ 245369648U, // VDUP16q
+ 243272464U, // VDUP32d
+ 245369616U, // VDUP32q
+ 247466768U, // VDUP8d
+ 249563920U, // VDUP8q
+ 4088531968U, // VDUPLN16d
+ 4088532032U, // VDUPLN16q
+ 4088663040U, // VDUPLN32d
+ 4088663104U, // VDUPLN32q
+ 4088466432U, // VDUPLN8d
+ 4088466496U, // VDUPLN8q
+ 4088663040U, // VDUPLNfd
+ 4088663104U, // VDUPLNfq
+ 243272464U, // VDUPfd
+ 4088663040U, // VDUPfdf
+ 245369616U, // VDUPfq
+ 4088663104U, // VDUPfqf
+ 4076863760U, // VEORd
+ 4076863824U, // VEORq
+ 4071620608U, // VEXTd16
+ 4071620608U, // VEXTd32
+ 4071620608U, // VEXTd8
+ 4071620608U, // VEXTdf
+ 4071620672U, // VEXTq16
+ 4071620672U, // VEXTq32
+ 4071620672U, // VEXTq8
+ 4071620672U, // VEXTqf
+ 235932432U, // VGETLNi32
+ 235932464U, // VGETLNs16
+ 240126736U, // VGETLNs8
+ 244321072U, // VGETLNu16
+ 248515344U, // VGETLNu8
+ 4060086336U, // VHADDsv16i8
+ 4062183424U, // VHADDsv2i32
+ 4061134848U, // VHADDsv4i16
+ 4062183488U, // VHADDsv4i32
+ 4061134912U, // VHADDsv8i16
+ 4060086272U, // VHADDsv8i8
+ 4076863552U, // VHADDuv16i8
+ 4078960640U, // VHADDuv2i32
+ 4077912064U, // VHADDuv4i16
+ 4078960704U, // VHADDuv4i32
+ 4077912128U, // VHADDuv8i16
+ 4076863488U, // VHADDuv8i8
+ 4060086848U, // VHSUBsv16i8
+ 4062183936U, // VHSUBsv2i32
+ 4061135360U, // VHSUBsv4i16
+ 4062184000U, // VHSUBsv4i32
+ 4061135424U, // VHSUBsv8i16
+ 4060086784U, // VHSUBsv8i8
+ 4076864064U, // VHSUBuv16i8
+ 4078961152U, // VHSUBuv2i32
+ 4077912576U, // VHSUBuv4i16
+ 4078961216U, // VHSUBuv4i32
+ 4077912640U, // VHSUBuv8i16
+ 4076864000U, // VHSUBuv8i8
+ 4095739712U, // VLD1d16
+ 4095739776U, // VLD1d32
+ 4095739840U, // VLD1d64
+ 4095739648U, // VLD1d8
+ 4095739776U, // VLD1df
+ 4095740480U, // VLD1q16
+ 4095740544U, // VLD1q32
+ 4095740608U, // VLD1q64
+ 4095740416U, // VLD1q8
+ 4095740544U, // VLD1qf
+ 4104127744U, // VLD2LNd16
+ 4104128768U, // VLD2LNd32
+ 4104126720U, // VLD2LNd8
+ 4104127776U, // VLD2LNq16a
+ 4104127776U, // VLD2LNq16b
+ 4104128832U, // VLD2LNq32a
+ 4104128832U, // VLD2LNq32b
+ 4095739968U, // VLD2d16
+ 4095740032U, // VLD2d32
+ 4095740608U, // VLD2d64
+ 4095739904U, // VLD2d8
+ 4095738688U, // VLD2q16
+ 4095738752U, // VLD2q32
+ 4095738624U, // VLD2q8
+ 4104128000U, // VLD3LNd16
+ 4104129024U, // VLD3LNd32
+ 4104126976U, // VLD3LNd8
+ 4104128032U, // VLD3LNq16a
+ 4104128032U, // VLD3LNq16b
+ 4104129088U, // VLD3LNq32a
+ 4104129088U, // VLD3LNq32b
+ 4095738944U, // VLD3d16
+ 4095739008U, // VLD3d32
+ 4095739584U, // VLD3d64
+ 4095738880U, // VLD3d8
+ 4095739200U, // VLD3q16a
+ 4095739200U, // VLD3q16b
+ 4095739264U, // VLD3q32a
+ 4095739264U, // VLD3q32b
+ 4095739136U, // VLD3q8a
+ 4095739136U, // VLD3q8b
+ 4104128256U, // VLD4LNd16
+ 4104129280U, // VLD4LNd32
+ 4104127232U, // VLD4LNd8
+ 4104128288U, // VLD4LNq16a
+ 4104128288U, // VLD4LNq16b
+ 4104129344U, // VLD4LNq32a
+ 4104129344U, // VLD4LNq32b
+ 4095737920U, // VLD4d16
+ 4095737984U, // VLD4d32
+ 4095738560U, // VLD4d64
+ 4095737856U, // VLD4d8
+ 4095738176U, // VLD4q16a
+ 4095738176U, // VLD4q16b
+ 4095738240U, // VLD4q32a
+ 4095738240U, // VLD4q32b
+ 4095738112U, // VLD4q8a
+ 4095738112U, // VLD4q8b
+ 202377984U, // VLDMD
+ 202377728U, // VLDMS
+ 219155200U, // VLDRD
+ 210766592U, // VLDRQ
+ 219154944U, // VLDRS
+ 4060090112U, // VMAXfd
+ 4060090176U, // VMAXfq
+ 4060087872U, // VMAXsv16i8
+ 4062184960U, // VMAXsv2i32
+ 4061136384U, // VMAXsv4i16
+ 4062185024U, // VMAXsv4i32
+ 4061136448U, // VMAXsv8i16
+ 4060087808U, // VMAXsv8i8
+ 4076865088U, // VMAXuv16i8
+ 4078962176U, // VMAXuv2i32
+ 4077913600U, // VMAXuv4i16
+ 4078962240U, // VMAXuv4i32
+ 4077913664U, // VMAXuv8i16
+ 4076865024U, // VMAXuv8i8
+ 4062187264U, // VMINfd
+ 4062187328U, // VMINfq
+ 4060087888U, // VMINsv16i8
+ 4062184976U, // VMINsv2i32
+ 4061136400U, // VMINsv4i16
+ 4062185040U, // VMINsv4i32
+ 4061136464U, // VMINsv8i16
+ 4060087824U, // VMINsv8i8
+ 4076865104U, // VMINuv16i8
+ 4078962192U, // VMINuv2i32
+ 4077913616U, // VMINuv4i16
+ 4078962256U, // VMINuv4i32
+ 4077913680U, // VMINuv8i16
+ 4076865040U, // VMINuv8i8
+ 234883840U, // VMLAD
+ 4070572608U, // VMLALslsv2i32
+ 4069524032U, // VMLALslsv4i16
+ 4087349824U, // VMLALsluv2i32
+ 4086301248U, // VMLALsluv4i16
+ 4070574080U, // VMLALsv2i64
+ 4069525504U, // VMLALsv4i32
+ 4068476928U, // VMLALsv8i16
+ 4087351296U, // VMLALuv2i64
+ 4086302720U, // VMLALuv4i32
+ 4085254144U, // VMLALuv8i16
+ 234883584U, // VMLAS
+ 4060089616U, // VMLAfd
+ 4060089680U, // VMLAfq
+ 4070572352U, // VMLAslfd
+ 4087349568U, // VMLAslfq
+ 4070572096U, // VMLAslv2i32
+ 4069523520U, // VMLAslv4i16
+ 4087349312U, // VMLAslv4i32
+ 4086300736U, // VMLAslv8i16
+ 4060088640U, // VMLAv16i8
+ 4062185728U, // VMLAv2i32
+ 4061137152U, // VMLAv4i16
+ 4062185792U, // VMLAv4i32
+ 4061137216U, // VMLAv8i16
+ 4060088576U, // VMLAv8i8
+ 234883904U, // VMLSD
+ 4070573632U, // VMLSLslsv2i32
+ 4069525056U, // VMLSLslsv4i16
+ 4087350848U, // VMLSLsluv2i32
+ 4086302272U, // VMLSLsluv4i16
+ 4070574592U, // VMLSLsv2i64
+ 4069526016U, // VMLSLsv4i32
+ 4068477440U, // VMLSLsv8i16
+ 4087351808U, // VMLSLuv2i64
+ 4086303232U, // VMLSLuv4i32
+ 4085254656U, // VMLSLuv8i16
+ 234883648U, // VMLSS
+ 4062186768U, // VMLSfd
+ 4062186832U, // VMLSfq
+ 4070573376U, // VMLSslfd
+ 4087350592U, // VMLSslfq
+ 4070573120U, // VMLSslv2i32
+ 4069524544U, // VMLSslv4i16
+ 4087350336U, // VMLSslv4i32
+ 4086301760U, // VMLSslv8i16
+ 4076865856U, // VMLSv16i8
+ 4078962944U, // VMLSv2i32
+ 4077914368U, // VMLSv4i16
+ 4078963008U, // VMLSv4i32
+ 4077914432U, // VMLSv8i16
+ 4076865792U, // VMLSv8i8
+ 246418240U, // VMOVD
+ 205523728U, // VMOVDRR
+ 246418240U, // VMOVDcc
+ 4062183696U, // VMOVDneon
+ 4070574608U, // VMOVLsv2i64
+ 4069526032U, // VMOVLsv4i32
+ 4069001744U, // VMOVLsv8i16
+ 4087351824U, // VMOVLuv2i64
+ 4086303248U, // VMOVLuv4i32
+ 4085778960U, // VMOVLuv8i16
+ 4089053696U, // VMOVNv2i32
+ 4088791552U, // VMOVNv4i16
+ 4088529408U, // VMOVNv8i8
+ 4062183760U, // VMOVQ
+ 206572304U, // VMOVRRD
+ 235932176U, // VMOVRS
+ 246417984U, // VMOVS
+ 234883600U, // VMOVSR
+ 246417984U, // VMOVScc
+ 4068478544U, // VMOVv16i8
+ 4068478512U, // VMOVv1i64
+ 4068474896U, // VMOVv2i32
+ 4068478576U, // VMOVv2i64
+ 4068476944U, // VMOVv4i16
+ 4068474960U, // VMOVv4i32
+ 4068477008U, // VMOVv8i16
+ 4068478480U, // VMOVv8i8
+ 236980992U, // VMULD
+ 4068478464U, // VMULLp
+ 4070574656U, // VMULLslsv2i32
+ 4069526080U, // VMULLslsv4i16
+ 4087351872U, // VMULLsluv2i32
+ 4086303296U, // VMULLsluv4i16
+ 4070575104U, // VMULLsv2i64
+ 4069526528U, // VMULLsv4i32
+ 4068477952U, // VMULLsv8i16
+ 4087352320U, // VMULLuv2i64
+ 4086303744U, // VMULLuv4i32
+ 4085255168U, // VMULLuv8i16
+ 236980736U, // VMULS
+ 4076866832U, // VMULfd
+ 4076866832U, // VMULfd_sfp
+ 4076866896U, // VMULfq
+ 4076865808U, // VMULpd
+ 4076865872U, // VMULpq
+ 4070574400U, // VMULslfd
+ 4087351616U, // VMULslfq
+ 4070574144U, // VMULslv2i32
+ 4069525568U, // VMULslv4i16
+ 4087351360U, // VMULslv4i32
+ 4086302784U, // VMULslv8i16
+ 4060088656U, // VMULv16i8
+ 4062185744U, // VMULv2i32
+ 4061137168U, // VMULv4i16
+ 4062185808U, // VMULv4i32
+ 4061137232U, // VMULv8i16
+ 4060088592U, // VMULv8i8
+ 4088399232U, // VMVNd
+ 4088399296U, // VMVNq
+ 246483776U, // VNEGD
+ 246483776U, // VNEGDcc
+ 246483520U, // VNEGS
+ 246483520U, // VNEGScc
+ 4088989568U, // VNEGf32d
+ 4088989568U, // VNEGf32d_sfp
+ 4088989632U, // VNEGf32q
+ 4088726400U, // VNEGs16d
+ 4088726464U, // VNEGs16q
+ 4088988544U, // VNEGs32d
+ 4088988608U, // VNEGs32q
+ 4088464256U, // VNEGs8d
+ 4088464320U, // VNEGs8q
+ 235932480U, // VNMLAD
+ 235932224U, // VNMLAS
+ 235932416U, // VNMLSD
+ 235932160U, // VNMLSS
+ 236981056U, // VNMULD
+ 236980800U, // VNMULS
+ 4063232272U, // VORNd
+ 4063232336U, // VORNq
+ 4062183696U, // VORRd
+ 4062183760U, // VORRq
+ 4088399424U, // VPADALsv16i8
+ 4088923648U, // VPADALsv2i32
+ 4088661504U, // VPADALsv4i16
+ 4088923712U, // VPADALsv4i32
+ 4088661568U, // VPADALsv8i16
+ 4088399360U, // VPADALsv8i8
+ 4088399552U, // VPADALuv16i8
+ 4088923776U, // VPADALuv2i32
+ 4088661632U, // VPADALuv4i16
+ 4088923840U, // VPADALuv4i32
+ 4088661696U, // VPADALuv8i16
+ 4088399488U, // VPADALuv8i8
+ 4088398400U, // VPADDLsv16i8
+ 4088922624U, // VPADDLsv2i32
+ 4088660480U, // VPADDLsv4i16
+ 4088922688U, // VPADDLsv4i32
+ 4088660544U, // VPADDLsv8i16
+ 4088398336U, // VPADDLsv8i8
+ 4088398528U, // VPADDLuv16i8
+ 4088922752U, // VPADDLuv2i32
+ 4088660608U, // VPADDLuv4i16
+ 4088922816U, // VPADDLuv4i32
+ 4088660672U, // VPADDLuv8i16
+ 4088398464U, // VPADDLuv8i8
+ 4076866816U, // VPADDf
+ 4061137680U, // VPADDi16
+ 4062186256U, // VPADDi32
+ 4060089104U, // VPADDi8
+ 4076867328U, // VPMAXf
+ 4061137408U, // VPMAXs16
+ 4062185984U, // VPMAXs32
+ 4060088832U, // VPMAXs8
+ 4077914624U, // VPMAXu16
+ 4078963200U, // VPMAXu32
+ 4076866048U, // VPMAXu8
+ 4078964480U, // VPMINf
+ 4061137424U, // VPMINs16
+ 4062186000U, // VPMINs32
+ 4060088848U, // VPMINs8
+ 4077914640U, // VPMINu16
+ 4078963216U, // VPMINu32
+ 4076866064U, // VPMINu8
+ 4088399680U, // VQABSv16i8
+ 4088923904U, // VQABSv2i32
+ 4088661760U, // VQABSv4i16
+ 4088923968U, // VQABSv4i32
+ 4088661824U, // VQABSv8i16
+ 4088399616U, // VQABSv8i8
+ 4060086352U, // VQADDsv16i8
+ 4063232016U, // VQADDsv1i64
+ 4062183440U, // VQADDsv2i32
+ 4063232080U, // VQADDsv2i64
+ 4061134864U, // VQADDsv4i16
+ 4062183504U, // VQADDsv4i32
+ 4061134928U, // VQADDsv8i16
+ 4060086288U, // VQADDsv8i8
+ 4076863568U, // VQADDuv16i8
+ 4080009232U, // VQADDuv1i64
+ 4078960656U, // VQADDuv2i32
+ 4080009296U, // VQADDuv2i64
+ 4077912080U, // VQADDuv4i16
+ 4078960720U, // VQADDuv4i32
+ 4077912144U, // VQADDuv8i16
+ 4076863504U, // VQADDuv8i8
+ 4070572864U, // VQDMLALslv2i32
+ 4069524288U, // VQDMLALslv4i16
+ 4070574336U, // VQDMLALv2i64
+ 4069525760U, // VQDMLALv4i32
+ 4070573888U, // VQDMLSLslv2i32
+ 4069525312U, // VQDMLSLslv4i16
+ 4070574848U, // VQDMLSLv2i64
+ 4069526272U, // VQDMLSLv4i32
+ 4070575168U, // VQDMULHslv2i32
+ 4069526592U, // VQDMULHslv4i16
+ 4087352384U, // VQDMULHslv4i32
+ 4086303808U, // VQDMULHslv8i16
+ 4062186240U, // VQDMULHv2i32
+ 4061137664U, // VQDMULHv4i16
+ 4062186304U, // VQDMULHv4i32
+ 4061137728U, // VQDMULHv8i16
+ 4070574912U, // VQDMULLslv2i32
+ 4069526336U, // VQDMULLslv4i16
+ 4070575360U, // VQDMULLv2i64
+ 4069526784U, // VQDMULLv4i32
+ 4089053760U, // VQMOVNsuv2i32
+ 4088791616U, // VQMOVNsuv4i16
+ 4088529472U, // VQMOVNsuv8i8
+ 4089053824U, // VQMOVNsv2i32
+ 4088791680U, // VQMOVNsv4i16
+ 4088529536U, // VQMOVNsv8i8
+ 4089053888U, // VQMOVNuv2i32
+ 4088791744U, // VQMOVNuv4i16
+ 4088529600U, // VQMOVNuv8i8
+ 4088399808U, // VQNEGv16i8
+ 4088924032U, // VQNEGv2i32
+ 4088661888U, // VQNEGv4i16
+ 4088924096U, // VQNEGv4i32
+ 4088661952U, // VQNEGv8i16
+ 4088399744U, // VQNEGv8i8
+ 4070575424U, // VQRDMULHslv2i32
+ 4069526848U, // VQRDMULHslv4i16
+ 4087352640U, // VQRDMULHslv4i32
+ 4086304064U, // VQRDMULHslv8i16
+ 4078963456U, // VQRDMULHv2i32
+ 4077914880U, // VQRDMULHv4i16
+ 4078963520U, // VQRDMULHv4i32
+ 4077914944U, // VQRDMULHv8i16
+ 4060087632U, // VQRSHLsv16i8
+ 4063233296U, // VQRSHLsv1i64
+ 4062184720U, // VQRSHLsv2i32
+ 4063233360U, // VQRSHLsv2i64
+ 4061136144U, // VQRSHLsv4i16
+ 4062184784U, // VQRSHLsv4i32
+ 4061136208U, // VQRSHLsv8i16
+ 4060087568U, // VQRSHLsv8i8
+ 4076864848U, // VQRSHLuv16i8
+ 4080010512U, // VQRSHLuv1i64
+ 4078961936U, // VQRSHLuv2i32
+ 4080010576U, // VQRSHLuv2i64
+ 4077913360U, // VQRSHLuv4i16
+ 4078962000U, // VQRSHLuv4i32
+ 4077913424U, // VQRSHLuv8i16
+ 4076864784U, // VQRSHLuv8i8
+ 4070574416U, // VQRSHRNsv2i32
+ 4069525840U, // VQRSHRNsv4i16
+ 4069001552U, // VQRSHRNsv8i8
+ 4087351632U, // VQRSHRNuv2i32
+ 4086303056U, // VQRSHRNuv4i16
+ 4085778768U, // VQRSHRNuv8i8
+ 4087351376U, // VQRSHRUNv2i32
+ 4086302800U, // VQRSHRUNv4i16
+ 4085778512U, // VQRSHRUNv8i8
+ 4069001040U, // VQSHLsiv16i8
+ 4068476816U, // VQSHLsiv1i64
+ 4070573840U, // VQSHLsiv2i32
+ 4068476880U, // VQSHLsiv2i64
+ 4069525264U, // VQSHLsiv4i16
+ 4070573904U, // VQSHLsiv4i32
+ 4069525328U, // VQSHLsiv8i16
+ 4069000976U, // VQSHLsiv8i8
+ 4085778000U, // VQSHLsuv16i8
+ 4085253776U, // VQSHLsuv1i64
+ 4087350800U, // VQSHLsuv2i32
+ 4085253840U, // VQSHLsuv2i64
+ 4086302224U, // VQSHLsuv4i16
+ 4087350864U, // VQSHLsuv4i32
+ 4086302288U, // VQSHLsuv8i16
+ 4085777936U, // VQSHLsuv8i8
+ 4060087376U, // VQSHLsv16i8
+ 4063233040U, // VQSHLsv1i64
+ 4062184464U, // VQSHLsv2i32
+ 4063233104U, // VQSHLsv2i64
+ 4061135888U, // VQSHLsv4i16
+ 4062184528U, // VQSHLsv4i32
+ 4061135952U, // VQSHLsv8i16
+ 4060087312U, // VQSHLsv8i8
+ 4085778256U, // VQSHLuiv16i8
+ 4085254032U, // VQSHLuiv1i64
+ 4087351056U, // VQSHLuiv2i32
+ 4085254096U, // VQSHLuiv2i64
+ 4086302480U, // VQSHLuiv4i16
+ 4087351120U, // VQSHLuiv4i32
+ 4086302544U, // VQSHLuiv8i16
+ 4085778192U, // VQSHLuiv8i8
+ 4076864592U, // VQSHLuv16i8
+ 4080010256U, // VQSHLuv1i64
+ 4078961680U, // VQSHLuv2i32
+ 4080010320U, // VQSHLuv2i64
+ 4077913104U, // VQSHLuv4i16
+ 4078961744U, // VQSHLuv4i32
+ 4077913168U, // VQSHLuv8i16
+ 4076864528U, // VQSHLuv8i8
+ 4070574352U, // VQSHRNsv2i32
+ 4069525776U, // VQSHRNsv4i16
+ 4069001488U, // VQSHRNsv8i8
+ 4087351568U, // VQSHRNuv2i32
+ 4086302992U, // VQSHRNuv4i16
+ 4085778704U, // VQSHRNuv8i8
+ 4087351312U, // VQSHRUNv2i32
+ 4086302736U, // VQSHRUNv4i16
+ 4085778448U, // VQSHRUNv8i8
+ 4060086864U, // VQSUBsv16i8
+ 4063232528U, // VQSUBsv1i64
+ 4062183952U, // VQSUBsv2i32
+ 4063232592U, // VQSUBsv2i64
+ 4061135376U, // VQSUBsv4i16
+ 4062184016U, // VQSUBsv4i32
+ 4061135440U, // VQSUBsv8i16
+ 4060086800U, // VQSUBsv8i8
+ 4076864080U, // VQSUBuv16i8
+ 4080009744U, // VQSUBuv1i64
+ 4078961168U, // VQSUBuv2i32
+ 4080009808U, // VQSUBuv2i64
+ 4077912592U, // VQSUBuv4i16
+ 4078961232U, // VQSUBuv4i32
+ 4077912656U, // VQSUBuv8i16
+ 4076864016U, // VQSUBuv8i8
+ 4087350272U, // VRADDHNv2i32
+ 4086301696U, // VRADDHNv4i16
+ 4085253120U, // VRADDHNv8i8
+ 4089119744U, // VRECPEd
+ 4089120000U, // VRECPEfd
+ 4089120064U, // VRECPEfq
+ 4089119808U, // VRECPEq
+ 4060090128U, // VRECPSfd
+ 4060090192U, // VRECPSfq
+ 4088398080U, // VREV16d8
+ 4088398144U, // VREV16q8
+ 4088660096U, // VREV32d16
+ 4088397952U, // VREV32d8
+ 4088660160U, // VREV32q16
+ 4088398016U, // VREV32q8
+ 4088659968U, // VREV64d16
+ 4088922112U, // VREV64d32
+ 4088397824U, // VREV64d8
+ 4088922112U, // VREV64df
+ 4088660032U, // VREV64q16
+ 4088922176U, // VREV64q32
+ 4088397888U, // VREV64q8
+ 4088922176U, // VREV64qf
+ 4060086592U, // VRHADDsv16i8
+ 4062183680U, // VRHADDsv2i32
+ 4061135104U, // VRHADDsv4i16
+ 4062183744U, // VRHADDsv4i32
+ 4061135168U, // VRHADDsv8i16
+ 4060086528U, // VRHADDsv8i8
+ 4076863808U, // VRHADDuv16i8
+ 4078960896U, // VRHADDuv2i32
+ 4077912320U, // VRHADDuv4i16
+ 4078960960U, // VRHADDuv4i32
+ 4077912384U, // VRHADDuv8i16
+ 4076863744U, // VRHADDuv8i8
+ 4060087616U, // VRSHLsv16i8
+ 4063233280U, // VRSHLsv1i64
+ 4062184704U, // VRSHLsv2i32
+ 4063233344U, // VRSHLsv2i64
+ 4061136128U, // VRSHLsv4i16
+ 4062184768U, // VRSHLsv4i32
+ 4061136192U, // VRSHLsv8i16
+ 4060087552U, // VRSHLsv8i8
+ 4076864832U, // VRSHLuv16i8
+ 4080010496U, // VRSHLuv1i64
+ 4078961920U, // VRSHLuv2i32
+ 4080010560U, // VRSHLuv2i64
+ 4077913344U, // VRSHLuv4i16
+ 4078961984U, // VRSHLuv4i32
+ 4077913408U, // VRSHLuv8i16
+ 4076864768U, // VRSHLuv8i8
+ 4070574160U, // VRSHRNv2i32
+ 4069525584U, // VRSHRNv4i16
+ 4069001296U, // VRSHRNv8i8
+ 4068999760U, // VRSHRsv16i8
+ 4068475536U, // VRSHRsv1i64
+ 4070572560U, // VRSHRsv2i32
+ 4068475600U, // VRSHRsv2i64
+ 4069523984U, // VRSHRsv4i16
+ 4070572624U, // VRSHRsv4i32
+ 4069524048U, // VRSHRsv8i16
+ 4068999696U, // VRSHRsv8i8
+ 4085776976U, // VRSHRuv16i8
+ 4085252752U, // VRSHRuv1i64
+ 4087349776U, // VRSHRuv2i32
+ 4085252816U, // VRSHRuv2i64
+ 4086301200U, // VRSHRuv4i16
+ 4087349840U, // VRSHRuv4i32
+ 4086301264U, // VRSHRuv8i16
+ 4085776912U, // VRSHRuv8i8
+ 4089119872U, // VRSQRTEd
+ 4089120128U, // VRSQRTEfd
+ 4089120192U, // VRSQRTEfq
+ 4089119936U, // VRSQRTEq
+ 4062187280U, // VRSQRTSfd
+ 4062187344U, // VRSQRTSfq
+ 4069000016U, // VRSRAsv16i8
+ 4068475792U, // VRSRAsv1i64
+ 4070572816U, // VRSRAsv2i32
+ 4068475856U, // VRSRAsv2i64
+ 4069524240U, // VRSRAsv4i16
+ 4070572880U, // VRSRAsv4i32
+ 4069524304U, // VRSRAsv8i16
+ 4068999952U, // VRSRAsv8i8
+ 4085777232U, // VRSRAuv16i8
+ 4085253008U, // VRSRAuv1i64
+ 4087350032U, // VRSRAuv2i32
+ 4085253072U, // VRSRAuv2i64
+ 4086301456U, // VRSRAuv4i16
+ 4087350096U, // VRSRAuv4i32
+ 4086301520U, // VRSRAuv8i16
+ 4085777168U, // VRSRAuv8i8
+ 4087350784U, // VRSUBHNv2i32
+ 4086302208U, // VRSUBHNv4i16
+ 4085253632U, // VRSUBHNv8i8
+ 234883888U, // VSETLNi16
+ 234883856U, // VSETLNi32
+ 239078160U, // VSETLNi8
+ 4088791808U, // VSHLLi16
+ 4089053952U, // VSHLLi32
+ 4088529664U, // VSHLLi8
+ 4070574608U, // VSHLLsv2i64
+ 4069526032U, // VSHLLsv4i32
+ 4069001744U, // VSHLLsv8i16
+ 4087351824U, // VSHLLuv2i64
+ 4086303248U, // VSHLLuv4i32
+ 4085778960U, // VSHLLuv8i16
+ 4069000528U, // VSHLiv16i8
+ 4068476304U, // VSHLiv1i64
+ 4070573328U, // VSHLiv2i32
+ 4068476368U, // VSHLiv2i64
+ 4069524752U, // VSHLiv4i16
+ 4070573392U, // VSHLiv4i32
+ 4069524816U, // VSHLiv8i16
+ 4069000464U, // VSHLiv8i8
+ 4060087360U, // VSHLsv16i8
+ 4063233024U, // VSHLsv1i64
+ 4062184448U, // VSHLsv2i32
+ 4063233088U, // VSHLsv2i64
+ 4061135872U, // VSHLsv4i16
+ 4062184512U, // VSHLsv4i32
+ 4061135936U, // VSHLsv8i16
+ 4060087296U, // VSHLsv8i8
+ 4076864576U, // VSHLuv16i8
+ 4080010240U, // VSHLuv1i64
+ 4078961664U, // VSHLuv2i32
+ 4080010304U, // VSHLuv2i64
+ 4077913088U, // VSHLuv4i16
+ 4078961728U, // VSHLuv4i32
+ 4077913152U, // VSHLuv8i16
+ 4076864512U, // VSHLuv8i8
+ 4070574096U, // VSHRNv2i32
+ 4069525520U, // VSHRNv4i16
+ 4069001232U, // VSHRNv8i8
+ 4068999248U, // VSHRsv16i8
+ 4068475024U, // VSHRsv1i64
+ 4070572048U, // VSHRsv2i32
+ 4068475088U, // VSHRsv2i64
+ 4069523472U, // VSHRsv4i16
+ 4070572112U, // VSHRsv4i32
+ 4069523536U, // VSHRsv8i16
+ 4068999184U, // VSHRsv8i8
+ 4085776464U, // VSHRuv16i8
+ 4085252240U, // VSHRuv1i64
+ 4087349264U, // VSHRuv2i32
+ 4085252304U, // VSHRuv2i64
+ 4086300688U, // VSHRuv4i16
+ 4087349328U, // VSHRuv4i32
+ 4086300752U, // VSHRuv8i16
+ 4085776400U, // VSHRuv8i8
+ 246942656U, // VSITOD
+ 246942400U, // VSITOS
+ 4085777744U, // VSLIv16i8
+ 4085253520U, // VSLIv1i64
+ 4087350544U, // VSLIv2i32
+ 4085253584U, // VSLIv2i64
+ 4086301968U, // VSLIv4i16
+ 4087350608U, // VSLIv4i32
+ 4086302032U, // VSLIv8i16
+ 4085777680U, // VSLIv8i8
+ 246483904U, // VSQRTD
+ 246483648U, // VSQRTS
+ 4068999504U, // VSRAsv16i8
+ 4068475280U, // VSRAsv1i64
+ 4070572304U, // VSRAsv2i32
+ 4068475344U, // VSRAsv2i64
+ 4069523728U, // VSRAsv4i16
+ 4070572368U, // VSRAsv4i32
+ 4069523792U, // VSRAsv8i16
+ 4068999440U, // VSRAsv8i8
+ 4085776720U, // VSRAuv16i8
+ 4085252496U, // VSRAuv1i64
+ 4087349520U, // VSRAuv2i32
+ 4085252560U, // VSRAuv2i64
+ 4086300944U, // VSRAuv4i16
+ 4087349584U, // VSRAuv4i32
+ 4086301008U, // VSRAuv8i16
+ 4085776656U, // VSRAuv8i8
+ 4085777488U, // VSRIv16i8
+ 4085253264U, // VSRIv1i64
+ 4087350288U, // VSRIv2i32
+ 4085253328U, // VSRIv2i64
+ 4086301712U, // VSRIv4i16
+ 4087350352U, // VSRIv4i32
+ 4086301776U, // VSRIv8i16
+ 4085777424U, // VSRIv8i8
+ 4093642560U, // VST1d16
+ 4093642624U, // VST1d32
+ 4093642688U, // VST1d64
+ 4093642496U, // VST1d8
+ 4093642624U, // VST1df
+ 4093643328U, // VST1q16
+ 4093643392U, // VST1q32
+ 4093643456U, // VST1q64
+ 4093643264U, // VST1q8
+ 4093643392U, // VST1qf
+ 4102030592U, // VST2LNd16
+ 4102031616U, // VST2LNd32
+ 4102029568U, // VST2LNd8
+ 4102030624U, // VST2LNq16a
+ 4102030624U, // VST2LNq16b
+ 4102031680U, // VST2LNq32a
+ 4102031680U, // VST2LNq32b
+ 4093642816U, // VST2d16
+ 4093642880U, // VST2d32
+ 4093643456U, // VST2d64
+ 4093642752U, // VST2d8
+ 4093641536U, // VST2q16
+ 4093641600U, // VST2q32
+ 4093641472U, // VST2q8
+ 4102030848U, // VST3LNd16
+ 4102031872U, // VST3LNd32
+ 4102029824U, // VST3LNd8
+ 4102030880U, // VST3LNq16a
+ 4102030880U, // VST3LNq16b
+ 4102031936U, // VST3LNq32a
+ 4102031936U, // VST3LNq32b
+ 4093641792U, // VST3d16
+ 4093641856U, // VST3d32
+ 4093642432U, // VST3d64
+ 4093641728U, // VST3d8
+ 4093642048U, // VST3q16a
+ 4093642048U, // VST3q16b
+ 4093642112U, // VST3q32a
+ 4093642112U, // VST3q32b
+ 4093641984U, // VST3q8a
+ 4093641984U, // VST3q8b
+ 4102031104U, // VST4LNd16
+ 4102032128U, // VST4LNd32
+ 4102030080U, // VST4LNd8
+ 4102031136U, // VST4LNq16a
+ 4102031136U, // VST4LNq16b
+ 4102032192U, // VST4LNq32a
+ 4102032192U, // VST4LNq32b
+ 4093640768U, // VST4d16
+ 4093640832U, // VST4d32
+ 4093641408U, // VST4d64
+ 4093640704U, // VST4d8
+ 4093641024U, // VST4q16a
+ 4093641024U, // VST4q16b
+ 4093641088U, // VST4q32a
+ 4093641088U, // VST4q32b
+ 4093640960U, // VST4q8a
+ 4093640960U, // VST4q8b
+ 201329408U, // VSTMD
+ 201329152U, // VSTMS
+ 218106624U, // VSTRD
+ 209718016U, // VSTRQ
+ 218106368U, // VSTRS
+ 238029632U, // VSUBD
+ 4070573568U, // VSUBHNv2i32
+ 4069524992U, // VSUBHNv4i16
+ 4068476416U, // VSUBHNv8i8
+ 4070572544U, // VSUBLsv2i64
+ 4069523968U, // VSUBLsv4i32
+ 4068475392U, // VSUBLsv8i16
+ 4087349760U, // VSUBLuv2i64
+ 4086301184U, // VSUBLuv4i32
+ 4085252608U, // VSUBLuv8i16
+ 238029376U, // VSUBS
+ 4070572800U, // VSUBWsv2i64
+ 4069524224U, // VSUBWsv4i32
+ 4068475648U, // VSUBWsv8i16
+ 4087350016U, // VSUBWuv2i64
+ 4086301440U, // VSUBWuv4i32
+ 4085252864U, // VSUBWuv8i16
+ 4062186752U, // VSUBfd
+ 4062186752U, // VSUBfd_sfp
+ 4062186816U, // VSUBfq
+ 4076865600U, // VSUBv16i8
+ 4080011264U, // VSUBv1i64
+ 4078962688U, // VSUBv2i32
+ 4080011328U, // VSUBv2i64
+ 4077914112U, // VSUBv4i16
+ 4078962752U, // VSUBv4i32
+ 4077914176U, // VSUBv8i16
+ 4076865536U, // VSUBv8i8
+ 4088399872U, // VTBL1
+ 4088400128U, // VTBL2
+ 4088400384U, // VTBL3
+ 4088400640U, // VTBL4
+ 4088399936U, // VTBX1
+ 4088400192U, // VTBX2
+ 4088400448U, // VTBX3
+ 4088400704U, // VTBX4
+ 247270336U, // VTOSIZD
+ 247270080U, // VTOSIZS
+ 247204800U, // VTOUIZD
+ 247204544U, // VTOUIZS
+ 4088791168U, // VTRNd16
+ 4089053312U, // VTRNd32
+ 4088529024U, // VTRNd8
+ 4088791232U, // VTRNq16
+ 4089053376U, // VTRNq32
+ 4088529088U, // VTRNq8
+ 4060088400U, // VTSTv16i8
+ 4062185488U, // VTSTv2i32
+ 4061136912U, // VTSTv4i16
+ 4062185552U, // VTSTv4i32
+ 4061136976U, // VTSTv8i16
+ 4060088336U, // VTSTv8i8
+ 246942528U, // VUITOD
+ 246942272U, // VUITOS
+ 4088791296U, // VUZPd16
+ 4089053440U, // VUZPd32
+ 4088529152U, // VUZPd8
+ 4088791360U, // VUZPq16
+ 4089053504U, // VUZPq32
+ 4088529216U, // VUZPq8
+ 4088791424U, // VZIPd16
+ 4089053568U, // VZIPd32
+ 4088529280U, // VZIPd8
+ 4088791488U, // VZIPq16
+ 4089053632U, // VZIPq32
+ 4088529344U, // VZIPq8
+ 0U, // t2ADCSri
+ 0U, // t2ADCSrr
+ 0U, // t2ADCSrs
+ 0U, // t2ADCri
+ 0U, // t2ADCrr
+ 0U, // t2ADCrs
+ 0U, // t2ADDSri
+ 0U, // t2ADDSrr
+ 0U, // t2ADDSrs
+ 0U, // t2ADDrSPi
+ 0U, // t2ADDrSPi12
+ 0U, // t2ADDrSPs
+ 0U, // t2ADDri
+ 0U, // t2ADDri12
+ 0U, // t2ADDrr
+ 0U, // t2ADDrs
+ 0U, // t2ANDri
+ 0U, // t2ANDrr
+ 0U, // t2ANDrs
+ 0U, // t2ASRri
+ 0U, // t2ASRrr
+ 0U, // t2B
+ 0U, // t2BFC
+ 0U, // t2BICri
+ 0U, // t2BICrr
+ 0U, // t2BICrs
+ 0U, // t2BR_JT
+ 0U, // t2Bcc
+ 0U, // t2CLZ
+ 0U, // t2CMNri
+ 0U, // t2CMNrr
+ 0U, // t2CMNrs
+ 0U, // t2CMNzri
+ 0U, // t2CMNzrr
+ 0U, // t2CMNzrs
+ 0U, // t2CMPri
+ 0U, // t2CMPrr
+ 0U, // t2CMPrs
+ 0U, // t2CMPzri
+ 0U, // t2CMPzrr
+ 0U, // t2CMPzrs
+ 0U, // t2EORri
+ 0U, // t2EORrr
+ 0U, // t2EORrs
+ 0U, // t2IT
+ 0U, // t2Int_MemBarrierV7
+ 0U, // t2Int_SyncBarrierV7
+ 0U, // t2Int_eh_sjlj_setjmp
+ 0U, // t2LDM
+ 0U, // t2LDM_RET
+ 0U, // t2LDRB_POST
+ 0U, // t2LDRB_PRE
+ 0U, // t2LDRBi12
+ 0U, // t2LDRBi8
+ 0U, // t2LDRBpci
+ 0U, // t2LDRBs
+ 0U, // t2LDRDi8
+ 0U, // t2LDRDpci
+ 0U, // t2LDREX
+ 0U, // t2LDREXB
+ 0U, // t2LDREXD
+ 0U, // t2LDREXH
+ 0U, // t2LDRH_POST
+ 0U, // t2LDRH_PRE
+ 0U, // t2LDRHi12
+ 0U, // t2LDRHi8
+ 0U, // t2LDRHpci
+ 0U, // t2LDRHs
+ 0U, // t2LDRSB_POST
+ 0U, // t2LDRSB_PRE
+ 0U, // t2LDRSBi12
+ 0U, // t2LDRSBi8
+ 0U, // t2LDRSBpci
+ 0U, // t2LDRSBs
+ 0U, // t2LDRSH_POST
+ 0U, // t2LDRSH_PRE
+ 0U, // t2LDRSHi12
+ 0U, // t2LDRSHi8
+ 0U, // t2LDRSHpci
+ 0U, // t2LDRSHs
+ 0U, // t2LDR_POST
+ 0U, // t2LDR_PRE
+ 0U, // t2LDRi12
+ 0U, // t2LDRi8
+ 0U, // t2LDRpci
+ 0U, // t2LDRpci_pic
+ 0U, // t2LDRs
+ 0U, // t2LEApcrel
+ 0U, // t2LEApcrelJT
+ 0U, // t2LSLri
+ 0U, // t2LSLrr
+ 0U, // t2LSRri
+ 0U, // t2LSRrr
+ 0U, // t2MLA
+ 0U, // t2MLS
+ 0U, // t2MOVCCasr
+ 0U, // t2MOVCCi
+ 0U, // t2MOVCClsl
+ 0U, // t2MOVCClsr
+ 0U, // t2MOVCCr
+ 0U, // t2MOVCCror
+ 0U, // t2MOVTi16
+ 0U, // t2MOVi
+ 0U, // t2MOVi16
+ 0U, // t2MOVi32imm
+ 0U, // t2MOVr
+ 0U, // t2MOVrx
+ 0U, // t2MOVsra_flag
+ 0U, // t2MOVsrl_flag
+ 0U, // t2MUL
+ 0U, // t2MVNi
+ 0U, // t2MVNr
+ 0U, // t2MVNs
+ 0U, // t2ORNri
+ 0U, // t2ORNrr
+ 0U, // t2ORNrs
+ 0U, // t2ORRri
+ 0U, // t2ORRrr
+ 0U, // t2ORRrs
+ 0U, // t2PKHBT
+ 0U, // t2PKHTB
+ 0U, // t2REV
+ 0U, // t2REV16
+ 0U, // t2REVSH
+ 0U, // t2RORri
+ 0U, // t2RORrr
+ 0U, // t2RSBSri
+ 0U, // t2RSBSrs
+ 0U, // t2RSBri
+ 0U, // t2RSBrs
+ 0U, // t2SBCSri
+ 0U, // t2SBCSrr
+ 0U, // t2SBCSrs
+ 0U, // t2SBCri
+ 0U, // t2SBCrr
+ 0U, // t2SBCrs
+ 0U, // t2SBFX
+ 0U, // t2SMLABB
+ 0U, // t2SMLABT
+ 0U, // t2SMLAL
+ 0U, // t2SMLATB
+ 0U, // t2SMLATT
+ 0U, // t2SMLAWB
+ 0U, // t2SMLAWT
+ 0U, // t2SMMLA
+ 0U, // t2SMMLS
+ 0U, // t2SMMUL
+ 0U, // t2SMULBB
+ 0U, // t2SMULBT
+ 0U, // t2SMULL
+ 0U, // t2SMULTB
+ 0U, // t2SMULTT
+ 0U, // t2SMULWB
+ 0U, // t2SMULWT
+ 0U, // t2STM
+ 0U, // t2STRB_POST
+ 0U, // t2STRB_PRE
+ 0U, // t2STRBi12
+ 0U, // t2STRBi8
+ 0U, // t2STRBs
+ 0U, // t2STRDi8
+ 0U, // t2STREX
+ 0U, // t2STREXB
+ 0U, // t2STREXD
+ 0U, // t2STREXH
+ 0U, // t2STRH_POST
+ 0U, // t2STRH_PRE
+ 0U, // t2STRHi12
+ 0U, // t2STRHi8
+ 0U, // t2STRHs
+ 0U, // t2STR_POST
+ 0U, // t2STR_PRE
+ 0U, // t2STRi12
+ 0U, // t2STRi8
+ 0U, // t2STRs
+ 0U, // t2SUBSri
+ 0U, // t2SUBSrr
+ 0U, // t2SUBSrs
+ 0U, // t2SUBrSPi
+ 0U, // t2SUBrSPi12
+ 0U, // t2SUBrSPi12_
+ 0U, // t2SUBrSPi_
+ 0U, // t2SUBrSPs
+ 0U, // t2SUBrSPs_
+ 0U, // t2SUBri
+ 0U, // t2SUBri12
+ 0U, // t2SUBrr
+ 0U, // t2SUBrs
+ 0U, // t2SXTABrr
+ 0U, // t2SXTABrr_rot
+ 0U, // t2SXTAHrr
+ 0U, // t2SXTAHrr_rot
+ 0U, // t2SXTBr
+ 0U, // t2SXTBr_rot
+ 0U, // t2SXTHr
+ 0U, // t2SXTHr_rot
+ 0U, // t2TBB
+ 0U, // t2TBH
+ 0U, // t2TEQri
+ 0U, // t2TEQrr
+ 0U, // t2TEQrs
+ 0U, // t2TPsoft
+ 0U, // t2TSTri
+ 0U, // t2TSTrr
+ 0U, // t2TSTrs
+ 0U, // t2UBFX
+ 0U, // t2UMAAL
+ 0U, // t2UMLAL
+ 0U, // t2UMULL
+ 0U, // t2UXTABrr
+ 0U, // t2UXTABrr_rot
+ 0U, // t2UXTAHrr
+ 0U, // t2UXTAHrr_rot
+ 0U, // t2UXTB16r
+ 0U, // t2UXTB16r_rot
+ 0U, // t2UXTBr
+ 0U, // t2UXTBr_rot
+ 0U, // t2UXTHr
+ 0U, // t2UXTHr_rot
+ 0U, // tADC
+ 0U, // tADDhirr
+ 0U, // tADDi3
+ 0U, // tADDi8
+ 0U, // tADDrPCi
+ 0U, // tADDrSP
+ 0U, // tADDrSPi
+ 0U, // tADDrr
+ 0U, // tADDspi
+ 0U, // tADDspr
+ 0U, // tADDspr_
+ 0U, // tADJCALLSTACKDOWN
+ 0U, // tADJCALLSTACKUP
+ 0U, // tAND
+ 0U, // tANDsp
+ 0U, // tASRri
+ 0U, // tASRrr
+ 0U, // tB
+ 0U, // tBIC
+ 0U, // tBL
+ 0U, // tBLXi
+ 0U, // tBLXi_r9
+ 0U, // tBLXr
+ 0U, // tBLXr_r9
+ 0U, // tBLr9
+ 0U, // tBRIND
+ 0U, // tBR_JTr
+ 0U, // tBX
+ 0U, // tBX_RET
+ 0U, // tBX_RET_vararg
+ 0U, // tBXr9
+ 0U, // tBcc
+ 0U, // tBfar
+ 0U, // tCBNZ
+ 0U, // tCBZ
+ 0U, // tCMN
+ 0U, // tCMNZ
+ 0U, // tCMPhir
+ 0U, // tCMPi8
+ 0U, // tCMPr
+ 0U, // tCMPzhir
+ 0U, // tCMPzi8
+ 0U, // tCMPzr
+ 0U, // tEOR
+ 0U, // tInt_eh_sjlj_setjmp
+ 0U, // tLDM
+ 0U, // tLDR
+ 0U, // tLDRB
+ 0U, // tLDRH
+ 0U, // tLDRSB
+ 0U, // tLDRSH
+ 0U, // tLDRcp
+ 0U, // tLDRpci
+ 0U, // tLDRpci_pic
+ 0U, // tLDRspi
+ 0U, // tLEApcrel
+ 0U, // tLEApcrelJT
+ 0U, // tLSLri
+ 0U, // tLSLrr
+ 0U, // tLSRri
+ 0U, // tLSRrr
+ 0U, // tMOVCCi
+ 0U, // tMOVCCr
+ 0U, // tMOVCCr_pseudo
+ 0U, // tMOVSr
+ 0U, // tMOVgpr2gpr
+ 0U, // tMOVgpr2tgpr
+ 0U, // tMOVi8
+ 0U, // tMOVr
+ 0U, // tMOVtgpr2gpr
+ 0U, // tMUL
+ 0U, // tMVN
+ 0U, // tORR
+ 0U, // tPICADD
+ 0U, // tPOP
+ 0U, // tPOP_RET
+ 0U, // tPUSH
+ 0U, // tREV
+ 0U, // tREV16
+ 0U, // tREVSH
+ 0U, // tROR
+ 0U, // tRSB
+ 0U, // tRestore
+ 0U, // tSBC
+ 0U, // tSTM
+ 0U, // tSTR
+ 0U, // tSTRB
+ 0U, // tSTRH
+ 0U, // tSTRspi
+ 0U, // tSUBi3
+ 0U, // tSUBi8
+ 0U, // tSUBrr
+ 0U, // tSUBspi
+ 0U, // tSUBspi_
+ 0U, // tSXTB
+ 0U, // tSXTH
+ 0U, // tSpill
+ 0U, // tTPsoft
+ 0U, // tTST
+ 0U, // tUXTB
+ 0U, // tUXTH
+ 0U
+ };
+ const unsigned opcode = MI.getOpcode();
+ unsigned Value = InstBits[opcode];
+ unsigned op = 0;
+ op = op; // suppress warning
+ switch (opcode) {
+ case ARM::ADCSSri:
+ case ARM::ADCSSrr:
+ case ARM::ADCSSrs:
+ case ARM::ADCri:
+ case ARM::ADCrr:
+ case ARM::ADCrs:
+ case ARM::ADDSri:
+ case ARM::ADDSrr:
+ case ARM::ADDSrs:
+ case ARM::ADDri:
+ case ARM::ADDrr:
+ case ARM::ADDrs:
+ case ARM::ADJCALLSTACKDOWN:
+ case ARM::ADJCALLSTACKUP:
+ case ARM::ANDri:
+ case ARM::ANDrr:
+ case ARM::ANDrs:
+ case ARM::ATOMIC_CMP_SWAP_I16:
+ case ARM::ATOMIC_CMP_SWAP_I32:
+ case ARM::ATOMIC_CMP_SWAP_I8:
+ case ARM::ATOMIC_LOAD_ADD_I16:
+ case ARM::ATOMIC_LOAD_ADD_I32:
+ case ARM::ATOMIC_LOAD_ADD_I8:
+ case ARM::ATOMIC_LOAD_AND_I16:
+ case ARM::ATOMIC_LOAD_AND_I32:
+ case ARM::ATOMIC_LOAD_AND_I8:
+ case ARM::ATOMIC_LOAD_NAND_I16:
+ case ARM::ATOMIC_LOAD_NAND_I32:
+ case ARM::ATOMIC_LOAD_NAND_I8:
+ case ARM::ATOMIC_LOAD_OR_I16:
+ case ARM::ATOMIC_LOAD_OR_I32:
+ case ARM::ATOMIC_LOAD_OR_I8:
+ case ARM::ATOMIC_LOAD_SUB_I16:
+ case ARM::ATOMIC_LOAD_SUB_I32:
+ case ARM::ATOMIC_LOAD_SUB_I8:
+ case ARM::ATOMIC_LOAD_XOR_I16:
+ case ARM::ATOMIC_LOAD_XOR_I32:
+ case ARM::ATOMIC_LOAD_XOR_I8:
+ case ARM::ATOMIC_SWAP_I16:
+ case ARM::ATOMIC_SWAP_I32:
+ case ARM::ATOMIC_SWAP_I8:
+ case ARM::B:
+ case ARM::BFC:
+ case ARM::BICri:
+ case ARM::BICrr:
+ case ARM::BICrs:
+ case ARM::BL:
+ case ARM::BLX:
+ case ARM::BLXr9:
+ case ARM::BL_pred:
+ case ARM::BLr9:
+ case ARM::BLr9_pred:
+ case ARM::BRIND:
+ case ARM::BR_JTadd:
+ case ARM::BR_JTm:
+ case ARM::BR_JTr:
+ case ARM::BX:
+ case ARM::BX_RET:
+ case ARM::BXr9:
+ case ARM::Bcc:
+ case ARM::CLZ:
+ case ARM::CMNri:
+ case ARM::CMNrr:
+ case ARM::CMNrs:
+ case ARM::CMNzri:
+ case ARM::CMNzrr:
+ case ARM::CMNzrs:
+ case ARM::CMPri:
+ case ARM::CMPrr:
+ case ARM::CMPrs:
+ case ARM::CMPzri:
+ case ARM::CMPzrr:
+ case ARM::CMPzrs:
+ case ARM::CONSTPOOL_ENTRY:
+ case ARM::EORri:
+ case ARM::EORrr:
+ case ARM::EORrs:
+ case ARM::FCONSTD:
+ case ARM::FCONSTS:
+ case ARM::FMSTAT:
+ case ARM::Int_MemBarrierV6:
+ case ARM::Int_MemBarrierV7:
+ case ARM::Int_SyncBarrierV6:
+ case ARM::Int_SyncBarrierV7:
+ case ARM::Int_eh_sjlj_setjmp:
+ case ARM::LDM:
+ case ARM::LDM_RET:
+ case ARM::LDR:
+ case ARM::LDRB:
+ case ARM::LDRB_POST:
+ case ARM::LDRB_PRE:
+ case ARM::LDRD:
+ case ARM::LDREX:
+ case ARM::LDREXB:
+ case ARM::LDREXD:
+ case ARM::LDREXH:
+ case ARM::LDRH:
+ case ARM::LDRH_POST:
+ case ARM::LDRH_PRE:
+ case ARM::LDRSB:
+ case ARM::LDRSB_POST:
+ case ARM::LDRSB_PRE:
+ case ARM::LDRSH:
+ case ARM::LDRSH_POST:
+ case ARM::LDRSH_PRE:
+ case ARM::LDR_POST:
+ case ARM::LDR_PRE:
+ case ARM::LDRcp:
+ case ARM::LEApcrel:
+ case ARM::LEApcrelJT:
+ case ARM::MLA:
+ case ARM::MLS:
+ case ARM::MOVCCi:
+ case ARM::MOVCCr:
+ case ARM::MOVCCs:
+ case ARM::MOVTi16:
+ case ARM::MOVi:
+ case ARM::MOVi16:
+ case ARM::MOVi2pieces:
+ case ARM::MOVi32imm:
+ case ARM::MOVr:
+ case ARM::MOVrx:
+ case ARM::MOVs:
+ case ARM::MOVsra_flag:
+ case ARM::MOVsrl_flag:
+ case ARM::MUL:
+ case ARM::MVNi:
+ case ARM::MVNr:
+ case ARM::MVNs:
+ case ARM::ORRri:
+ case ARM::ORRrr:
+ case ARM::ORRrs:
+ case ARM::PICADD:
+ case ARM::PICLDR:
+ case ARM::PICLDRB:
+ case ARM::PICLDRH:
+ case ARM::PICLDRSB:
+ case ARM::PICLDRSH:
+ case ARM::PICSTR:
+ case ARM::PICSTRB:
+ case ARM::PICSTRH:
+ case ARM::PKHBT:
+ case ARM::PKHTB:
+ case ARM::REV:
+ case ARM::REV16:
+ case ARM::REVSH:
+ case ARM::RSBSri:
+ case ARM::RSBSrs:
+ case ARM::RSBri:
+ case ARM::RSBrs:
+ case ARM::RSCSri:
+ case ARM::RSCSrs:
+ case ARM::RSCri:
+ case ARM::RSCrs:
+ case ARM::SBCSSri:
+ case ARM::SBCSSrr:
+ case ARM::SBCSSrs:
+ case ARM::SBCri:
+ case ARM::SBCrr:
+ case ARM::SBCrs:
+ case ARM::SBFX:
+ case ARM::SMLABB:
+ case ARM::SMLABT:
+ case ARM::SMLAL:
+ case ARM::SMLATB:
+ case ARM::SMLATT:
+ case ARM::SMLAWB:
+ case ARM::SMLAWT:
+ case ARM::SMMLA:
+ case ARM::SMMLS:
+ case ARM::SMMUL:
+ case ARM::SMULBB:
+ case ARM::SMULBT:
+ case ARM::SMULL:
+ case ARM::SMULTB:
+ case ARM::SMULTT:
+ case ARM::SMULWB:
+ case ARM::SMULWT:
+ case ARM::STM:
+ case ARM::STR:
+ case ARM::STRB:
+ case ARM::STRB_POST:
+ case ARM::STRB_PRE:
+ case ARM::STRD:
+ case ARM::STREX:
+ case ARM::STREXB:
+ case ARM::STREXD:
+ case ARM::STREXH:
+ case ARM::STRH:
+ case ARM::STRH_POST:
+ case ARM::STRH_PRE:
+ case ARM::STR_POST:
+ case ARM::STR_PRE:
+ case ARM::SUBSri:
+ case ARM::SUBSrr:
+ case ARM::SUBSrs:
+ case ARM::SUBri:
+ case ARM::SUBrr:
+ case ARM::SUBrs:
+ case ARM::SXTABrr:
+ case ARM::SXTABrr_rot:
+ case ARM::SXTAHrr:
+ case ARM::SXTAHrr_rot:
+ case ARM::SXTBr:
+ case ARM::SXTBr_rot:
+ case ARM::SXTHr:
+ case ARM::SXTHr_rot:
+ case ARM::TEQri:
+ case ARM::TEQrr:
+ case ARM::TEQrs:
+ case ARM::TPsoft:
+ case ARM::TSTri:
+ case ARM::TSTrr:
+ case ARM::TSTrs:
+ case ARM::UBFX:
+ case ARM::UMAAL:
+ case ARM::UMLAL:
+ case ARM::UMULL:
+ case ARM::UXTABrr:
+ case ARM::UXTABrr_rot:
+ case ARM::UXTAHrr:
+ case ARM::UXTAHrr_rot:
+ case ARM::UXTB16r:
+ case ARM::UXTB16r_rot:
+ case ARM::UXTBr:
+ case ARM::UXTBr_rot:
+ case ARM::UXTHr:
+ case ARM::UXTHr_rot:
+ case ARM::VABALsv2i64:
+ case ARM::VABALsv4i32:
+ case ARM::VABALsv8i16:
+ case ARM::VABALuv2i64:
+ case ARM::VABALuv4i32:
+ case ARM::VABALuv8i16:
+ case ARM::VABAsv16i8:
+ case ARM::VABAsv2i32:
+ case ARM::VABAsv4i16:
+ case ARM::VABAsv4i32:
+ case ARM::VABAsv8i16:
+ case ARM::VABAsv8i8:
+ case ARM::VABAuv16i8:
+ case ARM::VABAuv2i32:
+ case ARM::VABAuv4i16:
+ case ARM::VABAuv4i32:
+ case ARM::VABAuv8i16:
+ case ARM::VABAuv8i8:
+ case ARM::VABDLsv2i64:
+ case ARM::VABDLsv4i32:
+ case ARM::VABDLsv8i16:
+ case ARM::VABDLuv2i64:
+ case ARM::VABDLuv4i32:
+ case ARM::VABDLuv8i16:
+ case ARM::VABDfd:
+ case ARM::VABDfq:
+ case ARM::VABDsv16i8:
+ case ARM::VABDsv2i32:
+ case ARM::VABDsv4i16:
+ case ARM::VABDsv4i32:
+ case ARM::VABDsv8i16:
+ case ARM::VABDsv8i8:
+ case ARM::VABDuv16i8:
+ case ARM::VABDuv2i32:
+ case ARM::VABDuv4i16:
+ case ARM::VABDuv4i32:
+ case ARM::VABDuv8i16:
+ case ARM::VABDuv8i8:
+ case ARM::VABSD:
+ case ARM::VABSS:
+ case ARM::VABSfd:
+ case ARM::VABSfd_sfp:
+ case ARM::VABSfq:
+ case ARM::VABSv16i8:
+ case ARM::VABSv2i32:
+ case ARM::VABSv4i16:
+ case ARM::VABSv4i32:
+ case ARM::VABSv8i16:
+ case ARM::VABSv8i8:
+ case ARM::VACGEd:
+ case ARM::VACGEq:
+ case ARM::VACGTd:
+ case ARM::VACGTq:
+ case ARM::VADDD:
+ case ARM::VADDHNv2i32:
+ case ARM::VADDHNv4i16:
+ case ARM::VADDHNv8i8:
+ case ARM::VADDLsv2i64:
+ case ARM::VADDLsv4i32:
+ case ARM::VADDLsv8i16:
+ case ARM::VADDLuv2i64:
+ case ARM::VADDLuv4i32:
+ case ARM::VADDLuv8i16:
+ case ARM::VADDS:
+ case ARM::VADDWsv2i64:
+ case ARM::VADDWsv4i32:
+ case ARM::VADDWsv8i16:
+ case ARM::VADDWuv2i64:
+ case ARM::VADDWuv4i32:
+ case ARM::VADDWuv8i16:
+ case ARM::VADDfd:
+ case ARM::VADDfd_sfp:
+ case ARM::VADDfq:
+ case ARM::VADDv16i8:
+ case ARM::VADDv1i64:
+ case ARM::VADDv2i32:
+ case ARM::VADDv2i64:
+ case ARM::VADDv4i16:
+ case ARM::VADDv4i32:
+ case ARM::VADDv8i16:
+ case ARM::VADDv8i8:
+ case ARM::VANDd:
+ case ARM::VANDq:
+ case ARM::VBICd:
+ case ARM::VBICq:
+ case ARM::VBSLd:
+ case ARM::VBSLq:
+ case ARM::VCEQfd:
+ case ARM::VCEQfq:
+ case ARM::VCEQv16i8:
+ case ARM::VCEQv2i32:
+ case ARM::VCEQv4i16:
+ case ARM::VCEQv4i32:
+ case ARM::VCEQv8i16:
+ case ARM::VCEQv8i8:
+ case ARM::VCGEfd:
+ case ARM::VCGEfq:
+ case ARM::VCGEsv16i8:
+ case ARM::VCGEsv2i32:
+ case ARM::VCGEsv4i16:
+ case ARM::VCGEsv4i32:
+ case ARM::VCGEsv8i16:
+ case ARM::VCGEsv8i8:
+ case ARM::VCGEuv16i8:
+ case ARM::VCGEuv2i32:
+ case ARM::VCGEuv4i16:
+ case ARM::VCGEuv4i32:
+ case ARM::VCGEuv8i16:
+ case ARM::VCGEuv8i8:
+ case ARM::VCGTfd:
+ case ARM::VCGTfq:
+ case ARM::VCGTsv16i8:
+ case ARM::VCGTsv2i32:
+ case ARM::VCGTsv4i16:
+ case ARM::VCGTsv4i32:
+ case ARM::VCGTsv8i16:
+ case ARM::VCGTsv8i8:
+ case ARM::VCGTuv16i8:
+ case ARM::VCGTuv2i32:
+ case ARM::VCGTuv4i16:
+ case ARM::VCGTuv4i32:
+ case ARM::VCGTuv8i16:
+ case ARM::VCGTuv8i8:
+ case ARM::VCLSv16i8:
+ case ARM::VCLSv2i32:
+ case ARM::VCLSv4i16:
+ case ARM::VCLSv4i32:
+ case ARM::VCLSv8i16:
+ case ARM::VCLSv8i8:
+ case ARM::VCLZv16i8:
+ case ARM::VCLZv2i32:
+ case ARM::VCLZv4i16:
+ case ARM::VCLZv4i32:
+ case ARM::VCLZv8i16:
+ case ARM::VCLZv8i8:
+ case ARM::VCMPED:
+ case ARM::VCMPES:
+ case ARM::VCMPEZD:
+ case ARM::VCMPEZS:
+ case ARM::VCNTd:
+ case ARM::VCNTq:
+ case ARM::VCVTDS:
+ case ARM::VCVTSD:
+ case ARM::VCVTf2sd:
+ case ARM::VCVTf2sd_sfp:
+ case ARM::VCVTf2sq:
+ case ARM::VCVTf2ud:
+ case ARM::VCVTf2ud_sfp:
+ case ARM::VCVTf2uq:
+ case ARM::VCVTf2xsd:
+ case ARM::VCVTf2xsq:
+ case ARM::VCVTf2xud:
+ case ARM::VCVTf2xuq:
+ case ARM::VCVTs2fd:
+ case ARM::VCVTs2fd_sfp:
+ case ARM::VCVTs2fq:
+ case ARM::VCVTu2fd:
+ case ARM::VCVTu2fd_sfp:
+ case ARM::VCVTu2fq:
+ case ARM::VCVTxs2fd:
+ case ARM::VCVTxs2fq:
+ case ARM::VCVTxu2fd:
+ case ARM::VCVTxu2fq:
+ case ARM::VDIVD:
+ case ARM::VDIVS:
+ case ARM::VDUP16d:
+ case ARM::VDUP16q:
+ case ARM::VDUP32d:
+ case ARM::VDUP32q:
+ case ARM::VDUP8d:
+ case ARM::VDUP8q:
+ case ARM::VDUPLN16d:
+ case ARM::VDUPLN16q:
+ case ARM::VDUPLN32d:
+ case ARM::VDUPLN32q:
+ case ARM::VDUPLN8d:
+ case ARM::VDUPLN8q:
+ case ARM::VDUPLNfd:
+ case ARM::VDUPLNfq:
+ case ARM::VDUPfd:
+ case ARM::VDUPfdf:
+ case ARM::VDUPfq:
+ case ARM::VDUPfqf:
+ case ARM::VEORd:
+ case ARM::VEORq:
+ case ARM::VEXTd16:
+ case ARM::VEXTd32:
+ case ARM::VEXTd8:
+ case ARM::VEXTdf:
+ case ARM::VEXTq16:
+ case ARM::VEXTq32:
+ case ARM::VEXTq8:
+ case ARM::VEXTqf:
+ case ARM::VGETLNi32:
+ case ARM::VGETLNs16:
+ case ARM::VGETLNs8:
+ case ARM::VGETLNu16:
+ case ARM::VGETLNu8:
+ case ARM::VHADDsv16i8:
+ case ARM::VHADDsv2i32:
+ case ARM::VHADDsv4i16:
+ case ARM::VHADDsv4i32:
+ case ARM::VHADDsv8i16:
+ case ARM::VHADDsv8i8:
+ case ARM::VHADDuv16i8:
+ case ARM::VHADDuv2i32:
+ case ARM::VHADDuv4i16:
+ case ARM::VHADDuv4i32:
+ case ARM::VHADDuv8i16:
+ case ARM::VHADDuv8i8:
+ case ARM::VHSUBsv16i8:
+ case ARM::VHSUBsv2i32:
+ case ARM::VHSUBsv4i16:
+ case ARM::VHSUBsv4i32:
+ case ARM::VHSUBsv8i16:
+ case ARM::VHSUBsv8i8:
+ case ARM::VHSUBuv16i8:
+ case ARM::VHSUBuv2i32:
+ case ARM::VHSUBuv4i16:
+ case ARM::VHSUBuv4i32:
+ case ARM::VHSUBuv8i16:
+ case ARM::VHSUBuv8i8:
+ case ARM::VLD1d16:
+ case ARM::VLD1d32:
+ case ARM::VLD1d64:
+ case ARM::VLD1d8:
+ case ARM::VLD1df:
+ case ARM::VLD1q16:
+ case ARM::VLD1q32:
+ case ARM::VLD1q64:
+ case ARM::VLD1q8:
+ case ARM::VLD1qf:
+ case ARM::VLD2LNd16:
+ case ARM::VLD2LNd32:
+ case ARM::VLD2LNd8:
+ case ARM::VLD2LNq16a:
+ case ARM::VLD2LNq16b:
+ case ARM::VLD2LNq32a:
+ case ARM::VLD2LNq32b:
+ case ARM::VLD2d16:
+ case ARM::VLD2d32:
+ case ARM::VLD2d64:
+ case ARM::VLD2d8:
+ case ARM::VLD2q16:
+ case ARM::VLD2q32:
+ case ARM::VLD2q8:
+ case ARM::VLD3LNd16:
+ case ARM::VLD3LNd32:
+ case ARM::VLD3LNd8:
+ case ARM::VLD3LNq16a:
+ case ARM::VLD3LNq16b:
+ case ARM::VLD3LNq32a:
+ case ARM::VLD3LNq32b:
+ case ARM::VLD3d16:
+ case ARM::VLD3d32:
+ case ARM::VLD3d64:
+ case ARM::VLD3d8:
+ case ARM::VLD3q16a:
+ case ARM::VLD3q16b:
+ case ARM::VLD3q32a:
+ case ARM::VLD3q32b:
+ case ARM::VLD3q8a:
+ case ARM::VLD3q8b:
+ case ARM::VLD4LNd16:
+ case ARM::VLD4LNd32:
+ case ARM::VLD4LNd8:
+ case ARM::VLD4LNq16a:
+ case ARM::VLD4LNq16b:
+ case ARM::VLD4LNq32a:
+ case ARM::VLD4LNq32b:
+ case ARM::VLD4d16:
+ case ARM::VLD4d32:
+ case ARM::VLD4d64:
+ case ARM::VLD4d8:
+ case ARM::VLD4q16a:
+ case ARM::VLD4q16b:
+ case ARM::VLD4q32a:
+ case ARM::VLD4q32b:
+ case ARM::VLD4q8a:
+ case ARM::VLD4q8b:
+ case ARM::VLDMD:
+ case ARM::VLDMS:
+ case ARM::VLDRD:
+ case ARM::VLDRQ:
+ case ARM::VLDRS:
+ case ARM::VMAXfd:
+ case ARM::VMAXfq:
+ case ARM::VMAXsv16i8:
+ case ARM::VMAXsv2i32:
+ case ARM::VMAXsv4i16:
+ case ARM::VMAXsv4i32:
+ case ARM::VMAXsv8i16:
+ case ARM::VMAXsv8i8:
+ case ARM::VMAXuv16i8:
+ case ARM::VMAXuv2i32:
+ case ARM::VMAXuv4i16:
+ case ARM::VMAXuv4i32:
+ case ARM::VMAXuv8i16:
+ case ARM::VMAXuv8i8:
+ case ARM::VMINfd:
+ case ARM::VMINfq:
+ case ARM::VMINsv16i8:
+ case ARM::VMINsv2i32:
+ case ARM::VMINsv4i16:
+ case ARM::VMINsv4i32:
+ case ARM::VMINsv8i16:
+ case ARM::VMINsv8i8:
+ case ARM::VMINuv16i8:
+ case ARM::VMINuv2i32:
+ case ARM::VMINuv4i16:
+ case ARM::VMINuv4i32:
+ case ARM::VMINuv8i16:
+ case ARM::VMINuv8i8:
+ case ARM::VMLAD:
+ case ARM::VMLALslsv2i32:
+ case ARM::VMLALslsv4i16:
+ case ARM::VMLALsluv2i32:
+ case ARM::VMLALsluv4i16:
+ case ARM::VMLALsv2i64:
+ case ARM::VMLALsv4i32:
+ case ARM::VMLALsv8i16:
+ case ARM::VMLALuv2i64:
+ case ARM::VMLALuv4i32:
+ case ARM::VMLALuv8i16:
+ case ARM::VMLAS:
+ case ARM::VMLAfd:
+ case ARM::VMLAfq:
+ case ARM::VMLAslfd:
+ case ARM::VMLAslfq:
+ case ARM::VMLAslv2i32:
+ case ARM::VMLAslv4i16:
+ case ARM::VMLAslv4i32:
+ case ARM::VMLAslv8i16:
+ case ARM::VMLAv16i8:
+ case ARM::VMLAv2i32:
+ case ARM::VMLAv4i16:
+ case ARM::VMLAv4i32:
+ case ARM::VMLAv8i16:
+ case ARM::VMLAv8i8:
+ case ARM::VMLSD:
+ case ARM::VMLSLslsv2i32:
+ case ARM::VMLSLslsv4i16:
+ case ARM::VMLSLsluv2i32:
+ case ARM::VMLSLsluv4i16:
+ case ARM::VMLSLsv2i64:
+ case ARM::VMLSLsv4i32:
+ case ARM::VMLSLsv8i16:
+ case ARM::VMLSLuv2i64:
+ case ARM::VMLSLuv4i32:
+ case ARM::VMLSLuv8i16:
+ case ARM::VMLSS:
+ case ARM::VMLSfd:
+ case ARM::VMLSfq:
+ case ARM::VMLSslfd:
+ case ARM::VMLSslfq:
+ case ARM::VMLSslv2i32:
+ case ARM::VMLSslv4i16:
+ case ARM::VMLSslv4i32:
+ case ARM::VMLSslv8i16:
+ case ARM::VMLSv16i8:
+ case ARM::VMLSv2i32:
+ case ARM::VMLSv4i16:
+ case ARM::VMLSv4i32:
+ case ARM::VMLSv8i16:
+ case ARM::VMLSv8i8:
+ case ARM::VMOVD:
+ case ARM::VMOVDRR:
+ case ARM::VMOVDcc:
+ case ARM::VMOVDneon:
+ case ARM::VMOVLsv2i64:
+ case ARM::VMOVLsv4i32:
+ case ARM::VMOVLsv8i16:
+ case ARM::VMOVLuv2i64:
+ case ARM::VMOVLuv4i32:
+ case ARM::VMOVLuv8i16:
+ case ARM::VMOVNv2i32:
+ case ARM::VMOVNv4i16:
+ case ARM::VMOVNv8i8:
+ case ARM::VMOVQ:
+ case ARM::VMOVRRD:
+ case ARM::VMOVRS:
+ case ARM::VMOVS:
+ case ARM::VMOVSR:
+ case ARM::VMOVScc:
+ case ARM::VMOVv16i8:
+ case ARM::VMOVv1i64:
+ case ARM::VMOVv2i32:
+ case ARM::VMOVv2i64:
+ case ARM::VMOVv4i16:
+ case ARM::VMOVv4i32:
+ case ARM::VMOVv8i16:
+ case ARM::VMOVv8i8:
+ case ARM::VMULD:
+ case ARM::VMULLp:
+ case ARM::VMULLslsv2i32:
+ case ARM::VMULLslsv4i16:
+ case ARM::VMULLsluv2i32:
+ case ARM::VMULLsluv4i16:
+ case ARM::VMULLsv2i64:
+ case ARM::VMULLsv4i32:
+ case ARM::VMULLsv8i16:
+ case ARM::VMULLuv2i64:
+ case ARM::VMULLuv4i32:
+ case ARM::VMULLuv8i16:
+ case ARM::VMULS:
+ case ARM::VMULfd:
+ case ARM::VMULfd_sfp:
+ case ARM::VMULfq:
+ case ARM::VMULpd:
+ case ARM::VMULpq:
+ case ARM::VMULslfd:
+ case ARM::VMULslfq:
+ case ARM::VMULslv2i32:
+ case ARM::VMULslv4i16:
+ case ARM::VMULslv4i32:
+ case ARM::VMULslv8i16:
+ case ARM::VMULv16i8:
+ case ARM::VMULv2i32:
+ case ARM::VMULv4i16:
+ case ARM::VMULv4i32:
+ case ARM::VMULv8i16:
+ case ARM::VMULv8i8:
+ case ARM::VMVNd:
+ case ARM::VMVNq:
+ case ARM::VNEGD:
+ case ARM::VNEGDcc:
+ case ARM::VNEGS:
+ case ARM::VNEGScc:
+ case ARM::VNEGf32d:
+ case ARM::VNEGf32d_sfp:
+ case ARM::VNEGf32q:
+ case ARM::VNEGs16d:
+ case ARM::VNEGs16q:
+ case ARM::VNEGs32d:
+ case ARM::VNEGs32q:
+ case ARM::VNEGs8d:
+ case ARM::VNEGs8q:
+ case ARM::VNMLAD:
+ case ARM::VNMLAS:
+ case ARM::VNMLSD:
+ case ARM::VNMLSS:
+ case ARM::VNMULD:
+ case ARM::VNMULS:
+ case ARM::VORNd:
+ case ARM::VORNq:
+ case ARM::VORRd:
+ case ARM::VORRq:
+ case ARM::VPADALsv16i8:
+ case ARM::VPADALsv2i32:
+ case ARM::VPADALsv4i16:
+ case ARM::VPADALsv4i32:
+ case ARM::VPADALsv8i16:
+ case ARM::VPADALsv8i8:
+ case ARM::VPADALuv16i8:
+ case ARM::VPADALuv2i32:
+ case ARM::VPADALuv4i16:
+ case ARM::VPADALuv4i32:
+ case ARM::VPADALuv8i16:
+ case ARM::VPADALuv8i8:
+ case ARM::VPADDLsv16i8:
+ case ARM::VPADDLsv2i32:
+ case ARM::VPADDLsv4i16:
+ case ARM::VPADDLsv4i32:
+ case ARM::VPADDLsv8i16:
+ case ARM::VPADDLsv8i8:
+ case ARM::VPADDLuv16i8:
+ case ARM::VPADDLuv2i32:
+ case ARM::VPADDLuv4i16:
+ case ARM::VPADDLuv4i32:
+ case ARM::VPADDLuv8i16:
+ case ARM::VPADDLuv8i8:
+ case ARM::VPADDf:
+ case ARM::VPADDi16:
+ case ARM::VPADDi32:
+ case ARM::VPADDi8:
+ case ARM::VPMAXf:
+ case ARM::VPMAXs16:
+ case ARM::VPMAXs32:
+ case ARM::VPMAXs8:
+ case ARM::VPMAXu16:
+ case ARM::VPMAXu32:
+ case ARM::VPMAXu8:
+ case ARM::VPMINf:
+ case ARM::VPMINs16:
+ case ARM::VPMINs32:
+ case ARM::VPMINs8:
+ case ARM::VPMINu16:
+ case ARM::VPMINu32:
+ case ARM::VPMINu8:
+ case ARM::VQABSv16i8:
+ case ARM::VQABSv2i32:
+ case ARM::VQABSv4i16:
+ case ARM::VQABSv4i32:
+ case ARM::VQABSv8i16:
+ case ARM::VQABSv8i8:
+ case ARM::VQADDsv16i8:
+ case ARM::VQADDsv1i64:
+ case ARM::VQADDsv2i32:
+ case ARM::VQADDsv2i64:
+ case ARM::VQADDsv4i16:
+ case ARM::VQADDsv4i32:
+ case ARM::VQADDsv8i16:
+ case ARM::VQADDsv8i8:
+ case ARM::VQADDuv16i8:
+ case ARM::VQADDuv1i64:
+ case ARM::VQADDuv2i32:
+ case ARM::VQADDuv2i64:
+ case ARM::VQADDuv4i16:
+ case ARM::VQADDuv4i32:
+ case ARM::VQADDuv8i16:
+ case ARM::VQADDuv8i8:
+ case ARM::VQDMLALslv2i32:
+ case ARM::VQDMLALslv4i16:
+ case ARM::VQDMLALv2i64:
+ case ARM::VQDMLALv4i32:
+ case ARM::VQDMLSLslv2i32:
+ case ARM::VQDMLSLslv4i16:
+ case ARM::VQDMLSLv2i64:
+ case ARM::VQDMLSLv4i32:
+ case ARM::VQDMULHslv2i32:
+ case ARM::VQDMULHslv4i16:
+ case ARM::VQDMULHslv4i32:
+ case ARM::VQDMULHslv8i16:
+ case ARM::VQDMULHv2i32:
+ case ARM::VQDMULHv4i16:
+ case ARM::VQDMULHv4i32:
+ case ARM::VQDMULHv8i16:
+ case ARM::VQDMULLslv2i32:
+ case ARM::VQDMULLslv4i16:
+ case ARM::VQDMULLv2i64:
+ case ARM::VQDMULLv4i32:
+ case ARM::VQMOVNsuv2i32:
+ case ARM::VQMOVNsuv4i16:
+ case ARM::VQMOVNsuv8i8:
+ case ARM::VQMOVNsv2i32:
+ case ARM::VQMOVNsv4i16:
+ case ARM::VQMOVNsv8i8:
+ case ARM::VQMOVNuv2i32:
+ case ARM::VQMOVNuv4i16:
+ case ARM::VQMOVNuv8i8:
+ case ARM::VQNEGv16i8:
+ case ARM::VQNEGv2i32:
+ case ARM::VQNEGv4i16:
+ case ARM::VQNEGv4i32:
+ case ARM::VQNEGv8i16:
+ case ARM::VQNEGv8i8:
+ case ARM::VQRDMULHslv2i32:
+ case ARM::VQRDMULHslv4i16:
+ case ARM::VQRDMULHslv4i32:
+ case ARM::VQRDMULHslv8i16:
+ case ARM::VQRDMULHv2i32:
+ case ARM::VQRDMULHv4i16:
+ case ARM::VQRDMULHv4i32:
+ case ARM::VQRDMULHv8i16:
+ case ARM::VQRSHLsv16i8:
+ case ARM::VQRSHLsv1i64:
+ case ARM::VQRSHLsv2i32:
+ case ARM::VQRSHLsv2i64:
+ case ARM::VQRSHLsv4i16:
+ case ARM::VQRSHLsv4i32:
+ case ARM::VQRSHLsv8i16:
+ case ARM::VQRSHLsv8i8:
+ case ARM::VQRSHLuv16i8:
+ case ARM::VQRSHLuv1i64:
+ case ARM::VQRSHLuv2i32:
+ case ARM::VQRSHLuv2i64:
+ case ARM::VQRSHLuv4i16:
+ case ARM::VQRSHLuv4i32:
+ case ARM::VQRSHLuv8i16:
+ case ARM::VQRSHLuv8i8:
+ case ARM::VQRSHRNsv2i32:
+ case ARM::VQRSHRNsv4i16:
+ case ARM::VQRSHRNsv8i8:
+ case ARM::VQRSHRNuv2i32:
+ case ARM::VQRSHRNuv4i16:
+ case ARM::VQRSHRNuv8i8:
+ case ARM::VQRSHRUNv2i32:
+ case ARM::VQRSHRUNv4i16:
+ case ARM::VQRSHRUNv8i8:
+ case ARM::VQSHLsiv16i8:
+ case ARM::VQSHLsiv1i64:
+ case ARM::VQSHLsiv2i32:
+ case ARM::VQSHLsiv2i64:
+ case ARM::VQSHLsiv4i16:
+ case ARM::VQSHLsiv4i32:
+ case ARM::VQSHLsiv8i16:
+ case ARM::VQSHLsiv8i8:
+ case ARM::VQSHLsuv16i8:
+ case ARM::VQSHLsuv1i64:
+ case ARM::VQSHLsuv2i32:
+ case ARM::VQSHLsuv2i64:
+ case ARM::VQSHLsuv4i16:
+ case ARM::VQSHLsuv4i32:
+ case ARM::VQSHLsuv8i16:
+ case ARM::VQSHLsuv8i8:
+ case ARM::VQSHLsv16i8:
+ case ARM::VQSHLsv1i64:
+ case ARM::VQSHLsv2i32:
+ case ARM::VQSHLsv2i64:
+ case ARM::VQSHLsv4i16:
+ case ARM::VQSHLsv4i32:
+ case ARM::VQSHLsv8i16:
+ case ARM::VQSHLsv8i8:
+ case ARM::VQSHLuiv16i8:
+ case ARM::VQSHLuiv1i64:
+ case ARM::VQSHLuiv2i32:
+ case ARM::VQSHLuiv2i64:
+ case ARM::VQSHLuiv4i16:
+ case ARM::VQSHLuiv4i32:
+ case ARM::VQSHLuiv8i16:
+ case ARM::VQSHLuiv8i8:
+ case ARM::VQSHLuv16i8:
+ case ARM::VQSHLuv1i64:
+ case ARM::VQSHLuv2i32:
+ case ARM::VQSHLuv2i64:
+ case ARM::VQSHLuv4i16:
+ case ARM::VQSHLuv4i32:
+ case ARM::VQSHLuv8i16:
+ case ARM::VQSHLuv8i8:
+ case ARM::VQSHRNsv2i32:
+ case ARM::VQSHRNsv4i16:
+ case ARM::VQSHRNsv8i8:
+ case ARM::VQSHRNuv2i32:
+ case ARM::VQSHRNuv4i16:
+ case ARM::VQSHRNuv8i8:
+ case ARM::VQSHRUNv2i32:
+ case ARM::VQSHRUNv4i16:
+ case ARM::VQSHRUNv8i8:
+ case ARM::VQSUBsv16i8:
+ case ARM::VQSUBsv1i64:
+ case ARM::VQSUBsv2i32:
+ case ARM::VQSUBsv2i64:
+ case ARM::VQSUBsv4i16:
+ case ARM::VQSUBsv4i32:
+ case ARM::VQSUBsv8i16:
+ case ARM::VQSUBsv8i8:
+ case ARM::VQSUBuv16i8:
+ case ARM::VQSUBuv1i64:
+ case ARM::VQSUBuv2i32:
+ case ARM::VQSUBuv2i64:
+ case ARM::VQSUBuv4i16:
+ case ARM::VQSUBuv4i32:
+ case ARM::VQSUBuv8i16:
+ case ARM::VQSUBuv8i8:
+ case ARM::VRADDHNv2i32:
+ case ARM::VRADDHNv4i16:
+ case ARM::VRADDHNv8i8:
+ case ARM::VRECPEd:
+ case ARM::VRECPEfd:
+ case ARM::VRECPEfq:
+ case ARM::VRECPEq:
+ case ARM::VRECPSfd:
+ case ARM::VRECPSfq:
+ case ARM::VREV16d8:
+ case ARM::VREV16q8:
+ case ARM::VREV32d16:
+ case ARM::VREV32d8:
+ case ARM::VREV32q16:
+ case ARM::VREV32q8:
+ case ARM::VREV64d16:
+ case ARM::VREV64d32:
+ case ARM::VREV64d8:
+ case ARM::VREV64df:
+ case ARM::VREV64q16:
+ case ARM::VREV64q32:
+ case ARM::VREV64q8:
+ case ARM::VREV64qf:
+ case ARM::VRHADDsv16i8:
+ case ARM::VRHADDsv2i32:
+ case ARM::VRHADDsv4i16:
+ case ARM::VRHADDsv4i32:
+ case ARM::VRHADDsv8i16:
+ case ARM::VRHADDsv8i8:
+ case ARM::VRHADDuv16i8:
+ case ARM::VRHADDuv2i32:
+ case ARM::VRHADDuv4i16:
+ case ARM::VRHADDuv4i32:
+ case ARM::VRHADDuv8i16:
+ case ARM::VRHADDuv8i8:
+ case ARM::VRSHLsv16i8:
+ case ARM::VRSHLsv1i64:
+ case ARM::VRSHLsv2i32:
+ case ARM::VRSHLsv2i64:
+ case ARM::VRSHLsv4i16:
+ case ARM::VRSHLsv4i32:
+ case ARM::VRSHLsv8i16:
+ case ARM::VRSHLsv8i8:
+ case ARM::VRSHLuv16i8:
+ case ARM::VRSHLuv1i64:
+ case ARM::VRSHLuv2i32:
+ case ARM::VRSHLuv2i64:
+ case ARM::VRSHLuv4i16:
+ case ARM::VRSHLuv4i32:
+ case ARM::VRSHLuv8i16:
+ case ARM::VRSHLuv8i8:
+ case ARM::VRSHRNv2i32:
+ case ARM::VRSHRNv4i16:
+ case ARM::VRSHRNv8i8:
+ case ARM::VRSHRsv16i8:
+ case ARM::VRSHRsv1i64:
+ case ARM::VRSHRsv2i32:
+ case ARM::VRSHRsv2i64:
+ case ARM::VRSHRsv4i16:
+ case ARM::VRSHRsv4i32:
+ case ARM::VRSHRsv8i16:
+ case ARM::VRSHRsv8i8:
+ case ARM::VRSHRuv16i8:
+ case ARM::VRSHRuv1i64:
+ case ARM::VRSHRuv2i32:
+ case ARM::VRSHRuv2i64:
+ case ARM::VRSHRuv4i16:
+ case ARM::VRSHRuv4i32:
+ case ARM::VRSHRuv8i16:
+ case ARM::VRSHRuv8i8:
+ case ARM::VRSQRTEd:
+ case ARM::VRSQRTEfd:
+ case ARM::VRSQRTEfq:
+ case ARM::VRSQRTEq:
+ case ARM::VRSQRTSfd:
+ case ARM::VRSQRTSfq:
+ case ARM::VRSRAsv16i8:
+ case ARM::VRSRAsv1i64:
+ case ARM::VRSRAsv2i32:
+ case ARM::VRSRAsv2i64:
+ case ARM::VRSRAsv4i16:
+ case ARM::VRSRAsv4i32:
+ case ARM::VRSRAsv8i16:
+ case ARM::VRSRAsv8i8:
+ case ARM::VRSRAuv16i8:
+ case ARM::VRSRAuv1i64:
+ case ARM::VRSRAuv2i32:
+ case ARM::VRSRAuv2i64:
+ case ARM::VRSRAuv4i16:
+ case ARM::VRSRAuv4i32:
+ case ARM::VRSRAuv8i16:
+ case ARM::VRSRAuv8i8:
+ case ARM::VRSUBHNv2i32:
+ case ARM::VRSUBHNv4i16:
+ case ARM::VRSUBHNv8i8:
+ case ARM::VSETLNi16:
+ case ARM::VSETLNi32:
+ case ARM::VSETLNi8:
+ case ARM::VSHLLi16:
+ case ARM::VSHLLi32:
+ case ARM::VSHLLi8:
+ case ARM::VSHLLsv2i64:
+ case ARM::VSHLLsv4i32:
+ case ARM::VSHLLsv8i16:
+ case ARM::VSHLLuv2i64:
+ case ARM::VSHLLuv4i32:
+ case ARM::VSHLLuv8i16:
+ case ARM::VSHLiv16i8:
+ case ARM::VSHLiv1i64:
+ case ARM::VSHLiv2i32:
+ case ARM::VSHLiv2i64:
+ case ARM::VSHLiv4i16:
+ case ARM::VSHLiv4i32:
+ case ARM::VSHLiv8i16:
+ case ARM::VSHLiv8i8:
+ case ARM::VSHLsv16i8:
+ case ARM::VSHLsv1i64:
+ case ARM::VSHLsv2i32:
+ case ARM::VSHLsv2i64:
+ case ARM::VSHLsv4i16:
+ case ARM::VSHLsv4i32:
+ case ARM::VSHLsv8i16:
+ case ARM::VSHLsv8i8:
+ case ARM::VSHLuv16i8:
+ case ARM::VSHLuv1i64:
+ case ARM::VSHLuv2i32:
+ case ARM::VSHLuv2i64:
+ case ARM::VSHLuv4i16:
+ case ARM::VSHLuv4i32:
+ case ARM::VSHLuv8i16:
+ case ARM::VSHLuv8i8:
+ case ARM::VSHRNv2i32:
+ case ARM::VSHRNv4i16:
+ case ARM::VSHRNv8i8:
+ case ARM::VSHRsv16i8:
+ case ARM::VSHRsv1i64:
+ case ARM::VSHRsv2i32:
+ case ARM::VSHRsv2i64:
+ case ARM::VSHRsv4i16:
+ case ARM::VSHRsv4i32:
+ case ARM::VSHRsv8i16:
+ case ARM::VSHRsv8i8:
+ case ARM::VSHRuv16i8:
+ case ARM::VSHRuv1i64:
+ case ARM::VSHRuv2i32:
+ case ARM::VSHRuv2i64:
+ case ARM::VSHRuv4i16:
+ case ARM::VSHRuv4i32:
+ case ARM::VSHRuv8i16:
+ case ARM::VSHRuv8i8:
+ case ARM::VSITOD:
+ case ARM::VSITOS:
+ case ARM::VSLIv16i8:
+ case ARM::VSLIv1i64:
+ case ARM::VSLIv2i32:
+ case ARM::VSLIv2i64:
+ case ARM::VSLIv4i16:
+ case ARM::VSLIv4i32:
+ case ARM::VSLIv8i16:
+ case ARM::VSLIv8i8:
+ case ARM::VSQRTD:
+ case ARM::VSQRTS:
+ case ARM::VSRAsv16i8:
+ case ARM::VSRAsv1i64:
+ case ARM::VSRAsv2i32:
+ case ARM::VSRAsv2i64:
+ case ARM::VSRAsv4i16:
+ case ARM::VSRAsv4i32:
+ case ARM::VSRAsv8i16:
+ case ARM::VSRAsv8i8:
+ case ARM::VSRAuv16i8:
+ case ARM::VSRAuv1i64:
+ case ARM::VSRAuv2i32:
+ case ARM::VSRAuv2i64:
+ case ARM::VSRAuv4i16:
+ case ARM::VSRAuv4i32:
+ case ARM::VSRAuv8i16:
+ case ARM::VSRAuv8i8:
+ case ARM::VSRIv16i8:
+ case ARM::VSRIv1i64:
+ case ARM::VSRIv2i32:
+ case ARM::VSRIv2i64:
+ case ARM::VSRIv4i16:
+ case ARM::VSRIv4i32:
+ case ARM::VSRIv8i16:
+ case ARM::VSRIv8i8:
+ case ARM::VST1d16:
+ case ARM::VST1d32:
+ case ARM::VST1d64:
+ case ARM::VST1d8:
+ case ARM::VST1df:
+ case ARM::VST1q16:
+ case ARM::VST1q32:
+ case ARM::VST1q64:
+ case ARM::VST1q8:
+ case ARM::VST1qf:
+ case ARM::VST2LNd16:
+ case ARM::VST2LNd32:
+ case ARM::VST2LNd8:
+ case ARM::VST2LNq16a:
+ case ARM::VST2LNq16b:
+ case ARM::VST2LNq32a:
+ case ARM::VST2LNq32b:
+ case ARM::VST2d16:
+ case ARM::VST2d32:
+ case ARM::VST2d64:
+ case ARM::VST2d8:
+ case ARM::VST2q16:
+ case ARM::VST2q32:
+ case ARM::VST2q8:
+ case ARM::VST3LNd16:
+ case ARM::VST3LNd32:
+ case ARM::VST3LNd8:
+ case ARM::VST3LNq16a:
+ case ARM::VST3LNq16b:
+ case ARM::VST3LNq32a:
+ case ARM::VST3LNq32b:
+ case ARM::VST3d16:
+ case ARM::VST3d32:
+ case ARM::VST3d64:
+ case ARM::VST3d8:
+ case ARM::VST3q16a:
+ case ARM::VST3q16b:
+ case ARM::VST3q32a:
+ case ARM::VST3q32b:
+ case ARM::VST3q8a:
+ case ARM::VST3q8b:
+ case ARM::VST4LNd16:
+ case ARM::VST4LNd32:
+ case ARM::VST4LNd8:
+ case ARM::VST4LNq16a:
+ case ARM::VST4LNq16b:
+ case ARM::VST4LNq32a:
+ case ARM::VST4LNq32b:
+ case ARM::VST4d16:
+ case ARM::VST4d32:
+ case ARM::VST4d64:
+ case ARM::VST4d8:
+ case ARM::VST4q16a:
+ case ARM::VST4q16b:
+ case ARM::VST4q32a:
+ case ARM::VST4q32b:
+ case ARM::VST4q8a:
+ case ARM::VST4q8b:
+ case ARM::VSTMD:
+ case ARM::VSTMS:
+ case ARM::VSTRD:
+ case ARM::VSTRQ:
+ case ARM::VSTRS:
+ case ARM::VSUBD:
+ case ARM::VSUBHNv2i32:
+ case ARM::VSUBHNv4i16:
+ case ARM::VSUBHNv8i8:
+ case ARM::VSUBLsv2i64:
+ case ARM::VSUBLsv4i32:
+ case ARM::VSUBLsv8i16:
+ case ARM::VSUBLuv2i64:
+ case ARM::VSUBLuv4i32:
+ case ARM::VSUBLuv8i16:
+ case ARM::VSUBS:
+ case ARM::VSUBWsv2i64:
+ case ARM::VSUBWsv4i32:
+ case ARM::VSUBWsv8i16:
+ case ARM::VSUBWuv2i64:
+ case ARM::VSUBWuv4i32:
+ case ARM::VSUBWuv8i16:
+ case ARM::VSUBfd:
+ case ARM::VSUBfd_sfp:
+ case ARM::VSUBfq:
+ case ARM::VSUBv16i8:
+ case ARM::VSUBv1i64:
+ case ARM::VSUBv2i32:
+ case ARM::VSUBv2i64:
+ case ARM::VSUBv4i16:
+ case ARM::VSUBv4i32:
+ case ARM::VSUBv8i16:
+ case ARM::VSUBv8i8:
+ case ARM::VTBL1:
+ case ARM::VTBL2:
+ case ARM::VTBL3:
+ case ARM::VTBL4:
+ case ARM::VTBX1:
+ case ARM::VTBX2:
+ case ARM::VTBX3:
+ case ARM::VTBX4:
+ case ARM::VTOSIZD:
+ case ARM::VTOSIZS:
+ case ARM::VTOUIZD:
+ case ARM::VTOUIZS:
+ case ARM::VTRNd16:
+ case ARM::VTRNd32:
+ case ARM::VTRNd8:
+ case ARM::VTRNq16:
+ case ARM::VTRNq32:
+ case ARM::VTRNq8:
+ case ARM::VTSTv16i8:
+ case ARM::VTSTv2i32:
+ case ARM::VTSTv4i16:
+ case ARM::VTSTv4i32:
+ case ARM::VTSTv8i16:
+ case ARM::VTSTv8i8:
+ case ARM::VUITOD:
+ case ARM::VUITOS:
+ case ARM::VUZPd16:
+ case ARM::VUZPd32:
+ case ARM::VUZPd8:
+ case ARM::VUZPq16:
+ case ARM::VUZPq32:
+ case ARM::VUZPq8:
+ case ARM::VZIPd16:
+ case ARM::VZIPd32:
+ case ARM::VZIPd8:
+ case ARM::VZIPq16:
+ case ARM::VZIPq32:
+ case ARM::VZIPq8:
+ case ARM::t2ADCSri:
+ case ARM::t2ADCSrr:
+ case ARM::t2ADCSrs:
+ case ARM::t2ADCri:
+ case ARM::t2ADCrr:
+ case ARM::t2ADCrs:
+ case ARM::t2ADDSri:
+ case ARM::t2ADDSrr:
+ case ARM::t2ADDSrs:
+ case ARM::t2ADDrSPi:
+ case ARM::t2ADDrSPi12:
+ case ARM::t2ADDrSPs:
+ case ARM::t2ADDri:
+ case ARM::t2ADDri12:
+ case ARM::t2ADDrr:
+ case ARM::t2ADDrs:
+ case ARM::t2ANDri:
+ case ARM::t2ANDrr:
+ case ARM::t2ANDrs:
+ case ARM::t2ASRri:
+ case ARM::t2ASRrr:
+ case ARM::t2B:
+ case ARM::t2BFC:
+ case ARM::t2BICri:
+ case ARM::t2BICrr:
+ case ARM::t2BICrs:
+ case ARM::t2BR_JT:
+ case ARM::t2Bcc:
+ case ARM::t2CLZ:
+ case ARM::t2CMNri:
+ case ARM::t2CMNrr:
+ case ARM::t2CMNrs:
+ case ARM::t2CMNzri:
+ case ARM::t2CMNzrr:
+ case ARM::t2CMNzrs:
+ case ARM::t2CMPri:
+ case ARM::t2CMPrr:
+ case ARM::t2CMPrs:
+ case ARM::t2CMPzri:
+ case ARM::t2CMPzrr:
+ case ARM::t2CMPzrs:
+ case ARM::t2EORri:
+ case ARM::t2EORrr:
+ case ARM::t2EORrs:
+ case ARM::t2IT:
+ case ARM::t2Int_MemBarrierV7:
+ case ARM::t2Int_SyncBarrierV7:
+ case ARM::t2Int_eh_sjlj_setjmp:
+ case ARM::t2LDM:
+ case ARM::t2LDM_RET:
+ case ARM::t2LDRB_POST:
+ case ARM::t2LDRB_PRE:
+ case ARM::t2LDRBi12:
+ case ARM::t2LDRBi8:
+ case ARM::t2LDRBpci:
+ case ARM::t2LDRBs:
+ case ARM::t2LDRDi8:
+ case ARM::t2LDRDpci:
+ case ARM::t2LDREX:
+ case ARM::t2LDREXB:
+ case ARM::t2LDREXD:
+ case ARM::t2LDREXH:
+ case ARM::t2LDRH_POST:
+ case ARM::t2LDRH_PRE:
+ case ARM::t2LDRHi12:
+ case ARM::t2LDRHi8:
+ case ARM::t2LDRHpci:
+ case ARM::t2LDRHs:
+ case ARM::t2LDRSB_POST:
+ case ARM::t2LDRSB_PRE:
+ case ARM::t2LDRSBi12:
+ case ARM::t2LDRSBi8:
+ case ARM::t2LDRSBpci:
+ case ARM::t2LDRSBs:
+ case ARM::t2LDRSH_POST:
+ case ARM::t2LDRSH_PRE:
+ case ARM::t2LDRSHi12:
+ case ARM::t2LDRSHi8:
+ case ARM::t2LDRSHpci:
+ case ARM::t2LDRSHs:
+ case ARM::t2LDR_POST:
+ case ARM::t2LDR_PRE:
+ case ARM::t2LDRi12:
+ case ARM::t2LDRi8:
+ case ARM::t2LDRpci:
+ case ARM::t2LDRpci_pic:
+ case ARM::t2LDRs:
+ case ARM::t2LEApcrel:
+ case ARM::t2LEApcrelJT:
+ case ARM::t2LSLri:
+ case ARM::t2LSLrr:
+ case ARM::t2LSRri:
+ case ARM::t2LSRrr:
+ case ARM::t2MLA:
+ case ARM::t2MLS:
+ case ARM::t2MOVCCasr:
+ case ARM::t2MOVCCi:
+ case ARM::t2MOVCClsl:
+ case ARM::t2MOVCClsr:
+ case ARM::t2MOVCCr:
+ case ARM::t2MOVCCror:
+ case ARM::t2MOVTi16:
+ case ARM::t2MOVi:
+ case ARM::t2MOVi16:
+ case ARM::t2MOVi32imm:
+ case ARM::t2MOVr:
+ case ARM::t2MOVrx:
+ case ARM::t2MOVsra_flag:
+ case ARM::t2MOVsrl_flag:
+ case ARM::t2MUL:
+ case ARM::t2MVNi:
+ case ARM::t2MVNr:
+ case ARM::t2MVNs:
+ case ARM::t2ORNri:
+ case ARM::t2ORNrr:
+ case ARM::t2ORNrs:
+ case ARM::t2ORRri:
+ case ARM::t2ORRrr:
+ case ARM::t2ORRrs:
+ case ARM::t2PKHBT:
+ case ARM::t2PKHTB:
+ case ARM::t2REV:
+ case ARM::t2REV16:
+ case ARM::t2REVSH:
+ case ARM::t2RORri:
+ case ARM::t2RORrr:
+ case ARM::t2RSBSri:
+ case ARM::t2RSBSrs:
+ case ARM::t2RSBri:
+ case ARM::t2RSBrs:
+ case ARM::t2SBCSri:
+ case ARM::t2SBCSrr:
+ case ARM::t2SBCSrs:
+ case ARM::t2SBCri:
+ case ARM::t2SBCrr:
+ case ARM::t2SBCrs:
+ case ARM::t2SBFX:
+ case ARM::t2SMLABB:
+ case ARM::t2SMLABT:
+ case ARM::t2SMLAL:
+ case ARM::t2SMLATB:
+ case ARM::t2SMLATT:
+ case ARM::t2SMLAWB:
+ case ARM::t2SMLAWT:
+ case ARM::t2SMMLA:
+ case ARM::t2SMMLS:
+ case ARM::t2SMMUL:
+ case ARM::t2SMULBB:
+ case ARM::t2SMULBT:
+ case ARM::t2SMULL:
+ case ARM::t2SMULTB:
+ case ARM::t2SMULTT:
+ case ARM::t2SMULWB:
+ case ARM::t2SMULWT:
+ case ARM::t2STM:
+ case ARM::t2STRB_POST:
+ case ARM::t2STRB_PRE:
+ case ARM::t2STRBi12:
+ case ARM::t2STRBi8:
+ case ARM::t2STRBs:
+ case ARM::t2STRDi8:
+ case ARM::t2STREX:
+ case ARM::t2STREXB:
+ case ARM::t2STREXD:
+ case ARM::t2STREXH:
+ case ARM::t2STRH_POST:
+ case ARM::t2STRH_PRE:
+ case ARM::t2STRHi12:
+ case ARM::t2STRHi8:
+ case ARM::t2STRHs:
+ case ARM::t2STR_POST:
+ case ARM::t2STR_PRE:
+ case ARM::t2STRi12:
+ case ARM::t2STRi8:
+ case ARM::t2STRs:
+ case ARM::t2SUBSri:
+ case ARM::t2SUBSrr:
+ case ARM::t2SUBSrs:
+ case ARM::t2SUBrSPi:
+ case ARM::t2SUBrSPi12:
+ case ARM::t2SUBrSPi12_:
+ case ARM::t2SUBrSPi_:
+ case ARM::t2SUBrSPs:
+ case ARM::t2SUBrSPs_:
+ case ARM::t2SUBri:
+ case ARM::t2SUBri12:
+ case ARM::t2SUBrr:
+ case ARM::t2SUBrs:
+ case ARM::t2SXTABrr:
+ case ARM::t2SXTABrr_rot:
+ case ARM::t2SXTAHrr:
+ case ARM::t2SXTAHrr_rot:
+ case ARM::t2SXTBr:
+ case ARM::t2SXTBr_rot:
+ case ARM::t2SXTHr:
+ case ARM::t2SXTHr_rot:
+ case ARM::t2TBB:
+ case ARM::t2TBH:
+ case ARM::t2TEQri:
+ case ARM::t2TEQrr:
+ case ARM::t2TEQrs:
+ case ARM::t2TPsoft:
+ case ARM::t2TSTri:
+ case ARM::t2TSTrr:
+ case ARM::t2TSTrs:
+ case ARM::t2UBFX:
+ case ARM::t2UMAAL:
+ case ARM::t2UMLAL:
+ case ARM::t2UMULL:
+ case ARM::t2UXTABrr:
+ case ARM::t2UXTABrr_rot:
+ case ARM::t2UXTAHrr:
+ case ARM::t2UXTAHrr_rot:
+ case ARM::t2UXTB16r:
+ case ARM::t2UXTB16r_rot:
+ case ARM::t2UXTBr:
+ case ARM::t2UXTBr_rot:
+ case ARM::t2UXTHr:
+ case ARM::t2UXTHr_rot:
+ case ARM::tADC:
+ case ARM::tADDhirr:
+ case ARM::tADDi3:
+ case ARM::tADDi8:
+ case ARM::tADDrPCi:
+ case ARM::tADDrSP:
+ case ARM::tADDrSPi:
+ case ARM::tADDrr:
+ case ARM::tADDspi:
+ case ARM::tADDspr:
+ case ARM::tADDspr_:
+ case ARM::tADJCALLSTACKDOWN:
+ case ARM::tADJCALLSTACKUP:
+ case ARM::tAND:
+ case ARM::tANDsp:
+ case ARM::tASRri:
+ case ARM::tASRrr:
+ case ARM::tB:
+ case ARM::tBIC:
+ case ARM::tBL:
+ case ARM::tBLXi:
+ case ARM::tBLXi_r9:
+ case ARM::tBLXr:
+ case ARM::tBLXr_r9:
+ case ARM::tBLr9:
+ case ARM::tBRIND:
+ case ARM::tBR_JTr:
+ case ARM::tBX:
+ case ARM::tBX_RET:
+ case ARM::tBX_RET_vararg:
+ case ARM::tBXr9:
+ case ARM::tBcc:
+ case ARM::tBfar:
+ case ARM::tCBNZ:
+ case ARM::tCBZ:
+ case ARM::tCMN:
+ case ARM::tCMNZ:
+ case ARM::tCMPhir:
+ case ARM::tCMPi8:
+ case ARM::tCMPr:
+ case ARM::tCMPzhir:
+ case ARM::tCMPzi8:
+ case ARM::tCMPzr:
+ case ARM::tEOR:
+ case ARM::tInt_eh_sjlj_setjmp:
+ case ARM::tLDM:
+ case ARM::tLDR:
+ case ARM::tLDRB:
+ case ARM::tLDRH:
+ case ARM::tLDRSB:
+ case ARM::tLDRSH:
+ case ARM::tLDRcp:
+ case ARM::tLDRpci:
+ case ARM::tLDRpci_pic:
+ case ARM::tLDRspi:
+ case ARM::tLEApcrel:
+ case ARM::tLEApcrelJT:
+ case ARM::tLSLri:
+ case ARM::tLSLrr:
+ case ARM::tLSRri:
+ case ARM::tLSRrr:
+ case ARM::tMOVCCi:
+ case ARM::tMOVCCr:
+ case ARM::tMOVCCr_pseudo:
+ case ARM::tMOVSr:
+ case ARM::tMOVgpr2gpr:
+ case ARM::tMOVgpr2tgpr:
+ case ARM::tMOVi8:
+ case ARM::tMOVr:
+ case ARM::tMOVtgpr2gpr:
+ case ARM::tMUL:
+ case ARM::tMVN:
+ case ARM::tORR:
+ case ARM::tPICADD:
+ case ARM::tPOP:
+ case ARM::tPOP_RET:
+ case ARM::tPUSH:
+ case ARM::tREV:
+ case ARM::tREV16:
+ case ARM::tREVSH:
+ case ARM::tROR:
+ case ARM::tRSB:
+ case ARM::tRestore:
+ case ARM::tSBC:
+ case ARM::tSTM:
+ case ARM::tSTR:
+ case ARM::tSTRB:
+ case ARM::tSTRH:
+ case ARM::tSTRspi:
+ case ARM::tSUBi3:
+ case ARM::tSUBi8:
+ case ARM::tSUBrr:
+ case ARM::tSUBspi:
+ case ARM::tSUBspi_:
+ case ARM::tSXTB:
+ case ARM::tSXTH:
+ case ARM::tSpill:
+ case ARM::tTPsoft:
+ case ARM::tTST:
+ case ARM::tUXTB:
+ case ARM::tUXTH: {
+ break;
+ }
+ default:
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Not supported instr: " << MI;
+ llvm_report_error(Msg.str());
+ }
+ return Value;
+}
+
diff --git a/libclamav/c++/ARMGenDAGISel.inc b/libclamav/c++/ARMGenDAGISel.inc
new file mode 100644
index 0000000..8ffbed3
--- /dev/null
+++ b/libclamav/c++/ARMGenDAGISel.inc
@@ -0,0 +1,39117 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// DAG Instruction Selector for the ARM target
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+// *** NOTE: This file is #included into the middle of the target
+// *** instruction selector class. These functions are really methods.
+
+// Include standard, target-independent definitions and methods used
+// by the instruction selector.
+#include "llvm/CodeGen/DAGISelHeader.h"
+
+
+// Node transformations.
+inline SDValue Transform_DSubReg_f64_other_reg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
+
+}
+inline SDValue Transform_DSubReg_f64_reg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
+
+}
+inline SDValue Transform_DSubReg_i16_reg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
+
+}
+inline SDValue Transform_DSubReg_i32_reg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
+
+}
+inline SDValue Transform_DSubReg_i8_reg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
+
+}
+inline SDValue Transform_SSubReg_f32_reg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
+
+}
+inline SDValue Transform_SubReg_i16_lane(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
+
+}
+inline SDValue Transform_SubReg_i32_lane(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
+
+}
+inline SDValue Transform_SubReg_i8_lane(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
+
+}
+inline SDValue Transform_VMOV_get_imm16(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 2, *CurDAG);
+
+}
+inline SDValue Transform_VMOV_get_imm32(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 4, *CurDAG);
+
+}
+inline SDValue Transform_VMOV_get_imm64(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 8, *CurDAG);
+
+}
+inline SDValue Transform_VMOV_get_imm8(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 1, *CurDAG);
+
+}
+inline SDValue Transform_hi16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
+
+}
+inline SDValue Transform_imm_comp_XFORM(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
+
+}
+inline SDValue Transform_imm_neg_XFORM(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
+
+}
+inline SDValue Transform_lo16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
+ MVT::i32);
+
+}
+inline SDValue Transform_so_imm2part_1(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_so_imm2part_2(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_so_imm_neg_XFORM(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
+
+}
+inline SDValue Transform_so_imm_not_XFORM(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
+
+}
+inline SDValue Transform_so_neg_imm2part_1(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_so_neg_imm2part_2(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_t2_so_imm2part_1(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_t2_so_imm2part_2(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_t2_so_imm_neg_XFORM(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
+
+}
+inline SDValue Transform_t2_so_imm_not_XFORM(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
+
+}
+inline SDValue Transform_t2_so_neg_imm2part_1(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_t2_so_neg_imm2part_2(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_thumb_immshifted_shamt(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+inline SDValue Transform_thumb_immshifted_val(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+
+}
+
+// Predicate functions.
+inline bool Predicate_atomic_cmp_swap_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_cmp_swap_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_cmp_swap_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_cmp_swap_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_add_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_add_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_add_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_add_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_and_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_and_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_and_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_and_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_max_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_max_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_max_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_max_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_min_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_min_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_min_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_min_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_nand_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_nand_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_nand_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_nand_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_or_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_or_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_or_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_or_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_sub_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_sub_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_sub_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_sub_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_umax_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_umax_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_umax_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_umax_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_umin_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_umin_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_umin_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_umin_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_xor_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_xor_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_xor_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_xor_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_swap_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_swap_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_swap_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_swap_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_bf_inv_mask_imm(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ uint32_t v = (uint32_t)N->getZExtValue();
+ if (v == 0xffffffff)
+ return 0;
+ // there can be 1's on either or both "outsides", all the "inside"
+ // bits must be 0's
+ unsigned int lsb = 0, msb = 31;
+ while (v & (1 << msb)) --msb;
+ while (v & (1 << lsb)) ++lsb;
+ for (unsigned int i = lsb; i <= msb; ++i) {
+ if (v & (1 << i))
+ return 0;
+ }
+ return 1;
+
+}
+inline bool Predicate_cvtff(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
+
+}
+inline bool Predicate_cvtfs(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
+
+}
+inline bool Predicate_cvtfu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
+
+}
+inline bool Predicate_cvtsf(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
+
+}
+inline bool Predicate_cvtss(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
+
+}
+inline bool Predicate_cvtsu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
+
+}
+inline bool Predicate_cvtuf(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
+
+}
+inline bool Predicate_cvtus(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
+
+}
+inline bool Predicate_cvtuu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
+
+}
+inline bool Predicate_extload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
+
+}
+inline bool Predicate_extloadf32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_extloadf64(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
+
+}
+inline bool Predicate_extloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_extloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_extloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_extloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_imm0_255(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)N->getZExtValue() < 256;
+
+}
+inline bool Predicate_imm0_255_comp(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ~((uint32_t)N->getZExtValue()) < 256;
+
+}
+inline bool Predicate_imm0_255_neg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)(-N->getZExtValue()) < 255;
+
+}
+inline bool Predicate_imm0_31(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (int32_t)N->getZExtValue() < 32;
+
+}
+inline bool Predicate_imm0_4095(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)N->getZExtValue() < 4096;
+
+}
+inline bool Predicate_imm0_4095_neg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)(-N->getZExtValue()) < 4096;
+
+}
+inline bool Predicate_imm0_65535(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)N->getZExtValue() < 65536;
+
+}
+inline bool Predicate_imm0_7(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)N->getZExtValue() < 8;
+
+}
+inline bool Predicate_imm0_7_neg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)-N->getZExtValue() < 8;
+
+}
+inline bool Predicate_imm16_31(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
+
+}
+inline bool Predicate_imm1_15(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
+
+}
+inline bool Predicate_imm1_31(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
+
+}
+inline bool Predicate_imm8_255(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
+
+}
+inline bool Predicate_imm8_255_neg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ unsigned Val = -N->getZExtValue();
+ return Val >= 8 && Val < 256;
+
+}
+inline bool Predicate_immAllOnes(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+ return N->isAllOnesValue();
+}
+inline bool Predicate_immAllOnesV(SDNode *N) {
+
+ return ISD::isBuildVectorAllOnes(N);
+
+}
+inline bool Predicate_immAllOnesV_bc(SDNode *N) {
+
+ return ISD::isBuildVectorAllOnes(N);
+
+}
+inline bool Predicate_immAllZerosV(SDNode *N) {
+
+ return ISD::isBuildVectorAllZeros(N);
+
+}
+inline bool Predicate_immAllZerosV_bc(SDNode *N) {
+
+ return ISD::isBuildVectorAllZeros(N);
+
+}
+inline bool Predicate_istore(SDNode *N) {
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_itruncstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_lo16AllZero(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Returns true if all low 16-bits are 0.
+ return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
+
+}
+inline bool Predicate_load(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
+
+}
+inline bool Predicate_post_store(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
+
+}
+inline bool Predicate_post_truncst(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
+
+}
+inline bool Predicate_post_truncstf32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_post_truncsti1(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_post_truncsti16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_post_truncsti32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_post_truncsti8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_pre_store(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+
+}
+inline bool Predicate_pre_truncst(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+
+}
+inline bool Predicate_pre_truncstf32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_pre_truncsti1(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_pre_truncsti16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_pre_truncsti32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_pre_truncsti8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_rot_imm(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ int32_t v = (int32_t)N->getZExtValue();
+ return v == 8 || v == 16 || v == 24;
+
+}
+inline bool Predicate_sext_16_node(SDNode *N) {
+
+ return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
+
+}
+inline bool Predicate_sextload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
+
+}
+inline bool Predicate_sextloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_sextloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_sextloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_sextloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_so_imm(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
+
+}
+inline bool Predicate_so_imm2part(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
+
+}
+inline bool Predicate_so_imm_neg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
+
+}
+inline bool Predicate_so_imm_not(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
+
+}
+inline bool Predicate_so_neg_imm2part(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
+
+}
+inline bool Predicate_store(SDNode *N) {
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_t2_so_imm(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
+
+}
+inline bool Predicate_t2_so_imm2part(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
+
+}
+inline bool Predicate_t2_so_imm_neg(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
+
+}
+inline bool Predicate_t2_so_imm_not(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
+
+}
+inline bool Predicate_t2_so_neg_imm2part(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
+
+}
+inline bool Predicate_thumb_immshifted(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
+
+}
+inline bool Predicate_truncstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_truncstoref32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_truncstoref64(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
+
+}
+inline bool Predicate_truncstorei16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_truncstorei32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_truncstorei8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_unindexedload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+}
+inline bool Predicate_unindexedstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+}
+inline bool Predicate_vfp_f32imm(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
+
+}
+inline bool Predicate_vfp_f64imm(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
+
+}
+inline bool Predicate_vmovImm16(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vmovImm32(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vmovImm64(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vmovImm8(SDNode *N) {
+
+ return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vtFP(SDNode *inN) {
+ VTSDNode *N = cast<VTSDNode>(inN);
+ return N->getVT().isFloatingPoint();
+}
+inline bool Predicate_vtInt(SDNode *inN) {
+ VTSDNode *N = cast<VTSDNode>(inN);
+ return N->getVT().isInteger();
+}
+inline bool Predicate_zextload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
+
+}
+inline bool Predicate_zextloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_zextloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_zextloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_zextloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+
+
+DISABLE_INLINE SDNode *Emit_0(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
+ SDValue Ops0[] = { N1, N2, N3, Tmp3, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+}
+SDNode *Select_ARMISD_BR2_JT(const SDValue &N) {
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_0(N, ARM::t2BR_JT);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_1(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ SDValue Ops0[] = { N1, N2, Tmp2, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N1.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain1);
+ Chain1 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, N2, Tmp2, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ Chain1 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ const SDValue Froms[] = {
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain1.getNode(), Chain1.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_3(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ SDValue Ops0[] = { N10, N11, N2, Tmp3, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+}
+SDNode *Select_ARMISD_BR_JT(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (ARMbrjt:isVoid (ld:i32 addrmode2:i32:$target)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Emits: (BR_JTm:isVoid addrmode2:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ if (SelectAddrMode2(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_2(N, ARM::BR_JTm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMbrjt:isVoid (add:i32 GPR:i32:$target, GPR:i32:$idx), (tjumptable:i32):$jt, (imm:i32):$id)
+ // Emits: (BR_JTadd:isVoid GPR:i32:$target, GPR:i32:$idx, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::ADD) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, ARM::BR_JTadd);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMbrjt:isVoid GPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Emits: (BR_JTr:isVoid GPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Pattern complexity = 9 cost = 1 size = 0
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_1(N, ARM::BR_JTr);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMbrjt:isVoid tGPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Emits: (tBR_JTr:isVoid tGPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_1(N, ARM::tBR_JTr);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ARMISD_CALL(const SDValue &N) {
+
+ // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (BL:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_4(N, ARM::BL, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (BLr9:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_4(N, ARM::BLr9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (tBLXi:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_4(N, ARM::tBLXi, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (tBLXi_r9:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_4(N, ARM::tBLXi_r9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (tBLXi:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::tBLXi, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (tBLXi_r9:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::tBLXi_r9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (BL:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::BL, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (BLr9:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::BLr9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid GPR:i32:$func)
+ // Emits: (BLX:isVoid GPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::BLX, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid GPR:i32:$func)
+ // Emits: (BLXr9:isVoid GPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::BLXr9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid GPR:i32:$dst)
+ // Emits: (tBLXr:isVoid GPR:i32:$dst)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::tBLXr, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall:isVoid GPR:i32:$dst)
+ // Emits: (tBLXr_r9:isVoid GPR:i32:$dst)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::tBLXr_r9, 1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_CALL_NOLINK(const SDValue &N) {
+
+ // Pattern: (ARMcall_nolink:isVoid GPR:i32:$func)
+ // Emits: (BX:isVoid GPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::BX, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall_nolink:isVoid GPR:i32:$func)
+ // Emits: (BXr9:isVoid GPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::BXr9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall_nolink:isVoid tGPR:i32:$func)
+ // Emits: (tBX:isVoid tGPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::tBX, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall_nolink:isVoid tGPR:i32:$func)
+ // Emits: (tBXr9:isVoid tGPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::tBXr9, 1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ Ops0.push_back(Tmp1);
+ Ops0.push_back(Tmp2);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ARMISD_CALL_PRED(const SDValue &N) {
+
+ // Pattern: (ARMcall_pred:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (BL_pred:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_5(N, ARM::BL_pred, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcall_pred:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (BLr9_pred:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_5(N, ARM::BLr9_pred, 1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_6(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_7(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_8(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_9(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp3, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_10(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N11, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_11(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_12(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_13(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_14(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_15(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+SDNode *Select_ARMISD_CMP(const SDValue &N) {
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, (sub:i32 0:i32, so_reg:i32:$b))
+ // Emits: (CMNrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ if (SelectShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_11(N, ARM::CMNrs, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (sub:i32 0:i32, t2_so_reg:i32:$rhs))
+ // Emits: (t2CMNrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ if (SelectT2ShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_13(N, ARM::t2CMNrs, CPTmpN11_0, CPTmpN11_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (CMPrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_8(N, ARM::CMPrs, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b))
+ // Emits: (CMNri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N11.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_9(N, ARM::CMNri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
+ // Emits: (t2CMNri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N11.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_9(N, ARM::t2CMNri);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2CMPrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_12(N, ARM::t2CMPrs, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, (sub:i32 0:i32, GPR:i32:$b))
+ // Emits: (CMNrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_10(N, ARM::CMNrr);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid tGPR:i32:$lhs, (sub:i32 0:i32, tGPR:i32:$rhs))
+ // Emits: (tCMN:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_10(N, ARM::tCMN);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (sub:i32 0:i32, GPR:i32:$rhs))
+ // Emits: (t2CMNrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_10(N, ARM::t2CMNrr);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (CMPri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_6(N, ARM::CMPri);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_255>>:$rhs)
+ // Emits: (tCMPi8:isVoid tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm0_255(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_6(N, ARM::tCMPi8);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2CMPri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_6(N, ARM::t2CMPri);
+ return Result;
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
+ // Emits: (t2CMNri:isVoid GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm_neg(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_14(N, ARM::t2CMNri);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
+ // Emits: (CMNri:isVoid GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm_neg(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_15(N, ARM::CMNri);
+ return Result;
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Emits: (CMPrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_7(N, ARM::CMPrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tCMPr:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_7(N, ARM::tCMPr);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2CMPrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_7(N, ARM::t2CMPrr);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_CMPFP(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (arm_cmpfp:isVoid DPR:f64:$a, DPR:f64:$b)
+ // Emits: (VCMPED:isVoid DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_7(N, ARM::VCMPED);
+ return Result;
+ }
+
+ // Pattern: (arm_cmpfp:isVoid SPR:f32:$a, SPR:f32:$b)
+ // Emits: (VCMPES:isVoid SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_7(N, ARM::VCMPES);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_16(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, N0, Tmp1, Tmp2);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+SDNode *Select_ARMISD_CMPFPw0(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (arm_cmpfp0:isVoid DPR:f64:$a)
+ // Emits: (VCMPEZD:isVoid DPR:f64:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_16(N, ARM::VCMPEZD);
+ return Result;
+ }
+
+ // Pattern: (arm_cmpfp0:isVoid SPR:f32:$a)
+ // Emits: (VCMPEZS:isVoid SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_16(N, ARM::VCMPEZS);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_17(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, Tmp3, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_18(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_19(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_20(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, CPTmpN01_0, CPTmpN01_1, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_21(const SDValue &N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_22(const SDValue &N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp3, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_24(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N01, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_25(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, CPTmpN00_0, CPTmpN00_1, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, so_reg:i32:$b), 0:i32)
+ // Emits: (TSTrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_19(N, ARM::TSTrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, so_reg:i32:$b), 0:i32)
+ // Emits: (TEQrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_19(N, ARM::TEQrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, so_reg:i32:$b))
+ // Emits: (CMNzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ if (SelectShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_11(N, ARM::CMNzrs, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 so_reg:i32:$b, GPR:i32:$a), 0:i32)
+ // Emits: (TSTrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ SDValue CPTmpN00_2;
+ if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_21(N, ARM::TSTrs, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 so_reg:i32:$b, GPR:i32:$a), 0:i32)
+ // Emits: (TEQrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ SDValue CPTmpN00_2;
+ if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_21(N, ARM::TEQrs, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, so_reg:i32:$b), GPR:i32:$a)
+ // Emits: (CMNzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_25(N, ARM::CMNzrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, t2_so_reg:i32:$rhs))
+ // Emits: (t2CMNzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ if (SelectT2ShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_13(N, ARM::t2CMNzrs, CPTmpN11_0, CPTmpN11_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs), 0:i32)
+ // Emits: (t2TSTrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_20(N, ARM::t2TSTrs, CPTmpN01_0, CPTmpN01_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs), 0:i32)
+ // Emits: (t2TEQrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_20(N, ARM::t2TEQrs, CPTmpN01_0, CPTmpN01_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, t2_so_reg:i32:$rhs), GPR:i32:$lhs)
+ // Emits: (t2CMNzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_27(N, ARM::t2CMNzrs, CPTmpN01_0, CPTmpN01_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs), 0:i32)
+ // Emits: (t2TSTrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_28(N, ARM::t2TSTrs, CPTmpN00_0, CPTmpN00_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs), 0:i32)
+ // Emits: (t2TEQrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 20 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_28(N, ARM::t2TEQrs, CPTmpN00_0, CPTmpN00_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b), 0:i32)
+ // Emits: (TSTri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_17(N, ARM::TSTri);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b), 0:i32)
+ // Emits: (TEQri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_17(N, ARM::TEQri);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (CMPzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_8(N, ARM::CMPzrs, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b))
+ // Emits: (CMNzri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N11.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_9(N, ARM::CMNzri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
+ // Emits: (t2CMNzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N11.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_9(N, ARM::t2CMNzri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), 0:i32)
+ // Emits: (t2TSTri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_17(N, ARM::t2TSTri);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), 0:i32)
+ // Emits: (t2TEQri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_17(N, ARM::t2TEQri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (CMPzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_22(N, ARM::CMPzrs, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b), GPR:i32:$a)
+ // Emits: (CMNzri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_23(N, ARM::CMNzri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
+ // Emits: (t2CMNzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_23(N, ARM::t2CMNzri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2CMPzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_12(N, ARM::t2CMPzrs, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2CMPzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_26(N, ARM::t2CMPzrs, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, GPR:i32:$b), 0:i32)
+ // Emits: (TSTrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_18(N, ARM::TSTrr);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, GPR:i32:$b), 0:i32)
+ // Emits: (TEQrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_18(N, ARM::TEQrr);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, GPR:i32:$b))
+ // Emits: (CMNzrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 11 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_10(N, ARM::CMNzrr);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, (sub:i32 0:i32, tGPR:i32:$rhs))
+ // Emits: (tCMNZ:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_10(N, ARM::tCMNZ);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 tGPR:i32:$lhs, tGPR:i32:$rhs), 0:i32)
+ // Emits: (tTST:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_18(N, ARM::tTST);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, GPR:i32:$rhs))
+ // Emits: (t2CMNzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_10(N, ARM::t2CMNzrr);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, GPR:i32:$rhs), 0:i32)
+ // Emits: (t2TSTrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_18(N, ARM::t2TSTrr);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, GPR:i32:$rhs), 0:i32)
+ // Emits: (t2TEQrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_18(N, ARM::t2TEQrr);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, GPR:i32:$b), GPR:i32:$a)
+ // Emits: (CMNzrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_24(N, ARM::CMNzrr);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, tGPR:i32:$rhs), tGPR:i32:$lhs)
+ // Emits: (tCMNZ:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_24(N, ARM::tCMNZ);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, GPR:i32:$rhs), GPR:i32:$lhs)
+ // Emits: (t2CMNzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_24(N, ARM::t2CMNzrr);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (CMPzri:isVoid GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_6(N, ARM::CMPzri);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_255>>:$rhs)
+ // Emits: (tCMPzi8:isVoid tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm0_255(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_6(N, ARM::tCMPzi8);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2CMPzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_6(N, ARM::t2CMPzri);
+ return Result;
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
+ // Emits: (t2CMNri:isVoid GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm_neg(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_14(N, ARM::t2CMNri);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
+ // Emits: (CMNri:isVoid GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm_neg(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_15(N, ARM::CMNri);
+ return Result;
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Emits: (CMPzrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_7(N, ARM::CMPzrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tCMPzr:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_7(N, ARM::tCMPzr);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2CMPzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_7(N, ARM::t2CMPzrr);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_29(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0);
+}
+SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(const SDValue &N) {
+
+ // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
+ // Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_29(N, ARM::Int_eh_sjlj_setjmp);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
+ // Emits: (tInt_eh_sjlj_setjmp:isVoid GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_29(N, ARM::tInt_eh_sjlj_setjmp);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
+ // Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_29(N, ARM::t2Int_eh_sjlj_setjmp);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_30(const SDValue &N, unsigned Opc0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Tmp0, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+SDNode *Select_ARMISD_FMSTAT(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_30(N, ARM::FMSTAT);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_31(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_32(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp3, Tmp4, Tmp5), 0);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp6, Tmp7);
+}
+SDNode *Select_ARMISD_FTOSI_f32(const SDValue &N) {
+
+ // Pattern: (arm_ftosi:f32 DPR:f64:$a)
+ // Emits: (VTOSIZD:f32 DPR:f64:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_31(N, ARM::VTOSIZD, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (arm_ftosi:f32 SPR:f32:$a)
+ // Emits: (VTOSIZS:f32 SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_31(N, ARM::VTOSIZS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (arm_ftosi:f32 SPR:f32:$a)
+ // Emits: (EXTRACT_SUBREG:f32 (VCVTf2sd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 4 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_FTOUI_f32(const SDValue &N) {
+
+ // Pattern: (arm_ftoui:f32 DPR:f64:$a)
+ // Emits: (VTOUIZD:f32 DPR:f64:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_31(N, ARM::VTOUIZD, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (arm_ftoui:f32 SPR:f32:$a)
+ // Emits: (VTOUIZS:f32 SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_31(N, ARM::VTOUIZS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (arm_ftoui:f32 SPR:f32:$a)
+ // Emits: (EXTRACT_SUBREG:f32 (VCVTf2ud_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 4 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_33(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+DISABLE_INLINE SDNode *Emit_34(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
+}
+SDNode *Select_ARMISD_MEMBARRIER(const SDValue &N) {
+
+ // Pattern: (ARMMemBarrierV7:isVoid)
+ // Emits: (Int_MemBarrierV7:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV7Ops())) {
+ SDNode *Result = Emit_33(N, ARM::Int_MemBarrierV7);
+ return Result;
+ }
+
+ // Pattern: (ARMMemBarrierV6:isVoid GPR:i32:$zero)
+ // Emits: (Int_MemBarrierV6:isVoid GPR:i32:$zero)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_34(N, ARM::Int_MemBarrierV6);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMMemBarrierV7:isVoid)
+ // Emits: (t2Int_MemBarrierV7:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_33(N, ARM::t2Int_MemBarrierV7);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_35(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_36(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_37(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, N010, Tmp1, Chain0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ARMISD_PIC_ADD_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
+ // Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::Wrapper) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
+ // Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::Wrapper) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (ARMpic_add:i32 GPR:i32:$a, (imm:i32):$cp)
+ // Emits: (PICADD:i32 GPR:i32:$a, (imm:i32):$cp)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::PICADD, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMpic_add:i32 GPR:i32:$lhs, (imm:i32):$cp)
+ // Emits: (tPICADD:i32 GPR:i32:$lhs, (imm:i32):$cp)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_36(N, ARM::tPICADD, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_38(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue Tmp0 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
+}
+DISABLE_INLINE SDNode *Emit_39(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { Chain, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 2 : 1);
+}
+SDNode *Select_ARMISD_RET_FLAG(const SDValue &N) {
+
+ // Pattern: (ARMretflag:isVoid)
+ // Emits: (BX_RET:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_38(N, ARM::BX_RET);
+ return Result;
+ }
+
+ // Pattern: (ARMretflag:isVoid)
+ // Emits: (tBX_RET:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb())) {
+ SDNode *Result = Emit_39(N, ARM::tBX_RET);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_40(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(1);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ARMISD_RRX_i32(const SDValue &N) {
+
+ // Pattern: (ARMrrx:i32 GPR:i32:$src)
+ // Emits: (MOVrx:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_40(N, ARM::MOVrx, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (ARMrrx:i32 GPR:i32:$src)
+ // Emits: (t2MOVrx:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_40(N, ARM::t2MOVrx, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_SITOF_f32(const SDValue &N) {
+
+ // Pattern: (arm_sitof:f32 SPR:f32:$a)
+ // Emits: (VSITOS:f32 SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_31(N, ARM::VSITOS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (arm_sitof:f32 SPR:f32:$a)
+ // Emits: (EXTRACT_SUBREG:f32 (VCVTs2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 4 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTs2fd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_SITOF_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_31(N, ARM::VSITOD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_41(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, Tmp2);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_42(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ARMISD_SRA_FLAG_i32(const SDValue &N) {
+
+ // Pattern: (ARMsra_flag:i32 GPR:i32:$src)
+ // Emits: (MOVsra_flag:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_41(N, ARM::MOVsra_flag, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (ARMsra_flag:i32 GPR:i32:$src)
+ // Emits: (t2MOVsra_flag:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_42(N, ARM::t2MOVsra_flag, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_SRL_FLAG_i32(const SDValue &N) {
+
+ // Pattern: (ARMsrl_flag:i32 GPR:i32:$src)
+ // Emits: (MOVsrl_flag:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_41(N, ARM::MOVsrl_flag, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (ARMsrl_flag:i32 GPR:i32:$src)
+ // Emits: (t2MOVsrl_flag:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_42(N, ARM::t2MOVsrl_flag, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_SYNCBARRIER(const SDValue &N) {
+
+ // Pattern: (ARMSyncBarrierV7:isVoid)
+ // Emits: (Int_SyncBarrierV7:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV7Ops())) {
+ SDNode *Result = Emit_33(N, ARM::Int_SyncBarrierV7);
+ return Result;
+ }
+
+ // Pattern: (ARMSyncBarrierV6:isVoid GPR:i32:$zero)
+ // Emits: (Int_SyncBarrierV6:isVoid GPR:i32:$zero)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_34(N, ARM::Int_SyncBarrierV6);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMSyncBarrierV7:isVoid)
+ // Emits: (t2Int_SyncBarrierV7:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_33(N, ARM::t2Int_SyncBarrierV7);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_43(const SDValue &N, unsigned Opc0) {
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32);
+}
+SDNode *Select_ARMISD_THREAD_POINTER_i32(const SDValue &N) {
+
+ // Pattern: (ARMthread_pointer:i32)
+ // Emits: (TPsoft:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_43(N, ARM::TPsoft);
+ return Result;
+ }
+
+ // Pattern: (ARMthread_pointer:i32)
+ // Emits: (tTPsoft:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb())) {
+ SDNode *Result = Emit_43(N, ARM::tTPsoft);
+ return Result;
+ }
+
+ // Pattern: (ARMthread_pointer:i32)
+ // Emits: (t2TPsoft:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_43(N, ARM::t2TPsoft);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_UITOF_f32(const SDValue &N) {
+
+ // Pattern: (arm_uitof:f32 SPR:f32:$a)
+ // Emits: (VUITOS:f32 SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_31(N, ARM::VUITOS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (arm_uitof:f32 SPR:f32:$a)
+ // Emits: (EXTRACT_SUBREG:f32 (VCVTu2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 4 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTu2fd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_UITOF_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_31(N, ARM::VUITOD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_44(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ARMISD_VCEQ_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, ARM::VCEQv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCEQ_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, ARM::VCEQv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCEQ_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, ARM::VCEQv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCEQ_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, ARM::VCEQv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCEQ_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (NEONvceq:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VCEQv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, ARM::VCEQv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvceq:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VCEQfd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_44(N, ARM::VCEQfd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCEQ_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (NEONvceq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VCEQv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, ARM::VCEQv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvceq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VCEQfq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_44(N, ARM::VCEQfq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGE_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGEsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGE_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGEsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGE_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGEsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGE_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGEsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGE_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (NEONvcge:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VCGEsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGEsv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvcge:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VCGEfd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_44(N, ARM::VCGEfd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGE_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (NEONvcge:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VCGEsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGEsv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvcge:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VCGEfq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_44(N, ARM::VCGEfq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGEU_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGEuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGEU_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGEuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGEU_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGEuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGEU_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGEuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGEU_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGEuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGEU_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGEuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGT_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGTsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGT_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGTsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGT_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGTsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGT_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGTsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGT_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (NEONvcgt:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VCGTsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGTsv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvcgt:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VCGTfd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_44(N, ARM::VCGTfd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGT_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (NEONvcgt:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VCGTsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGTsv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvcgt:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VCGTfq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_44(N, ARM::VCGTfq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGTU_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGTuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGTU_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, ARM::VCGTuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGTU_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGTuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGTU_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, ARM::VCGTuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGTU_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGTuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VCGTU_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, ARM::VCGTuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VDUP8d, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VDUP8q, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VDUP16d, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VDUP16q, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VDUP32d, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VDUP32q, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_45(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, Tmp1, Tmp2);
+}
+SDNode *Select_ARMISD_VDUP_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (NEONvdup:v2f32 (bitconvert:f32 GPR:i32:$src))
+ // Emits: (VDUPfd:v2f32 GPR:i32:$src)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ if (N0.getValueType() == MVT::f32 &&
+ N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_45(N, ARM::VDUPfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (NEONvdup:v2f32 SPR:f32:$src)
+ // Emits: (VDUPfdf:v2f32 SPR:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_31(N, ARM::VDUPfdf, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUP_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (NEONvdup:v4f32 (bitconvert:f32 GPR:i32:$src))
+ // Emits: (VDUPfq:v4f32 GPR:i32:$src)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ if (N0.getValueType() == MVT::f32 &&
+ N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_45(N, ARM::VDUPfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (NEONvdup:v4f32 SPR:f32:$src)
+ // Emits: (VDUPfqf:v4f32 SPR:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_31(N, ARM::VDUPfqf, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUPLANE_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLN8d, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_46(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_DSubReg_i8_reg(Tmp1.getNode());
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = Transform_SubReg_i8_lane(Tmp1.getNode());
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+}
+SDNode *Select_ARMISD_VDUPLANE_v16i8(const SDValue &N) {
+
+ // Pattern: (NEONvduplane:v16i8 DPR:v8i8:$src, (imm:i32):$lane)
+ // Emits: (VDUPLN8q:v16i8 DPR:v8i8:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLN8q, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (NEONvduplane:v16i8 QPR:v16i8:$src, (imm:i32):$lane)
+ // Emits: (VDUPLN8q:v16i8 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUPLANE_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLN16d, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_47(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_DSubReg_i16_reg(Tmp1.getNode());
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = Transform_SubReg_i16_lane(Tmp1.getNode());
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+}
+SDNode *Select_ARMISD_VDUPLANE_v8i16(const SDValue &N) {
+
+ // Pattern: (NEONvduplane:v8i16 DPR:v4i16:$src, (imm:i32):$lane)
+ // Emits: (VDUPLN16q:v8i16 DPR:v4i16:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLN16q, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (NEONvduplane:v8i16 QPR:v8i16:$src, (imm:i32):$lane)
+ // Emits: (VDUPLN16q:v8i16 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUPLANE_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLN32d, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_48(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_DSubReg_i32_reg(Tmp1.getNode());
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = Transform_SubReg_i32_lane(Tmp1.getNode());
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+}
+SDNode *Select_ARMISD_VDUPLANE_v4i32(const SDValue &N) {
+
+ // Pattern: (NEONvduplane:v4i32 DPR:v2i32:$src, (imm:i32):$lane)
+ // Emits: (VDUPLN32q:v4i32 DPR:v2i32:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLN32q, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (NEONvduplane:v4i32 QPR:v4i32:$src, (imm:i32):$lane)
+ // Emits: (VDUPLN32q:v4i32 (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_49(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_f64_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp5 = Transform_DSubReg_f64_other_reg(Tmp2.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, Tmp4, Tmp5);
+}
+SDNode *Select_ARMISD_VDUPLANE_v2i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::i64, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUPLANE_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLNfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUPLANE_v4f32(const SDValue &N) {
+
+ // Pattern: (NEONvduplane:v4f32 DPR:v2f32:$src, (imm:i32):$lane)
+ // Emits: (VDUPLNfq:v4f32 DPR:v2f32:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_35(N, ARM::VDUPLNfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (NEONvduplane:v4f32 QPR:v4f32:$src, (imm:i32):$lane)
+ // Emits: (VDUPLNfq:v4f32 (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VDUPLANE_v2f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::f64, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_50(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ARMISD_VEXT_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTd8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTq8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTd16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTq16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTd32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTq32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTdf, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VEXT_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VEXTqf, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VGETLANEs_i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (NEONvgetlanes:i32 DPR:v8i8:$src, (imm:i32):$lane)
+ // Emits: (VGETLNs8:i32 DPR:v8i8:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VGETLNs8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvgetlanes:i32 DPR:v4i16:$src, (imm:i32):$lane)
+ // Emits: (VGETLNs16:i32 DPR:v4i16:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VGETLNs16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (NEONvgetlanes:i32 QPR:v16i8:$src, (imm:i32):$lane)
+ // Emits: (VGETLNs8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNs8, MVT::v8i8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvgetlanes:i32 QPR:v8i16:$src, (imm:i32):$lane)
+ // Emits: (VGETLNs16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNs16, MVT::v4i16, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VGETLANEu_i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (NEONvgetlaneu:i32 DPR:v8i8:$src, (imm:i32):$lane)
+ // Emits: (VGETLNu8:i32 DPR:v8i8:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VGETLNu8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvgetlaneu:i32 DPR:v4i16:$src, (imm:i32):$lane)
+ // Emits: (VGETLNu16:i32 DPR:v4i16:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VGETLNu16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (NEONvgetlaneu:i32 QPR:v16i8:$src, (imm:i32):$lane)
+ // Emits: (VGETLNu8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNu8, MVT::v8i8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (NEONvgetlaneu:i32 QPR:v8i16:$src, (imm:i32):$lane)
+ // Emits: (VGETLNu16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNu16, MVT::v4i16, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VMOVDRR_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_44(N, ARM::VMOVDRR, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNs_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRNsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNs_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRNsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNs_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRNsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNsu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRUNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNsu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRUNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNsu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRUNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRNuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRNuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQRSHRNu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VQRSHRNuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLs_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsiv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLsu_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLsuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHLu_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VQSHLuiv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNs_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRNsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNs_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRNsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNs_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRNsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNsu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRUNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNsu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRUNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNsu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRUNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRNuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRNuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VQSHRNu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VQSHRNuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV16_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV16d8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV16_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV16q8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV32_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV32d8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV32_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV32q8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV32_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV32d16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV32_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV32q16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64d8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64q8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64d16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64q16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64d32, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64q32, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64df, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VREV64_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VREV64qf, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRN_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRN_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRN_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRs_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VRSHRu_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VRSHRuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHL_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHLiv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLi_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLi8, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLi_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLi16, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLi_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLi32, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLs_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLs_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLs_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLu_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLu_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHLLu_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_35(N, ARM::VSHLLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRN_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_35(N, ARM::VSHRNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRN_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_35(N, ARM::VSHRNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRN_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_35(N, ARM::VSHRNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRs_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSHRu_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::VSHRuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSLI_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSLIv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VSRI_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSRIv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VTST_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, ARM::VTSTv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VTST_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, ARM::VTSTv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VTST_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, ARM::VTSTv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VTST_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, ARM::VTSTv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VTST_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, ARM::VTSTv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_VTST_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, ARM::VTSTv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
+
+ // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
+ // Emits: (t2LEApcrel:i32 (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!Subtarget->useMovt())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_31(N, ARM::t2LEApcrel, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
+ // Emits: (t2LEApcrel:i32 (tconstpool:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_31(N, ARM::t2LEApcrel, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
+ // Emits: (t2MOVi32imm:i32 (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (Subtarget->useMovt())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_31(N, ARM::t2MOVi32imm, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
+ // Emits: (LEApcrel:i32 (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!Subtarget->useMovt())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_31(N, ARM::LEApcrel, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
+ // Emits: (LEApcrel:i32 (tconstpool:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_31(N, ARM::LEApcrel, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
+ // Emits: (MOVi32imm:i32 (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->useMovt())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_31(N, ARM::MOVi32imm, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
+ // Emits: (tLEApcrel:i32 (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_31(N, ARM::tLEApcrel, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
+ // Emits: (tLEApcrel:i32 (tconstpool:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_31(N, ARM::tLEApcrel, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_WrapperJT_i32(const SDValue &N) {
+
+ // Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
+ // Emits: (t2LEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::t2LEApcrelJT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
+ // Emits: (LEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::LEApcrelJT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
+ // Emits: (tLEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_35(N, ARM::tLEApcrelJT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ARMISD_tCALL(const SDValue &N) {
+
+ // Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (tBL:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_4(N, ARM::tBL, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (tBLr9:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (tBL:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::tBL, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (tBLr9:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMtcall:isVoid GPR:i32:$func)
+ // Emits: (tBLXr:isVoid GPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::tBLXr, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMtcall:isVoid GPR:i32:$func)
+ // Emits: (tBLXr_r9:isVoid GPR:i32:$func)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_4(N, ARM::tBLXr_r9, 1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_51(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_52(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N100, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_53(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_54(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N100, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_55(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_56(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_57(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_58(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, N1, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_59(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, N1, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_60(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N110, N0, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_61(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N110, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_62(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N110, N0, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_63(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N1010, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_64(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N1010, N0, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_65(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_66(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_67(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_imm_neg_XFORM(Tmp2.getNode());
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_68(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_69(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_70(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_71(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_t2_so_imm2part_1(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp7 = Transform_t2_so_imm2part_2(Tmp1.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_72(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_t2_so_neg_imm2part_1(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp7 = Transform_t2_so_neg_imm2part_2(Tmp1.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_73(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_74(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_so_imm2part_1(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp7 = Transform_so_imm2part_2(Tmp1.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_75(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_so_neg_imm2part_1(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp7 = Transform_so_neg_imm2part_2(Tmp1.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1000, N1100, N0, Tmp11, Tmp12 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N11, N0, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_78(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1000, N110, N0, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_79(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N110, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N1100, N0, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N11, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N10100 = N1010.getOperand(0);
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N10100, N0, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N101, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N000, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N000, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N11, N0, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N010, N1, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N110, N100, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N010, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N010, N000, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N110, N100, N0, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N010, N1, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N010, N000, N1, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N101, N1000, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N0010, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N001, N0000, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N101, N1000, N0, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N0010, N1, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N001, N0000, N1, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1100, N1000, N0, Tmp11, Tmp12 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0000, N0100, N1, Tmp11, Tmp12 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0100, N0000, N1, Tmp11, Tmp12 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1100, N100, N0, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0000, N010, N1, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0100, N000, N1, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N11, N100, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N010, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N000, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N110, N1000, N0, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N0100, N1, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N010, N0000, N1, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_116(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N110, N10, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N01, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N010, N00, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N10000 = N1000.getOperand(0);
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N101, N10000, N0, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N00100 = N0010.getOperand(0);
+ SDValue N00101 = N0010.getOperand(1);
+ SDValue N0011 = N001.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N00100, N1, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N001, N00000, N1, Tmp9, Tmp10 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N101, N100, N0, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N001, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N001, N000, N1, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_ADD_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp6) {
+ int64_t CN7 = Tmp6->getSExtValue();
+ if (CN7 == INT64_C(16) &&
+ N1001.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)))
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 38 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_76(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)))
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 38 cost = 1 size = 0
+ SDNode *Result = Emit_104(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6) {
+ int64_t CN7 = Tmp6->getSExtValue();
+ if (CN7 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0001.getValueType() == MVT::i32 &&
+ N001.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 38 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_105(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 38 cost = 1 size = 0
+ SDNode *Result = Emit_106(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32))
+ // Emits: (UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(255)) &&
+ N10.getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_54(N, ARM::UXTABrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32))
+ // Emits: (UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
+ N10.getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_54(N, ARM::UXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32))
+ // Emits: (t2UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(255)) &&
+ N10.getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_54(N, ARM::t2UXTABrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32))
+ // Emits: (t2UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
+ N10.getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_54(N, ARM::t2UXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32), GPR:i32:$LHS)
+ // Emits: (UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_87(N, ARM::UXTABrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32), GPR:i32:$LHS)
+ // Emits: (UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
+ N00.getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_87(N, ARM::UXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32), GPR:i32:$LHS)
+ // Emits: (t2UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_87(N, ARM::t2UXTABrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32), GPR:i32:$LHS)
+ // Emits: (t2UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 34 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
+ N00.getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_87(N, ARM::t2UXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if (N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N1001.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_78(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)))
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_80(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32))
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SRA) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N10101.getValueType() == MVT::i32 &&
+ N1011.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_82(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)))
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_107(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0001.getValueType() == MVT::i32 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_108(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_109(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N1001.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_113(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_114(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0001.getValueType() == MVT::i32 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_115(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32))
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SRA) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N10001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_119(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::SRA) {
+ SDValue N0010 = N001.getOperand(0);
+ if (N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00101.getValueType() == MVT::i32 &&
+ N0011.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_120(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SRA) {
+ SDValue N0000 = N000.getOperand(0);
+ if (N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00001.getValueType() == MVT::i32 &&
+ N0001.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_121(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 255:i32))
+ // Emits: (UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_53(N, ARM::UXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 65535:i32))
+ // Emits: (UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_53(N, ARM::UXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 255:i32))
+ // Emits: (t2UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_53(N, ARM::t2UXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 65535:i32))
+ // Emits: (t2UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N10, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_53(N, ARM::t2UXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 255:i32), GPR:i32:$LHS)
+ // Emits: (UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_86(N, ARM::UXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 65535:i32), GPR:i32:$LHS)
+ // Emits: (UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_86(N, ARM::UXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 255:i32), GPR:i32:$LHS)
+ // Emits: (t2UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_86(N, ARM::t2UXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 65535:i32), GPR:i32:$LHS)
+ // Emits: (t2UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_86(N, ARM::t2UXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
+ // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_62(N, ARM::SMLATT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32))
+ // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SRA) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N1011.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_64(N, ARM::SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
+ // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_62(N, ARM::t2SMLATT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32))
+ // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SRA) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N1011.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_64(N, ARM::t2SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
+ // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_94(N, ARM::SMLATT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_95(N, ARM::SMLATT, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ SDNode *Result = Emit_96(N, ARM::SMLATT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32))
+ // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SRA) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N1001.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_100(N, ARM::SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::SRA) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0011.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_101(N, ARM::SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SRA) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0001.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_102(N, ARM::SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
+ // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N101.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_94(N, ARM::t2SMLATT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
+ // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_95(N, ARM::t2SMLATT, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
+ // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ SDNode *Result = Emit_96(N, ARM::t2SMLATT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32))
+ // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SRA) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N1001.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_100(N, ARM::t2SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32), GPR:i32:$acc)
+ // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::SRA) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0011.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_101(N, ARM::t2SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
+ // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SRA) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0001.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_102(N, ARM::t2SMLAWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)))
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_61(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_61(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32))
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ if (cast<VTSDNode>(N1011)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_63(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)))
+ // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_61(N, ARM::t2SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
+ // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_61(N, ARM::t2SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32))
+ // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ if (cast<VTSDNode>(N1011)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_63(N, ARM::t2SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)))
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_91(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_92(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)), GPR:i32:$acc)
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_93(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)))
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_91(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_92(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_93(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32))
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ if (cast<VTSDNode>(N1001)->getVT() == MVT::i16) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_97(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ if (cast<VTSDNode>(N0011)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_98(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ if (cast<VTSDNode>(N0001)->getVT() == MVT::i16) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_99(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)))
+ // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_91(N, ARM::t2SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
+ // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_92(N, ARM::t2SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)), GPR:i32:$acc)
+ // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_93(N, ARM::t2SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)))
+ // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_91(N, ARM::t2SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
+ // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_92(N, ARM::t2SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
+ // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_93(N, ARM::t2SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32))
+ // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ if (cast<VTSDNode>(N1001)->getVT() == MVT::i16) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_97(N, ARM::t2SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32), GPR:i32:$acc)
+ // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ if (cast<VTSDNode>(N0011)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_98(N, ARM::t2SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32), GPR:i32:$acc)
+ // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (N000.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ if (cast<VTSDNode>(N0001)->getVT() == MVT::i16) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_99(N, ARM::t2SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (ADDrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_57(N, ARM::ADDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32)))
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (Predicate_sext_16_node(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_79(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b))
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (Predicate_sext_16_node(N11.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_81(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32))
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (Predicate_sext_16_node(N101.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_83(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (ADDrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_88(N, ARM::ADDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a))
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ if (Predicate_sext_16_node(N11.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_110(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (Predicate_sext_16_node(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_111(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a), GPR:i32:$acc)
+ // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (Predicate_sext_16_node(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_112(N, ARM::SMLABT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, (sra:i32 GPR:i32:$a, 16:i32)))
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (Predicate_sext_16_node(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N111.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_116(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b), GPR:i32:$acc)
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ if (Predicate_sext_16_node(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_117(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
+ // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (Predicate_sext_16_node(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_118(N, ARM::SMLATB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, GPR:i32:$a), 16:i32))
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getOperand(0);
+ if (Predicate_sext_16_node(N100.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_122(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (Predicate_sext_16_node(N001.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_123(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, GPR:i32:$a), 16:i32), GPR:i32:$acc)
+ // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if (Predicate_sext_16_node(N000.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_124(N, ARM::SMLAWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N101.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other))
+ // Emits: (SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i8 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_52(N, ARM::SXTABrr_rot, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other))
+ // Emits: (SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_52(N, ARM::SXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N101.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other))
+ // Emits: (t2SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i8 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_52(N, ARM::t2SXTABrr_rot, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other))
+ // Emits: (t2SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_52(N, ARM::t2SXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N001.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other), GPR:i32:$LHS)
+ // Emits: (SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_85(N, ARM::SXTABrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other), GPR:i32:$LHS)
+ // Emits: (SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_85(N, ARM::SXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N001.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other), GPR:i32:$LHS)
+ // Emits: (t2SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_85(N, ARM::t2SXTABrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other), GPR:i32:$LHS)
+ // Emits: (t2SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_85(N, ARM::t2SXTAHrr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (cast<VTSDNode>(N111)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_60(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2ADDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_68(N, ARM::t2ADDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
+ // Emits: (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (cast<VTSDNode>(N111)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_60(N, ARM::t2SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_90(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2ADDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_103(N, ARM::t2ADDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
+ // Emits: (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_90(N, ARM::t2SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_imm0_255_neg>><<X:imm_neg_XFORM>>:$imm)
+ // Emits: (t2SUBri:i32 GPR:i32:$src, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_255_neg>>:$imm))
+ // Pattern complexity = 8 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm0_255_neg(N1.getNode())) {
+ SDNode *Result = Emit_69(N, ARM::t2SUBri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b))
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+ if (Predicate_sext_16_node(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (Predicate_sext_16_node(N11.getNode())) {
+ SDNode *Result = Emit_77(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), GPR:i32:$acc)
+ // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (Predicate_sext_16_node(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (Predicate_sext_16_node(N01.getNode())) {
+ SDNode *Result = Emit_59(N, ARM::SMLABB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (ADDri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::ADDri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
+ // Emits: (tADDi3:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_7(N1.getNode())) {
+ SDNode *Result = Emit_65(N, ARM::tADDi3, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255>>:$rhs)
+ // Emits: (tADDi8:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm8_255(N1.getNode())) {
+ SDNode *Result = Emit_65(N, ARM::tADDi8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7_neg>><<X:imm_neg_XFORM>>:$rhs)
+ // Emits: (tSUBi3:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32):$rhs))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_7_neg(N1.getNode())) {
+ SDNode *Result = Emit_67(N, ARM::tSUBi3, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255_neg>><<X:imm_neg_XFORM>>:$rhs)
+ // Emits: (tSUBi8:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32):$rhs))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm8_255_neg(N1.getNode())) {
+ SDNode *Result = Emit_67(N, ARM::tSUBi8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2ADDri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2ADDri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_4095>>:$rhs)
+ // Emits: (t2ADDri12:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_4095(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2ADDri12, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
+ // Emits: (t2SUBri:i32 GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm_neg(N1.getNode())) {
+ SDNode *Result = Emit_70(N, ARM::t2SUBri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_imm0_4095_neg>><<X:imm_neg_XFORM>>:$imm)
+ // Emits: (t2SUBri12:i32 GPR:i32:$src, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_4095_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_4095_neg(N1.getNode())) {
+ SDNode *Result = Emit_69(N, ARM::t2SUBri12, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
+ // Emits: (SUBri:i32 GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm_neg(N1.getNode())) {
+ SDNode *Result = Emit_73(N, ARM::SUBri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
+ // Emits: (t2ADDri:i32 (t2ADDri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ if (Predicate_t2_so_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_71(N, ARM::t2ADDri, ARM::t2ADDri, MVT::i32, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_neg_imm2part>>:$RHS)
+ // Emits: (t2SUBri:i32 (t2SUBri:i32 GPR:i32:$LHS, (t2_so_neg_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_neg_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ if (Predicate_t2_so_neg_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_72(N, ARM::t2SUBri, ARM::t2SUBri, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
+ // Emits: (ADDri:i32 (ADDri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ if (Predicate_so_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_74(N, ARM::ADDri, ARM::ADDri, MVT::i32, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_neg_imm2part>>:$RHS)
+ // Emits: (SUBri:i32 (SUBri:i32 GPR:i32:$LHS, (so_neg_imm2part_1:i32 (imm:i32):$RHS)), (so_neg_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ if (Predicate_so_neg_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_75(N, ARM::SUBri, ARM::SUBri, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i8:Other))
+ // Emits: (SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_51(N, ARM::SXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i16:Other))
+ // Emits: (SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_51(N, ARM::SXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
+ // Emits: (MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_58(N, ARM::MLA, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 (mulhs:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
+ // Emits: (SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MULHS) {
+ SDNode *Result = Emit_59(N, ARM::SMMLA, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i8:Other))
+ // Emits: (t2SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_51(N, ARM::t2SXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i16:Other))
+ // Emits: (t2SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_51(N, ARM::t2SXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (mul:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
+ // Emits: (t2MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_59(N, ARM::t2MLA, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (mulhs:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
+ // Emits: (t2SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MULHS) {
+ SDNode *Result = Emit_59(N, ARM::t2SMMLA, MVT::i32);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i8:Other), GPR:i32:$LHS)
+ // Emits: (SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_84(N, ARM::SXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i16:Other), GPR:i32:$LHS)
+ // Emits: (SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_84(N, ARM::SXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_89(N, ARM::MLA, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MULHS) {
+ SDNode *Result = Emit_77(N, ARM::SMMLA, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i8:Other), GPR:i32:$LHS)
+ // Emits: (t2SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_84(N, ARM::t2SXTABrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i16:Other), GPR:i32:$LHS)
+ // Emits: (t2SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_84(N, ARM::t2SXTAHrr, MVT::i32);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (t2MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_77(N, ARM::t2MLA, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (t2SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MULHS) {
+ SDNode *Result = Emit_77(N, ARM::t2SMMLA, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (ADDrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_56(N, ARM::ADDrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tADDrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_66(N, ARM::tADDrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ADDrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_56(N, ARM::t2ADDrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_125(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, N11, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_126(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, N01, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvrshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvrshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v8i8 (NEONvshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
+ // Emits: (VSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 (NEONvshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
+ // Emits: (VSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 (NEONvrshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
+ // Emits: (VRSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 (NEONvrshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
+ // Emits: (VRSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 DPR:v8i8:$src1, (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3))
+ // Emits: (VMLAv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3), DPR:v8i8:$src1)
+ // Emits: (VMLAv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VADDv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv8i8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvrshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvrshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v16i8 (NEONvshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
+ // Emits: (VSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 (NEONvshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
+ // Emits: (VSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 (NEONvrshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
+ // Emits: (VRSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 (NEONvrshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
+ // Emits: (VRSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 QPR:v16i8:$src1, (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3))
+ // Emits: (VMLAv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3), QPR:v16i8:$src1)
+ // Emits: (VMLAv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VADDv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv16i8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_129(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, N110, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_130(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N11, N100, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, N010, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_132(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N01, N000, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_129(N, ARM::VMLAslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2))
+ // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_130(N, ARM::VMLAslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:v4i16 (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)), DPR:v4i16:$src1)
+ // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_131(N, ARM::VMLAslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i16 (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2), DPR:v4i16:$src1)
+ // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_132(N, ARM::VMLAslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvrshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvrshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v4i16 (NEONvshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
+ // Emits: (VSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 (NEONvshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
+ // Emits: (VSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 (NEONvrshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
+ // Emits: (VRSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 (NEONvrshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
+ // Emits: (VRSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3))
+ // Emits: (VMLAv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3), DPR:v4i16:$src1)
+ // Emits: (VMLAv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VADDv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv4i16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_133(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N110, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N0, N10, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N0, N11, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N010, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, N00, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N000, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, N01, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_129(N, ARM::VMLAslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_130(N, ARM::VMLAslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)), QPR:v8i16:$src1)
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_131(N, ARM::VMLAslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2), QPR:v8i16:$src1)
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_132(N, ARM::VMLAslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)), QPR:v8i16:$src1)
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_135(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2), QPR:v8i16:$src1)
+ // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_136(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvrshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvrshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 (NEONvshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
+ // Emits: (VSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 (NEONvshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
+ // Emits: (VSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 (NEONvrshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
+ // Emits: (VRSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 (NEONvrshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
+ // Emits: (VRSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3))
+ // Emits: (VMLAv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3), QPR:v8i16:$src1)
+ // Emits: (VMLAv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VADDv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv8i16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_129(N, ARM::VMLAslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2))
+ // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_130(N, ARM::VMLAslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:v2i32 (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)), DPR:v2i32:$src1)
+ // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_131(N, ARM::VMLAslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v2i32 (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2), DPR:v2i32:$src1)
+ // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_132(N, ARM::VMLAslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvrshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvrshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v2i32 (NEONvshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
+ // Emits: (VSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 (NEONvshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
+ // Emits: (VSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 (NEONvrshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
+ // Emits: (VRSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 (NEONvrshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
+ // Emits: (VRSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3))
+ // Emits: (VMLAv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3), DPR:v2i32:$src1)
+ // Emits: (VMLAv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VADDv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_137(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N110, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N0, N10, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_138(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N0, N11, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_139(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N010, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, N00, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_140(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N000, Tmp4), 0);
+ SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, N01, Tmp5, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+}
+SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_129(N, ARM::VMLAslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_130(N, ARM::VMLAslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)), QPR:v4i32:$src1)
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_131(N, ARM::VMLAslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2), QPR:v4i32:$src1)
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_132(N, ARM::VMLAslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)), QPR:v4i32:$src1)
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2), QPR:v4i32:$src1)
+ // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvrshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvrshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 (NEONvshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
+ // Emits: (VSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 (NEONvshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
+ // Emits: (VSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 (NEONvrshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
+ // Emits: (VRSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 (NEONvrshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
+ // Emits: (VRSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3))
+ // Emits: (VMLAv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3), QPR:v4i32:$src1)
+ // Emits: (VMLAv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VADDv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvrshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvrshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v1i64 (NEONvshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
+ // Emits: (VSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v1i64 (NEONvshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
+ // Emits: (VSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v1i64 (NEONvrshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
+ // Emits: (VRSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v1i64 (NEONvrshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
+ // Emits: (VRSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VADDv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv1i64, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VSRAuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvrshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvrshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
+ // Emits: (VRSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, ARM::VRSRAuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v2i64 (NEONvshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
+ // Emits: (VSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i64 (NEONvshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
+ // Emits: (VSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VSRAuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i64 (NEONvrshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
+ // Emits: (VRSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:v2i64 (NEONvrshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
+ // Emits: (VRSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_128(N, ARM::VRSRAuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VADDv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDv2i64, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_141(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_143(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_144(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_145(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_146(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_imm_neg_XFORM(Tmp2.getNode());
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, Tmp3, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (addc:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (ADDSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_143(N, ARM::ADDSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (ADDSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_148(N, ARM::ADDSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (addc:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2ADDSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_144(N, ARM::t2ADDSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2ADDSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_149(N, ARM::t2ADDSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (ADDSri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_141(N, ARM::ADDSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2ADDSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_141(N, ARM::t2ADDSri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
+ // Emits: (tADDi3:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_7(N1.getNode())) {
+ SDNode *Result = Emit_145(N, ARM::tADDi3, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255>>:$rhs)
+ // Emits: (tADDi8:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255>>:$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm8_255(N1.getNode())) {
+ SDNode *Result = Emit_145(N, ARM::tADDi8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7_neg>><<X:imm_neg_XFORM>>:$rhs)
+ // Emits: (tSUBi3:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_7_neg>>:$rhs))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_7_neg(N1.getNode())) {
+ SDNode *Result = Emit_147(N, ARM::tSUBi3, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255_neg>><<X:imm_neg_XFORM>>:$rhs)
+ // Emits: (tSUBi8:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm8_255_neg>>:$rhs))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm8_255_neg(N1.getNode())) {
+ SDNode *Result = Emit_147(N, ARM::tSUBi8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (addc:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (ADDSrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_142(N, ARM::ADDSrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (addc:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ADDSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_142(N, ARM::t2ADDSrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (addc:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tADDrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_146(N, ARM::tADDrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_152(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 8);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_154(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_156(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_157(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 7);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_159(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 8);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_160(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_161(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 7);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_162(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
+
+ // Pattern: (adde:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (ADCrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_152(N, ARM::ADCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (ADCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_155(N, ARM::ADCSSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (ADCrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_159(N, ARM::ADCrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (ADCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_160(N, ARM::ADCSSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2ADCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_157(N, ARM::t2ADCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2ADCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_158(N, ARM::t2ADCSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2ADCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_161(N, ARM::t2ADCrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2ADCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_162(N, ARM::t2ADCSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (ADCri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_150(N, ARM::ADCri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (ADCSSri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_153(N, ARM::ADCSSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2ADCri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_150(N, ARM::t2ADCri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2ADCSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_153(N, ARM::t2ADCSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (ADCrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_151(N, ARM::ADCrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (ADCSSrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_154(N, ARM::ADCSSrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (adde:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tADC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_156(N, ARM::tADC, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ADCrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_151(N, ARM::t2ADCrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (adde:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ADCSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_154(N, ARM::t2ADCSrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_164(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_165(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N10)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_166(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_167(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1, SDValue &CPTmpN10_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_168(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, N10, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN10_0, CPTmpN10_1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x8ULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_t2_so_imm_not_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_so_imm_not_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N00)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N1, N00, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN00_0, CPTmpN00_1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+SDNode *Select_ISD_AND_i32(const SDValue &N) {
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
+
+ // Pattern: (and:i32 (shl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
+ // Emits: (t2UXTB16r_rot:i32 GPR:i32:$Src, 24:i32)
+ // Pattern complexity = 32 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_170(N, ARM::t2UXTB16r_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (srl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
+ // Emits: (t2UXTB16r_rot:i32 GPR:i32:$Src, 8:i32)
+ // Pattern complexity = 32 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_171(N, ARM::t2UXTB16r_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
+
+ // Pattern: (and:i32 (shl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
+ // Emits: (UXTB16r_rot:i32 GPR:i32:$Src, 24:i32)
+ // Pattern complexity = 32 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_170(N, ARM::UXTB16r_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (srl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
+ // Emits: (UXTB16r_rot:i32 GPR:i32:$Src, 8:i32)
+ // Pattern complexity = 32 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_171(N, ARM::UXTB16r_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32)
+ // Emits: (UXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 31 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
+ N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_164(N, ARM::UXTBr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32)
+ // Emits: (UXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 31 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
+ N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_164(N, ARM::UXTHr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 16711935:i32)
+ // Emits: (UXTB16r_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 31 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(16711935)) &&
+ N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_164(N, ARM::UXTB16r_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+
+ // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32)
+ // Emits: (t2UXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 31 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
+ N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_164(N, ARM::t2UXTBr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32)
+ // Emits: (t2UXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 31 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
+ N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_164(N, ARM::t2UXTHr_rot, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 16711935:i32)
+ // Emits: (t2UXTB16r_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 31 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(16711935)) &&
+ N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_164(N, ARM::t2UXTB16r_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+
+ // Pattern: (and:i32 GPR:i32:$src, 255:i32)
+ // Emits: (UXTBr:i32 GPR:i32:$src)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_163(N, ARM::UXTBr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, 65535:i32)
+ // Emits: (UXTHr:i32 GPR:i32:$src)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_163(N, ARM::UXTHr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, 16711935:i32)
+ // Emits: (UXTB16r:i32 GPR:i32:$src)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
+ SDNode *Result = Emit_163(N, ARM::UXTB16r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+
+ // Pattern: (and:i32 GPR:i32:$src, 255:i32)
+ // Emits: (t2UXTBr:i32 GPR:i32:$src)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_163(N, ARM::t2UXTBr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, 65535:i32)
+ // Emits: (t2UXTHr:i32 GPR:i32:$src)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_163(N, ARM::t2UXTHr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, 16711935:i32)
+ // Emits: (t2UXTB16r:i32 GPR:i32:$src)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
+ SDNode *Result = Emit_163(N, ARM::t2UXTB16r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i32 GPR:i32:$a, (xor:i32 so_reg:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (BICrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 22 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue CPTmpN10_0;
+ SDValue CPTmpN10_1;
+ SDValue CPTmpN10_2;
+ if (SelectShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_167(N, ARM::BICrs, MVT::i32, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 so_reg:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
+ // Emits: (BICrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ SDValue CPTmpN00_2;
+ if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_178(N, ARM::BICrs, MVT::i32, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 19 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue CPTmpN10_0;
+ SDValue CPTmpN10_1;
+ if (SelectT2ShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_169(N, ARM::t2BICrs, MVT::i32, CPTmpN10_0, CPTmpN10_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
+ // Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_180(N, ARM::t2BICrs, MVT::i32, CPTmpN00_0, CPTmpN00_1);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (ANDrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_57(N, ARM::ANDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (ANDrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_88(N, ARM::ANDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$a, (xor:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_165(N, ARM::BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_165(N, ARM::t2BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i32 GPR:i32:$a, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_so_imm>>:$b))
+ // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N11.getNode())) {
+ SDNode *Result = Emit_174(N, ARM::BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
+ // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_so_imm(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_175(N, ARM::BICri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_so_imm>>:$b), GPR:i32:$a)
+ // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_immAllOnes(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N01.getNode())) {
+ SDNode *Result = Emit_176(N, ARM::BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
+ // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N11.getNode())) {
+ SDNode *Result = Emit_174(N, ARM::t2BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
+ // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_175(N, ARM::t2BICri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
+ // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_immAllOnes(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N01.getNode())) {
+ SDNode *Result = Emit_176(N, ARM::t2BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2ANDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_68(N, ARM::t2ANDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2ANDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_103(N, ARM::t2ANDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$a, (xor:i32 GPR:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (BICrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_166(N, ARM::BICrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 tGPR:i32:$lhs, (xor:i32 tGPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (tBIC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_168(N, ARM::tBIC, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (t2BICrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_166(N, ARM::t2BICrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 GPR:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
+ // Emits: (BICrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_177(N, ARM::BICrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 tGPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), tGPR:i32:$lhs)
+ // Emits: (tBIC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_179(N, ARM::tBIC, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
+ // Emits: (t2BICrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_177(N, ARM::t2BICrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+
+ // Pattern: (and:i32 tGPR:i32:$src, 255:i32)
+ // Emits: (tUXTB:i32 tGPR:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_163(N, ARM::tUXTB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 tGPR:i32:$src, 65535:i32)
+ // Emits: (tUXTH:i32 tGPR:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_163(N, ARM::tUXTH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (ANDri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::ANDri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_bf_inv_mask_imm>>:$imm)
+ // Emits: (BFC:i32 GPR:i32:$src, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_bf_inv_mask_imm(N1.getNode())) {
+ SDNode *Result = Emit_35(N, ARM::BFC, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2ANDri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2ANDri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_bf_inv_mask_imm>>:$imm)
+ // Emits: (t2BFC:i32 GPR:i32:$src, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_bf_inv_mask_imm(N1.getNode())) {
+ SDNode *Result = Emit_35(N, ARM::t2BFC, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$imm)
+ // Emits: (t2BICri:i32 GPR:i32:$src, (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm_not(N1.getNode())) {
+ SDNode *Result = Emit_172(N, ARM::t2BICri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+
+ // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_not>><<X:so_imm_not_XFORM>>:$imm)
+ // Emits: (BICri:i32 GPR:i32:$src, (so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_not>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm_not(N1.getNode())) {
+ SDNode *Result = Emit_173(N, ARM::BICri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (ANDrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_56(N, ARM::ANDrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tAND:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_66(N, ARM::tAND, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ANDrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_56(N, ARM::t2ANDrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N11, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N01, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_AND_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i32 DPR:v2i32:$src1, (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>))
+ // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N11.getNode())) {
+ SDNode *Result = Emit_51(N, ARM::VBICd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i32 DPR:v2i32:$src1, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2))
+ // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N10.getNode())) {
+ SDNode *Result = Emit_181(N, ARM::VBICd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v2i32 (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src1)
+ // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N01.getNode())) {
+ SDNode *Result = Emit_84(N, ARM::VBICd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2), DPR:v2i32:$src1)
+ // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N00.getNode())) {
+ SDNode *Result = Emit_182(N, ARM::VBICd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VANDd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VANDd, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v4i32 QPR:v4i32:$src1, (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
+ // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N11.getNode())) {
+ SDNode *Result = Emit_51(N, ARM::VBICq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v4i32 QPR:v4i32:$src1, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2))
+ // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N10.getNode())) {
+ SDNode *Result = Emit_181(N, ARM::VBICq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v4i32 (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src1)
+ // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N01.getNode())) {
+ SDNode *Result = Emit_84(N, ARM::VBICq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2), QPR:v4i32:$src1)
+ // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N00.getNode())) {
+ SDNode *Result = Emit_182(N, ARM::VBICq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VANDq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VANDq, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, N2, N3, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_8>>
+ // Emits: (ATOMIC_CMP_SWAP_I8:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_cmp_swap_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_16>>
+ // Emits: (ATOMIC_CMP_SWAP_I16:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_cmp_swap_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_32>>
+ // Emits: (ATOMIC_CMP_SWAP_I32:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_cmp_swap_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, N1, N2, Chain);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_8>>
+ // Emits: (ATOMIC_LOAD_ADD_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_add_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_16>>
+ // Emits: (ATOMIC_LOAD_ADD_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_add_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_32>>
+ // Emits: (ATOMIC_LOAD_ADD_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_add_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_8>>
+ // Emits: (ATOMIC_LOAD_AND_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_and_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_16>>
+ // Emits: (ATOMIC_LOAD_AND_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_and_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_32>>
+ // Emits: (ATOMIC_LOAD_AND_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_and_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_8>>
+ // Emits: (ATOMIC_LOAD_NAND_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_nand_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_16>>
+ // Emits: (ATOMIC_LOAD_NAND_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_nand_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_32>>
+ // Emits: (ATOMIC_LOAD_NAND_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_nand_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_8>>
+ // Emits: (ATOMIC_LOAD_OR_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_or_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_16>>
+ // Emits: (ATOMIC_LOAD_OR_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_or_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_32>>
+ // Emits: (ATOMIC_LOAD_OR_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_or_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_8>>
+ // Emits: (ATOMIC_LOAD_SUB_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_sub_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_16>>
+ // Emits: (ATOMIC_LOAD_SUB_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_sub_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_32>>
+ // Emits: (ATOMIC_LOAD_SUB_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_sub_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_8>>
+ // Emits: (ATOMIC_LOAD_XOR_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_xor_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_16>>
+ // Emits: (ATOMIC_LOAD_XOR_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_xor_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_32>>
+ // Emits: (ATOMIC_LOAD_XOR_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_load_xor_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_8>>
+ // Emits: (ATOMIC_SWAP_I8:i32 GPR:i32:$ptr, GPR:i32:$new)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_swap_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_16>>
+ // Emits: (ATOMIC_SWAP_I16:i32 GPR:i32:$ptr, GPR:i32:$new)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_swap_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_32>>
+ // Emits: (ATOMIC_SWAP_I32:i32 GPR:i32:$ptr, GPR:i32:$new)
+ // Pattern complexity = 4 cost = 11 size = 0
+ if (Predicate_atomic_swap_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I32, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_i32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_31(N, ARM::VMOVRS, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_31(N, ARM::VMOVSR, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_185(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ReplaceUses(N, N0);
+ return NULL;
+}
+SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:f64 DPR:v1i64:$src)
+ // Emits: DPR:f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 DPR:v2i32:$src)
+ // Emits: DPR:f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 DPR:v4i16:$src)
+ // Emits: DPR:f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 DPR:v8i8:$src)
+ // Emits: DPR:f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 DPR:v2f32:$src)
+ // Emits: DPR:f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v8i8 DPR:v1i64:$src)
+ // Emits: DPR:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 DPR:v2i32:$src)
+ // Emits: DPR:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 DPR:v4i16:$src)
+ // Emits: DPR:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 DPR:f64:$src)
+ // Emits: DPR:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 DPR:v2f32:$src)
+ // Emits: DPR:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v16i8 QPR:v2i64:$src)
+ // Emits: QPR:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 QPR:v4i32:$src)
+ // Emits: QPR:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 QPR:v8i16:$src)
+ // Emits: QPR:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 QPR:v2f64:$src)
+ // Emits: QPR:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 QPR:v4f32:$src)
+ // Emits: QPR:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4i16 DPR:v1i64:$src)
+ // Emits: DPR:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 DPR:v2i32:$src)
+ // Emits: DPR:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 DPR:v8i8:$src)
+ // Emits: DPR:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 DPR:f64:$src)
+ // Emits: DPR:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 DPR:v2f32:$src)
+ // Emits: DPR:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v8i16 QPR:v2i64:$src)
+ // Emits: QPR:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 QPR:v4i32:$src)
+ // Emits: QPR:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 QPR:v16i8:$src)
+ // Emits: QPR:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 QPR:v2f64:$src)
+ // Emits: QPR:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 QPR:v4f32:$src)
+ // Emits: QPR:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2i32 DPR:v1i64:$src)
+ // Emits: DPR:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 DPR:v4i16:$src)
+ // Emits: DPR:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 DPR:v8i8:$src)
+ // Emits: DPR:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 DPR:f64:$src)
+ // Emits: DPR:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 DPR:v2f32:$src)
+ // Emits: DPR:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4i32 QPR:v2i64:$src)
+ // Emits: QPR:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 QPR:v8i16:$src)
+ // Emits: QPR:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 QPR:v16i8:$src)
+ // Emits: QPR:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 QPR:v2f64:$src)
+ // Emits: QPR:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 QPR:v4f32:$src)
+ // Emits: QPR:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v1i64 DPR:v2i32:$src)
+ // Emits: DPR:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 DPR:v4i16:$src)
+ // Emits: DPR:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 DPR:v8i8:$src)
+ // Emits: DPR:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 DPR:f64:$src)
+ // Emits: DPR:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 DPR:v2f32:$src)
+ // Emits: DPR:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2i64 QPR:v4i32:$src)
+ // Emits: QPR:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 QPR:v8i16:$src)
+ // Emits: QPR:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 QPR:v16i8:$src)
+ // Emits: QPR:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 QPR:v2f64:$src)
+ // Emits: QPR:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 QPR:v4f32:$src)
+ // Emits: QPR:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2f32 DPR:f64:$src)
+ // Emits: DPR:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 DPR:v1i64:$src)
+ // Emits: DPR:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 DPR:v2i32:$src)
+ // Emits: DPR:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 DPR:v4i16:$src)
+ // Emits: DPR:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 DPR:v8i8:$src)
+ // Emits: DPR:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4f32 QPR:v2i64:$src)
+ // Emits: QPR:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 QPR:v4i32:$src)
+ // Emits: QPR:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 QPR:v8i16:$src)
+ // Emits: QPR:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 QPR:v16i8:$src)
+ // Emits: QPR:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 QPR:v2f64:$src)
+ // Emits: QPR:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2f64 QPR:v2i64:$src)
+ // Emits: QPR:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 QPR:v4i32:$src)
+ // Emits: QPR:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 QPR:v8i16:$src)
+ // Emits: QPR:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 QPR:v16i8:$src)
+ // Emits: QPR:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 QPR:v4f32:$src)
+ // Emits: QPR:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_185(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BR(const SDValue &N) {
+
+ // Pattern: (br:isVoid (bb:Other):$target)
+ // Emits: (B:isVoid (bb:Other):$target)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BasicBlock) {
+ SDNode *Result = Emit_34(N, ARM::B);
+ return Result;
+ }
+ }
+
+ // Pattern: (br:isVoid (bb:Other):$target)
+ // Emits: (tB:isVoid (bb:Other):$target)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BasicBlock) {
+ SDNode *Result = Emit_34(N, ARM::tB);
+ return Result;
+ }
+ }
+
+ // Pattern: (br:isVoid (bb:Other):$target)
+ // Emits: (t2B:isVoid (bb:Other):$target)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BasicBlock) {
+ SDNode *Result = Emit_34(N, ARM::t2B);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BRIND(const SDValue &N) {
+
+ // Pattern: (brind:isVoid GPR:i32:$dst)
+ // Emits: (BRIND:isVoid GPR:i32:$dst)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_34(N, ARM::BRIND);
+ return Result;
+ }
+ }
+
+ // Pattern: (brind:isVoid GPR:i32:$dst)
+ // Emits: (tBRIND:isVoid GPR:i32:$dst)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_34(N, ARM::tBRIND);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BSWAP_i32(const SDValue &N) {
+
+ // Pattern: (bswap:i32 GPR:i32:$src)
+ // Emits: (REV:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDNode *Result = Emit_31(N, ARM::REV, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (bswap:i32 tGPR:i32:$src)
+ // Emits: (tREV:i32 tGPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDNode *Result = Emit_31(N, ARM::tREV, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (bswap:i32 GPR:i32:$src)
+ // Emits: (t2REV:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_31(N, ARM::t2REV, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm8(N.getNode());
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm8(N.getNode())) {
+ SDNode *Result = Emit_186(N, ARM::VMOVv8i8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm8(N.getNode())) {
+ SDNode *Result = Emit_186(N, ARM::VMOVv16i8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm16(N.getNode());
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm16(N.getNode())) {
+ SDNode *Result = Emit_187(N, ARM::VMOVv4i16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm16(N.getNode())) {
+ SDNode *Result = Emit_187(N, ARM::VMOVv8i16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm32(N.getNode());
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm32(N.getNode())) {
+ SDNode *Result = Emit_188(N, ARM::VMOVv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm32(N.getNode())) {
+ SDNode *Result = Emit_188(N, ARM::VMOVv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm64(N.getNode());
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm64(N.getNode())) {
+ SDNode *Result = Emit_189(N, ARM::VMOVv1i64, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON()) &&
+ Predicate_vmovImm64(N.getNode())) {
+ SDNode *Result = Emit_189(N, ARM::VMOVv2i64, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { N1, N2, Tmp2, Tmp3, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
+
+ // Pattern: (ARMcallseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
+ // Emits: (ADJCALLSTACKUP:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_190(N, ARM::ADJCALLSTACKUP);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ARMcallseq_end:isVoid (imm:i32):$amt1, (imm:i32):$amt2)
+ // Emits: (tADJCALLSTACKUP:isVoid (imm:i32):$amt1, (imm:i32):$amt2)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_191(N, ARM::tADJCALLSTACKUP);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 4);
+ Chain = SDValue(ResNode, 0);
+ SDValue InFlag(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Tmp0, Chain);
+ Chain = SDValue(ResNode, 0);
+ SDValue InFlag(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
+
+ // Pattern: (ARMcallseq_start:isVoid (timm:i32):$amt)
+ // Emits: (ADJCALLSTACKDOWN:isVoid (timm:i32):$amt)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_192(N, ARM::ADJCALLSTACKDOWN);
+ return Result;
+ }
+ }
+
+ // Pattern: (ARMcallseq_start:isVoid (imm:i32):$amt)
+ // Emits: (tADJCALLSTACKDOWN:isVoid (imm:i32):$amt)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_193(N, ARM::tADJCALLSTACKDOWN);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_CTLZ_i32(const SDValue &N) {
+
+ // Pattern: (ctlz:i32 GPR:i32:$src)
+ // Emits: (CLZ:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps())) {
+ SDNode *Result = Emit_31(N, ARM::CLZ, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (ctlz:i32 GPR:i32:$src)
+ // Emits: (t2CLZ:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_31(N, ARM::t2CLZ, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0, Tmp1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = Transform_so_imm_not_XFORM(Tmp0.getNode());
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_thumb_immshifted_val(Tmp2.getNode());
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp1, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 4), 0);
+ SDValue Tmp7 = Transform_thumb_immshifted_shamt(Tmp2.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp0, Tmp6, Tmp7, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_imm_comp_XFORM(Tmp2.getNode());
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp1, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 4), 0);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp0, Tmp6, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+}
+DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = Transform_t2_so_imm_not_XFORM(Tmp0.getNode());
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_Constant_i32(const SDValue &N) {
+
+ // Pattern: (imm:i32)<<P:Predicate_t2_so_imm>>:$src
+ // Emits: (t2MOVi:i32 (imm:i32):$src)
+ // Pattern complexity = 5 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) &&
+ Predicate_t2_so_imm(N.getNode())) {
+ SDNode *Result = Emit_194(N, ARM::t2MOVi, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_so_imm>>:$src
+ // Emits: (MOVi:i32 (imm:i32):$src)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) &&
+ Predicate_so_imm(N.getNode())) {
+ SDNode *Result = Emit_194(N, ARM::MOVi, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_imm0_65535>>:$src
+ // Emits: (MOVi16:i32 (imm:i32):$src)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops()) &&
+ Predicate_imm0_65535(N.getNode())) {
+ SDNode *Result = Emit_195(N, ARM::MOVi16, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_so_imm_not>><<X:so_imm_not_XFORM>>:$imm
+ // Emits: (MVNi:i32 (so_imm_not_XFORM:i32 (imm:i32):$imm))
+ // Pattern complexity = 4 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) &&
+ Predicate_so_imm_not(N.getNode())) {
+ SDNode *Result = Emit_196(N, ARM::MVNi, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_so_imm2part>>:$src
+ // Emits: (MOVi2pieces:i32 (imm:i32):$src)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!Subtarget->hasV6T2Ops()) &&
+ Predicate_so_imm2part(N.getNode())) {
+ SDNode *Result = Emit_195(N, ARM::MOVi2pieces, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_imm0_255>>:$src
+ // Emits: (tMOVi8:i32 (imm:i32):$src)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) &&
+ Predicate_imm0_255(N.getNode())) {
+ SDNode *Result = Emit_197(N, ARM::tMOVi8, MVT::i32);
+ return Result;
+ }
+ if ((Subtarget->isThumb2())) {
+
+ // Pattern: (imm:i32)<<P:Predicate_imm0_65535>>:$src
+ // Emits: (t2MOVi16:i32 (imm:i32):$src)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_imm0_65535(N.getNode())) {
+ SDNode *Result = Emit_195(N, ARM::t2MOVi16, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$src
+ // Emits: (t2MVNi:i32 (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$src))
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_t2_so_imm_not(N.getNode())) {
+ SDNode *Result = Emit_200(N, ARM::t2MVNi, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+
+ // Pattern: (imm:i32)<<P:Predicate_thumb_immshifted>>:$src
+ // Emits: (tLSLri:i32 (tMOVi8:i32 (thumb_immshifted_val:i32 (imm:i32):$src)), (thumb_immshifted_shamt:i32 (imm:i32):$src))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_thumb_immshifted(N.getNode())) {
+ SDNode *Result = Emit_198(N, ARM::tMOVi8, ARM::tLSLri, MVT::i32, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_imm0_255_comp>>:$src
+ // Emits: (tMVN:i32 (tMOVi8:i32 (imm_comp_XFORM:i32 (imm:i32):$src)))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_imm0_255_comp(N.getNode())) {
+ SDNode *Result = Emit_199(N, ARM::tMOVi8, ARM::tMVN, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (imm:i32):$src
+ // Emits: (MOVi32imm:i32 (imm:i32):$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
+ SDNode *Result = Emit_195(N, ARM::MOVi32imm, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32):$src
+ // Emits: (t2MOVi32imm:i32 (imm:i32):$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_195(N, ARM::t2MOVi32imm, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstantFP(*cast<ConstantFPSDNode>(N)->getConstantFPValue(), cast<ConstantFPSDNode>(N)->getValueType(0));
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0, Tmp1, Tmp2);
+}
+SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP3()) &&
+ Predicate_vfp_f32imm(N.getNode())) {
+ SDNode *Result = Emit_201(N, ARM::FCONSTS, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP3()) &&
+ Predicate_vfp_f64imm(N.getNode())) {
+ SDNode *Result = Emit_201(N, ARM::FCONSTD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
+
+ // Pattern: (extractelt:i32 DPR:v2i32:$src, (imm:iPTR):$lane)
+ // Emits: (VGETLNi32:i32 DPR:v2i32:$src, (imm:i32):$lane)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_35(N, ARM::VGETLNi32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (extractelt:i32 QPR:v4i32:$src, (imm:iPTR):$lane)
+ // Emits: (VGETLNi32:i32 (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_SSubReg_f32_reg(Tmp3.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_SSubReg_f32_reg(Tmp3.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp4);
+}
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (extractelt:f32 DPR:v2f32:$src1, (imm:iPTR):$src2)
+ // Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v2f32 DPR:v2f32:$src1, DPR_VFP2:f64), (SSubReg_f32_reg:i32 (imm:i32):$src2))
+ // Pattern complexity = 6 cost = 2 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_202(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (extractelt:f32 QPR:v4f32:$src1, (imm:iPTR):$src2)
+ // Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v4f32 QPR:v4f32:$src1, QPR_VFP2:v16i8), (SSubReg_f32_reg:i32 (imm:i32):$src2))
+ // Pattern complexity = 6 cost = 2 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_203(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::v4f32, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_DSubReg_f64_reg(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_204(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FABS_f32(const SDValue &N) {
+
+ // Pattern: (fabs:f32 SPR:f32:$a)
+ // Emits: (VABSS:f32 SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_31(N, ARM::VABSS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fabs:f32 SPR:f32:$a)
+ // Emits: (EXTRACT_SUBREG:f32 (VABSfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 4 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VABSfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FABS_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_31(N, ARM::VABSD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N000, N001, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, unsigned Opc4, unsigned Opc5, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3, MVT::SimpleValueType VT4, MVT::SimpleValueType VT5) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc3, N.getDebugLoc(), VT3, Tmp4, N1, Tmp6), 0);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops4[] = { Tmp3, Tmp7, Tmp8, Tmp9 };
+ SDValue Tmp10(CurDAG->getMachineNode(Opc4, N.getDebugLoc(), VT4, Ops4, 4), 0);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc5, VT5, Tmp10, Tmp11);
+}
+DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N100, N101, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_FADD_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f32 (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)), SPR:f32:$dstin)
+ // Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_205(N, ARM::VMLSS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f32 SPR:f32:$dstin, (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)))
+ // Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FNEG) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_207(N, ARM::VMLSS, MVT::f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fadd:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b), SPR:f32:$dstin)
+ // Emits: (VMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fadd:f32 SPR:f32:$dstin, (fmul:f32 SPR:f32:$a, SPR:f32:$b))
+ // Emits: (VMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f32 SPR:f32:$a, SPR:f32:$b)
+ // Emits: (VADDS:f32 SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fadd:f32 SPR:f32:$a, SPR:f32:$b)
+ // Emits: (EXTRACT_SUBREG:f32 (VADDfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 6 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VADDfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FADD_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f64 (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)), DPR:f64:$dstin)
+ // Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_205(N, ARM::VMLSD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f64 DPR:f64:$dstin, (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)))
+ // Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FNEG) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_207(N, ARM::VMLSD, MVT::f64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fadd:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b), DPR:f64:$dstin)
+ // Emits: (VMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAD, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fadd:f64 DPR:f64:$dstin, (fmul:f64 DPR:f64:$a, DPR:f64:$b))
+ // Emits: (VMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f64 DPR:f64:$a, DPR:f64:$b)
+ // Emits: (VADDD:f64 DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_129(N, ARM::VMLAslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2))
+ // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_130(N, ARM::VMLAslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (fadd:v2f32 (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)), DPR:v2f32:$src1)
+ // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_131(N, ARM::VMLAslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v2f32 (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2), DPR:v2f32:$src1)
+ // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_132(N, ARM::VMLAslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3))
+ // Emits: (VMLAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:v2f32 (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3), DPR:v2f32:$src1)
+ // Emits: (VMLAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VADDfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDfd, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_129(N, ARM::VMLAslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_130(N, ARM::VMLAslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)), QPR:v4f32:$src1)
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_131(N, ARM::VMLAslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v4f32 (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2), QPR:v4f32:$src1)
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_132(N, ARM::VMLAslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)), QPR:v4f32:$src1)
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v4f32 (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2), QPR:v4f32:$src1)
+ // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N00.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3))
+ // Emits: (VMLAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLAfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3), QPR:v4f32:$src1)
+ // Emits: (VMLAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_127(N, ARM::VMLAfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VADDfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VADDfq, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_44(N, ARM::VDIVS, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_44(N, ARM::VDIVD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N0, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
+ if ((!HonorSignDependentRoundingFPMath())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:f32 (fneg:f32 SPR:f32:$a), SPR:f32:$b)
+ // Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FNEG) {
+ SDNode *Result = Emit_208(N, ARM::VNMULS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fmul:f32 SPR:f32:$b, (fneg:f32 SPR:f32:$a))
+ // Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FNEG) {
+ SDNode *Result = Emit_209(N, ARM::VNMULS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f32 SPR:f32:$a, SPR:f32:$b)
+ // Emits: (VMULS:f32 SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_44(N, ARM::VMULS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fmul:f32 SPR:f32:$a, SPR:f32:$b)
+ // Emits: (EXTRACT_SUBREG:f32 (VMULfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 6 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VMULfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
+ if ((!HonorSignDependentRoundingFPMath())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:f64 (fneg:f64 DPR:f64:$a), DPR:f64:$b)
+ // Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FNEG) {
+ SDNode *Result = Emit_208(N, ARM::VNMULD, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fmul:f64 DPR:f64:$b, (fneg:f64 DPR:f64:$a))
+ // Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FNEG) {
+ SDNode *Result = Emit_209(N, ARM::VNMULD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f64 DPR:f64:$a, DPR:f64:$b)
+ // Emits: (VMULD:f64 DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_44(N, ARM::VMULD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FMUL_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:v2f32 DPR:v2f32:$src1, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane))
+ // Emits: (VMULslfd:v2f32 DPR:v2f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_126(N, ARM::VMULslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane), DPR:v2f32:$src1)
+ // Emits: (VMULslfd:v2f32 DPR:v2f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_128(N, ARM::VMULslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VMULfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VMULfd, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp3), 0);
+ SDValue Tmp5 = Transform_SubReg_i32_lane(Tmp2.getNode());
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N0, Tmp4, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp5 = Transform_SubReg_i32_lane(Tmp2.getNode());
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, Tmp4, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:v4f32 QPR:v4f32:$src1, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane))
+ // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_126(N, ARM::VMULslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane), QPR:v4f32:$src1)
+ // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_128(N, ARM::VMULslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:v4f32 QPR:v4f32:$src1, (NEONvduplane:v4f32 QPR:v4f32:$src2, (imm:i32):$lane))
+ // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 9 cost = 2 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src2, (imm:i32):$lane), QPR:v4f32:$src1)
+ // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 9 cost = 2 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VMULfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VMULfq, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
+
+ // Pattern: (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b))
+ // Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_212(N, ARM::VNMULS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f32 SPR:f32:$a)
+ // Emits: (VNEGS:f32 SPR:f32:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_31(N, ARM::VNEGS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fneg:f32 SPR:f32:$a)
+ // Emits: (EXTRACT_SUBREG:f32 (VNEGf32d_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 4 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VNEGf32d_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+
+ // Pattern: (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b))
+ // Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_212(N, ARM::VNMULD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f64 DPR:f64:$a)
+ // Emits: (VNEGD:f64 DPR:f64:$a)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_31(N, ARM::VNEGD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FNEG_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VNEGf32d, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FNEG_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_31(N, ARM::VNEGf32q, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTDS, MVT::f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_31(N, ARM::VCVTSD, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_SINT_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTf2sd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_SINT_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTf2sq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_UINT_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTf2ud, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_UINT_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTf2uq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_31(N, ARM::VSQRTS, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_31(N, ARM::VSQRTD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fsub:f32 (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)), SPR:f32:$dstin)
+ // Emits: (VNMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_205(N, ARM::VNMLAS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b), SPR:f32:$dstin)
+ // Emits: (VNMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_127(N, ARM::VNMLSS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f32 SPR:f32:$dstin, (fmul:f32 SPR:f32:$a, SPR:f32:$b))
+ // Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f32 SPR:f32:$a, SPR:f32:$b)
+ // Emits: (VSUBS:f32 SPR:f32:$a, SPR:f32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_44(N, ARM::VSUBS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 SPR:f32:$a, SPR:f32:$b)
+ // Emits: (EXTRACT_SUBREG:f32 (VSUBfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
+ // Pattern complexity = 3 cost = 6 size = 0
+ if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
+ SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VSUBfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fsub:f64 (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)), DPR:f64:$dstin)
+ // Emits: (VNMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_205(N, ARM::VNMLAD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b), DPR:f64:$dstin)
+ // Emits: (VNMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_127(N, ARM::VNMLSD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 DPR:f64:$dstin, (fmul:f64 DPR:f64:$a, DPR:f64:$b))
+ // Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->useNEONForSinglePrecisionFP())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 DPR:f64:$a, DPR:f64:$b)
+ // Emits: (VSUBD:f64 DPR:f64:$a, DPR:f64:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasVFP2())) {
+ SDNode *Result = Emit_44(N, ARM::VSUBD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_129(N, ARM::VMLSslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2))
+ // Emits: (VMLSslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_130(N, ARM::VMLSslfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3))
+ // Emits: (VMLSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDNode *Result = Emit_125(N, ARM::VMLSfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VSUBfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBfd, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_129(N, ARM::VMLSslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
+ // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_130(N, ARM::VMLSslfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
+ // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3))
+ // Emits: (VMLSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VSUBfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBfq, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_50(N, ARM::VSETLNi8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i8_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp6 = Transform_SubReg_i8_lane(Tmp2.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp10 = Transform_DSubReg_i8_reg(Tmp2.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, N0, Tmp9, Tmp10);
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_213(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_50(N, ARM::VSETLNi16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp2.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp10 = Transform_DSubReg_i16_reg(Tmp2.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, N0, Tmp9, Tmp10);
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_214(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_50(N, ARM::VSETLNi32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp2.getNode());
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp10 = Transform_DSubReg_i32_reg(Tmp2.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, N0, Tmp9, Tmp10);
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_215(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp1 = CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = Transform_SSubReg_f32_reg(Tmp4.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, N1, Tmp5);
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_216(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp1 = CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = Transform_SSubReg_f32_reg(Tmp4.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, N1, Tmp5);
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_217(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_f64_reg(Tmp2.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_218(N, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, N3, Tmp4, Tmp5, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+}
+SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(105)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3)) {
+ SDValue N3 = N.getOperand(3);
+ if (N2.getValueType() == MVT::i32) {
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v8i8:$src)
+ // Emits: (VST1d8:isVoid addrmode6:i32:$addr, DPR:v8i8:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_219(N, ARM::VST1d8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v4i16:$src)
+ // Emits: (VST1d16:isVoid addrmode6:i32:$addr, DPR:v4i16:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_219(N, ARM::VST1d16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v2i32:$src)
+ // Emits: (VST1d32:isVoid addrmode6:i32:$addr, DPR:v2i32:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_219(N, ARM::VST1d32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v2f32:$src)
+ // Emits: (VST1df:isVoid addrmode6:i32:$addr, DPR:v2f32:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_219(N, ARM::VST1df, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v1i64:$src)
+ // Emits: (VST1d64:isVoid addrmode6:i32:$addr, DPR:v1i64:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_219(N, ARM::VST1d64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v16i8:$src)
+ // Emits: (VST1q8:isVoid addrmode6:i32:$addr, QPR:v16i8:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_219(N, ARM::VST1q8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v8i16:$src)
+ // Emits: (VST1q16:isVoid addrmode6:i32:$addr, QPR:v8i16:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_219(N, ARM::VST1q16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v4i32:$src)
+ // Emits: (VST1q32:isVoid addrmode6:i32:$addr, QPR:v4i32:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_219(N, ARM::VST1q32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v4f32:$src)
+ // Emits: (VST1qf:isVoid addrmode6:i32:$addr, QPR:v4f32:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_219(N, ARM::VST1qf, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v2i64:$src)
+ // Emits: (VST1q64:isVoid addrmode6:i32:$addr, QPR:v2i64:$src)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (N3.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_219(N, ARM::VST1q64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N2, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N2, N3, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp3, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N2, N3, N4, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_224(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N2, N3, N4, N5, Tmp7, Tmp8 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ SDValue N6 = N.getOperand(6);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N2, N3, N4, N5, N6, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 8);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i8 28:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VHADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(28)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VHADDsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 29:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VHADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(29)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VHADDuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 91:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VRHADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(91)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 92:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VRHADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(92)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 64:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 65:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 16:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VADDHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VADDHNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 88:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VRADDHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(88)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VRADDHNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 53:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMULpd:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(53)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMULpd, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 30:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VHSUBsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(30)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 31:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VHSUBuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(31)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 86:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQSUBsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 87:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQSUBuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 112:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VSUBHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(112)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VSUBHNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 98:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VRSUBHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(98)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VRSUBHNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 9:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VABDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VABDsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 10:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VABDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(10)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VABDuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 5:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VABAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(5)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VABAsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 6:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VABAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VABAuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 39:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMAXsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMAXsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 40:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMAXuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(40)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMAXuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 41:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMINsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMINsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 42:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMINuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(42)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMINuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 56:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VPADDi8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(56)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPADDi8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 59:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VPMAXs8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(59)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXs8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 60:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VPMAXu8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(60)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXu8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 61:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VPMINs8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(61)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPMINs8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 62:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VPMINu8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(62)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPMINu8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 103:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 104:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 94:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VRSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 95:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VRSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 83:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 85:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 78:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQRSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 79:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VQRSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 11:iPTR, DPR:v8i8:$src)
+ // Emits: (VABSv8i8:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VABSv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 63:iPTR, DPR:v8i8:$src)
+ // Emits: (VQABSv8i8:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(63)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VQABSv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 73:iPTR, DPR:v8i8:$src)
+ // Emits: (VQNEGv8i8:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(73)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VQNEGv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 21:iPTR, DPR:v8i8:$src)
+ // Emits: (VCLSv8i8:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(21)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VCLSv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 22:iPTR, DPR:v8i8:$src)
+ // Emits: (VCLZv8i8:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(22)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VCLZv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 23:iPTR, DPR:v8i8:$src)
+ // Emits: (VCNTd:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(23)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VCNTd, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 49:iPTR, QPR:v8i16:$src)
+ // Emits: (VMOVNv8i8:v8i8 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(49)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VMOVNv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 70:iPTR, QPR:v8i16:$src)
+ // Emits: (VQMOVNsv8i8:v8i8 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(70)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNsv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 72:iPTR, QPR:v8i16:$src)
+ // Emits: (VQMOVNuv8i8:v8i8 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(72)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 71:iPTR, QPR:v8i16:$src)
+ // Emits: (VQMOVNsuv8i8:v8i8 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(71)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNsuv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 117:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$src)
+ // Emits: (VTBL1:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(117)) {
+ SDNode *Result = Emit_220(N, ARM::VTBL1, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 118:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
+ // Emits: (VTBL2:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(118)) {
+ SDNode *Result = Emit_221(N, ARM::VTBL2, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 119:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
+ // Emits: (VTBL3:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(119)) {
+ SDNode *Result = Emit_223(N, ARM::VTBL3, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 120:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
+ // Emits: (VTBL4:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(120)) {
+ SDNode *Result = Emit_224(N, ARM::VTBL4, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 121:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$src)
+ // Emits: (VTBX1:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(121)) {
+ SDNode *Result = Emit_221(N, ARM::VTBX1, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 122:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
+ // Emits: (VTBX2:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(122)) {
+ SDNode *Result = Emit_223(N, ARM::VTBX2, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 123:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
+ // Emits: (VTBX3:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(123)) {
+ SDNode *Result = Emit_224(N, ARM::VTBX3, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 124:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
+ // Emits: (VTBX4:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(124)) {
+ SDNode *Result = Emit_225(N, ARM::VTBX4, MVT::v8i8);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 28:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VHADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(28)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VHADDsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 29:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VHADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(29)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VHADDuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 91:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VRHADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(91)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 92:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VRHADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(92)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 64:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 65:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 53:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VMULpq:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(53)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VMULpq, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 30:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VHSUBsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(30)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 31:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VHSUBuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(31)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 86:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQSUBsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 87:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQSUBuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 9:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VABDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VABDsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 10:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VABDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(10)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VABDuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 5:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Emits: (VABAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(5)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8 &&
+ N3.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_221(N, ARM::VABAsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 6:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Emits: (VABAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8 &&
+ N3.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_221(N, ARM::VABAuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 39:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VMAXsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VMAXsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 40:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VMAXuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(40)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VMAXuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 41:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VMINsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VMINsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 42:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VMINuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(42)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VMINuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 103:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 104:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 94:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VRSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 95:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VRSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 83:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 85:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 78:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQRSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 79:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VQRSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v16i8 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 11:iPTR, QPR:v16i8:$src)
+ // Emits: (VABSv16i8:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VABSv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 63:iPTR, QPR:v16i8:$src)
+ // Emits: (VQABSv16i8:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(63)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VQABSv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 73:iPTR, QPR:v16i8:$src)
+ // Emits: (VQNEGv16i8:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(73)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VQNEGv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 21:iPTR, QPR:v16i8:$src)
+ // Emits: (VCLSv16i8:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(21)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VCLSv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 22:iPTR, QPR:v16i8:$src)
+ // Emits: (VCLZv16i8:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(22)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VCLZv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 23:iPTR, QPR:v16i8:$src)
+ // Emits: (VCNTq:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(23)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VCNTq, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N20, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_227(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N2, N10, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 68:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VQDMULHslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 74:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VQRDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VQRDMULHslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 68:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
+ // Emits: (VQDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_227(N, ARM::VQDMULHslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 74:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
+ // Emits: (VQRDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_227(N, ARM::VQRDMULHslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 28:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VHADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(28)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VHADDsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 29:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VHADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(29)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VHADDuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 91:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VRHADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(91)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 92:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VRHADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(92)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 64:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 65:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 16:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VADDHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VADDHNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 88:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VRADDHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(88)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VRADDHNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 68:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQDMULHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQDMULHv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 74:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQRDMULHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQRDMULHv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 30:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VHSUBsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(30)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 31:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VHSUBuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(31)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 86:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQSUBsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 87:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQSUBuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 112:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VSUBHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(112)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VSUBHNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 98:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VRSUBHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(98)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VRSUBHNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 9:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VABDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VABDsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 10:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VABDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(10)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VABDuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 5:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VABAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(5)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VABAsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 6:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VABAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VABAuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 39:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMAXsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VMAXsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 40:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMAXuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(40)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VMAXuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 41:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMINsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VMINsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 42:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMINuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(42)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VMINuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 56:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VPADDi16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(56)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPADDi16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 57:iPTR, DPR:v8i8:$src)
+ // Emits: (VPADDLsv8i8:v4i16 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(57)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLsv8i8, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 58:iPTR, DPR:v8i8:$src)
+ // Emits: (VPADDLuv8i8:v4i16 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(58)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLuv8i8, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 54:iPTR, DPR:v4i16:$src1, DPR:v8i8:$src2)
+ // Emits: (VPADALsv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(54)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPADALsv8i8, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 55:iPTR, DPR:v4i16:$src1, DPR:v8i8:$src2)
+ // Emits: (VPADALuv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(55)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VPADALuv8i8, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 59:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VPMAXs16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(59)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXs16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 60:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VPMAXu16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(60)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXu16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 61:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VPMINs16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(61)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPMINs16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 62:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VPMINu16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(62)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPMINu16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 103:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 104:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 94:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VRSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 95:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VRSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 83:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 85:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 78:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQRSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 79:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQRSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 11:iPTR, DPR:v4i16:$src)
+ // Emits: (VABSv4i16:v4i16 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VABSv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 63:iPTR, DPR:v4i16:$src)
+ // Emits: (VQABSv4i16:v4i16 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(63)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VQABSv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 73:iPTR, DPR:v4i16:$src)
+ // Emits: (VQNEGv4i16:v4i16 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(73)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VQNEGv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 21:iPTR, DPR:v4i16:$src)
+ // Emits: (VCLSv4i16:v4i16 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(21)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VCLSv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 22:iPTR, DPR:v4i16:$src)
+ // Emits: (VCLZv4i16:v4i16 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(22)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VCLZv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 49:iPTR, QPR:v4i32:$src)
+ // Emits: (VMOVNv4i16:v4i16 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(49)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VMOVNv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 70:iPTR, QPR:v4i32:$src)
+ // Emits: (VQMOVNsv4i16:v4i16 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(70)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNsv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 72:iPTR, QPR:v4i32:$src)
+ // Emits: (VQMOVNuv4i16:v4i16 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(72)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 71:iPTR, QPR:v4i32:$src)
+ // Emits: (VQMOVNsuv4i16:v4i16 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(71)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNsuv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = Transform_DSubReg_i16_reg(Tmp4.getNode());
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N20, Tmp5), 0);
+ SDValue Tmp7 = Transform_SubReg_i16_lane(Tmp4.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, Tmp6, Tmp7, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N2, N1, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_230(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N2, N1, N3, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_231(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = Transform_DSubReg_i16_reg(Tmp4.getNode());
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp5), 0);
+ SDValue Tmp7 = Transform_SubReg_i16_lane(Tmp4.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N2, Tmp6, Tmp7, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VQDMULHslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VQRDMULHslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
+ // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_227(N, ARM::VQDMULHslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
+ // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_227(N, ARM::VQRDMULHslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
+ // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
+ // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N10.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
+ // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N10.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 17:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VADDLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(17)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VADDLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 18:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VADDLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(18)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VADDLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 19:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Emits: (VADDWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(19)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VADDWsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 20:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Emits: (VADDWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(20)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VADDWuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 28:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VHADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(28)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VHADDsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 29:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VHADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(29)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VHADDuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 91:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VRHADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(91)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 92:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VRHADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(92)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 64:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 65:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQDMULHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQDMULHv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQRDMULHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQRDMULHv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 51:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMULLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMULLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 52:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMULLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMULLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 50:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VMULLp:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(50)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VMULLp, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 43:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VMLALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VMLALsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 44:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VMLALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VMLALuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 45:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VMLSLsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VMLSLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 46:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VMLSLuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VMLSLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 113:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VSUBLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(113)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VSUBLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 114:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VSUBLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(114)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VSUBLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 115:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Emits: (VSUBWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(115)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VSUBWsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 116:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Emits: (VSUBWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(116)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VSUBWuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 30:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VHSUBsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(30)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 31:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VHSUBuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(31)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 86:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQSUBsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 87:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQSUBuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 9:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VABDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VABDsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 10:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VABDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(10)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VABDuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 7:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VABDLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(7)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VABDLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 8:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VABDLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_220(N, ARM::VABDLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 5:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Emits: (VABAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(5)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N3.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_221(N, ARM::VABAsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 6:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Emits: (VABAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N3.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_221(N, ARM::VABAuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 3:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VABALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(3)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VABALsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 4:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Emits: (VABALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(4)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i8 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_221(N, ARM::VABALuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 39:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VMAXsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VMAXsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 40:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VMAXuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(40)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VMAXuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 41:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VMINsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VMINsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 42:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VMINuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(42)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VMINuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 57:iPTR, QPR:v16i8:$src)
+ // Emits: (VPADDLsv16i8:v8i16 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(57)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLsv16i8, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 58:iPTR, QPR:v16i8:$src)
+ // Emits: (VPADDLuv16i8:v8i16 QPR:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(58)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLuv16i8, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 54:iPTR, QPR:v8i16:$src1, QPR:v16i8:$src2)
+ // Emits: (VPADALsv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(54)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VPADALsv16i8, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 55:iPTR, QPR:v8i16:$src1, QPR:v16i8:$src2)
+ // Emits: (VPADALuv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(55)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_220(N, ARM::VPADALuv16i8, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 103:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 104:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 94:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VRSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 95:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VRSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 83:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 85:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 78:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQRSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 79:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VQRSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i16 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 11:iPTR, QPR:v8i16:$src)
+ // Emits: (VABSv8i16:v8i16 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VABSv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 63:iPTR, QPR:v8i16:$src)
+ // Emits: (VQABSv8i16:v8i16 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(63)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VQABSv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 73:iPTR, QPR:v8i16:$src)
+ // Emits: (VQNEGv8i16:v8i16 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(73)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VQNEGv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 21:iPTR, QPR:v8i16:$src)
+ // Emits: (VCLSv8i16:v8i16 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(21)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VCLSv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 22:iPTR, QPR:v8i16:$src)
+ // Emits: (VCLZv8i16:v8i16 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(22)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VCLZv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 47:iPTR, DPR:v8i8:$src)
+ // Emits: (VMOVLsv8i16:v8i16 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(47)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VMOVLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 48:iPTR, DPR:v8i8:$src)
+ // Emits: (VMOVLuv8i16:v8i16 DPR:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(48)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_222(N, ARM::VMOVLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 19:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1)
+ // Emits: (VADDWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(19)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_229(N, ARM::VADDWsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 20:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1)
+ // Emits: (VADDWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(20)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_229(N, ARM::VADDWuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 43:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
+ // Emits: (VMLALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_230(N, ARM::VMLALsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 44:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
+ // Emits: (VMLALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_230(N, ARM::VMLALuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 45:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
+ // Emits: (VMLSLsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_230(N, ARM::VMLSLsv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 46:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
+ // Emits: (VMLSLuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v8i8 &&
+ N2.getValueType() == MVT::v8i16 &&
+ N3.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_230(N, ARM::VMLSLuv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 68:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VQDMULHslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 74:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VQRDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VQRDMULHslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 68:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
+ // Emits: (VQDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_227(N, ARM::VQDMULHslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 74:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
+ // Emits: (VQRDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_227(N, ARM::VQRDMULHslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 24:iPTR, DPR:v2f32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTf2xsd:v2i32 DPR:v2f32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(24)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTf2xsd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 25:iPTR, DPR:v2f32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTf2xud:v2i32 DPR:v2f32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(25)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTf2xud, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 28:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VHADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(28)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VHADDsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 29:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VHADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(29)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VHADDuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 91:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VRHADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(91)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 92:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VRHADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(92)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 64:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 65:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 16:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VADDHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VADDHNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 88:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VRADDHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(88)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VRADDHNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 68:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQDMULHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQDMULHv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 74:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQRDMULHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQRDMULHv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 30:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VHSUBsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(30)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 31:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VHSUBuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(31)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 86:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQSUBsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 87:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQSUBuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 112:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VSUBHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(112)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VSUBHNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 98:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VRSUBHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(98)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VRSUBHNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 12:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VACGEd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_220(N, ARM::VACGEd, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 14:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VACGTd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_220(N, ARM::VACGTd, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 9:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VABDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VABDsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 10:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VABDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(10)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VABDuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 5:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VABAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(5)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VABAsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 6:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VABAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VABAuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 39:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMAXsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VMAXsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 40:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMAXuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(40)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VMAXuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 41:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMINsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VMINsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 42:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMINuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(42)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VMINuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 56:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VPADDi32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(56)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPADDi32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 57:iPTR, DPR:v4i16:$src)
+ // Emits: (VPADDLsv4i16:v2i32 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(57)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLsv4i16, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 58:iPTR, DPR:v4i16:$src)
+ // Emits: (VPADDLuv4i16:v2i32 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(58)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLuv4i16, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 54:iPTR, DPR:v2i32:$src1, DPR:v4i16:$src2)
+ // Emits: (VPADALsv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(54)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPADALsv4i16, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 55:iPTR, DPR:v2i32:$src1, DPR:v4i16:$src2)
+ // Emits: (VPADALuv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(55)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VPADALuv4i16, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 59:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VPMAXs32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(59)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXs32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 60:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VPMAXu32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(60)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXu32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 61:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VPMINs32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(61)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPMINs32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 62:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VPMINu32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(62)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPMINu32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 89:iPTR, DPR:v2i32:$src)
+ // Emits: (VRECPEd:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(89)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VRECPEd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 96:iPTR, DPR:v2i32:$src)
+ // Emits: (VRSQRTEd:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(96)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VRSQRTEd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 103:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 104:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 94:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VRSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 95:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VRSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 83:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 85:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 78:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQRSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 79:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQRSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 11:iPTR, DPR:v2i32:$src)
+ // Emits: (VABSv2i32:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VABSv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 63:iPTR, DPR:v2i32:$src)
+ // Emits: (VQABSv2i32:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(63)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VQABSv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 73:iPTR, DPR:v2i32:$src)
+ // Emits: (VQNEGv2i32:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(73)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VQNEGv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 21:iPTR, DPR:v2i32:$src)
+ // Emits: (VCLSv2i32:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(21)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VCLSv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 22:iPTR, DPR:v2i32:$src)
+ // Emits: (VCLZv2i32:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(22)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VCLZv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 49:iPTR, QPR:v2i64:$src)
+ // Emits: (VMOVNv2i32:v2i32 QPR:v2i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(49)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_222(N, ARM::VMOVNv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 70:iPTR, QPR:v2i64:$src)
+ // Emits: (VQMOVNsv2i32:v2i32 QPR:v2i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(70)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNsv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 72:iPTR, QPR:v2i64:$src)
+ // Emits: (VQMOVNuv2i32:v2i32 QPR:v2i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(72)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 71:iPTR, QPR:v2i64:$src)
+ // Emits: (VQMOVNsuv2i32:v2i32 QPR:v2i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(71)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_222(N, ARM::VQMOVNsuv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_233(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N31)->getZExtValue()), MVT::i32);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N2, N30, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_234(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = Transform_DSubReg_i32_reg(Tmp4.getNode());
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N20, Tmp5), 0);
+ SDValue Tmp7 = Transform_SubReg_i32_lane(Tmp4.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, Tmp6, Tmp7, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_235(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N31)->getZExtValue()), MVT::i32);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N2, N1, N30, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_236(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = Transform_DSubReg_i32_reg(Tmp4.getNode());
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp5), 0);
+ SDValue Tmp7 = Transform_SubReg_i32_lane(Tmp4.getNode());
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N2, Tmp6, Tmp7, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VQDMULHslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VQRDMULHslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 51:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VMULLslsv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VMULLslsv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 52:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VMULLsluv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VMULLsluv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 69:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULLslv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(69)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_226(N, ARM::VQDMULLslv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLALslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_233(N, ARM::VMLALslsv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLALsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_233(N, ARM::VMLALsluv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLALslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_233(N, ARM::VQDMLALslv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_233(N, ARM::VMLSLslsv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_233(N, ARM::VMLSLsluv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLSLslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_233(N, ARM::VQDMLSLslv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
+ // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_227(N, ARM::VQDMULHslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
+ // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_227(N, ARM::VQRDMULHslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 51:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
+ // Emits: (VMULLslsv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_227(N, ARM::VMULLslsv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 52:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
+ // Emits: (VMULLsluv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_227(N, ARM::VMULLsluv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 69:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
+ // Emits: (VQDMULLslv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(69)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N10.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_227(N, ARM::VQDMULLslv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLALslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_235(N, ARM::VMLALslsv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLALsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_235(N, ARM::VMLALsluv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLALslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_235(N, ARM::VQDMLALslv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_235(N, ARM::VMLSLslsv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_235(N, ARM::VMLSLsluv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLSLslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16 &&
+ N30.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_235(N, ARM::VQDMLSLslv4i16, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
+ // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
+ // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N10.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_236(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
+ // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 14 cost = 2 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N10.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_236(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 24:iPTR, QPR:v4f32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTf2xsq:v4i32 QPR:v4f32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(24)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTf2xsq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 25:iPTR, QPR:v4f32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTf2xuq:v4i32 QPR:v4f32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(25)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTf2xuq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 17:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VADDLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(17)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VADDLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 18:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VADDLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(18)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VADDLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 19:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Emits: (VADDWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(19)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VADDWsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 20:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Emits: (VADDWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(20)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VADDWuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 28:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VHADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(28)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VHADDsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 29:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VHADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(29)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VHADDuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 91:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VRHADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(91)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 92:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VRHADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(92)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VRHADDuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 64:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 65:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQDMULHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(68)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQDMULHv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQRDMULHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(74)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQRDMULHv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 51:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMULLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VMULLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 52:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMULLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VMULLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 69:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VQDMULLv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(69)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VQDMULLv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VMLALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VMLALsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VMLALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VMLALuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VQDMLALv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VMLSLsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VMLSLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VMLSLuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VMLSLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VQDMLSLv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 113:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VSUBLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(113)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VSUBLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 114:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VSUBLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(114)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VSUBLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 115:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Emits: (VSUBWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(115)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VSUBWsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 116:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Emits: (VSUBWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(116)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VSUBWuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 30:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VHSUBsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(30)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 31:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VHSUBuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(31)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VHSUBuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 86:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQSUBsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 87:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQSUBuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 13:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VACGEq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_220(N, ARM::VACGEq, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 15:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VACGTq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_220(N, ARM::VACGTq, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 9:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VABDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VABDsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 10:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VABDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(10)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VABDuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 7:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VABDLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(7)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VABDLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 8:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VABDLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_220(N, ARM::VABDLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 5:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Emits: (VABAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(5)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_221(N, ARM::VABAsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 6:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Emits: (VABAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_221(N, ARM::VABAuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 3:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VABALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(3)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VABALsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 4:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Emits: (VABALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(4)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i16 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_221(N, ARM::VABALuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 39:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VMAXsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VMAXsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 40:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VMAXuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(40)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VMAXuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 41:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VMINsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VMINsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 42:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VMINuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(42)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VMINuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 57:iPTR, QPR:v8i16:$src)
+ // Emits: (VPADDLsv8i16:v4i32 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(57)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLsv8i16, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 58:iPTR, QPR:v8i16:$src)
+ // Emits: (VPADDLuv8i16:v4i32 QPR:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(58)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLuv8i16, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 54:iPTR, QPR:v4i32:$src1, QPR:v8i16:$src2)
+ // Emits: (VPADALsv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(54)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VPADALsv8i16, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 55:iPTR, QPR:v4i32:$src1, QPR:v8i16:$src2)
+ // Emits: (VPADALuv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(55)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_220(N, ARM::VPADALuv8i16, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 89:iPTR, QPR:v4i32:$src)
+ // Emits: (VRECPEq:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(89)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VRECPEq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 96:iPTR, QPR:v4i32:$src)
+ // Emits: (VRSQRTEq:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(96)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VRSQRTEq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 103:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 104:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 94:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VRSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 95:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VRSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 83:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 85:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 78:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQRSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 79:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VQRSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i32 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 11:iPTR, QPR:v4i32:$src)
+ // Emits: (VABSv4i32:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VABSv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 63:iPTR, QPR:v4i32:$src)
+ // Emits: (VQABSv4i32:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(63)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VQABSv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 73:iPTR, QPR:v4i32:$src)
+ // Emits: (VQNEGv4i32:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(73)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VQNEGv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 21:iPTR, QPR:v4i32:$src)
+ // Emits: (VCLSv4i32:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(21)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VCLSv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 22:iPTR, QPR:v4i32:$src)
+ // Emits: (VCLZv4i32:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(22)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VCLZv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 47:iPTR, DPR:v4i16:$src)
+ // Emits: (VMOVLsv4i32:v4i32 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(47)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VMOVLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 48:iPTR, DPR:v4i16:$src)
+ // Emits: (VMOVLuv4i32:v4i32 DPR:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(48)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_222(N, ARM::VMOVLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 19:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1)
+ // Emits: (VADDWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(19)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_229(N, ARM::VADDWsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 20:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1)
+ // Emits: (VADDWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(20)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_229(N, ARM::VADDWuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
+ // Emits: (VMLALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_230(N, ARM::VMLALsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
+ // Emits: (VMLALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_230(N, ARM::VMLALuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
+ // Emits: (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_230(N, ARM::VQDMLALv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
+ // Emits: (VMLSLsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_230(N, ARM::VMLSLsv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
+ // Emits: (VMLSLuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_230(N, ARM::VMLSLuv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
+ // Emits: (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v4i16 &&
+ N2.getValueType() == MVT::v4i32 &&
+ N3.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_230(N, ARM::VQDMLSLv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v1i64 64:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQADDsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 65:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQADDuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 86:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQSUBsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 87:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQSUBuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 57:iPTR, DPR:v2i32:$src)
+ // Emits: (VPADDLsv2i32:v1i64 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(57)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLsv2i32, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 58:iPTR, DPR:v2i32:$src)
+ // Emits: (VPADDLuv2i32:v1i64 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(58)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLuv2i32, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 54:iPTR, DPR:v1i64:$src1, DPR:v2i32:$src2)
+ // Emits: (VPADALsv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(54)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPADALsv2i32, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 55:iPTR, DPR:v1i64:$src1, DPR:v2i32:$src2)
+ // Emits: (VPADALuv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(55)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VPADALuv2i32, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 103:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 104:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 94:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VRSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 95:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VRSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 83:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 85:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 78:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQRSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 79:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Emits: (VQRSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v1i64 &&
+ N2.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv1i64, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 51:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VMULLslsv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VMULLslsv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 52:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VMULLsluv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VMULLsluv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 69:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VQDMULLslv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(69)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ if (N21.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_226(N, ARM::VQDMULLslv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLALslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_233(N, ARM::VMLALslsv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLALsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_233(N, ARM::VMLALsluv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLALslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_233(N, ARM::VQDMLALslv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_233(N, ARM::VMLSLslsv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_233(N, ARM::VMLSLsluv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLSLslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_233(N, ARM::VQDMLSLslv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 51:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
+ // Emits: (VMULLslsv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_227(N, ARM::VMULLslsv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 52:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
+ // Emits: (VMULLsluv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_227(N, ARM::VMULLsluv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 69:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
+ // Emits: (VQDMULLslv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(69)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N10.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_227(N, ARM::VQDMULLslv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLALslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_235(N, ARM::VMLALslsv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLALsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_235(N, ARM::VMLALsluv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLALslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_235(N, ARM::VQDMLALslv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_235(N, ARM::VMLSLslsv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VMLSLsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_235(N, ARM::VMLSLsluv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
+ // Emits: (VQDMLSLslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ if (N31.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32 &&
+ N30.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_235(N, ARM::VQDMLSLslv2i32, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 17:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VADDLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(17)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VADDLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 18:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VADDLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(18)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VADDLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 19:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Emits: (VADDWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(19)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VADDWsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 20:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Emits: (VADDWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(20)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VADDWuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 64:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQADDsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(64)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQADDsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 65:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQADDuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(65)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQADDuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 51:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMULLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(51)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VMULLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 52:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMULLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(52)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VMULLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 69:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VQDMULLv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(69)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VQDMULLv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VMLALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VMLALsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VMLALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VMLALuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VQDMLALv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VMLSLsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VMLSLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VMLSLuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VMLSLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VQDMLSLv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 113:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VSUBLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(113)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VSUBLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 114:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VSUBLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(114)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VSUBLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 115:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Emits: (VSUBWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(115)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VSUBWsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 116:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Emits: (VSUBWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(116)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VSUBWuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 86:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQSUBsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(86)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 87:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQSUBuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(87)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSUBuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 7:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VABDLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(7)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VABDLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 8:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VABDLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_220(N, ARM::VABDLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 3:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VABALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(3)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VABALsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 4:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Emits: (VABALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(4)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i32 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_221(N, ARM::VABALuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 57:iPTR, QPR:v4i32:$src)
+ // Emits: (VPADDLsv4i32:v2i64 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(57)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLsv4i32, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 58:iPTR, QPR:v4i32:$src)
+ // Emits: (VPADDLuv4i32:v2i64 QPR:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(58)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_222(N, ARM::VPADDLuv4i32, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 54:iPTR, QPR:v2i64:$src1, QPR:v4i32:$src2)
+ // Emits: (VPADALsv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(54)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VPADALsv4i32, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 55:iPTR, QPR:v2i64:$src1, QPR:v4i32:$src2)
+ // Emits: (VPADALuv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(55)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_220(N, ARM::VPADALuv4i32, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 103:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(103)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VSHLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 104:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(104)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VSHLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 94:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VRSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(94)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 95:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VRSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(95)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VRSHLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 83:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(83)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 85:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(85)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQSHLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 78:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQRSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(78)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 79:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Emits: (VQRSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(79)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i64 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_220(N, ARM::VQRSHLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 47:iPTR, DPR:v2i32:$src)
+ // Emits: (VMOVLsv2i64:v2i64 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(47)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VMOVLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 48:iPTR, DPR:v2i32:$src)
+ // Emits: (VMOVLuv2i64:v2i64 DPR:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(48)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_222(N, ARM::VMOVLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 19:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1)
+ // Emits: (VADDWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(19)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_229(N, ARM::VADDWsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 20:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1)
+ // Emits: (VADDWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(20)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_229(N, ARM::VADDWuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
+ // Emits: (VMLALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(43)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_230(N, ARM::VMLALsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
+ // Emits: (VMLALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(44)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_230(N, ARM::VMLALuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
+ // Emits: (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(66)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_230(N, ARM::VQDMLALv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
+ // Emits: (VMLSLsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(45)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_230(N, ARM::VMLSLsv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
+ // Emits: (VMLSLuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(46)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_230(N, ARM::VMLSLuv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
+ // Emits: (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(67)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N1.getValueType() == MVT::v2i32 &&
+ N2.getValueType() == MVT::v2i64 &&
+ N3.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_230(N, ARM::VQDMLSLv2i64, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f32 26:iPTR, DPR:v2i32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTxs2fd:v2f32 DPR:v2i32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(26)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTxs2fd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 27:iPTR, DPR:v2i32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTxu2fd:v2f32 DPR:v2i32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(27)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTxu2fd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 9:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VABDfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VABDfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 39:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VMAXfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VMAXfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 41:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VMINfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VMINfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 56:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VPADDf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(56)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VPADDf, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 59:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VPMAXf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(59)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VPMAXf, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 61:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VPMINf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(61)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VPMINf, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 89:iPTR, DPR:v2f32:$src)
+ // Emits: (VRECPEfd:v2f32 DPR:v2f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(89)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_222(N, ARM::VRECPEfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 90:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VRECPSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(90)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VRECPSfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 96:iPTR, DPR:v2f32:$src)
+ // Emits: (VRSQRTEfd:v2f32 DPR:v2f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(96)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_222(N, ARM::VRSQRTEfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 97:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Emits: (VRSQRTSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(97)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v2f32 &&
+ N2.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_220(N, ARM::VRSQRTSfd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f32 11:iPTR, DPR:v2f32:$src)
+ // Emits: (VABSfd:v2f32 DPR:v2f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_222(N, ARM::VABSfd, MVT::v2f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 26:iPTR, QPR:v4i32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTxs2fq:v4f32 QPR:v4i32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(26)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTxs2fq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 27:iPTR, QPR:v4i32:$src, (imm:i32):$SIMM)
+ // Emits: (VCVTxu2fq:v4f32 QPR:v4i32:$src, (imm:i32):$SIMM)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(27)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_232(N, ARM::VCVTxu2fq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 9:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VABDfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4f32 &&
+ N2.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_220(N, ARM::VABDfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 39:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VMAXfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(39)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4f32 &&
+ N2.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_220(N, ARM::VMAXfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 41:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VMINfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(41)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4f32 &&
+ N2.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_220(N, ARM::VMINfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 89:iPTR, QPR:v4f32:$src)
+ // Emits: (VRECPEfq:v4f32 QPR:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(89)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_222(N, ARM::VRECPEfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 90:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VRECPSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(90)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4f32 &&
+ N2.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_220(N, ARM::VRECPSfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 96:iPTR, QPR:v4f32:$src)
+ // Emits: (VRSQRTEfq:v4f32 QPR:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(96)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_222(N, ARM::VRSQRTEfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 97:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Emits: (VRSQRTSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(97)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1.getValueType() == MVT::v4f32 &&
+ N2.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_220(N, ARM::VRSQRTSfq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 11:iPTR, QPR:v4f32:$src)
+ // Emits: (VABSfq:v4f32 QPR:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_222(N, ARM::VABSfq, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, Tmp3, Tmp4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+}
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1d8, MVT::v8i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1q8, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1d16, MVT::v4i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1q16, MVT::v8i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1d32, MVT::v2i32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1q32, MVT::v4i32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1d64, MVT::v1i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1q64, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1df, MVT::v2f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_237(N, ARM::VLD1qf, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_238(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, Tmp1, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 5);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_239(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp1, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_240(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N10, Tmp1, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp1, Tmp2, Chain };
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ Chain = SDValue(Tmp3.getNode(), 1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
+ MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDNode *ResNode = CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp3, Tmp4, Tmp5);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
+ ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp3, Tmp4, Chain };
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ Chain = SDValue(Tmp5.getNode(), 1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp1, Tmp5, Tmp6, Tmp7, Tmp8 };
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp10 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
+ MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops2[] = { Tmp0, Tmp9, Tmp10, Tmp11, Tmp12 };
+ SDNode *ResNode = CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Ops2, 5);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
+ ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_243(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp3, Tmp4, Chain };
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ Chain = SDValue(Tmp5.getNode(), 1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp1, Tmp5, Tmp6, Tmp7, Tmp8 };
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp10 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
+ SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
+ MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops2[] = { Tmp0, Tmp9, Tmp10, Tmp11, Tmp12 };
+ SDNode *ResNode = CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Ops2, 5);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
+ ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ return ResNode;
+}
+SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (PICLDR:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDR, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (PICLDRH:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (PICLDRB:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (PICLDRSH:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDRSH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (PICLDRSB:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDRSB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_rr:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (tLDRSB:i32 t_addrmode_rr:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectThumbAddrModeRR(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::tLDRSB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_rr:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (tLDRSH:i32 t_addrmode_rr:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectThumbAddrModeRR(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::tLDRSH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LDR:i32 addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDR, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (LDRH:i32 addrmode3:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (LDRB:i32 addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (LDRSH:i32 addrmode3:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRSH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (LDRSB:i32 addrmode3:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRSB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_s4:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (tLDR:i32 t_addrmode_s4:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS4(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDR, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (tLDRH:i32 t_addrmode_s2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (t2LDRs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (t2LDRHs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRHs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (t2LDRSHs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRSHs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (t2LDRSBs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRSBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (tLDRH:i32 t_addrmode_s2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::tLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (t2LDRHs:i32 t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::t2LDRHs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (LDRB:i32 addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (LDRB:i32 addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (LDRB:i32 addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (LDRH:i32 addrmode3:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_239(N, ARM::LDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (tSXTB:i32 (tLDRB:i32 t_addrmode_s1:i32:$addr))
+ // Pattern complexity = 16 cost = 2 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_241(N, ARM::tLDRB, ARM::tSXTB, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (tSXTH:i32 (tLDRH:i32 t_addrmode_s2:i32:$addr))
+ // Pattern complexity = 16 cost = 2 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_241(N, ARM::tLDRH, ARM::tSXTH, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (tASRri:i32 (tLSLri:i32 (tLDRB:i32 t_addrmode_s1:i32:$addr), 24:i32), 24:i32)
+ // Pattern complexity = 16 cost = 3 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_242(N, ARM::tLDRB, ARM::tLSLri, ARM::tASRri, MVT::i32, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (tASRri:i32 (tLSLri:i32 (tLDRH:i32 t_addrmode_s1:i32:$addr), 16:i32), 16:i32)
+ // Pattern complexity = 16 cost = 3 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_243(N, ARM::tLDRH, ARM::tLSLri, ARM::tASRri, MVT::i32, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 t_addrmode_sp:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (tLDRspi:i32 t_addrmode_sp:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectThumbAddrModeSP(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::tLDRspi, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (t2LDRi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (t2LDRi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (t2LDRHi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRHi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (t2LDRHi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRHi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (t2LDRSHi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRSHi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (t2LDRSHi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRSHi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (t2LDRSBi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRSBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (t2LDRSBi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRSBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (t2LDRHi12:i32 t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRHi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (t2LDRHi8:i32 t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::t2LDRHi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (PICLDRB:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (PICLDRH:i32 addrmodepc:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::PICLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (tLDRpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::tLDRpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (t2LDRpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (t2LDRHpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRHpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (t2LDRSHpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRSHpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (t2LDRSBpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRSBpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (t2LDRHpci:i32 (tconstpool:i32):$addr)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_240(N, ARM::t2LDRHpci, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrMode5(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::VLDRS, MVT::f32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
+ if ((Subtarget->hasVFP2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrMode5(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::VLDRD, MVT::f64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrMode4(N, N1, CPTmpN1_0, CPTmpN1_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_238(N, ARM::VLDRQ, MVT::v2f64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_244(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N10, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_245(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N10, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N10, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_247(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp10 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp11 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N100, Tmp10, Tmp11 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N10, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N10, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_250(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N100, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_251(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N1, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_252(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N00, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_253(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N00, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_254(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp10 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp11 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N000, Tmp10, Tmp11 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_255(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N100, N00, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_256(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, N00, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_257(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N000, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N0, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_MUL_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp6) {
+ int64_t CN7 = Tmp6->getSExtValue();
+ if (CN7 == INT64_C(16) &&
+ N001.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+
+ // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32))
+ // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 35 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_247(N, ARM::SMULBB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32))
+ // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 35 cost = 1 size = 0
+ SDNode *Result = Emit_254(N, ARM::SMULBB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
+ // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 27 cost = 1 size = 0
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N001.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_248(N, ARM::SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N01.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32))
+ // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 27 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_250(N, ARM::SMULTB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32))
+ // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 27 cost = 1 size = 0
+ SDNode *Result = Emit_255(N, ARM::SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
+ // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N001.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_257(N, ARM::SMULTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
+ // Emits: (SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N01.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_246(N, ARM::SMULTT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
+ // Emits: (t2SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N01.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_246(N, ARM::t2SMULTT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
+ // Emits: (SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N01.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_253(N, ARM::SMULTT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
+ // Emits: (t2SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N01.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_253(N, ARM::t2SMULTT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32))
+ // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_245(N, ARM::SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other))
+ // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_245(N, ARM::SMULTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32))
+ // Emits: (t2SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_245(N, ARM::t2SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other))
+ // Emits: (t2SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_245(N, ARM::t2SMULTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other))
+ // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_252(N, ARM::SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32))
+ // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_252(N, ARM::SMULTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other))
+ // Emits: (t2SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_252(N, ARM::t2SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32))
+ // Emits: (t2SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_252(N, ARM::t2SMULTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32))
+ // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (Predicate_sext_16_node(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_249(N, ARM::SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (Predicate_sext_16_node(N1.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b)
+ // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_251(N, ARM::SMULTB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a)
+ // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDNode *Result = Emit_256(N, ARM::SMULBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, (sra:i32 GPR:i32:$a, 16:i32))
+ // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (Predicate_sext_16_node(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_258(N, ARM::SMULTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other))
+ // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_244(N, ARM::SMULBB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other))
+ // Emits: (t2SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_244(N, ARM::t2SMULBB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b)
+ // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 5 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (Predicate_sext_16_node(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (Predicate_sext_16_node(N1.getNode())) {
+ SDNode *Result = Emit_44(N, ARM::SMULBB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (MUL:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_56(N, ARM::MUL, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tMUL:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_66(N, ARM::tMUL, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (t2MUL:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_44(N, ARM::t2MUL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v8i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VMULv8i8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VMULv16i8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v4i16 DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VMULslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_126(N, ARM::VMULslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
+ // Emits: (VMULslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_128(N, ARM::VMULslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VMULv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VMULv4i16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp3), 0);
+ SDValue Tmp5 = Transform_SubReg_i16_lane(Tmp2.getNode());
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N0, Tmp4, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_260(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp5 = Transform_SubReg_i16_lane(Tmp2.getNode());
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { N1, Tmp4, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v8i16 QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
+ // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_126(N, ARM::VMULslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
+ // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_128(N, ARM::VMULslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v8i16 QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
+ // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 9 cost = 2 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_259(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
+ // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 9 cost = 2 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_260(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VMULv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VMULv8i16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v2i32 DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VMULslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_126(N, ARM::VMULslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
+ // Emits: (VMULslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_128(N, ARM::VMULslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VMULv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VMULv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v4i32 QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
+ // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_126(N, ARM::VMULslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
+ // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_128(N, ARM::VMULslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v4i32 QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
+ // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 9 cost = 2 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
+ // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 9 cost = 2 size = 0
+ if (N0.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VMULv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VMULv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MULHS_i32(const SDValue &N) {
+
+ // Pattern: (mulhs:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (SMMUL:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDNode *Result = Emit_44(N, ARM::SMMUL, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mulhs:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (t2SMMUL:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_44(N, ARM::t2SMMUL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_261(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_hi16(Tmp2.getNode());
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N11000 = N1100.getOperand(0);
+ SDValue N11001 = N1100.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ SDValue N11100 = N1110.getOperand(0);
+ SDValue N11101 = N1110.getOperand(1);
+ SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N100, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_264(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xFFFFULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N10, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N10, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N10, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_268(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N10000 = N1000.getOperand(0);
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N10100 = N1010.getOperand(0);
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_269(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ SDValue N00100 = N0010.getOperand(0);
+ SDValue N00101 = N0010.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N01000 = N0100.getOperand(0);
+ SDValue N01001 = N0100.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ SDValue N01100 = N0110.getOperand(0);
+ SDValue N01101 = N0110.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N000, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N00, Tmp4, Tmp5, Tmp6 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N00, Tmp3, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N10, N00, Tmp5, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_OR_i32(const SDValue &N) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp3 &&
+ CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6 &&
+ CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
+ N1100.getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp3 &&
+ CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6 &&
+ CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
+ N1100.getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp3 &&
+ CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6 &&
+ CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
+ N1100.getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::OR) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::AND) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
+ N1000.getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
+ N110.getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
+ N110.getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
+ N1000.getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
+ N1010.getOpcode() == ISD::SRL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp3) {
+ if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
+ N1110.getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
+ N1100.getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
+ N100.getOpcode() == ISD::SRL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6 &&
+ CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
+ N1110.getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::OR) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
+ N0010.getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
+ N0000.getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
+ N010.getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
+ N010.getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
+ N0000.getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
+ N0010.getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N00.getOpcode() == ISD::AND) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
+ N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
+ N0110.getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
+ N0100.getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
+ N000.getOpcode() == ISD::SRL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
+ N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
+ N0100.getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
+ N0110.getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::OR) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::AND) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
+ N1000.getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
+ N110.getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
+ N110.getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
+ N1000.getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
+ N1010.getOpcode() == ISD::SRL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp3) {
+ if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
+ N1110.getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
+ N1100.getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
+ N100.getOpcode() == ISD::SRL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6 &&
+ CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
+ N1110.getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::OR) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
+ N0010.getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
+ N0000.getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
+ N010.getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
+ N010.getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
+ N0000.getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
+ N0010.getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N00.getOpcode() == ISD::AND) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
+ N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
+ N0110.getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
+ N0100.getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
+ N000.getOpcode() == ISD::SRL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
+ N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
+ N0100.getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (tREV16:i32 tGPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
+ N0110.getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(255)) &&
+ N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::OR) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::AND) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
+ N1000.getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
+ N110.getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
+ N110.getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
+ N1000.getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
+ N1010.getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
+ N1000.getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getOperand(0);
+ if (N000 == N10000) {
+ SDValue N10001 = N1000.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ if (Tmp6 &&
+ CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
+ N1010.getOpcode() == ISD::SRL) {
+ SDValue N10100 = N1010.getOperand(0);
+ if (N000 == N10100) {
+ SDValue N10101 = N1010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp9 &&
+ CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
+ N110.getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getOperand(0);
+ if (N000 == N1100) {
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N10001.getValueType() == MVT::i32 &&
+ N10101.getValueType() == MVT::i32 &&
+ N1101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp3) {
+ if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
+ N1110.getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
+ N1100.getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
+ N100.getOpcode() == ISD::SRL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
+ N1110.getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
+ N100.getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N000 == N1000) {
+ SDValue N1001 = N100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ if (Tmp6 &&
+ CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
+ N1100.getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getOperand(0);
+ if (N000 == N11000) {
+ SDValue N11001 = N1100.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ if (Tmp9 &&
+ CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
+ N1110.getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getOperand(0);
+ if (N000 == N11100) {
+ SDValue N11101 = N1110.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N001.getValueType() == MVT::i32 &&
+ N1001.getValueType() == MVT::i32 &&
+ N11001.getValueType() == MVT::i32 &&
+ N11101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::OR) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
+ N0010.getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
+ N0000.getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
+ N010.getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
+ N010.getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
+ N0000.getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
+ N0010.getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
+ N0000.getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getOperand(0);
+ SDValue N00001 = N0000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getOperand(0);
+ SDValue N0011 = N001.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ if (Tmp3 &&
+ CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
+ N0010.getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getOperand(0);
+ if (N00000 == N00100) {
+ SDValue N00101 = N0010.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp6 &&
+ CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
+ N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ if (N00000 == N0100) {
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N00000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N00001.getValueType() == MVT::i32 &&
+ N00101.getValueType() == MVT::i32 &&
+ N0101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N00.getOpcode() == ISD::AND) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
+ N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
+ N0110.getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
+ N0100.getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
+ N000.getOpcode() == ISD::SRL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
+ N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp3) {
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
+ N0100.getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
+ N0110.getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
+ // Emits: (t2REV16:i32 GPR:i32:$src)
+ // Pattern complexity = 73 cost = 1 size = 0
+ if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
+ N0100.getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getOperand(0);
+ if (N0000 == N01000) {
+ SDValue N01001 = N0100.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(8)) {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getOperand(0);
+ SDValue N0111 = N011.getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ if (Tmp6 &&
+ CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
+ N0110.getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getOperand(0);
+ if (N0000 == N01100) {
+ SDValue N01101 = N0110.getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ if (Tmp7) {
+ int64_t CN8 = Tmp7->getSExtValue();
+ if (CN8 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp9 &&
+ CheckAndMask(N10, Tmp9, INT64_C(255)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ if (N0000 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp10) {
+ int64_t CN11 = Tmp10->getSExtValue();
+ if (CN11 == INT64_C(8) &&
+ N0001.getValueType() == MVT::i32 &&
+ N01001.getValueType() == MVT::i32 &&
+ N01101.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32))
+ // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
+ N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, ARM::PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535))) {
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32))
+ // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, ARM::t2PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32))
+ // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_imm1_15(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, ARM::t2PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32))
+ // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
+ N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ Predicate_imm1_15(N101.getNode()) &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, ARM::PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
+ // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
+ N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
+ N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_271(N, ARM::PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+
+ // Pattern: (or:i32 (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
+ // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
+ N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_271(N, ARM::t2PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
+ // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_imm1_15(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
+ N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_271(N, ARM::t2PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+
+ // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
+ // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
+ // Pattern complexity = 26 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant &&
+ Predicate_imm1_15(N001.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
+ N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_271(N, ARM::PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32))
+ // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 25 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
+ N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, ARM::PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32))
+ // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
+ N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant &&
+ N101.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, ARM::t2PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
+ // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(4294901760)) &&
+ N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
+ N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_271(N, ARM::PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i32 (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
+ // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(4294901760)) &&
+ N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
+ N001.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_271(N, ARM::t2PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (t2ORNrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 19 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue CPTmpN10_0;
+ SDValue CPTmpN10_1;
+ if (SelectT2ShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_169(N, ARM::t2ORNrs, MVT::i32, CPTmpN10_0, CPTmpN10_1);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 GPR:i32:$src2, 4294901760:i32))
+ // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760))) {
+ SDNode *Result = Emit_265(N, ARM::t2PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (srl:i32 GPR:i32:$src2, 16:i32))
+ // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_267(N, ARM::t2PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 GPR:i32:$src2, 4294901760:i32))
+ // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(4294901760))) {
+ SDNode *Result = Emit_265(N, ARM::PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (srl:i32 GPR:i32:$src2, 16:i32))
+ // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(16) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_267(N, ARM::PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i32 (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
+ // Emits: (t2ORNrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue CPTmpN00_0;
+ SDValue CPTmpN00_1;
+ if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_180(N, ARM::t2ORNrs, MVT::i32, CPTmpN00_0, CPTmpN00_1);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src2, 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
+ // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535))) {
+ SDNode *Result = Emit_272(N, ARM::t2PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (srl:i32 GPR:i32:$src2, 16:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
+ // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2 &&
+ CheckAndMask(N10, Tmp2, INT64_C(4294901760)) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_274(N, ARM::t2PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src2, 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
+ // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp1 &&
+ CheckAndMask(N10, Tmp1, INT64_C(65535))) {
+ SDNode *Result = Emit_272(N, ARM::PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (srl:i32 GPR:i32:$src2, 16:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
+ // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp2 &&
+ CheckAndMask(N10, Tmp2, INT64_C(4294901760)) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_274(N, ARM::PKHTB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt))
+ // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
+ // Pattern complexity = 18 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N11.getNode()) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_266(N, ARM::t2PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt))
+ // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
+ // Pattern complexity = 18 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N11.getNode()) &&
+ N11.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_266(N, ARM::PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), (and:i32 GPR:i32:$src1, 65535:i32))
+ // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
+ // Pattern complexity = 18 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_273(N, ARM::t2PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), (and:i32 GPR:i32:$src1, 65535:i32))
+ // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
+ // Pattern complexity = 18 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_imm16_31(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_273(N, ARM::PKHBT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src, 65535:i32), (imm:i32)<<P:Predicate_lo16AllZero>><<X:hi16>>:$imm)
+ // Emits: (MOVTi16:i32 GPR:i32:$src, (hi16:i32 (imm:i32):$imm))
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_lo16AllZero(N1.getNode())) {
+ SDNode *Result = Emit_261(N, ARM::MOVTi16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (ORRrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_57(N, ARM::ORRrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 (and:i32 GPR:i32:$src, 65535:i32), (imm:i32)<<P:Predicate_lo16AllZero>><<X:hi16>>:$imm)
+ // Emits: (t2MOVTi16:i32 GPR:i32:$src, (hi16:i32 (imm:i32):$imm))
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0 &&
+ CheckAndMask(N00, Tmp0, INT64_C(65535))) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_lo16AllZero(N1.getNode())) {
+ SDNode *Result = Emit_261(N, ARM::t2MOVTi16, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (ORRrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_88(N, ARM::ORRrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_165(N, ARM::t2ORNri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
+ // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_immAllOnes(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N11.getNode())) {
+ SDNode *Result = Emit_174(N, ARM::t2ORNri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i32 (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
+ // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_175(N, ARM::t2ORNri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
+ // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (Predicate_immAllOnes(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N01.getNode())) {
+ SDNode *Result = Emit_176(N, ARM::t2ORNri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2ORRrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_68(N, ARM::t2ORRrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2ORRrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_103(N, ARM::t2ORRrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (t2ORNrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_166(N, ARM::t2ORNrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
+ // Emits: (t2ORNrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_177(N, ARM::t2ORNrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$src, 4294901760:i32)
+ // Emits: (t2MOVTi16:i32 GPR:i32:$src, 65535:i32)
+ // Pattern complexity = 8 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckOrMask(N0, Tmp0, INT64_C(4294901760))) {
+ SDNode *Result = Emit_264(N, ARM::t2MOVTi16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$src, 4294901760:i32)
+ // Emits: (MOVTi16:i32 GPR:i32:$src, 65535:i32)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckOrMask(N0, Tmp0, INT64_C(4294901760))) {
+ SDNode *Result = Emit_264(N, ARM::MOVTi16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (ORRri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::ORRri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2ORRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2ORRri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$imm)
+ // Emits: (t2ORNri:i32 GPR:i32:$src, (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm_not(N1.getNode())) {
+ SDNode *Result = Emit_172(N, ARM::t2ORNri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
+ // Emits: (t2ORRri:i32 (t2ORRri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ if (Predicate_t2_so_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_71(N, ARM::t2ORRri, ARM::t2ORRri, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+
+ // Pattern: (or:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
+ // Emits: (ORRri:i32 (ORRri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_74(N, ARM::ORRri, ARM::ORRri, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (ORRrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_56(N, ARM::ORRrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tORR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_66(N, ARM::tORR, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ORRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_56(N, ARM::t2ORRrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N00, N10, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N00, N11, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, N10, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, N11, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_279(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N010, N10, N00, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N010, N11, N00, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N011, N10, N00, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N011, N11, N00, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_283(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N10, N01, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_284(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N000, N11, N01, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_285(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N001, N10, N01, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_286(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N001, N11, N01, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ {
+ SDValue N01 = N0.getOperand(1);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N01 == N110) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N111.getNode())) {
+ SDNode *Result = Emit_275(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111) {
+ SDNode *Result = Emit_275(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N01 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N101.getNode())) {
+ SDNode *Result = Emit_276(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ if (N01 == N101) {
+ SDNode *Result = Emit_276(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N00 == N110) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N111.getNode())) {
+ SDNode *Result = Emit_277(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ if (N00 == N111) {
+ SDNode *Result = Emit_277(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N00 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N101.getNode())) {
+ SDNode *Result = Emit_278(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ if (N00 == N101) {
+ SDNode *Result = Emit_278(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N01.getOpcode() == ISD::XOR) {
+ SDValue N010 = N01.getOperand(0);
+ {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N011.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N010 == N11) {
+ SDNode *Result = Emit_279(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N010 == N10) {
+ SDNode *Result = Emit_280(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N010.getNode())) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11) {
+ SDNode *Result = Emit_281(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N011 == N10) {
+ SDNode *Result = Emit_282(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N00.getOpcode() == ISD::XOR) {
+ SDValue N000 = N00.getOperand(0);
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N001.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N000 == N11) {
+ SDNode *Result = Emit_283(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N000 == N10) {
+ SDNode *Result = Emit_284(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N001 == N11) {
+ SDNode *Result = Emit_285(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
+ // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N001 == N10) {
+ SDNode *Result = Emit_286(N, ARM::VBSLd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v2i32 DPR:v2i32:$src1, (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>))
+ // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N11.getNode())) {
+ SDNode *Result = Emit_51(N, ARM::VORNd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 DPR:v2i32:$src1, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2))
+ // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N10.getNode())) {
+ SDNode *Result = Emit_181(N, ARM::VORNd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (or:v2i32 (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src1)
+ // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N01.getNode())) {
+ SDNode *Result = Emit_84(N, ARM::VORNd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2), DPR:v2i32:$src1)
+ // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N00.getNode())) {
+ SDNode *Result = Emit_182(N, ARM::VORNd, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VORRd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VORRd, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ {
+ SDValue N01 = N0.getOperand(1);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N01 == N110) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N111.getNode())) {
+ SDNode *Result = Emit_275(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111) {
+ SDNode *Result = Emit_275(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N01 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N101.getNode())) {
+ SDNode *Result = Emit_276(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ if (N01 == N101) {
+ SDNode *Result = Emit_276(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N00 == N110) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N111.getNode())) {
+ SDNode *Result = Emit_277(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ if (N00 == N111) {
+ SDNode *Result = Emit_277(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N00 == N100) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N101.getNode())) {
+ SDNode *Result = Emit_278(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ if (N00 == N101) {
+ SDNode *Result = Emit_278(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N01.getOpcode() == ISD::XOR) {
+ SDValue N010 = N01.getOperand(0);
+ {
+ SDValue N011 = N01.getOperand(1);
+ if (N011.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N011.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N010 == N11) {
+ SDNode *Result = Emit_279(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N010 == N10) {
+ SDNode *Result = Emit_280(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N010.getNode())) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11) {
+ SDNode *Result = Emit_281(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N011 == N10) {
+ SDNode *Result = Emit_282(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N00.getOpcode() == ISD::XOR) {
+ SDValue N000 = N00.getOperand(0);
+ {
+ SDValue N001 = N00.getOperand(1);
+ if (N001.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N001.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N000 == N11) {
+ SDNode *Result = Emit_283(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N000 == N10) {
+ SDNode *Result = Emit_284(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N001 == N11) {
+ SDNode *Result = Emit_285(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
+ // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (N001 == N10) {
+ SDNode *Result = Emit_286(N, ARM::VBSLq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (or:v4i32 QPR:v4i32:$src1, (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
+ // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N11.getNode())) {
+ SDNode *Result = Emit_51(N, ARM::VORNq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 QPR:v4i32:$src1, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2))
+ // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N10.getNode())) {
+ SDNode *Result = Emit_181(N, ARM::VORNq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (or:v4i32 (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src1)
+ // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N01.getNode())) {
+ SDNode *Result = Emit_84(N, ARM::VORNq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2), QPR:v4i32:$src1)
+ // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N00.getNode())) {
+ SDNode *Result = Emit_182(N, ARM::VORNq, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VORRq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VORRq, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_287(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2) {
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN_0, CPTmpN_1, CPTmpN_2, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
+
+ // Pattern: so_reg:i32:$src
+ // Emits: (MOVs:i32 so_reg:i32:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (rotr:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
+ // Emits: (t2RORri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm1_31(N1.getNode()) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_55(N, ARM::t2RORri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (rotr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tROR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_66(N, ARM::tROR, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (rotr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2RORrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_56(N, ARM::t2RORrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_288(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops1[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+}
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_289(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops2[] = { Tmp1, N0, Tmp3, Tmp4, Tmp5 };
+ SDValue Tmp6(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Ops2, 5), 0);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0x5ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp0, Tmp6, Tmp7);
+}
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_290(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0, Tmp2);
+}
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x5ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0, Tmp2);
+}
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_291(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_i32(const SDValue &N) {
+
+ // Pattern: so_reg:i32:$src
+ // Emits: (MOVs:i32 so_reg:i32:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (shl:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
+ // Emits: (t2LSLri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm1_31(N1.getNode()) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_55(N, ARM::t2LSLri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Emits: (tLSLri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_65(N, ARM::tLSLri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (shl:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tLSLrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_66(N, ARM::tLSLrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (shl:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2LSLrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_56(N, ARM::t2LSLrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_292(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_293(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_294(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0000, Tmp6, Tmp7);
+}
+DISABLE_INLINE SDNode *Emit_295(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, Tmp6, Tmp7);
+}
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
+
+ // Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32), (shl:i32 GPR:i32:$src, 8:i32)), i16:Other)
+ // Emits: (REVSH:i32 GPR:i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0 &&
+ CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SHL) {
+ SDValue N010 = N01.getOperand(0);
+ if (N0000 == N010) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp3) {
+ int64_t CN4 = Tmp3->getSExtValue();
+ if (CN4 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_294(N, ARM::REVSH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 tGPR:i32:$src, 65280:i32), 8:i32), (shl:i32 tGPR:i32:$src, 8:i32)), i16:Other)
+ // Emits: (tREVSH:i32 tGPR:i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0 &&
+ CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SHL) {
+ SDValue N010 = N01.getOperand(0);
+ if (N0000 == N010) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp3) {
+ int64_t CN4 = Tmp3->getSExtValue();
+ if (CN4 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_294(N, ARM::tREVSH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32), (shl:i32 GPR:i32:$src, 8:i32)), i16:Other)
+ // Emits: (t2REVSH:i32 GPR:i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0 &&
+ CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SHL) {
+ SDValue N010 = N01.getOperand(0);
+ if (N0000 == N010) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp3) {
+ int64_t CN4 = Tmp3->getSExtValue();
+ if (CN4 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_294(N, ARM::t2REVSH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 (or:i32 (shl:i32 GPR:i32:$src, 8:i32), (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32)), i16:Other)
+ // Emits: (REVSH:i32 GPR:i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRL) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp2 &&
+ CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
+ N000 == N0100) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp3) {
+ int64_t CN4 = Tmp3->getSExtValue();
+ if (CN4 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_295(N, ARM::REVSH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 (or:i32 (shl:i32 tGPR:i32:$src, 8:i32), (srl:i32 (and:i32 tGPR:i32:$src, 65280:i32), 8:i32)), i16:Other)
+ // Emits: (tREVSH:i32 tGPR:i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRL) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp2 &&
+ CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
+ N000 == N0100) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp3) {
+ int64_t CN4 = Tmp3->getSExtValue();
+ if (CN4 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_295(N, ARM::tREVSH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 (or:i32 (shl:i32 GPR:i32:$src, 8:i32), (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32)), i16:Other)
+ // Emits: (t2REVSH:i32 GPR:i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRL) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp2 &&
+ CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
+ N000 == N0100) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp3) {
+ int64_t CN4 = Tmp3->getSExtValue();
+ if (CN4 == INT64_C(8)) {
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N001.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_295(N, ARM::t2REVSH, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other)
+ // Emits: (SXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_293(N, ARM::SXTBr_rot, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other)
+ // Emits: (SXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_293(N, ARM::SXTHr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_rot_imm(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other)
+ // Emits: (t2SXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_293(N, ARM::t2SXTBr_rot, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other)
+ // Emits: (t2SXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_293(N, ARM::t2SXTHr_rot, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i32 GPR:i32:$src, i8:Other)
+ // Emits: (SXTBr:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_292(N, ARM::SXTBr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i32 GPR:i32:$src, i16:Other)
+ // Emits: (SXTHr:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_292(N, ARM::SXTHr, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i32 tGPR:i32:$src, i8:Other)
+ // Emits: (tSXTB:i32 tGPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_292(N, ARM::tSXTB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i32 tGPR:i32:$src, i16:Other)
+ // Emits: (tSXTH:i32 tGPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_292(N, ARM::tSXTH, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i32 GPR:i32:$src, i8:Other)
+ // Emits: (t2SXTBr:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_292(N, ARM::t2SXTBr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i32 GPR:i32:$src, i16:Other)
+ // Emits: (t2SXTHr:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_292(N, ARM::t2SXTHr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SINT_TO_FP_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTs2fd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SINT_TO_FP_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTs2fq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_296(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N010, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N010, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N0100, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N00, N01, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_300(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N000, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N000, Tmp6, Tmp7 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N0000, Tmp8, Tmp9 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N01, N00, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_SRA_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32)
+ // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 27 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N0101.getValueType() == MVT::i32 &&
+ N011.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_298(N, ARM::SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32)
+ // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 27 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(16) &&
+ N0001.getValueType() == MVT::i32 &&
+ N001.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_302(N, ARM::SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32)
+ // Emits: (SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N011.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_297(N, ARM::SMULWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32)
+ // Emits: (t2SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N011.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_297(N, ARM::t2SMULWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32)
+ // Emits: (SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N001.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_301(N, ARM::SMULWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32)
+ // Emits: (t2SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(16) &&
+ N001.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_301(N, ARM::t2SMULWT, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32)
+ // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_296(N, ARM::SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32)
+ // Emits: (t2SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_296(N, ARM::t2SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32)
+ // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_300(N, ARM::SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32)
+ // Emits: (t2SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_300(N, ARM::t2SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: so_reg:i32:$src
+ // Emits: (MOVs:i32 so_reg:i32:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32)
+ // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (Predicate_sext_16_node(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_299(N, ARM::SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, GPR:i32:$a), 16:i32)
+ // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (Predicate_sext_16_node(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_303(N, ARM::SMULWB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
+ // Emits: (t2ASRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm1_31(N1.getNode()) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_55(N, ARM::t2ASRri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Emits: (tASRri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_65(N, ARM::tASRri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sra:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tASRrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_66(N, ARM::tASRrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sra:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2ASRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_56(N, ARM::t2ASRrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_i32(const SDValue &N) {
+
+ // Pattern: so_reg:i32:$src
+ // Emits: (MOVs:i32 so_reg:i32:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (srl:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
+ // Emits: (t2LSRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_imm1_31(N1.getNode()) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_55(N, ARM::t2LSRri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Emits: (tLSRri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_65(N, ARM::tLSRri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (srl:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tLSRrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_66(N, ARM::tLSRrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (srl:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2LSRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_56(N, ARM::t2LSRrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_304(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, N2, CPTmpN3_0, CPTmpN3_1, Tmp3, Tmp4, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_305(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, N2, CPTmpN3_0, Tmp3, Tmp4, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_STORE_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_istore(N.getNode())) {
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (STR_PRE:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_pre_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_304(N, ARM::STR_PRE, MVT::i32, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_post_store>>
+ // Emits: (STR_POST:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_post_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_304(N, ARM::STR_POST, MVT::i32, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_itruncstore(N.getNode())) {
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
+ // Emits: (STRH_PRE:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_pre_truncst(N.getNode()) &&
+ Predicate_pre_truncsti16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrMode3Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_304(N, ARM::STRH_PRE, MVT::i32, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti16>>
+ // Emits: (STRH_POST:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_post_truncst(N.getNode()) &&
+ Predicate_post_truncsti16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrMode3Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_304(N, ARM::STRH_POST, MVT::i32, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
+ // Emits: (STRB_PRE:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_pre_truncst(N.getNode()) &&
+ Predicate_pre_truncsti8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_304(N, ARM::STRB_PRE, MVT::i32, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti8>>
+ // Emits: (STRB_POST:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_post_truncst(N.getNode()) &&
+ Predicate_post_truncsti8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_304(N, ARM::STRB_POST, MVT::i32, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_istore(N.getNode())) {
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (t2STR_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_305(N, ARM::t2STR_PRE, MVT::i32, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_post_store>>
+ // Emits: (t2STR_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_post_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_305(N, ARM::t2STR_POST, MVT::i32, CPTmpN3_0);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_itruncstore(N.getNode())) {
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
+ // Emits: (t2STRH_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_truncst(N.getNode()) &&
+ Predicate_pre_truncsti16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_305(N, ARM::t2STRH_PRE, MVT::i32, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti16>>
+ // Emits: (t2STRH_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_post_truncst(N.getNode()) &&
+ Predicate_post_truncsti16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_305(N, ARM::t2STRH_POST, MVT::i32, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
+ // Emits: (t2STRB_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_truncst(N.getNode()) &&
+ Predicate_pre_truncsti8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_305(N, ARM::t2STRB_PRE, MVT::i32, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti8>>
+ // Emits: (t2STRB_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_post_truncst(N.getNode()) &&
+ Predicate_post_truncsti8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32 &&
+ N3.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_305(N, ARM::t2STRB_POST, MVT::i32, CPTmpN3_0);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_306(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Tmp2, Tmp3, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_307(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, Tmp2, Tmp3, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_STORE(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (PICSTR:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::PICSTR, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (PICSTRH:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::PICSTRH, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (PICSTRB:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
+ // Pattern complexity = 23 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::PICSTRB, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, addrmode2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STR:isVoid GPR:i32:$src, addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectAddrMode2(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::STR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPR:i32:$src, addrmode3:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (STRH:isVoid GPR:i32:$src, addrmode3:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectAddrMode3(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::STRH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, addrmode2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (STRB:isVoid GPR:i32:$src, addrmode2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectAddrMode2(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::STRB, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+
+ // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s4:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (tSTR:isVoid tGPR:i32:$src, t_addrmode_s4:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectThumbAddrModeS4(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::tSTR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (tSTRB:isVoid tGPR:i32:$src, t_addrmode_s1:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectThumbAddrModeS1(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::tSTRB, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (tSTRH:isVoid tGPR:i32:$src, t_addrmode_s2:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectThumbAddrModeS2(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::tSTRH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (t2STRs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectT2AddrModeSoReg(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::t2STRs, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (t2STRBs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectT2AddrModeSoReg(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::t2STRBs, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (t2STRHs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ if (SelectT2AddrModeSoReg(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, ARM::t2STRHs, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_sp:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (tSTRspi:isVoid tGPR:i32:$src, t_addrmode_sp:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectThumbAddrModeSP(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::tSTRspi, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (t2STRi12:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::t2STRi12, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (t2STRi8:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::t2STRi8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (t2STRBi12:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::t2STRBi12, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (t2STRBi8:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::t2STRBi8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (t2STRHi12:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm12(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::t2STRHi12, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (t2STRHi8:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectT2AddrModeImm8(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::t2STRHi8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasVFP2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrMode5(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+
+ // Pattern: (st:isVoid DPR:f64:$src, addrmode5:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (VSTRD:isVoid DPR:f64:$src, addrmode5:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::VSTRD, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid SPR:f32:$src, addrmode5:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (VSTRS:isVoid SPR:f32:$src, addrmode5:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::VSTRS, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid QPR:v2f64:$src, addrmode4:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (VSTRQ:isVoid QPR:v2f64:$src, addrmode4:i32:$addr)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrMode4(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::v2f64 &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, ARM::VSTRQ, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_308(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_309(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp2, N1, Tmp4, Tmp5 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_311(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+}
+SDNode *Select_ISD_SUB_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (SUBrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_57(N, ARM::SUBrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (RSBrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_88(N, ARM::RSBrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2SUBrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_68(N, ARM::t2SUBrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 t2_so_reg:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2RSBrs:i32 GPR:i32:$rhs, t2_so_reg:i32:$lhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_311(N, ARM::t2RSBrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 0:i32, tGPR:i32:$src)
+ // Emits: (tRSB:i32 tGPR:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_309(N, ARM::tRSB, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (SUBri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::SUBri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
+ // Emits: (RSBri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N0.getNode())) {
+ SDNode *Result = Emit_308(N, ARM::RSBri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sub:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2SUBri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2SUBri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sub:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_4095>>:$rhs)
+ // Emits: (t2SUBri12:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm0_4095(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2SUBri12, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$lhs, GPR:i32:$rhs)
+ // Emits: (t2RSBri:i32 GPR:i32:$rhs, (imm:i32):$lhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N0.getNode())) {
+ SDNode *Result = Emit_310(N, ARM::t2RSBri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (MLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_77(N, ARM::MLS, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (SMMLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MULHS) {
+ SDNode *Result = Emit_77(N, ARM::SMMLS, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sub:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (t2MLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_77(N, ARM::t2MLS, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sub:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
+ // Emits: (t2SMMLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::MULHS) {
+ SDNode *Result = Emit_77(N, ARM::t2SMMLS, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (SUBrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_56(N, ARM::SUBrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sub:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tSUBrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_66(N, ARM::tSUBrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sub:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2SUBrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_56(N, ARM::t2SUBrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_312(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp1, Tmp2);
+}
+SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
+
+ // Pattern: (sub:v8i8 (build_vector:v8i8)<<P:Predicate_immAllZerosV>>, DPR:v8i8:$src)
+ // Emits: (VNEGs8d:v8i8 DPR:v8i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs8d, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v8i8 (bitconvert:v8i8)<<P:Predicate_immAllZerosV_bc>>, DPR:v8i8:$src)
+ // Emits: (VNEGs8d:v8i8 DPR:f64:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs8d, MVT::v8i8);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (sub:v8i8 DPR:v8i8:$src1, (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3))
+ // Emits: (VMLSv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSv8i8, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Emits: (VSUBv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBv8i8, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
+
+ // Pattern: (sub:v16i8 (build_vector:v16i8)<<P:Predicate_immAllZerosV>>, QPR:v16i8:$src)
+ // Emits: (VNEGs8q:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs8q, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v16i8 (bitconvert:v16i8)<<P:Predicate_immAllZerosV_bc>>, QPR:v16i8:$src)
+ // Emits: (VNEGs8q:v16i8 QPR:v16i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs8q, MVT::v16i8);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (sub:v16i8 QPR:v16i8:$src1, (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3))
+ // Emits: (VMLSv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSv16i8, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Emits: (VSUBv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBv16i8, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_129(N, ARM::VMLSslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2))
+ // Emits: (VMLSslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_130(N, ARM::VMLSslv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i16 (build_vector:v4i16)<<P:Predicate_immAllZerosV>>, DPR:v4i16:$src)
+ // Emits: (VNEGs16d:v4i16 DPR:v4i16:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs16d, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v4i16 (bitconvert:v4i16)<<P:Predicate_immAllZerosV_bc>>, DPR:v4i16:$src)
+ // Emits: (VNEGs16d:v4i16 DPR:f64:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs16d, MVT::v4i16);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3))
+ // Emits: (VMLSv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSv4i16, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Emits: (VSUBv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBv4i16, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_129(N, ARM::VMLSslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
+ // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_130(N, ARM::VMLSslv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
+ // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v8i16 (build_vector:v8i16)<<P:Predicate_immAllZerosV>>, QPR:v8i16:$src)
+ // Emits: (VNEGs16q:v8i16 QPR:v8i16:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs16q, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v8i16 (bitconvert:v8i16)<<P:Predicate_immAllZerosV_bc>>, QPR:v8i16:$src)
+ // Emits: (VNEGs16q:v8i16 QPR:v16i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs16q, MVT::v8i16);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3))
+ // Emits: (VMLSv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSv8i16, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Emits: (VSUBv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBv8i16, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_129(N, ARM::VMLSslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2))
+ // Emits: (VMLSslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_130(N, ARM::VMLSslv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, DPR:v2i32:$src)
+ // Emits: (VNEGs32d:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs32d, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllZerosV_bc>>, DPR:v2i32:$src)
+ // Emits: (VNEGs32d:v2i32 DPR:f64:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs32d, MVT::v2i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3))
+ // Emits: (VMLSv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSv2i32, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VSUBv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBv2i32, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_129(N, ARM::VMLSslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
+ // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_130(N, ARM::VMLSslv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)))
+ // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
+ // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N10.getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i32 (build_vector:v4i32)<<P:Predicate_immAllZerosV>>, QPR:v4i32:$src)
+ // Emits: (VNEGs32q:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs32q, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllZerosV_bc>>, QPR:v4i32:$src)
+ // Emits: (VNEGs32q:v4i32 QPR:v16i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VNEGs32q, MVT::v4i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasNEON())) {
+
+ // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3))
+ // Emits: (VMLSv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::MUL) {
+ SDNode *Result = Emit_125(N, ARM::VMLSv4i32, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VSUBv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_44(N, ARM::VSUBv4i32, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v1i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VSUBv1i64, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v2i64(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VSUBv2i64, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_313(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_314(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1, Tmp2);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_315(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (subc:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (SUBSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_143(N, ARM::SUBSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (RSBSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_148(N, ARM::RSBSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (subc:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2SUBSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_144(N, ARM::t2SUBSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 t2_so_reg:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2RSBSrs:i32 GPR:i32:$rhs, t2_so_reg:i32:$lhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_315(N, ARM::t2RSBSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (subc:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (SUBSri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_141(N, ARM::SUBSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
+ // Emits: (RSBSri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N0.getNode())) {
+ SDNode *Result = Emit_313(N, ARM::RSBSri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (subc:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2SUBSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_141(N, ARM::t2SUBSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$lhs, GPR:i32:$rhs)
+ // Emits: (t2RSBSri:i32 GPR:i32:$rhs, (imm:i32):$lhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N0.getNode())) {
+ SDNode *Result = Emit_314(N, ARM::t2RSBSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (SUBSrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDNode *Result = Emit_142(N, ARM::SUBSrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (subc:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2SUBSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_142(N, ARM::t2SUBSrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (subc:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tSUBrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_146(N, ARM::tSUBrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_316(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_317(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
+
+ // Pattern: (sube:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (SBCrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_152(N, ARM::SBCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (SBCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_155(N, ARM::SBCSSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+
+ // Pattern: (sube:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (RSCrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_159(N, ARM::RSCrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (RSCSrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ SDNode *Result = Emit_160(N, ARM::RSCSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2SBCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_157(N, ARM::t2SBCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2SBCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_158(N, ARM::t2SBCSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (SBCri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_150(N, ARM::SBCri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (SBCSSri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_153(N, ARM::SBCSSri, MVT::i32);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_so_imm(N0.getNode())) {
+
+ // Pattern: (sube:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
+ // Emits: (RSCri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_316(N, ARM::RSCri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
+ // Emits: (RSCSri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ SDNode *Result = Emit_317(N, ARM::RSCSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2SBCri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_150(N, ARM::t2SBCri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2SBCSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_153(N, ARM::t2SBCSri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (SBCrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_151(N, ARM::SBCrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (SBCSSrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_154(N, ARM::SBCSSrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tSBC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_156(N, ARM::tSBC, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2SBCrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_151(N, ARM::t2SBCrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2SBCSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ SDNode *Result = Emit_154(N, ARM::t2SBCSrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_UINT_TO_FP_v2f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTu2fd, MVT::v2f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_UINT_TO_FP_v4f32(const SDValue &N) {
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_31(N, ARM::VCVTu2fq, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_318(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_319(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_320(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_321(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_322(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { CPTmpN0_0, CPTmpN0_1, Tmp1, Tmp2 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_323(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_XOR_i32(const SDValue &N) {
+
+ // Pattern: (xor:i32 so_reg:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (MVNs:i32 so_reg:i32:$src)
+ // Pattern complexity = 19 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_319(N, ARM::MVNs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (xor:i32 t2_so_reg:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (t2MVNs:i32 t2_so_reg:i32:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_322(N, ARM::t2MVNs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (EORrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
+ SDNode *Result = Emit_57(N, ARM::EORrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 so_reg:i32:$b, GPR:i32:$a)
+ // Emits: (EORrs:i32 GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ SDValue CPTmpN0_2;
+ if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
+ SDNode *Result = Emit_88(N, ARM::EORrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2EORrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_68(N, ARM::t2EORrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (t2MVNi:i32 (imm:i32):$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_321(N, ARM::t2MVNi, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
+ // Emits: (t2EORrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
+ {
+ SDValue CPTmpN0_0;
+ SDValue CPTmpN0_1;
+ if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
+ SDNode *Result = Emit_103(N, ARM::t2EORrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$src)
+ // Emits: (t2MVNi:i32 (imm:i32):$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_323(N, ARM::t2MVNi, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (t2MVNr:i32 GPR:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_292(N, ARM::t2MVNr, MVT::i32);
+ return Result;
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
+ // Emits: (EORri:i32 GPR:i32:$a, (imm:i32):$b)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::EORri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (MVNr:i32 GPR:i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_318(N, ARM::MVNr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (xor:i32 tGPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (tMVN:i32 tGPR:i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_320(N, ARM::tMVN, MVT::i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2EORri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_t2_so_imm(N1.getNode())) {
+ SDNode *Result = Emit_55(N, ARM::t2EORri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
+ // Emits: (t2EORri:i32 (t2EORri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ if (Predicate_t2_so_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_71(N, ARM::t2EORri, ARM::t2EORri, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->isThumb())) {
+
+ // Pattern: (xor:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
+ // Emits: (EORri:i32 (EORri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
+ // Pattern complexity = 7 cost = 2 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_so_imm2part(N1.getNode())) {
+ SDNode *Result = Emit_74(N, ARM::EORri, ARM::EORri, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 GPR:i32:$a, GPR:i32:$b)
+ // Emits: (EORrr:i32 GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_56(N, ARM::EORrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Emits: (tEOR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDNode *Result = Emit_66(N, ARM::tEOR, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Emits: (t2EORrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_56(N, ARM::t2EORrr, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_XOR_v2i32(const SDValue &N) {
+
+ // Pattern: (xor:v2i32 DPR:v2i32:$src, (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)
+ // Emits: (VMVNd:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N1.getNode())) {
+ SDNode *Result = Emit_292(N, ARM::VMVNd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v2i32 DPR:v2i32:$src, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)
+ // Emits: (VMVNd:v2i32 DPR:f64:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N1.getNode())) {
+ SDNode *Result = Emit_292(N, ARM::VMVNd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v2i32 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>, DPR:v2i32:$src)
+ // Emits: (VMVNd:v2i32 DPR:v2i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VMVNd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src)
+ // Emits: (VMVNd:v2i32 DPR:f64:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VMVNd, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Emits: (VEORd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VEORd, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
+
+ // Pattern: (xor:v4i32 QPR:v4i32:$src, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
+ // Emits: (VMVNq:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N1.getNode())) {
+ SDNode *Result = Emit_292(N, ARM::VMVNq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 QPR:v4i32:$src, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
+ // Emits: (VMVNq:v4i32 QPR:v16i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N1.getNode())) {
+ SDNode *Result = Emit_292(N, ARM::VMVNq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, QPR:v4i32:$src)
+ // Emits: (VMVNq:v4i32 QPR:v4i32:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VMVNq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src)
+ // Emits: (VMVNq:v4i32 QPR:v16i8:$src)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N0.getNode())) {
+ SDNode *Result = Emit_312(N, ARM::VMVNq, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Emits: (VEORq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->hasNEON())) {
+ SDNode *Result = Emit_44(N, ARM::VEORq, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+// The main instruction selector code.
+SDNode *SelectCode(SDValue N) {
+ MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
+ switch (N.getOpcode()) {
+ default:
+ assert(!N.isMachineOpcode() && "Node already selected!");
+ break;
+ case ISD::EntryToken: // These nodes remain the same.
+ case ISD::BasicBlock:
+ case ISD::Register:
+ case ISD::HANDLENODE:
+ case ISD::TargetConstant:
+ case ISD::TargetConstantFP:
+ case ISD::TargetConstantPool:
+ case ISD::TargetFrameIndex:
+ case ISD::TargetExternalSymbol:
+ case ISD::TargetBlockAddress:
+ case ISD::TargetJumpTable:
+ case ISD::TargetGlobalTLSAddress:
+ case ISD::TargetGlobalAddress:
+ case ISD::TokenFactor:
+ case ISD::CopyFromReg:
+ case ISD::CopyToReg: {
+ return NULL;
+ }
+ case ISD::AssertSext:
+ case ISD::AssertZext: {
+ ReplaceUses(N, N.getOperand(0));
+ return NULL;
+ }
+ case ISD::INLINEASM: return Select_INLINEASM(N);
+ case ISD::EH_LABEL: return Select_EH_LABEL(N);
+ case ISD::UNDEF: return Select_UNDEF(N);
+ case ARMISD::BR2_JT: {
+ return Select_ARMISD_BR2_JT(N);
+ break;
+ }
+ case ARMISD::BR_JT: {
+ return Select_ARMISD_BR_JT(N);
+ break;
+ }
+ case ARMISD::CALL: {
+ return Select_ARMISD_CALL(N);
+ break;
+ }
+ case ARMISD::CALL_NOLINK: {
+ return Select_ARMISD_CALL_NOLINK(N);
+ break;
+ }
+ case ARMISD::CALL_PRED: {
+ return Select_ARMISD_CALL_PRED(N);
+ break;
+ }
+ case ARMISD::CMP: {
+ return Select_ARMISD_CMP(N);
+ break;
+ }
+ case ARMISD::CMPFP: {
+ return Select_ARMISD_CMPFP(N);
+ break;
+ }
+ case ARMISD::CMPFPw0: {
+ return Select_ARMISD_CMPFPw0(N);
+ break;
+ }
+ case ARMISD::CMPZ: {
+ return Select_ARMISD_CMPZ(N);
+ break;
+ }
+ case ARMISD::EH_SJLJ_SETJMP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_EH_SJLJ_SETJMP_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::FMSTAT: {
+ return Select_ARMISD_FMSTAT(N);
+ break;
+ }
+ case ARMISD::FTOSI: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ARMISD_FTOSI_f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::FTOUI: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ARMISD_FTOUI_f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::MEMBARRIER: {
+ return Select_ARMISD_MEMBARRIER(N);
+ break;
+ }
+ case ARMISD::PIC_ADD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_PIC_ADD_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::RET_FLAG: {
+ return Select_ARMISD_RET_FLAG(N);
+ break;
+ }
+ case ARMISD::RRX: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_RRX_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::SITOF: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ARMISD_SITOF_f32(N);
+ case MVT::f64:
+ return Select_ARMISD_SITOF_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::SRA_FLAG: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_SRA_FLAG_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::SRL_FLAG: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_SRL_FLAG_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::SYNCBARRIER: {
+ return Select_ARMISD_SYNCBARRIER(N);
+ break;
+ }
+ case ARMISD::THREAD_POINTER: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_THREAD_POINTER_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::UITOF: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ARMISD_UITOF_f32(N);
+ case MVT::f64:
+ return Select_ARMISD_UITOF_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VCEQ: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VCEQ_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VCEQ_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VCEQ_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VCEQ_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VCEQ_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VCEQ_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VCGE: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VCGE_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VCGE_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VCGE_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VCGE_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VCGE_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VCGE_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VCGEU: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VCGEU_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VCGEU_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VCGEU_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VCGEU_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VCGEU_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VCGEU_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VCGT: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VCGT_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VCGT_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VCGT_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VCGT_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VCGT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VCGT_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VCGTU: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VCGTU_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VCGTU_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VCGTU_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VCGTU_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VCGTU_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VCGTU_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VDUP: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VDUP_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VDUP_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VDUP_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VDUP_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VDUP_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VDUP_v4i32(N);
+ case MVT::v2f32:
+ return Select_ARMISD_VDUP_v2f32(N);
+ case MVT::v4f32:
+ return Select_ARMISD_VDUP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VDUPLANE: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VDUPLANE_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VDUPLANE_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VDUPLANE_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VDUPLANE_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VDUPLANE_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VDUPLANE_v4i32(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VDUPLANE_v2i64(N);
+ case MVT::v2f32:
+ return Select_ARMISD_VDUPLANE_v2f32(N);
+ case MVT::v4f32:
+ return Select_ARMISD_VDUPLANE_v4f32(N);
+ case MVT::v2f64:
+ return Select_ARMISD_VDUPLANE_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VEXT: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VEXT_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VEXT_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VEXT_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VEXT_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VEXT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VEXT_v4i32(N);
+ case MVT::v2f32:
+ return Select_ARMISD_VEXT_v2f32(N);
+ case MVT::v4f32:
+ return Select_ARMISD_VEXT_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VGETLANEs: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_VGETLANEs_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VGETLANEu: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_VGETLANEu_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VMOVDRR: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_ARMISD_VMOVDRR_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQRSHRNs: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQRSHRNs_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQRSHRNs_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQRSHRNs_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQRSHRNsu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQRSHRNsu_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQRSHRNsu_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQRSHRNsu_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQRSHRNu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQRSHRNu_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQRSHRNu_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQRSHRNu_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQSHLs: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQSHLs_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VQSHLs_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQSHLs_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VQSHLs_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQSHLs_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VQSHLs_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VQSHLs_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VQSHLs_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQSHLsu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQSHLsu_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VQSHLsu_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQSHLsu_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VQSHLsu_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQSHLsu_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VQSHLsu_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VQSHLsu_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VQSHLsu_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQSHLu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQSHLu_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VQSHLu_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQSHLu_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VQSHLu_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQSHLu_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VQSHLu_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VQSHLu_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VQSHLu_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQSHRNs: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQSHRNs_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQSHRNs_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQSHRNs_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQSHRNsu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQSHRNsu_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQSHRNsu_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQSHRNsu_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VQSHRNu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VQSHRNu_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VQSHRNu_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VQSHRNu_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VREV16: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VREV16_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VREV16_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VREV32: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VREV32_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VREV32_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VREV32_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VREV32_v8i16(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VREV64: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VREV64_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VREV64_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VREV64_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VREV64_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VREV64_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VREV64_v4i32(N);
+ case MVT::v2f32:
+ return Select_ARMISD_VREV64_v2f32(N);
+ case MVT::v4f32:
+ return Select_ARMISD_VREV64_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VRSHRN: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VRSHRN_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VRSHRN_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VRSHRN_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VRSHRs: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VRSHRs_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VRSHRs_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VRSHRs_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VRSHRs_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VRSHRs_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VRSHRs_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VRSHRs_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VRSHRs_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VRSHRu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VRSHRu_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VRSHRu_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VRSHRu_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VRSHRu_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VRSHRu_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VRSHRu_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VRSHRu_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VRSHRu_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHL: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VSHL_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VSHL_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VSHL_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VSHL_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VSHL_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSHL_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VSHL_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSHL_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHLLi: {
+ switch (NVT) {
+ case MVT::v8i16:
+ return Select_ARMISD_VSHLLi_v8i16(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSHLLi_v4i32(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSHLLi_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHLLs: {
+ switch (NVT) {
+ case MVT::v8i16:
+ return Select_ARMISD_VSHLLs_v8i16(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSHLLs_v4i32(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSHLLs_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHLLu: {
+ switch (NVT) {
+ case MVT::v8i16:
+ return Select_ARMISD_VSHLLu_v8i16(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSHLLu_v4i32(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSHLLu_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHRN: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VSHRN_v8i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VSHRN_v4i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VSHRN_v2i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHRs: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VSHRs_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VSHRs_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VSHRs_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VSHRs_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VSHRs_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSHRs_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VSHRs_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSHRs_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSHRu: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VSHRu_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VSHRu_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VSHRu_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VSHRu_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VSHRu_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSHRu_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VSHRu_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSHRu_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSLI: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VSLI_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VSLI_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VSLI_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VSLI_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VSLI_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSLI_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VSLI_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSLI_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VSRI: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VSRI_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VSRI_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VSRI_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VSRI_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VSRI_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VSRI_v4i32(N);
+ case MVT::v1i64:
+ return Select_ARMISD_VSRI_v1i64(N);
+ case MVT::v2i64:
+ return Select_ARMISD_VSRI_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::VTST: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ARMISD_VTST_v8i8(N);
+ case MVT::v16i8:
+ return Select_ARMISD_VTST_v16i8(N);
+ case MVT::v4i16:
+ return Select_ARMISD_VTST_v4i16(N);
+ case MVT::v8i16:
+ return Select_ARMISD_VTST_v8i16(N);
+ case MVT::v2i32:
+ return Select_ARMISD_VTST_v2i32(N);
+ case MVT::v4i32:
+ return Select_ARMISD_VTST_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::Wrapper: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_Wrapper_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::WrapperJT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_WrapperJT_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ARMISD::tCALL: {
+ return Select_ARMISD_tCALL(N);
+ break;
+ }
+ case ISD::ADD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADD_i32(N);
+ case MVT::v8i8:
+ return Select_ISD_ADD_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_ADD_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_ADD_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_ADD_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_ADD_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_ADD_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_ADD_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_ADD_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ADDC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADDC_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ADDE: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADDE_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::AND: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_AND_i32(N);
+ case MVT::v2i32:
+ return Select_ISD_AND_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_AND_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_CMP_SWAP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_CMP_SWAP_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_ADD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_ADD_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_AND: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_AND_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_NAND: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_NAND_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_OR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_OR_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_SUB: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_SUB_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_XOR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_XOR_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_SWAP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_SWAP_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BIT_CONVERT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_BIT_CONVERT_i32(N);
+ case MVT::f32:
+ return Select_ISD_BIT_CONVERT_f32(N);
+ case MVT::f64:
+ return Select_ISD_BIT_CONVERT_f64(N);
+ case MVT::v8i8:
+ return Select_ISD_BIT_CONVERT_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_BIT_CONVERT_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_BIT_CONVERT_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_BIT_CONVERT_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_BIT_CONVERT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_BIT_CONVERT_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_BIT_CONVERT_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_BIT_CONVERT_v2i64(N);
+ case MVT::v2f32:
+ return Select_ISD_BIT_CONVERT_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_BIT_CONVERT_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_BIT_CONVERT_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BR: {
+ return Select_ISD_BR(N);
+ break;
+ }
+ case ISD::BRIND: {
+ return Select_ISD_BRIND(N);
+ break;
+ }
+ case ISD::BSWAP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_BSWAP_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BUILD_VECTOR: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_BUILD_VECTOR_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_BUILD_VECTOR_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_BUILD_VECTOR_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_BUILD_VECTOR_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_BUILD_VECTOR_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_BUILD_VECTOR_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_BUILD_VECTOR_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_BUILD_VECTOR_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::CALLSEQ_END: {
+ return Select_ISD_CALLSEQ_END(N);
+ break;
+ }
+ case ISD::CALLSEQ_START: {
+ return Select_ISD_CALLSEQ_START(N);
+ break;
+ }
+ case ISD::CTLZ: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_CTLZ_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::Constant: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_Constant_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ConstantFP: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_ConstantFP_f32(N);
+ case MVT::f64:
+ return Select_ISD_ConstantFP_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::EXTRACT_VECTOR_ELT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_EXTRACT_VECTOR_ELT_i32(N);
+ case MVT::f32:
+ return Select_ISD_EXTRACT_VECTOR_ELT_f32(N);
+ case MVT::f64:
+ return Select_ISD_EXTRACT_VECTOR_ELT_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FABS: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FABS_f32(N);
+ case MVT::f64:
+ return Select_ISD_FABS_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FADD: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FADD_f32(N);
+ case MVT::f64:
+ return Select_ISD_FADD_f64(N);
+ case MVT::v2f32:
+ return Select_ISD_FADD_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_FADD_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FDIV: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FDIV_f32(N);
+ case MVT::f64:
+ return Select_ISD_FDIV_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FMUL: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FMUL_f32(N);
+ case MVT::f64:
+ return Select_ISD_FMUL_f64(N);
+ case MVT::v2f32:
+ return Select_ISD_FMUL_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_FMUL_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FNEG: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FNEG_f32(N);
+ case MVT::f64:
+ return Select_ISD_FNEG_f64(N);
+ case MVT::v2f32:
+ return Select_ISD_FNEG_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_FNEG_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_EXTEND: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_ISD_FP_EXTEND_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_ROUND: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FP_ROUND_f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_TO_SINT: {
+ switch (NVT) {
+ case MVT::v2i32:
+ return Select_ISD_FP_TO_SINT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_FP_TO_SINT_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_TO_UINT: {
+ switch (NVT) {
+ case MVT::v2i32:
+ return Select_ISD_FP_TO_UINT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_FP_TO_UINT_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSQRT: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSQRT_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSQRT_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSUB: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSUB_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSUB_f64(N);
+ case MVT::v2f32:
+ return Select_ISD_FSUB_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_FSUB_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INSERT_VECTOR_ELT: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_INSERT_VECTOR_ELT_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_INSERT_VECTOR_ELT_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_INSERT_VECTOR_ELT_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_INSERT_VECTOR_ELT_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_INSERT_VECTOR_ELT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_INSERT_VECTOR_ELT_v4i32(N);
+ case MVT::v2f32:
+ return Select_ISD_INSERT_VECTOR_ELT_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_INSERT_VECTOR_ELT_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_INSERT_VECTOR_ELT_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INTRINSIC_VOID: {
+ return Select_ISD_INTRINSIC_VOID(N);
+ break;
+ }
+ case ISD::INTRINSIC_WO_CHAIN: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v2i64(N);
+ case MVT::v2f32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INTRINSIC_W_CHAIN: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_INTRINSIC_W_CHAIN_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_INTRINSIC_W_CHAIN_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_INTRINSIC_W_CHAIN_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_INTRINSIC_W_CHAIN_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_INTRINSIC_W_CHAIN_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_INTRINSIC_W_CHAIN_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_INTRINSIC_W_CHAIN_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_INTRINSIC_W_CHAIN_v2i64(N);
+ case MVT::v2f32:
+ return Select_ISD_INTRINSIC_W_CHAIN_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_INTRINSIC_W_CHAIN_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::LOAD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_LOAD_i32(N);
+ case MVT::f32:
+ return Select_ISD_LOAD_f32(N);
+ case MVT::f64:
+ return Select_ISD_LOAD_f64(N);
+ case MVT::v2f64:
+ return Select_ISD_LOAD_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::MUL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_MUL_i32(N);
+ case MVT::v8i8:
+ return Select_ISD_MUL_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_MUL_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_MUL_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_MUL_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_MUL_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_MUL_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::MULHS: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_MULHS_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::OR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_OR_i32(N);
+ case MVT::v2i32:
+ return Select_ISD_OR_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_OR_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ROTR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ROTR_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SCALAR_TO_VECTOR: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_SCALAR_TO_VECTOR_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_SCALAR_TO_VECTOR_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_SCALAR_TO_VECTOR_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_SCALAR_TO_VECTOR_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_SCALAR_TO_VECTOR_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_SCALAR_TO_VECTOR_v4i32(N);
+ case MVT::v2f32:
+ return Select_ISD_SCALAR_TO_VECTOR_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_SCALAR_TO_VECTOR_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_SCALAR_TO_VECTOR_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SHL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SHL_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SIGN_EXTEND_INREG: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SIGN_EXTEND_INREG_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SINT_TO_FP: {
+ switch (NVT) {
+ case MVT::v2f32:
+ return Select_ISD_SINT_TO_FP_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_SINT_TO_FP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SRA: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SRA_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SRL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SRL_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::STORE: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_STORE_i32(N);
+ default:
+ return Select_ISD_STORE(N);
+ break;
+ }
+ break;
+ }
+ case ISD::SUB: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUB_i32(N);
+ case MVT::v8i8:
+ return Select_ISD_SUB_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_SUB_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_SUB_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_SUB_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_SUB_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_SUB_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_SUB_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_SUB_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SUBC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUBC_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SUBE: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUBE_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::UINT_TO_FP: {
+ switch (NVT) {
+ case MVT::v2f32:
+ return Select_ISD_UINT_TO_FP_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_UINT_TO_FP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::XOR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_XOR_i32(N);
+ case MVT::v2i32:
+ return Select_ISD_XOR_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_XOR_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ } // end of big switch.
+
+ if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&
+ N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
+ N.getOpcode() != ISD::INTRINSIC_VOID) {
+ CannotYetSelect(N);
+ } else {
+ CannotYetSelectIntrinsic(N);
+ }
+ return NULL;
+}
+
diff --git a/libclamav/c++/ARMGenInstrInfo.inc b/libclamav/c++/ARMGenInstrInfo.inc
new file mode 100644
index 0000000..9917512
--- /dev/null
+++ b/libclamav/c++/ARMGenInstrInfo.inc
@@ -0,0 +1,1702 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Instruction Descriptors
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+static const unsigned ImplicitList1[] = { ARM::CPSR, 0 };
+static const TargetRegisterClass* Barriers1[] = { &ARM::CCRRegClass, NULL };
+static const unsigned ImplicitList2[] = { ARM::SP, 0 };
+static const TargetRegisterClass* Barriers2[] = { &ARM::CCRRegClass, &ARM::DPR_8RegClass, NULL };
+static const unsigned ImplicitList3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
+static const unsigned ImplicitList4[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R9, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
+static const unsigned ImplicitList5[] = { ARM::FPSCR, 0 };
+static const TargetRegisterClass* Barriers3[] = { &ARM::DPRRegClass, &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, &ARM::tGPRRegClass, NULL };
+static const unsigned ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
+static const unsigned ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
+static const unsigned ImplicitList8[] = { ARM::LR, 0 };
+static const TargetRegisterClass* Barriers4[] = { &ARM::tGPRRegClass, NULL };
+static const unsigned ImplicitList9[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, 0 };
+static const unsigned ImplicitList10[] = { ARM::R0, ARM::LR, 0 };
+
+static const TargetOperandInfo OperandInfo2[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo3[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo4[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo5[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo6[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo7[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo8[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo9[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo10[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo11[] = { { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo12[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo13[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo14[] = { { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo15[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo17[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo22[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo23[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo25[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo26[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo27[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo28[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo29[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo30[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo31[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo33[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo36[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo37[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo40[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo41[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo42[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo43[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo44[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo45[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo46[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo52[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo53[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo54[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo65[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo80[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo81[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo82[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo83[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo89[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo91[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo92[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo93[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo94[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo95[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo96[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo97[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo98[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo99[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo102[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo103[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo104[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo105[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo106[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo107[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo108[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo109[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo110[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo113[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo115[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo116[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo118[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo119[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo120[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo121[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo122[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo123[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo124[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo125[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo126[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo127[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo128[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo129[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo133[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo134[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo135[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo136[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo137[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo138[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo139[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo140[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo141[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo142[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo143[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo144[] = { { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo145[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo146[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo147[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo152[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo154[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo155[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo156[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+
+static const TargetInstrDesc ARMInsts[] = {
+ { 0, 0, 0, 128, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
+ { 1, 0, 0, 128, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM
+ { 2, 1, 0, 128, "DBG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #2 = DBG_LABEL
+ { 3, 1, 0, 128, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #3 = EH_LABEL
+ { 4, 1, 0, 128, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #4 = GC_LABEL
+ { 5, 0, 0, 128, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
+ { 6, 3, 1, 128, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #6 = EXTRACT_SUBREG
+ { 7, 4, 1, 128, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #7 = INSERT_SUBREG
+ { 8, 1, 1, 128, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #8 = IMPLICIT_DEF
+ { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo40 }, // Inst #9 = SUBREG_TO_REG
+ { 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #10 = COPY_TO_REGCLASS
+ { 11, 3, 1, 88, "ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #11 = ADCSSri
+ { 12, 3, 1, 89, "ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #12 = ADCSSrr
+ { 13, 5, 1, 91, "ADCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #13 = ADCSSrs
+ { 14, 6, 1, 88, "ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #14 = ADCri
+ { 15, 6, 1, 89, "ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #15 = ADCrr
+ { 16, 8, 1, 91, "ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #16 = ADCrs
+ { 17, 5, 1, 88, "ADDSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #17 = ADDSri
+ { 18, 5, 1, 89, "ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #18 = ADDSrr
+ { 19, 7, 1, 91, "ADDSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #19 = ADDSrs
+ { 20, 6, 1, 88, "ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #20 = ADDri
+ { 21, 6, 1, 89, "ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #21 = ADDrr
+ { 22, 8, 1, 91, "ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #22 = ADDrs
+ { 23, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo11 }, // Inst #23 = ADJCALLSTACKDOWN
+ { 24, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo12 }, // Inst #24 = ADJCALLSTACKUP
+ { 25, 6, 1, 88, "ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #25 = ANDri
+ { 26, 6, 1, 89, "ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #26 = ANDrr
+ { 27, 8, 1, 91, "ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #27 = ANDrs
+ { 28, 4, 1, 128, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #28 = ATOMIC_CMP_SWAP_I16
+ { 29, 4, 1, 128, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #29 = ATOMIC_CMP_SWAP_I32
+ { 30, 4, 1, 128, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #30 = ATOMIC_CMP_SWAP_I8
+ { 31, 3, 1, 128, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #31 = ATOMIC_LOAD_ADD_I16
+ { 32, 3, 1, 128, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #32 = ATOMIC_LOAD_ADD_I32
+ { 33, 3, 1, 128, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #33 = ATOMIC_LOAD_ADD_I8
+ { 34, 3, 1, 128, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #34 = ATOMIC_LOAD_AND_I16
+ { 35, 3, 1, 128, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #35 = ATOMIC_LOAD_AND_I32
+ { 36, 3, 1, 128, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #36 = ATOMIC_LOAD_AND_I8
+ { 37, 3, 1, 128, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #37 = ATOMIC_LOAD_NAND_I16
+ { 38, 3, 1, 128, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #38 = ATOMIC_LOAD_NAND_I32
+ { 39, 3, 1, 128, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #39 = ATOMIC_LOAD_NAND_I8
+ { 40, 3, 1, 128, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #40 = ATOMIC_LOAD_OR_I16
+ { 41, 3, 1, 128, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #41 = ATOMIC_LOAD_OR_I32
+ { 42, 3, 1, 128, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #42 = ATOMIC_LOAD_OR_I8
+ { 43, 3, 1, 128, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #43 = ATOMIC_LOAD_SUB_I16
+ { 44, 3, 1, 128, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #44 = ATOMIC_LOAD_SUB_I32
+ { 45, 3, 1, 128, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #45 = ATOMIC_LOAD_SUB_I8
+ { 46, 3, 1, 128, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #46 = ATOMIC_LOAD_XOR_I16
+ { 47, 3, 1, 128, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #47 = ATOMIC_LOAD_XOR_I32
+ { 48, 3, 1, 128, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #48 = ATOMIC_LOAD_XOR_I8
+ { 49, 3, 1, 128, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #49 = ATOMIC_SWAP_I16
+ { 50, 3, 1, 128, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #50 = ATOMIC_SWAP_I32
+ { 51, 3, 1, 128, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #51 = ATOMIC_SWAP_I8
+ { 52, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #52 = B
+ { 53, 5, 1, 126, "BFC", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #53 = BFC
+ { 54, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #54 = BICri
+ { 55, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #55 = BICrr
+ { 56, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #56 = BICrs
+ { 57, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #57 = BL
+ { 58, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #58 = BLX
+ { 59, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #59 = BLXr9
+ { 60, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #60 = BL_pred
+ { 61, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #61 = BLr9
+ { 62, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #62 = BLr9_pred
+ { 63, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #63 = BRIND
+ { 64, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #64 = BR_JTadd
+ { 65, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #65 = BR_JTm
+ { 66, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #66 = BR_JTr
+ { 67, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #67 = BX
+ { 68, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #68 = BX_RET
+ { 69, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #69 = BXr9
+ { 70, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #70 = Bcc
+ { 71, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = CLZ
+ { 72, 4, 0, 97, "CMNri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #72 = CMNri
+ { 73, 4, 0, 98, "CMNrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #73 = CMNrr
+ { 74, 6, 0, 100, "CMNrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #74 = CMNrs
+ { 75, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #75 = CMNzri
+ { 76, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #76 = CMNzrr
+ { 77, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #77 = CMNzrs
+ { 78, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #78 = CMPri
+ { 79, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #79 = CMPrr
+ { 80, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #80 = CMPrs
+ { 81, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #81 = CMPzri
+ { 82, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #82 = CMPzrr
+ { 83, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #83 = CMPzrs
+ { 84, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo24 }, // Inst #84 = CONSTPOOL_ENTRY
+ { 85, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #85 = EORri
+ { 86, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #86 = EORrr
+ { 87, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #87 = EORrs
+ { 88, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #88 = FCONSTD
+ { 89, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo26 }, // Inst #89 = FCONSTS
+ { 90, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #90 = FMSTAT
+ { 91, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #91 = Int_MemBarrierV6
+ { 92, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #92 = Int_MemBarrierV7
+ { 93, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #93 = Int_SyncBarrierV6
+ { 94, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #94 = Int_SyncBarrierV7
+ { 95, 1, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #95 = Int_eh_sjlj_setjmp
+ { 96, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #96 = LDM
+ { 97, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #97 = LDM_RET
+ { 98, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #98 = LDR
+ { 99, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #99 = LDRB
+ { 100, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #100 = LDRB_POST
+ { 101, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #101 = LDRB_PRE
+ { 102, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #102 = LDRD
+ { 103, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #103 = LDREX
+ { 104, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #104 = LDREXB
+ { 105, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #105 = LDREXD
+ { 106, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #106 = LDREXH
+ { 107, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #107 = LDRH
+ { 108, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #108 = LDRH_POST
+ { 109, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #109 = LDRH_PRE
+ { 110, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #110 = LDRSB
+ { 111, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #111 = LDRSB_POST
+ { 112, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #112 = LDRSB_PRE
+ { 113, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #113 = LDRSH
+ { 114, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #114 = LDRSH_POST
+ { 115, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #115 = LDRSH_PRE
+ { 116, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #116 = LDR_POST
+ { 117, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #117 = LDR_PRE
+ { 118, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #118 = LDRcp
+ { 119, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #119 = LEApcrel
+ { 120, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo30 }, // Inst #120 = LEApcrelJT
+ { 121, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #121 = MLA
+ { 122, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #122 = MLS
+ { 123, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #123 = MOVCCi
+ { 124, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo33 }, // Inst #124 = MOVCCr
+ { 125, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo34 }, // Inst #125 = MOVCCs
+ { 126, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #126 = MOVTi16
+ { 127, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #127 = MOVi
+ { 128, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #128 = MOVi16
+ { 129, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #129 = MOVi2pieces
+ { 130, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #130 = MOVi32imm
+ { 131, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #131 = MOVr
+ { 132, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #132 = MOVrx
+ { 133, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #133 = MOVs
+ { 134, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #134 = MOVsra_flag
+ { 135, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #135 = MOVsrl_flag
+ { 136, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #136 = MUL
+ { 137, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #137 = MVNi
+ { 138, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #138 = MVNr
+ { 139, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #139 = MVNs
+ { 140, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #140 = ORRri
+ { 141, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #141 = ORRrr
+ { 142, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #142 = ORRrs
+ { 143, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #143 = PICADD
+ { 144, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #144 = PICLDR
+ { 145, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #145 = PICLDRB
+ { 146, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #146 = PICLDRH
+ { 147, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #147 = PICLDRSB
+ { 148, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #148 = PICLDRSH
+ { 149, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #149 = PICSTR
+ { 150, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #150 = PICSTRB
+ { 151, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #151 = PICSTRH
+ { 152, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #152 = PKHBT
+ { 153, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #153 = PKHTB
+ { 154, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #154 = REV
+ { 155, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #155 = REV16
+ { 156, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #156 = REVSH
+ { 157, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #157 = RSBSri
+ { 158, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #158 = RSBSrs
+ { 159, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #159 = RSBri
+ { 160, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #160 = RSBrs
+ { 161, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #161 = RSCSri
+ { 162, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #162 = RSCSrs
+ { 163, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #163 = RSCri
+ { 164, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #164 = RSCrs
+ { 165, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #165 = SBCSSri
+ { 166, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #166 = SBCSSrr
+ { 167, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #167 = SBCSSrs
+ { 168, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #168 = SBCri
+ { 169, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #169 = SBCrr
+ { 170, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #170 = SBCrs
+ { 171, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #171 = SBFX
+ { 172, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #172 = SMLABB
+ { 173, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #173 = SMLABT
+ { 174, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #174 = SMLAL
+ { 175, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #175 = SMLATB
+ { 176, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #176 = SMLATT
+ { 177, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #177 = SMLAWB
+ { 178, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #178 = SMLAWT
+ { 179, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #179 = SMMLA
+ { 180, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #180 = SMMLS
+ { 181, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #181 = SMMUL
+ { 182, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #182 = SMULBB
+ { 183, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #183 = SMULBT
+ { 184, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #184 = SMULL
+ { 185, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #185 = SMULTB
+ { 186, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #186 = SMULTT
+ { 187, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #187 = SMULWB
+ { 188, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #188 = SMULWT
+ { 189, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #189 = STM
+ { 190, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #190 = STR
+ { 191, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #191 = STRB
+ { 192, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #192 = STRB_POST
+ { 193, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #193 = STRB_PRE
+ { 194, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #194 = STRD
+ { 195, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #195 = STREX
+ { 196, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #196 = STREXB
+ { 197, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #197 = STREXD
+ { 198, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #198 = STREXH
+ { 199, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #199 = STRH
+ { 200, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #200 = STRH_POST
+ { 201, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #201 = STRH_PRE
+ { 202, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #202 = STR_POST
+ { 203, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #203 = STR_PRE
+ { 204, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #204 = SUBSri
+ { 205, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #205 = SUBSrr
+ { 206, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #206 = SUBSrs
+ { 207, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #207 = SUBri
+ { 208, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #208 = SUBrr
+ { 209, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #209 = SUBrs
+ { 210, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #210 = SXTABrr
+ { 211, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #211 = SXTABrr_rot
+ { 212, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #212 = SXTAHrr
+ { 213, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #213 = SXTAHrr_rot
+ { 214, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #214 = SXTBr
+ { 215, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #215 = SXTBr_rot
+ { 216, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #216 = SXTHr
+ { 217, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #217 = SXTHr_rot
+ { 218, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #218 = TEQri
+ { 219, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #219 = TEQrr
+ { 220, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #220 = TEQrs
+ { 221, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #221 = TPsoft
+ { 222, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #222 = TSTri
+ { 223, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #223 = TSTrr
+ { 224, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #224 = TSTrs
+ { 225, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #225 = UBFX
+ { 226, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #226 = UMAAL
+ { 227, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #227 = UMLAL
+ { 228, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #228 = UMULL
+ { 229, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #229 = UXTABrr
+ { 230, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #230 = UXTABrr_rot
+ { 231, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #231 = UXTAHrr
+ { 232, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #232 = UXTAHrr_rot
+ { 233, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #233 = UXTB16r
+ { 234, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #234 = UXTB16r_rot
+ { 235, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #235 = UXTBr
+ { 236, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #236 = UXTBr_rot
+ { 237, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #237 = UXTHr
+ { 238, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #238 = UXTHr_rot
+ { 239, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #239 = VABALsv2i64
+ { 240, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #240 = VABALsv4i32
+ { 241, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #241 = VABALsv8i16
+ { 242, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #242 = VABALuv2i64
+ { 243, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #243 = VABALuv4i32
+ { 244, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #244 = VABALuv8i16
+ { 245, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #245 = VABAsv16i8
+ { 246, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #246 = VABAsv2i32
+ { 247, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #247 = VABAsv4i16
+ { 248, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #248 = VABAsv4i32
+ { 249, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #249 = VABAsv8i16
+ { 250, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #250 = VABAsv8i8
+ { 251, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #251 = VABAuv16i8
+ { 252, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #252 = VABAuv2i32
+ { 253, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #253 = VABAuv4i16
+ { 254, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #254 = VABAuv4i32
+ { 255, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #255 = VABAuv8i16
+ { 256, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #256 = VABAuv8i8
+ { 257, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #257 = VABDLsv2i64
+ { 258, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #258 = VABDLsv4i32
+ { 259, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #259 = VABDLsv8i16
+ { 260, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #260 = VABDLuv2i64
+ { 261, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #261 = VABDLuv4i32
+ { 262, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #262 = VABDLuv8i16
+ { 263, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #263 = VABDfd
+ { 264, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #264 = VABDfq
+ { 265, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #265 = VABDsv16i8
+ { 266, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #266 = VABDsv2i32
+ { 267, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #267 = VABDsv4i16
+ { 268, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #268 = VABDsv4i32
+ { 269, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #269 = VABDsv8i16
+ { 270, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #270 = VABDsv8i8
+ { 271, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #271 = VABDuv16i8
+ { 272, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #272 = VABDuv2i32
+ { 273, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #273 = VABDuv4i16
+ { 274, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #274 = VABDuv4i32
+ { 275, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #275 = VABDuv8i16
+ { 276, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #276 = VABDuv8i8
+ { 277, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #277 = VABSD
+ { 278, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #278 = VABSS
+ { 279, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #279 = VABSfd
+ { 280, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #280 = VABSfd_sfp
+ { 281, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #281 = VABSfq
+ { 282, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #282 = VABSv16i8
+ { 283, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #283 = VABSv2i32
+ { 284, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #284 = VABSv4i16
+ { 285, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #285 = VABSv4i32
+ { 286, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #286 = VABSv8i16
+ { 287, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #287 = VABSv8i8
+ { 288, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #288 = VACGEd
+ { 289, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #289 = VACGEq
+ { 290, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #290 = VACGTd
+ { 291, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #291 = VACGTq
+ { 292, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #292 = VADDD
+ { 293, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #293 = VADDHNv2i32
+ { 294, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #294 = VADDHNv4i16
+ { 295, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #295 = VADDHNv8i8
+ { 296, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #296 = VADDLsv2i64
+ { 297, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #297 = VADDLsv4i32
+ { 298, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #298 = VADDLsv8i16
+ { 299, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #299 = VADDLuv2i64
+ { 300, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #300 = VADDLuv4i32
+ { 301, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #301 = VADDLuv8i16
+ { 302, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #302 = VADDS
+ { 303, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #303 = VADDWsv2i64
+ { 304, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #304 = VADDWsv4i32
+ { 305, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #305 = VADDWsv8i16
+ { 306, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #306 = VADDWuv2i64
+ { 307, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = VADDWuv4i32
+ { 308, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #308 = VADDWuv8i16
+ { 309, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #309 = VADDfd
+ { 310, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #310 = VADDfd_sfp
+ { 311, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #311 = VADDfq
+ { 312, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = VADDv16i8
+ { 313, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #313 = VADDv1i64
+ { 314, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #314 = VADDv2i32
+ { 315, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = VADDv2i64
+ { 316, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #316 = VADDv4i16
+ { 317, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #317 = VADDv4i32
+ { 318, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #318 = VADDv8i16
+ { 319, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #319 = VADDv8i8
+ { 320, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #320 = VANDd
+ { 321, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #321 = VANDq
+ { 322, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #322 = VBICd
+ { 323, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #323 = VBICq
+ { 324, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #324 = VBSLd
+ { 325, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #325 = VBSLq
+ { 326, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #326 = VCEQfd
+ { 327, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #327 = VCEQfq
+ { 328, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #328 = VCEQv16i8
+ { 329, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #329 = VCEQv2i32
+ { 330, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #330 = VCEQv4i16
+ { 331, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #331 = VCEQv4i32
+ { 332, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #332 = VCEQv8i16
+ { 333, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #333 = VCEQv8i8
+ { 334, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #334 = VCGEfd
+ { 335, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #335 = VCGEfq
+ { 336, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #336 = VCGEsv16i8
+ { 337, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #337 = VCGEsv2i32
+ { 338, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #338 = VCGEsv4i16
+ { 339, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #339 = VCGEsv4i32
+ { 340, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #340 = VCGEsv8i16
+ { 341, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #341 = VCGEsv8i8
+ { 342, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #342 = VCGEuv16i8
+ { 343, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #343 = VCGEuv2i32
+ { 344, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #344 = VCGEuv4i16
+ { 345, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #345 = VCGEuv4i32
+ { 346, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #346 = VCGEuv8i16
+ { 347, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #347 = VCGEuv8i8
+ { 348, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #348 = VCGTfd
+ { 349, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #349 = VCGTfq
+ { 350, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #350 = VCGTsv16i8
+ { 351, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #351 = VCGTsv2i32
+ { 352, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #352 = VCGTsv4i16
+ { 353, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #353 = VCGTsv4i32
+ { 354, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #354 = VCGTsv8i16
+ { 355, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #355 = VCGTsv8i8
+ { 356, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #356 = VCGTuv16i8
+ { 357, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #357 = VCGTuv2i32
+ { 358, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #358 = VCGTuv4i16
+ { 359, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #359 = VCGTuv4i32
+ { 360, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #360 = VCGTuv8i16
+ { 361, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #361 = VCGTuv8i8
+ { 362, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #362 = VCLSv16i8
+ { 363, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #363 = VCLSv2i32
+ { 364, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #364 = VCLSv4i16
+ { 365, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #365 = VCLSv4i32
+ { 366, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #366 = VCLSv8i16
+ { 367, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #367 = VCLSv8i8
+ { 368, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #368 = VCLZv16i8
+ { 369, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #369 = VCLZv2i32
+ { 370, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #370 = VCLZv4i16
+ { 371, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #371 = VCLZv4i32
+ { 372, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #372 = VCLZv8i16
+ { 373, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #373 = VCLZv8i8
+ { 374, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo47 }, // Inst #374 = VCMPED
+ { 375, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo48 }, // Inst #375 = VCMPES
+ { 376, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo55 }, // Inst #376 = VCMPEZD
+ { 377, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo56 }, // Inst #377 = VCMPEZS
+ { 378, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #378 = VCNTd
+ { 379, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #379 = VCNTq
+ { 380, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #380 = VCVTDS
+ { 381, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #381 = VCVTSD
+ { 382, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #382 = VCVTf2sd
+ { 383, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #383 = VCVTf2sd_sfp
+ { 384, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #384 = VCVTf2sq
+ { 385, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #385 = VCVTf2ud
+ { 386, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #386 = VCVTf2ud_sfp
+ { 387, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #387 = VCVTf2uq
+ { 388, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #388 = VCVTf2xsd
+ { 389, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #389 = VCVTf2xsq
+ { 390, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #390 = VCVTf2xud
+ { 391, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #391 = VCVTf2xuq
+ { 392, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #392 = VCVTs2fd
+ { 393, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #393 = VCVTs2fd_sfp
+ { 394, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #394 = VCVTs2fq
+ { 395, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #395 = VCVTu2fd
+ { 396, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #396 = VCVTu2fd_sfp
+ { 397, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #397 = VCVTu2fq
+ { 398, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #398 = VCVTxs2fd
+ { 399, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #399 = VCVTxs2fq
+ { 400, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #400 = VCVTxu2fd
+ { 401, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #401 = VCVTxu2fq
+ { 402, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #402 = VDIVD
+ { 403, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #403 = VDIVS
+ { 404, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #404 = VDUP16d
+ { 405, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #405 = VDUP16q
+ { 406, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #406 = VDUP32d
+ { 407, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #407 = VDUP32q
+ { 408, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #408 = VDUP8d
+ { 409, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #409 = VDUP8q
+ { 410, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #410 = VDUPLN16d
+ { 411, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #411 = VDUPLN16q
+ { 412, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #412 = VDUPLN32d
+ { 413, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #413 = VDUPLN32q
+ { 414, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #414 = VDUPLN8d
+ { 415, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #415 = VDUPLN8q
+ { 416, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #416 = VDUPLNfd
+ { 417, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #417 = VDUPLNfq
+ { 418, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo61 }, // Inst #418 = VDUPfd
+ { 419, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #419 = VDUPfdf
+ { 420, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo62 }, // Inst #420 = VDUPfq
+ { 421, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #421 = VDUPfqf
+ { 422, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #422 = VEORd
+ { 423, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #423 = VEORq
+ { 424, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #424 = VEXTd16
+ { 425, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #425 = VEXTd32
+ { 426, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #426 = VEXTd8
+ { 427, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #427 = VEXTdf
+ { 428, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #428 = VEXTq16
+ { 429, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #429 = VEXTq32
+ { 430, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #430 = VEXTq8
+ { 431, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #431 = VEXTqf
+ { 432, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #432 = VGETLNi32
+ { 433, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #433 = VGETLNs16
+ { 434, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #434 = VGETLNs8
+ { 435, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #435 = VGETLNu16
+ { 436, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo67 }, // Inst #436 = VGETLNu8
+ { 437, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #437 = VHADDsv16i8
+ { 438, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #438 = VHADDsv2i32
+ { 439, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #439 = VHADDsv4i16
+ { 440, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #440 = VHADDsv4i32
+ { 441, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #441 = VHADDsv8i16
+ { 442, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #442 = VHADDsv8i8
+ { 443, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #443 = VHADDuv16i8
+ { 444, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #444 = VHADDuv2i32
+ { 445, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #445 = VHADDuv4i16
+ { 446, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #446 = VHADDuv4i32
+ { 447, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #447 = VHADDuv8i16
+ { 448, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #448 = VHADDuv8i8
+ { 449, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #449 = VHSUBsv16i8
+ { 450, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #450 = VHSUBsv2i32
+ { 451, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #451 = VHSUBsv4i16
+ { 452, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #452 = VHSUBsv4i32
+ { 453, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #453 = VHSUBsv8i16
+ { 454, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #454 = VHSUBsv8i8
+ { 455, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #455 = VHSUBuv16i8
+ { 456, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #456 = VHSUBuv2i32
+ { 457, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #457 = VHSUBuv4i16
+ { 458, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #458 = VHSUBuv4i32
+ { 459, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #459 = VHSUBuv8i16
+ { 460, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #460 = VHSUBuv8i8
+ { 461, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #461 = VLD1d16
+ { 462, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #462 = VLD1d32
+ { 463, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #463 = VLD1d64
+ { 464, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #464 = VLD1d8
+ { 465, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #465 = VLD1df
+ { 466, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #466 = VLD1q16
+ { 467, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #467 = VLD1q32
+ { 468, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #468 = VLD1q64
+ { 469, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #469 = VLD1q8
+ { 470, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #470 = VLD1qf
+ { 471, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #471 = VLD2LNd16
+ { 472, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #472 = VLD2LNd32
+ { 473, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #473 = VLD2LNd8
+ { 474, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #474 = VLD2LNq16a
+ { 475, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #475 = VLD2LNq16b
+ { 476, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #476 = VLD2LNq32a
+ { 477, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #477 = VLD2LNq32b
+ { 478, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #478 = VLD2d16
+ { 479, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #479 = VLD2d32
+ { 480, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #480 = VLD2d64
+ { 481, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #481 = VLD2d8
+ { 482, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #482 = VLD2q16
+ { 483, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #483 = VLD2q32
+ { 484, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #484 = VLD2q8
+ { 485, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #485 = VLD3LNd16
+ { 486, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #486 = VLD3LNd32
+ { 487, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #487 = VLD3LNd8
+ { 488, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #488 = VLD3LNq16a
+ { 489, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #489 = VLD3LNq16b
+ { 490, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #490 = VLD3LNq32a
+ { 491, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #491 = VLD3LNq32b
+ { 492, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #492 = VLD3d16
+ { 493, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #493 = VLD3d32
+ { 494, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #494 = VLD3d64
+ { 495, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #495 = VLD3d8
+ { 496, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #496 = VLD3q16a
+ { 497, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #497 = VLD3q16b
+ { 498, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #498 = VLD3q32a
+ { 499, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #499 = VLD3q32b
+ { 500, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #500 = VLD3q8a
+ { 501, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #501 = VLD3q8b
+ { 502, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #502 = VLD4LNd16
+ { 503, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #503 = VLD4LNd32
+ { 504, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #504 = VLD4LNd8
+ { 505, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #505 = VLD4LNq16a
+ { 506, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #506 = VLD4LNq16b
+ { 507, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #507 = VLD4LNq32a
+ { 508, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #508 = VLD4LNq32b
+ { 509, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #509 = VLD4d16
+ { 510, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #510 = VLD4d32
+ { 511, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #511 = VLD4d64
+ { 512, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #512 = VLD4d8
+ { 513, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #513 = VLD4q16a
+ { 514, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #514 = VLD4q16b
+ { 515, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #515 = VLD4q32a
+ { 516, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #516 = VLD4q32b
+ { 517, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #517 = VLD4q8a
+ { 518, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #518 = VLD4q8b
+ { 519, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #519 = VLDMD
+ { 520, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #520 = VLDMS
+ { 521, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #521 = VLDRD
+ { 522, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #522 = VLDRQ
+ { 523, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #523 = VLDRS
+ { 524, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #524 = VMAXfd
+ { 525, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #525 = VMAXfq
+ { 526, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #526 = VMAXsv16i8
+ { 527, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #527 = VMAXsv2i32
+ { 528, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #528 = VMAXsv4i16
+ { 529, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #529 = VMAXsv4i32
+ { 530, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #530 = VMAXsv8i16
+ { 531, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #531 = VMAXsv8i8
+ { 532, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #532 = VMAXuv16i8
+ { 533, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #533 = VMAXuv2i32
+ { 534, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #534 = VMAXuv4i16
+ { 535, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #535 = VMAXuv4i32
+ { 536, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #536 = VMAXuv8i16
+ { 537, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #537 = VMAXuv8i8
+ { 538, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #538 = VMINfd
+ { 539, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #539 = VMINfq
+ { 540, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #540 = VMINsv16i8
+ { 541, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #541 = VMINsv2i32
+ { 542, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #542 = VMINsv4i16
+ { 543, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #543 = VMINsv4i32
+ { 544, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #544 = VMINsv8i16
+ { 545, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #545 = VMINsv8i8
+ { 546, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #546 = VMINuv16i8
+ { 547, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #547 = VMINuv2i32
+ { 548, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #548 = VMINuv4i16
+ { 549, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #549 = VMINuv4i32
+ { 550, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #550 = VMINuv8i16
+ { 551, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #551 = VMINuv8i8
+ { 552, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #552 = VMLAD
+ { 553, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #553 = VMLALslsv2i32
+ { 554, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #554 = VMLALslsv4i16
+ { 555, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #555 = VMLALsluv2i32
+ { 556, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #556 = VMLALsluv4i16
+ { 557, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #557 = VMLALsv2i64
+ { 558, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #558 = VMLALsv4i32
+ { 559, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #559 = VMLALsv8i16
+ { 560, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #560 = VMLALuv2i64
+ { 561, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #561 = VMLALuv4i32
+ { 562, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #562 = VMLALuv8i16
+ { 563, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #563 = VMLAS
+ { 564, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #564 = VMLAfd
+ { 565, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #565 = VMLAfq
+ { 566, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #566 = VMLAslfd
+ { 567, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #567 = VMLAslfq
+ { 568, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #568 = VMLAslv2i32
+ { 569, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #569 = VMLAslv4i16
+ { 570, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #570 = VMLAslv4i32
+ { 571, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #571 = VMLAslv8i16
+ { 572, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #572 = VMLAv16i8
+ { 573, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #573 = VMLAv2i32
+ { 574, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #574 = VMLAv4i16
+ { 575, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #575 = VMLAv4i32
+ { 576, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #576 = VMLAv8i16
+ { 577, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #577 = VMLAv8i8
+ { 578, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #578 = VMLSD
+ { 579, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #579 = VMLSLslsv2i32
+ { 580, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #580 = VMLSLslsv4i16
+ { 581, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #581 = VMLSLsluv2i32
+ { 582, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #582 = VMLSLsluv4i16
+ { 583, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #583 = VMLSLsv2i64
+ { 584, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #584 = VMLSLsv4i32
+ { 585, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #585 = VMLSLsv8i16
+ { 586, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #586 = VMLSLuv2i64
+ { 587, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #587 = VMLSLuv4i32
+ { 588, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #588 = VMLSLuv8i16
+ { 589, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #589 = VMLSS
+ { 590, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #590 = VMLSfd
+ { 591, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #591 = VMLSfq
+ { 592, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #592 = VMLSslfd
+ { 593, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #593 = VMLSslfq
+ { 594, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #594 = VMLSslv2i32
+ { 595, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #595 = VMLSslv4i16
+ { 596, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #596 = VMLSslv4i32
+ { 597, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #597 = VMLSslv8i16
+ { 598, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #598 = VMLSv16i8
+ { 599, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #599 = VMLSv2i32
+ { 600, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #600 = VMLSv4i16
+ { 601, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #601 = VMLSv4i32
+ { 602, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo42 }, // Inst #602 = VMLSv8i16
+ { 603, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #603 = VMLSv8i8
+ { 604, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #604 = VMOVD
+ { 605, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #605 = VMOVDRR
+ { 606, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #606 = VMOVDcc
+ { 607, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #607 = VMOVDneon
+ { 608, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #608 = VMOVLsv2i64
+ { 609, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #609 = VMOVLsv4i32
+ { 610, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #610 = VMOVLsv8i16
+ { 611, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #611 = VMOVLuv2i64
+ { 612, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #612 = VMOVLuv4i32
+ { 613, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #613 = VMOVLuv8i16
+ { 614, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #614 = VMOVNv2i32
+ { 615, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #615 = VMOVNv4i16
+ { 616, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #616 = VMOVNv8i8
+ { 617, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #617 = VMOVQ
+ { 618, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #618 = VMOVRRD
+ { 619, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #619 = VMOVRS
+ { 620, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #620 = VMOVS
+ { 621, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #621 = VMOVSR
+ { 622, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #622 = VMOVScc
+ { 623, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #623 = VMOVv16i8
+ { 624, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #624 = VMOVv1i64
+ { 625, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #625 = VMOVv2i32
+ { 626, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #626 = VMOVv2i64
+ { 627, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #627 = VMOVv4i16
+ { 628, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #628 = VMOVv4i32
+ { 629, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #629 = VMOVv8i16
+ { 630, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #630 = VMOVv8i8
+ { 631, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #631 = VMULD
+ { 632, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #632 = VMULLp
+ { 633, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #633 = VMULLslsv2i32
+ { 634, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #634 = VMULLslsv4i16
+ { 635, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #635 = VMULLsluv2i32
+ { 636, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #636 = VMULLsluv4i16
+ { 637, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #637 = VMULLsv2i64
+ { 638, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #638 = VMULLsv4i32
+ { 639, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #639 = VMULLsv8i16
+ { 640, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #640 = VMULLuv2i64
+ { 641, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #641 = VMULLuv4i32
+ { 642, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #642 = VMULLuv8i16
+ { 643, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #643 = VMULS
+ { 644, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #644 = VMULfd
+ { 645, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #645 = VMULfd_sfp
+ { 646, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #646 = VMULfq
+ { 647, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #647 = VMULpd
+ { 648, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #648 = VMULpq
+ { 649, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #649 = VMULslfd
+ { 650, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #650 = VMULslfq
+ { 651, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #651 = VMULslv2i32
+ { 652, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #652 = VMULslv4i16
+ { 653, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #653 = VMULslv4i32
+ { 654, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #654 = VMULslv8i16
+ { 655, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #655 = VMULv16i8
+ { 656, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #656 = VMULv2i32
+ { 657, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #657 = VMULv4i16
+ { 658, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #658 = VMULv4i32
+ { 659, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #659 = VMULv8i16
+ { 660, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #660 = VMULv8i8
+ { 661, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #661 = VMVNd
+ { 662, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #662 = VMVNq
+ { 663, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #663 = VNEGD
+ { 664, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #664 = VNEGDcc
+ { 665, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #665 = VNEGS
+ { 666, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #666 = VNEGScc
+ { 667, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #667 = VNEGf32d
+ { 668, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #668 = VNEGf32d_sfp
+ { 669, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #669 = VNEGf32q
+ { 670, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #670 = VNEGs16d
+ { 671, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #671 = VNEGs16q
+ { 672, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #672 = VNEGs32d
+ { 673, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #673 = VNEGs32q
+ { 674, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #674 = VNEGs8d
+ { 675, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #675 = VNEGs8q
+ { 676, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #676 = VNMLAD
+ { 677, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #677 = VNMLAS
+ { 678, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #678 = VNMLSD
+ { 679, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #679 = VNMLSS
+ { 680, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #680 = VNMULD
+ { 681, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #681 = VNMULS
+ { 682, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #682 = VORNd
+ { 683, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #683 = VORNq
+ { 684, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #684 = VORRd
+ { 685, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #685 = VORRq
+ { 686, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #686 = VPADALsv16i8
+ { 687, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #687 = VPADALsv2i32
+ { 688, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #688 = VPADALsv4i16
+ { 689, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #689 = VPADALsv4i32
+ { 690, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #690 = VPADALsv8i16
+ { 691, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #691 = VPADALsv8i8
+ { 692, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #692 = VPADALuv16i8
+ { 693, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #693 = VPADALuv2i32
+ { 694, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #694 = VPADALuv4i16
+ { 695, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #695 = VPADALuv4i32
+ { 696, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #696 = VPADALuv8i16
+ { 697, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #697 = VPADALuv8i8
+ { 698, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #698 = VPADDLsv16i8
+ { 699, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #699 = VPADDLsv2i32
+ { 700, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #700 = VPADDLsv4i16
+ { 701, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #701 = VPADDLsv4i32
+ { 702, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #702 = VPADDLsv8i16
+ { 703, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #703 = VPADDLsv8i8
+ { 704, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #704 = VPADDLuv16i8
+ { 705, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #705 = VPADDLuv2i32
+ { 706, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #706 = VPADDLuv4i16
+ { 707, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #707 = VPADDLuv4i32
+ { 708, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #708 = VPADDLuv8i16
+ { 709, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #709 = VPADDLuv8i8
+ { 710, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #710 = VPADDf
+ { 711, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #711 = VPADDi16
+ { 712, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #712 = VPADDi32
+ { 713, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #713 = VPADDi8
+ { 714, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #714 = VPMAXf
+ { 715, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #715 = VPMAXs16
+ { 716, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #716 = VPMAXs32
+ { 717, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #717 = VPMAXs8
+ { 718, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #718 = VPMAXu16
+ { 719, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #719 = VPMAXu32
+ { 720, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #720 = VPMAXu8
+ { 721, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #721 = VPMINf
+ { 722, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #722 = VPMINs16
+ { 723, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #723 = VPMINs32
+ { 724, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #724 = VPMINs8
+ { 725, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #725 = VPMINu16
+ { 726, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #726 = VPMINu32
+ { 727, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #727 = VPMINu8
+ { 728, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #728 = VQABSv16i8
+ { 729, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #729 = VQABSv2i32
+ { 730, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #730 = VQABSv4i16
+ { 731, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #731 = VQABSv4i32
+ { 732, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #732 = VQABSv8i16
+ { 733, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #733 = VQABSv8i8
+ { 734, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #734 = VQADDsv16i8
+ { 735, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #735 = VQADDsv1i64
+ { 736, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #736 = VQADDsv2i32
+ { 737, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #737 = VQADDsv2i64
+ { 738, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #738 = VQADDsv4i16
+ { 739, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #739 = VQADDsv4i32
+ { 740, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #740 = VQADDsv8i16
+ { 741, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #741 = VQADDsv8i8
+ { 742, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #742 = VQADDuv16i8
+ { 743, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #743 = VQADDuv1i64
+ { 744, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #744 = VQADDuv2i32
+ { 745, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #745 = VQADDuv2i64
+ { 746, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #746 = VQADDuv4i16
+ { 747, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #747 = VQADDuv4i32
+ { 748, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #748 = VQADDuv8i16
+ { 749, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #749 = VQADDuv8i8
+ { 750, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #750 = VQDMLALslv2i32
+ { 751, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #751 = VQDMLALslv4i16
+ { 752, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #752 = VQDMLALv2i64
+ { 753, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #753 = VQDMLALv4i32
+ { 754, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #754 = VQDMLSLslv2i32
+ { 755, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #755 = VQDMLSLslv4i16
+ { 756, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #756 = VQDMLSLv2i64
+ { 757, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo41 }, // Inst #757 = VQDMLSLv4i32
+ { 758, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #758 = VQDMULHslv2i32
+ { 759, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #759 = VQDMULHslv4i16
+ { 760, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #760 = VQDMULHslv4i32
+ { 761, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #761 = VQDMULHslv8i16
+ { 762, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #762 = VQDMULHv2i32
+ { 763, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #763 = VQDMULHv4i16
+ { 764, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #764 = VQDMULHv4i32
+ { 765, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #765 = VQDMULHv8i16
+ { 766, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #766 = VQDMULLslv2i32
+ { 767, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #767 = VQDMULLslv4i16
+ { 768, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #768 = VQDMULLv2i64
+ { 769, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #769 = VQDMULLv4i32
+ { 770, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #770 = VQMOVNsuv2i32
+ { 771, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #771 = VQMOVNsuv4i16
+ { 772, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #772 = VQMOVNsuv8i8
+ { 773, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #773 = VQMOVNsv2i32
+ { 774, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #774 = VQMOVNsv4i16
+ { 775, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #775 = VQMOVNsv8i8
+ { 776, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #776 = VQMOVNuv2i32
+ { 777, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #777 = VQMOVNuv4i16
+ { 778, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #778 = VQMOVNuv8i8
+ { 779, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #779 = VQNEGv16i8
+ { 780, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #780 = VQNEGv2i32
+ { 781, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #781 = VQNEGv4i16
+ { 782, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #782 = VQNEGv4i32
+ { 783, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #783 = VQNEGv8i16
+ { 784, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #784 = VQNEGv8i8
+ { 785, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #785 = VQRDMULHslv2i32
+ { 786, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #786 = VQRDMULHslv4i16
+ { 787, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #787 = VQRDMULHslv4i32
+ { 788, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #788 = VQRDMULHslv8i16
+ { 789, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #789 = VQRDMULHv2i32
+ { 790, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #790 = VQRDMULHv4i16
+ { 791, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #791 = VQRDMULHv4i32
+ { 792, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #792 = VQRDMULHv8i16
+ { 793, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #793 = VQRSHLsv16i8
+ { 794, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #794 = VQRSHLsv1i64
+ { 795, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #795 = VQRSHLsv2i32
+ { 796, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #796 = VQRSHLsv2i64
+ { 797, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #797 = VQRSHLsv4i16
+ { 798, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #798 = VQRSHLsv4i32
+ { 799, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #799 = VQRSHLsv8i16
+ { 800, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #800 = VQRSHLsv8i8
+ { 801, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #801 = VQRSHLuv16i8
+ { 802, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #802 = VQRSHLuv1i64
+ { 803, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #803 = VQRSHLuv2i32
+ { 804, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #804 = VQRSHLuv2i64
+ { 805, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #805 = VQRSHLuv4i16
+ { 806, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #806 = VQRSHLuv4i32
+ { 807, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #807 = VQRSHLuv8i16
+ { 808, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #808 = VQRSHLuv8i8
+ { 809, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #809 = VQRSHRNsv2i32
+ { 810, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #810 = VQRSHRNsv4i16
+ { 811, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #811 = VQRSHRNsv8i8
+ { 812, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #812 = VQRSHRNuv2i32
+ { 813, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #813 = VQRSHRNuv4i16
+ { 814, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #814 = VQRSHRNuv8i8
+ { 815, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #815 = VQRSHRUNv2i32
+ { 816, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #816 = VQRSHRUNv4i16
+ { 817, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #817 = VQRSHRUNv8i8
+ { 818, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #818 = VQSHLsiv16i8
+ { 819, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #819 = VQSHLsiv1i64
+ { 820, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #820 = VQSHLsiv2i32
+ { 821, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #821 = VQSHLsiv2i64
+ { 822, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #822 = VQSHLsiv4i16
+ { 823, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #823 = VQSHLsiv4i32
+ { 824, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #824 = VQSHLsiv8i16
+ { 825, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #825 = VQSHLsiv8i8
+ { 826, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #826 = VQSHLsuv16i8
+ { 827, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #827 = VQSHLsuv1i64
+ { 828, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #828 = VQSHLsuv2i32
+ { 829, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #829 = VQSHLsuv2i64
+ { 830, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #830 = VQSHLsuv4i16
+ { 831, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #831 = VQSHLsuv4i32
+ { 832, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #832 = VQSHLsuv8i16
+ { 833, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #833 = VQSHLsuv8i8
+ { 834, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #834 = VQSHLsv16i8
+ { 835, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #835 = VQSHLsv1i64
+ { 836, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #836 = VQSHLsv2i32
+ { 837, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #837 = VQSHLsv2i64
+ { 838, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #838 = VQSHLsv4i16
+ { 839, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #839 = VQSHLsv4i32
+ { 840, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #840 = VQSHLsv8i16
+ { 841, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #841 = VQSHLsv8i8
+ { 842, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #842 = VQSHLuiv16i8
+ { 843, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #843 = VQSHLuiv1i64
+ { 844, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #844 = VQSHLuiv2i32
+ { 845, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #845 = VQSHLuiv2i64
+ { 846, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #846 = VQSHLuiv4i16
+ { 847, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #847 = VQSHLuiv4i32
+ { 848, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #848 = VQSHLuiv8i16
+ { 849, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #849 = VQSHLuiv8i8
+ { 850, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #850 = VQSHLuv16i8
+ { 851, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #851 = VQSHLuv1i64
+ { 852, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #852 = VQSHLuv2i32
+ { 853, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #853 = VQSHLuv2i64
+ { 854, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #854 = VQSHLuv4i16
+ { 855, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #855 = VQSHLuv4i32
+ { 856, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #856 = VQSHLuv8i16
+ { 857, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #857 = VQSHLuv8i8
+ { 858, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #858 = VQSHRNsv2i32
+ { 859, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #859 = VQSHRNsv4i16
+ { 860, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #860 = VQSHRNsv8i8
+ { 861, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #861 = VQSHRNuv2i32
+ { 862, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #862 = VQSHRNuv4i16
+ { 863, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #863 = VQSHRNuv8i8
+ { 864, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #864 = VQSHRUNv2i32
+ { 865, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #865 = VQSHRUNv4i16
+ { 866, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #866 = VQSHRUNv8i8
+ { 867, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #867 = VQSUBsv16i8
+ { 868, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #868 = VQSUBsv1i64
+ { 869, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #869 = VQSUBsv2i32
+ { 870, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #870 = VQSUBsv2i64
+ { 871, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #871 = VQSUBsv4i16
+ { 872, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #872 = VQSUBsv4i32
+ { 873, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #873 = VQSUBsv8i16
+ { 874, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #874 = VQSUBsv8i8
+ { 875, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #875 = VQSUBuv16i8
+ { 876, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #876 = VQSUBuv1i64
+ { 877, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #877 = VQSUBuv2i32
+ { 878, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #878 = VQSUBuv2i64
+ { 879, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #879 = VQSUBuv4i16
+ { 880, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #880 = VQSUBuv4i32
+ { 881, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #881 = VQSUBuv8i16
+ { 882, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #882 = VQSUBuv8i8
+ { 883, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #883 = VRADDHNv2i32
+ { 884, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #884 = VRADDHNv4i16
+ { 885, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #885 = VRADDHNv8i8
+ { 886, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #886 = VRECPEd
+ { 887, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #887 = VRECPEfd
+ { 888, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #888 = VRECPEfq
+ { 889, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #889 = VRECPEq
+ { 890, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #890 = VRECPSfd
+ { 891, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #891 = VRECPSfq
+ { 892, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #892 = VREV16d8
+ { 893, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #893 = VREV16q8
+ { 894, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #894 = VREV32d16
+ { 895, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #895 = VREV32d8
+ { 896, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #896 = VREV32q16
+ { 897, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #897 = VREV32q8
+ { 898, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #898 = VREV64d16
+ { 899, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #899 = VREV64d32
+ { 900, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #900 = VREV64d8
+ { 901, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #901 = VREV64df
+ { 902, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #902 = VREV64q16
+ { 903, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #903 = VREV64q32
+ { 904, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #904 = VREV64q8
+ { 905, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #905 = VREV64qf
+ { 906, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #906 = VRHADDsv16i8
+ { 907, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #907 = VRHADDsv2i32
+ { 908, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #908 = VRHADDsv4i16
+ { 909, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #909 = VRHADDsv4i32
+ { 910, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #910 = VRHADDsv8i16
+ { 911, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #911 = VRHADDsv8i8
+ { 912, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #912 = VRHADDuv16i8
+ { 913, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #913 = VRHADDuv2i32
+ { 914, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #914 = VRHADDuv4i16
+ { 915, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #915 = VRHADDuv4i32
+ { 916, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #916 = VRHADDuv8i16
+ { 917, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #917 = VRHADDuv8i8
+ { 918, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #918 = VRSHLsv16i8
+ { 919, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #919 = VRSHLsv1i64
+ { 920, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #920 = VRSHLsv2i32
+ { 921, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #921 = VRSHLsv2i64
+ { 922, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #922 = VRSHLsv4i16
+ { 923, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #923 = VRSHLsv4i32
+ { 924, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #924 = VRSHLsv8i16
+ { 925, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #925 = VRSHLsv8i8
+ { 926, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #926 = VRSHLuv16i8
+ { 927, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #927 = VRSHLuv1i64
+ { 928, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #928 = VRSHLuv2i32
+ { 929, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #929 = VRSHLuv2i64
+ { 930, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #930 = VRSHLuv4i16
+ { 931, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #931 = VRSHLuv4i32
+ { 932, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #932 = VRSHLuv8i16
+ { 933, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #933 = VRSHLuv8i8
+ { 934, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #934 = VRSHRNv2i32
+ { 935, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #935 = VRSHRNv4i16
+ { 936, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #936 = VRSHRNv8i8
+ { 937, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #937 = VRSHRsv16i8
+ { 938, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #938 = VRSHRsv1i64
+ { 939, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #939 = VRSHRsv2i32
+ { 940, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #940 = VRSHRsv2i64
+ { 941, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #941 = VRSHRsv4i16
+ { 942, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #942 = VRSHRsv4i32
+ { 943, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #943 = VRSHRsv8i16
+ { 944, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #944 = VRSHRsv8i8
+ { 945, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #945 = VRSHRuv16i8
+ { 946, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #946 = VRSHRuv1i64
+ { 947, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #947 = VRSHRuv2i32
+ { 948, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #948 = VRSHRuv2i64
+ { 949, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #949 = VRSHRuv4i16
+ { 950, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #950 = VRSHRuv4i32
+ { 951, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #951 = VRSHRuv8i16
+ { 952, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #952 = VRSHRuv8i8
+ { 953, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #953 = VRSQRTEd
+ { 954, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #954 = VRSQRTEfd
+ { 955, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #955 = VRSQRTEfq
+ { 956, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #956 = VRSQRTEq
+ { 957, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #957 = VRSQRTSfd
+ { 958, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #958 = VRSQRTSfq
+ { 959, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #959 = VRSRAsv16i8
+ { 960, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #960 = VRSRAsv1i64
+ { 961, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #961 = VRSRAsv2i32
+ { 962, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #962 = VRSRAsv2i64
+ { 963, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #963 = VRSRAsv4i16
+ { 964, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #964 = VRSRAsv4i32
+ { 965, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #965 = VRSRAsv8i16
+ { 966, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #966 = VRSRAsv8i8
+ { 967, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #967 = VRSRAuv16i8
+ { 968, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #968 = VRSRAuv1i64
+ { 969, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #969 = VRSRAuv2i32
+ { 970, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #970 = VRSRAuv2i64
+ { 971, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #971 = VRSRAuv4i16
+ { 972, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #972 = VRSRAuv4i32
+ { 973, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #973 = VRSRAuv8i16
+ { 974, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #974 = VRSRAuv8i8
+ { 975, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #975 = VRSUBHNv2i32
+ { 976, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #976 = VRSUBHNv4i16
+ { 977, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #977 = VRSUBHNv8i8
+ { 978, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo107 }, // Inst #978 = VSETLNi16
+ { 979, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo107 }, // Inst #979 = VSETLNi32
+ { 980, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo107 }, // Inst #980 = VSETLNi8
+ { 981, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #981 = VSHLLi16
+ { 982, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #982 = VSHLLi32
+ { 983, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #983 = VSHLLi8
+ { 984, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #984 = VSHLLsv2i64
+ { 985, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #985 = VSHLLsv4i32
+ { 986, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #986 = VSHLLsv8i16
+ { 987, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #987 = VSHLLuv2i64
+ { 988, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #988 = VSHLLuv4i32
+ { 989, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #989 = VSHLLuv8i16
+ { 990, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #990 = VSHLiv16i8
+ { 991, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #991 = VSHLiv1i64
+ { 992, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #992 = VSHLiv2i32
+ { 993, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #993 = VSHLiv2i64
+ { 994, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #994 = VSHLiv4i16
+ { 995, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #995 = VSHLiv4i32
+ { 996, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #996 = VSHLiv8i16
+ { 997, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #997 = VSHLiv8i8
+ { 998, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #998 = VSHLsv16i8
+ { 999, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #999 = VSHLsv1i64
+ { 1000, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1000 = VSHLsv2i32
+ { 1001, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1001 = VSHLsv2i64
+ { 1002, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1002 = VSHLsv4i16
+ { 1003, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1003 = VSHLsv4i32
+ { 1004, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1004 = VSHLsv8i16
+ { 1005, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1005 = VSHLsv8i8
+ { 1006, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1006 = VSHLuv16i8
+ { 1007, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1007 = VSHLuv1i64
+ { 1008, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1008 = VSHLuv2i32
+ { 1009, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1009 = VSHLuv2i64
+ { 1010, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1010 = VSHLuv4i16
+ { 1011, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1011 = VSHLuv4i32
+ { 1012, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1012 = VSHLuv8i16
+ { 1013, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1013 = VSHLuv8i8
+ { 1014, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #1014 = VSHRNv2i32
+ { 1015, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #1015 = VSHRNv4i16
+ { 1016, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #1016 = VSHRNv8i8
+ { 1017, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1017 = VSHRsv16i8
+ { 1018, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1018 = VSHRsv1i64
+ { 1019, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1019 = VSHRsv2i32
+ { 1020, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1020 = VSHRsv2i64
+ { 1021, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1021 = VSHRsv4i16
+ { 1022, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1022 = VSHRsv4i32
+ { 1023, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1023 = VSHRsv8i16
+ { 1024, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1024 = VSHRsv8i8
+ { 1025, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1025 = VSHRuv16i8
+ { 1026, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1026 = VSHRuv1i64
+ { 1027, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1027 = VSHRuv2i32
+ { 1028, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1028 = VSHRuv2i64
+ { 1029, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1029 = VSHRuv4i16
+ { 1030, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1030 = VSHRuv4i32
+ { 1031, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1031 = VSHRuv8i16
+ { 1032, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1032 = VSHRuv8i8
+ { 1033, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1033 = VSITOD
+ { 1034, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1034 = VSITOS
+ { 1035, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1035 = VSLIv16i8
+ { 1036, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1036 = VSLIv1i64
+ { 1037, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1037 = VSLIv2i32
+ { 1038, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1038 = VSLIv2i64
+ { 1039, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1039 = VSLIv4i16
+ { 1040, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1040 = VSLIv4i32
+ { 1041, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1041 = VSLIv8i16
+ { 1042, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1042 = VSLIv8i8
+ { 1043, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1043 = VSQRTD
+ { 1044, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1044 = VSQRTS
+ { 1045, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1045 = VSRAsv16i8
+ { 1046, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1046 = VSRAsv1i64
+ { 1047, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1047 = VSRAsv2i32
+ { 1048, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1048 = VSRAsv2i64
+ { 1049, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1049 = VSRAsv4i16
+ { 1050, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1050 = VSRAsv4i32
+ { 1051, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1051 = VSRAsv8i16
+ { 1052, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1052 = VSRAsv8i8
+ { 1053, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1053 = VSRAuv16i8
+ { 1054, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1054 = VSRAuv1i64
+ { 1055, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1055 = VSRAuv2i32
+ { 1056, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1056 = VSRAuv2i64
+ { 1057, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1057 = VSRAuv4i16
+ { 1058, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1058 = VSRAuv4i32
+ { 1059, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1059 = VSRAuv8i16
+ { 1060, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1060 = VSRAuv8i8
+ { 1061, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1061 = VSRIv16i8
+ { 1062, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1062 = VSRIv1i64
+ { 1063, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1063 = VSRIv2i32
+ { 1064, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1064 = VSRIv2i64
+ { 1065, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1065 = VSRIv4i16
+ { 1066, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1066 = VSRIv4i32
+ { 1067, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #1067 = VSRIv8i16
+ { 1068, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1068 = VSRIv8i8
+ { 1069, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1069 = VST1d16
+ { 1070, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1070 = VST1d32
+ { 1071, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1071 = VST1d64
+ { 1072, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1072 = VST1d8
+ { 1073, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1073 = VST1df
+ { 1074, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1074 = VST1q16
+ { 1075, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1075 = VST1q32
+ { 1076, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1076 = VST1q64
+ { 1077, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1077 = VST1q8
+ { 1078, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1078 = VST1qf
+ { 1079, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1079 = VST2LNd16
+ { 1080, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1080 = VST2LNd32
+ { 1081, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1081 = VST2LNd8
+ { 1082, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1082 = VST2LNq16a
+ { 1083, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1083 = VST2LNq16b
+ { 1084, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1084 = VST2LNq32a
+ { 1085, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1085 = VST2LNq32b
+ { 1086, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1086 = VST2d16
+ { 1087, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1087 = VST2d32
+ { 1088, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1088 = VST2d64
+ { 1089, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1089 = VST2d8
+ { 1090, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1090 = VST2q16
+ { 1091, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1091 = VST2q32
+ { 1092, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1092 = VST2q8
+ { 1093, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1093 = VST3LNd16
+ { 1094, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1094 = VST3LNd32
+ { 1095, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1095 = VST3LNd8
+ { 1096, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1096 = VST3LNq16a
+ { 1097, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1097 = VST3LNq16b
+ { 1098, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1098 = VST3LNq32a
+ { 1099, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1099 = VST3LNq32b
+ { 1100, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1100 = VST3d16
+ { 1101, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1101 = VST3d32
+ { 1102, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1102 = VST3d64
+ { 1103, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1103 = VST3d8
+ { 1104, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1104 = VST3q16a
+ { 1105, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1105 = VST3q16b
+ { 1106, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1106 = VST3q32a
+ { 1107, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1107 = VST3q32b
+ { 1108, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1108 = VST3q8a
+ { 1109, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1109 = VST3q8b
+ { 1110, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1110 = VST4LNd16
+ { 1111, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1111 = VST4LNd32
+ { 1112, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1112 = VST4LNd8
+ { 1113, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1113 = VST4LNq16a
+ { 1114, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1114 = VST4LNq16b
+ { 1115, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1115 = VST4LNq32a
+ { 1116, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1116 = VST4LNq32b
+ { 1117, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1117 = VST4d16
+ { 1118, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1118 = VST4d32
+ { 1119, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1119 = VST4d64
+ { 1120, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1120 = VST4d8
+ { 1121, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1121 = VST4q16a
+ { 1122, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1122 = VST4q16b
+ { 1123, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1123 = VST4q32a
+ { 1124, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1124 = VST4q32b
+ { 1125, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1125 = VST4q8a
+ { 1126, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1126 = VST4q8b
+ { 1127, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1127 = VSTMD
+ { 1128, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1128 = VSTMS
+ { 1129, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1129 = VSTRD
+ { 1130, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #1130 = VSTRQ
+ { 1131, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #1131 = VSTRS
+ { 1132, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1132 = VSUBD
+ { 1133, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #1133 = VSUBHNv2i32
+ { 1134, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #1134 = VSUBHNv4i16
+ { 1135, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #1135 = VSUBHNv8i8
+ { 1136, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1136 = VSUBLsv2i64
+ { 1137, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1137 = VSUBLsv4i32
+ { 1138, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1138 = VSUBLsv8i16
+ { 1139, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1139 = VSUBLuv2i64
+ { 1140, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1140 = VSUBLuv4i32
+ { 1141, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #1141 = VSUBLuv8i16
+ { 1142, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #1142 = VSUBS
+ { 1143, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1143 = VSUBWsv2i64
+ { 1144, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1144 = VSUBWsv4i32
+ { 1145, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1145 = VSUBWsv8i16
+ { 1146, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1146 = VSUBWuv2i64
+ { 1147, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1147 = VSUBWuv4i32
+ { 1148, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1148 = VSUBWuv8i16
+ { 1149, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1149 = VSUBfd
+ { 1150, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1150 = VSUBfd_sfp
+ { 1151, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1151 = VSUBfq
+ { 1152, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1152 = VSUBv16i8
+ { 1153, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1153 = VSUBv1i64
+ { 1154, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1154 = VSUBv2i32
+ { 1155, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1155 = VSUBv2i64
+ { 1156, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1156 = VSUBv4i16
+ { 1157, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1157 = VSUBv4i32
+ { 1158, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1158 = VSUBv8i16
+ { 1159, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1159 = VSUBv8i8
+ { 1160, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1160 = VTBL1
+ { 1161, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1161 = VTBL2
+ { 1162, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1162 = VTBL3
+ { 1163, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1163 = VTBL4
+ { 1164, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #1164 = VTBX1
+ { 1165, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1165 = VTBX2
+ { 1166, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1166 = VTBX3
+ { 1167, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1167 = VTBX4
+ { 1168, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1168 = VTOSIZD
+ { 1169, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1169 = VTOSIZS
+ { 1170, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1170 = VTOUIZD
+ { 1171, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1171 = VTOUIZS
+ { 1172, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1172 = VTRNd16
+ { 1173, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1173 = VTRNd32
+ { 1174, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1174 = VTRNd8
+ { 1175, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1175 = VTRNq16
+ { 1176, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1176 = VTRNq32
+ { 1177, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1177 = VTRNq8
+ { 1178, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1178 = VTSTv16i8
+ { 1179, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1179 = VTSTv2i32
+ { 1180, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1180 = VTSTv4i16
+ { 1181, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1181 = VTSTv4i32
+ { 1182, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1182 = VTSTv8i16
+ { 1183, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1183 = VTSTv8i8
+ { 1184, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1184 = VUITOD
+ { 1185, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1185 = VUITOS
+ { 1186, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1186 = VUZPd16
+ { 1187, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1187 = VUZPd32
+ { 1188, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1188 = VUZPd8
+ { 1189, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1189 = VUZPq16
+ { 1190, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1190 = VUZPq32
+ { 1191, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1191 = VUZPq8
+ { 1192, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1192 = VZIPd16
+ { 1193, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1193 = VZIPd32
+ { 1194, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1194 = VZIPd8
+ { 1195, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1195 = VZIPq16
+ { 1196, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1196 = VZIPq32
+ { 1197, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1197 = VZIPq8
+ { 1198, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1198 = t2ADCSri
+ { 1199, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1199 = t2ADCSrr
+ { 1200, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo126 }, // Inst #1200 = t2ADCSrs
+ { 1201, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1201 = t2ADCri
+ { 1202, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1202 = t2ADCrr
+ { 1203, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1203 = t2ADCrs
+ { 1204, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1204 = t2ADDSri
+ { 1205, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1205 = t2ADDSrr
+ { 1206, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1206 = t2ADDSrs
+ { 1207, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1207 = t2ADDrSPi
+ { 1208, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1208 = t2ADDrSPi12
+ { 1209, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1209 = t2ADDrSPs
+ { 1210, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1210 = t2ADDri
+ { 1211, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1211 = t2ADDri12
+ { 1212, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1212 = t2ADDrr
+ { 1213, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1213 = t2ADDrs
+ { 1214, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1214 = t2ANDri
+ { 1215, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1215 = t2ANDrr
+ { 1216, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1216 = t2ANDrs
+ { 1217, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1217 = t2ASRri
+ { 1218, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1218 = t2ASRrr
+ { 1219, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1219 = t2B
+ { 1220, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1220 = t2BFC
+ { 1221, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1221 = t2BICri
+ { 1222, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1222 = t2BICrr
+ { 1223, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1223 = t2BICrs
+ { 1224, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1224 = t2BR_JT
+ { 1225, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1225 = t2Bcc
+ { 1226, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1226 = t2CLZ
+ { 1227, 4, 0, 97, "t2CMNri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1227 = t2CMNri
+ { 1228, 4, 0, 98, "t2CMNrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1228 = t2CMNrr
+ { 1229, 5, 0, 99, "t2CMNrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1229 = t2CMNrs
+ { 1230, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1230 = t2CMNzri
+ { 1231, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1231 = t2CMNzrr
+ { 1232, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1232 = t2CMNzrs
+ { 1233, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1233 = t2CMPri
+ { 1234, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1234 = t2CMPrr
+ { 1235, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1235 = t2CMPrs
+ { 1236, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1236 = t2CMPzri
+ { 1237, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1237 = t2CMPzrr
+ { 1238, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1238 = t2CMPzrs
+ { 1239, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1239 = t2EORri
+ { 1240, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1240 = t2EORrr
+ { 1241, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1241 = t2EORrs
+ { 1242, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1242 = t2IT
+ { 1243, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1243 = t2Int_MemBarrierV7
+ { 1244, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1244 = t2Int_SyncBarrierV7
+ { 1245, 1, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #1245 = t2Int_eh_sjlj_setjmp
+ { 1246, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1246 = t2LDM
+ { 1247, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1247 = t2LDM_RET
+ { 1248, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1248 = t2LDRB_POST
+ { 1249, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1249 = t2LDRB_PRE
+ { 1250, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1250 = t2LDRBi12
+ { 1251, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1251 = t2LDRBi8
+ { 1252, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1252 = t2LDRBpci
+ { 1253, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1253 = t2LDRBs
+ { 1254, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1254 = t2LDRDi8
+ { 1255, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1255 = t2LDRDpci
+ { 1256, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1256 = t2LDREX
+ { 1257, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1257 = t2LDREXB
+ { 1258, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1258 = t2LDREXD
+ { 1259, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1259 = t2LDREXH
+ { 1260, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1260 = t2LDRH_POST
+ { 1261, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1261 = t2LDRH_PRE
+ { 1262, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1262 = t2LDRHi12
+ { 1263, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1263 = t2LDRHi8
+ { 1264, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1264 = t2LDRHpci
+ { 1265, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1265 = t2LDRHs
+ { 1266, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1266 = t2LDRSB_POST
+ { 1267, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1267 = t2LDRSB_PRE
+ { 1268, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1268 = t2LDRSBi12
+ { 1269, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1269 = t2LDRSBi8
+ { 1270, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1270 = t2LDRSBpci
+ { 1271, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1271 = t2LDRSBs
+ { 1272, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1272 = t2LDRSH_POST
+ { 1273, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1273 = t2LDRSH_PRE
+ { 1274, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1274 = t2LDRSHi12
+ { 1275, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1275 = t2LDRSHi8
+ { 1276, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1276 = t2LDRSHpci
+ { 1277, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1277 = t2LDRSHs
+ { 1278, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1278 = t2LDR_POST
+ { 1279, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo128 }, // Inst #1279 = t2LDR_PRE
+ { 1280, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1280 = t2LDRi12
+ { 1281, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1281 = t2LDRi8
+ { 1282, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1282 = t2LDRpci
+ { 1283, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1283 = t2LDRpci_pic
+ { 1284, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1284 = t2LDRs
+ { 1285, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1285 = t2LEApcrel
+ { 1286, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo30 }, // Inst #1286 = t2LEApcrelJT
+ { 1287, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1287 = t2LSLri
+ { 1288, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1288 = t2LSLrr
+ { 1289, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1289 = t2LSRri
+ { 1290, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1290 = t2LSRrr
+ { 1291, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1291 = t2MLA
+ { 1292, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1292 = t2MLS
+ { 1293, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1293 = t2MOVCCasr
+ { 1294, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1294 = t2MOVCCi
+ { 1295, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1295 = t2MOVCClsl
+ { 1296, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1296 = t2MOVCClsr
+ { 1297, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1297 = t2MOVCCr
+ { 1298, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1298 = t2MOVCCror
+ { 1299, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1299 = t2MOVTi16
+ { 1300, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1300 = t2MOVi
+ { 1301, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1301 = t2MOVi16
+ { 1302, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1302 = t2MOVi32imm
+ { 1303, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #1303 = t2MOVr
+ { 1304, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #1304 = t2MOVrx
+ { 1305, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo130 }, // Inst #1305 = t2MOVsra_flag
+ { 1306, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo130 }, // Inst #1306 = t2MOVsrl_flag
+ { 1307, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1307 = t2MUL
+ { 1308, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1308 = t2MVNi
+ { 1309, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1309 = t2MVNr
+ { 1310, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1310 = t2MVNs
+ { 1311, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1311 = t2ORNri
+ { 1312, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1312 = t2ORNrr
+ { 1313, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1313 = t2ORNrs
+ { 1314, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1314 = t2ORRri
+ { 1315, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1315 = t2ORRrr
+ { 1316, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1316 = t2ORRrs
+ { 1317, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1317 = t2PKHBT
+ { 1318, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1318 = t2PKHTB
+ { 1319, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1319 = t2REV
+ { 1320, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1320 = t2REV16
+ { 1321, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1321 = t2REVSH
+ { 1322, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1322 = t2RORri
+ { 1323, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1323 = t2RORrr
+ { 1324, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo131 }, // Inst #1324 = t2RSBSri
+ { 1325, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1325 = t2RSBSrs
+ { 1326, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1326 = t2RSBri
+ { 1327, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1327 = t2RSBrs
+ { 1328, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1328 = t2SBCSri
+ { 1329, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1329 = t2SBCSrr
+ { 1330, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo126 }, // Inst #1330 = t2SBCSrs
+ { 1331, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1331 = t2SBCri
+ { 1332, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1332 = t2SBCrr
+ { 1333, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1333 = t2SBCrs
+ { 1334, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1334 = t2SBFX
+ { 1335, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1335 = t2SMLABB
+ { 1336, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1336 = t2SMLABT
+ { 1337, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1337 = t2SMLAL
+ { 1338, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1338 = t2SMLATB
+ { 1339, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1339 = t2SMLATT
+ { 1340, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1340 = t2SMLAWB
+ { 1341, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1341 = t2SMLAWT
+ { 1342, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1342 = t2SMMLA
+ { 1343, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1343 = t2SMMLS
+ { 1344, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1344 = t2SMMUL
+ { 1345, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1345 = t2SMULBB
+ { 1346, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1346 = t2SMULBT
+ { 1347, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1347 = t2SMULL
+ { 1348, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1348 = t2SMULTB
+ { 1349, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1349 = t2SMULTT
+ { 1350, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1350 = t2SMULWB
+ { 1351, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1351 = t2SMULWT
+ { 1352, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1352 = t2STM
+ { 1353, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1353 = t2STRB_POST
+ { 1354, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1354 = t2STRB_PRE
+ { 1355, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1355 = t2STRBi12
+ { 1356, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1356 = t2STRBi8
+ { 1357, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1357 = t2STRBs
+ { 1358, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1358 = t2STRDi8
+ { 1359, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1359 = t2STREX
+ { 1360, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1360 = t2STREXB
+ { 1361, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1361 = t2STREXD
+ { 1362, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1362 = t2STREXH
+ { 1363, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1363 = t2STRH_POST
+ { 1364, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1364 = t2STRH_PRE
+ { 1365, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1365 = t2STRHi12
+ { 1366, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1366 = t2STRHi8
+ { 1367, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1367 = t2STRHs
+ { 1368, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1368 = t2STR_POST
+ { 1369, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo133 }, // Inst #1369 = t2STR_PRE
+ { 1370, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1370 = t2STRi12
+ { 1371, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1371 = t2STRi8
+ { 1372, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1372 = t2STRs
+ { 1373, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1373 = t2SUBSri
+ { 1374, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1374 = t2SUBSrr
+ { 1375, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1375 = t2SUBSrs
+ { 1376, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1376 = t2SUBrSPi
+ { 1377, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1377 = t2SUBrSPi12
+ { 1378, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1378 = t2SUBrSPi12_
+ { 1379, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1379 = t2SUBrSPi_
+ { 1380, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1380 = t2SUBrSPs
+ { 1381, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo126 }, // Inst #1381 = t2SUBrSPs_
+ { 1382, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1382 = t2SUBri
+ { 1383, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1383 = t2SUBri12
+ { 1384, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1384 = t2SUBrr
+ { 1385, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1385 = t2SUBrs
+ { 1386, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1386 = t2SXTABrr
+ { 1387, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1387 = t2SXTABrr_rot
+ { 1388, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1388 = t2SXTAHrr
+ { 1389, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1389 = t2SXTAHrr_rot
+ { 1390, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1390 = t2SXTBr
+ { 1391, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1391 = t2SXTBr_rot
+ { 1392, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1392 = t2SXTHr
+ { 1393, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1393 = t2SXTHr_rot
+ { 1394, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1394 = t2TBB
+ { 1395, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1395 = t2TBH
+ { 1396, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1396 = t2TEQri
+ { 1397, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1397 = t2TEQrr
+ { 1398, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1398 = t2TEQrs
+ { 1399, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1399 = t2TPsoft
+ { 1400, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1400 = t2TSTri
+ { 1401, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1401 = t2TSTrr
+ { 1402, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1402 = t2TSTrs
+ { 1403, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1403 = t2UBFX
+ { 1404, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1404 = t2UMAAL
+ { 1405, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1405 = t2UMLAL
+ { 1406, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1406 = t2UMULL
+ { 1407, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1407 = t2UXTABrr
+ { 1408, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1408 = t2UXTABrr_rot
+ { 1409, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1409 = t2UXTAHrr
+ { 1410, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1410 = t2UXTAHrr_rot
+ { 1411, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1411 = t2UXTB16r
+ { 1412, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1412 = t2UXTB16r_rot
+ { 1413, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1413 = t2UXTBr
+ { 1414, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1414 = t2UXTBr_rot
+ { 1415, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1415 = t2UXTHr
+ { 1416, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1416 = t2UXTHr_rot
+ { 1417, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo134 }, // Inst #1417 = tADC
+ { 1418, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1418 = tADDhirr
+ { 1419, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1419 = tADDi3
+ { 1420, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1420 = tADDi8
+ { 1421, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1421 = tADDrPCi
+ { 1422, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1422 = tADDrSP
+ { 1423, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1423 = tADDrSPi
+ { 1424, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1424 = tADDrr
+ { 1425, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1425 = tADDspi
+ { 1426, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1426 = tADDspr
+ { 1427, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1427 = tADDspr_
+ { 1428, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1428 = tADJCALLSTACKDOWN
+ { 1429, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo127 }, // Inst #1429 = tADJCALLSTACKUP
+ { 1430, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1430 = tAND
+ { 1431, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo142 }, // Inst #1431 = tANDsp
+ { 1432, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1432 = tASRri
+ { 1433, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1433 = tASRrr
+ { 1434, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1434 = tB
+ { 1435, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1435 = tBIC
+ { 1436, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1436 = tBL
+ { 1437, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1437 = tBLXi
+ { 1438, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1438 = tBLXi_r9
+ { 1439, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1439 = tBLXr
+ { 1440, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1440 = tBLXr_r9
+ { 1441, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1441 = tBLr9
+ { 1442, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1442 = tBRIND
+ { 1443, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1443 = tBR_JTr
+ { 1444, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo144 }, // Inst #1444 = tBX
+ { 1445, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1445 = tBX_RET
+ { 1446, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1446 = tBX_RET_vararg
+ { 1447, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo144 }, // Inst #1447 = tBXr9
+ { 1448, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1448 = tBcc
+ { 1449, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1449 = tBfar
+ { 1450, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1450 = tCBNZ
+ { 1451, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1451 = tCBZ
+ { 1452, 4, 0, 98, "tCMN", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1452 = tCMN
+ { 1453, 4, 0, 98, "tCMNZ", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1453 = tCMNZ
+ { 1454, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1454 = tCMPhir
+ { 1455, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo146 }, // Inst #1455 = tCMPi8
+ { 1456, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1456 = tCMPr
+ { 1457, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1457 = tCMPzhir
+ { 1458, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo146 }, // Inst #1458 = tCMPzi8
+ { 1459, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1459 = tCMPzr
+ { 1460, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1460 = tEOR
+ { 1461, 1, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo16 }, // Inst #1461 = tInt_eh_sjlj_setjmp
+ { 1462, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1462 = tLDM
+ { 1463, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1463 = tLDR
+ { 1464, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1464 = tLDRB
+ { 1465, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1465 = tLDRH
+ { 1466, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1466 = tLDRSB
+ { 1467, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1467 = tLDRSH
+ { 1468, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1468 = tLDRcp
+ { 1469, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1469 = tLDRpci
+ { 1470, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1470 = tLDRpci_pic
+ { 1471, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1471 = tLDRspi
+ { 1472, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1472 = tLEApcrel
+ { 1473, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1473 = tLEApcrelJT
+ { 1474, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1474 = tLSLri
+ { 1475, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1475 = tLSLrr
+ { 1476, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1476 = tLSRri
+ { 1477, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1477 = tLSRrr
+ { 1478, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1478 = tMOVCCi
+ { 1479, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1479 = tMOVCCr
+ { 1480, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo148 }, // Inst #1480 = tMOVCCr_pseudo
+ { 1481, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo151 }, // Inst #1481 = tMOVSr
+ { 1482, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1482 = tMOVgpr2gpr
+ { 1483, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1483 = tMOVgpr2tgpr
+ { 1484, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1484 = tMOVi8
+ { 1485, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1485 = tMOVr
+ { 1486, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1486 = tMOVtgpr2gpr
+ { 1487, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1487 = tMUL
+ { 1488, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1488 = tMVN
+ { 1489, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1489 = tORR
+ { 1490, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1490 = tPICADD
+ { 1491, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo156 }, // Inst #1491 = tPOP
+ { 1492, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1492 = tPOP_RET
+ { 1493, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo156 }, // Inst #1493 = tPUSH
+ { 1494, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1494 = tREV
+ { 1495, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1495 = tREV16
+ { 1496, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1496 = tREVSH
+ { 1497, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo134 }, // Inst #1497 = tROR
+ { 1498, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1498 = tRSB
+ { 1499, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1499 = tRestore
+ { 1500, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo134 }, // Inst #1500 = tSBC
+ { 1501, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1501 = tSTM
+ { 1502, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1502 = tSTR
+ { 1503, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1503 = tSTRB
+ { 1504, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1504 = tSTRH
+ { 1505, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1505 = tSTRspi
+ { 1506, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1506 = tSUBi3
+ { 1507, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1507 = tSUBi8
+ { 1508, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1508 = tSUBrr
+ { 1509, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1509 = tSUBspi
+ { 1510, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1510 = tSUBspi_
+ { 1511, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1511 = tSXTB
+ { 1512, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1512 = tSXTH
+ { 1513, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1513 = tSpill
+ { 1514, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1514 = tTPsoft
+ { 1515, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1515 = tTST
+ { 1516, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1516 = tUXTB
+ { 1517, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1517 = tUXTH
+};
+} // End llvm namespace
diff --git a/libclamav/c++/ARMGenInstrNames.inc b/libclamav/c++/ARMGenInstrNames.inc
new file mode 100644
index 0000000..7da3f63
--- /dev/null
+++ b/libclamav/c++/ARMGenInstrNames.inc
@@ -0,0 +1,1534 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Instruction Enum Values
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace ARM {
+ enum {
+ PHI = 0,
+ INLINEASM = 1,
+ DBG_LABEL = 2,
+ EH_LABEL = 3,
+ GC_LABEL = 4,
+ KILL = 5,
+ EXTRACT_SUBREG = 6,
+ INSERT_SUBREG = 7,
+ IMPLICIT_DEF = 8,
+ SUBREG_TO_REG = 9,
+ COPY_TO_REGCLASS = 10,
+ ADCSSri = 11,
+ ADCSSrr = 12,
+ ADCSSrs = 13,
+ ADCri = 14,
+ ADCrr = 15,
+ ADCrs = 16,
+ ADDSri = 17,
+ ADDSrr = 18,
+ ADDSrs = 19,
+ ADDri = 20,
+ ADDrr = 21,
+ ADDrs = 22,
+ ADJCALLSTACKDOWN = 23,
+ ADJCALLSTACKUP = 24,
+ ANDri = 25,
+ ANDrr = 26,
+ ANDrs = 27,
+ ATOMIC_CMP_SWAP_I16 = 28,
+ ATOMIC_CMP_SWAP_I32 = 29,
+ ATOMIC_CMP_SWAP_I8 = 30,
+ ATOMIC_LOAD_ADD_I16 = 31,
+ ATOMIC_LOAD_ADD_I32 = 32,
+ ATOMIC_LOAD_ADD_I8 = 33,
+ ATOMIC_LOAD_AND_I16 = 34,
+ ATOMIC_LOAD_AND_I32 = 35,
+ ATOMIC_LOAD_AND_I8 = 36,
+ ATOMIC_LOAD_NAND_I16 = 37,
+ ATOMIC_LOAD_NAND_I32 = 38,
+ ATOMIC_LOAD_NAND_I8 = 39,
+ ATOMIC_LOAD_OR_I16 = 40,
+ ATOMIC_LOAD_OR_I32 = 41,
+ ATOMIC_LOAD_OR_I8 = 42,
+ ATOMIC_LOAD_SUB_I16 = 43,
+ ATOMIC_LOAD_SUB_I32 = 44,
+ ATOMIC_LOAD_SUB_I8 = 45,
+ ATOMIC_LOAD_XOR_I16 = 46,
+ ATOMIC_LOAD_XOR_I32 = 47,
+ ATOMIC_LOAD_XOR_I8 = 48,
+ ATOMIC_SWAP_I16 = 49,
+ ATOMIC_SWAP_I32 = 50,
+ ATOMIC_SWAP_I8 = 51,
+ B = 52,
+ BFC = 53,
+ BICri = 54,
+ BICrr = 55,
+ BICrs = 56,
+ BL = 57,
+ BLX = 58,
+ BLXr9 = 59,
+ BL_pred = 60,
+ BLr9 = 61,
+ BLr9_pred = 62,
+ BRIND = 63,
+ BR_JTadd = 64,
+ BR_JTm = 65,
+ BR_JTr = 66,
+ BX = 67,
+ BX_RET = 68,
+ BXr9 = 69,
+ Bcc = 70,
+ CLZ = 71,
+ CMNri = 72,
+ CMNrr = 73,
+ CMNrs = 74,
+ CMNzri = 75,
+ CMNzrr = 76,
+ CMNzrs = 77,
+ CMPri = 78,
+ CMPrr = 79,
+ CMPrs = 80,
+ CMPzri = 81,
+ CMPzrr = 82,
+ CMPzrs = 83,
+ CONSTPOOL_ENTRY = 84,
+ EORri = 85,
+ EORrr = 86,
+ EORrs = 87,
+ FCONSTD = 88,
+ FCONSTS = 89,
+ FMSTAT = 90,
+ Int_MemBarrierV6 = 91,
+ Int_MemBarrierV7 = 92,
+ Int_SyncBarrierV6 = 93,
+ Int_SyncBarrierV7 = 94,
+ Int_eh_sjlj_setjmp = 95,
+ LDM = 96,
+ LDM_RET = 97,
+ LDR = 98,
+ LDRB = 99,
+ LDRB_POST = 100,
+ LDRB_PRE = 101,
+ LDRD = 102,
+ LDREX = 103,
+ LDREXB = 104,
+ LDREXD = 105,
+ LDREXH = 106,
+ LDRH = 107,
+ LDRH_POST = 108,
+ LDRH_PRE = 109,
+ LDRSB = 110,
+ LDRSB_POST = 111,
+ LDRSB_PRE = 112,
+ LDRSH = 113,
+ LDRSH_POST = 114,
+ LDRSH_PRE = 115,
+ LDR_POST = 116,
+ LDR_PRE = 117,
+ LDRcp = 118,
+ LEApcrel = 119,
+ LEApcrelJT = 120,
+ MLA = 121,
+ MLS = 122,
+ MOVCCi = 123,
+ MOVCCr = 124,
+ MOVCCs = 125,
+ MOVTi16 = 126,
+ MOVi = 127,
+ MOVi16 = 128,
+ MOVi2pieces = 129,
+ MOVi32imm = 130,
+ MOVr = 131,
+ MOVrx = 132,
+ MOVs = 133,
+ MOVsra_flag = 134,
+ MOVsrl_flag = 135,
+ MUL = 136,
+ MVNi = 137,
+ MVNr = 138,
+ MVNs = 139,
+ ORRri = 140,
+ ORRrr = 141,
+ ORRrs = 142,
+ PICADD = 143,
+ PICLDR = 144,
+ PICLDRB = 145,
+ PICLDRH = 146,
+ PICLDRSB = 147,
+ PICLDRSH = 148,
+ PICSTR = 149,
+ PICSTRB = 150,
+ PICSTRH = 151,
+ PKHBT = 152,
+ PKHTB = 153,
+ REV = 154,
+ REV16 = 155,
+ REVSH = 156,
+ RSBSri = 157,
+ RSBSrs = 158,
+ RSBri = 159,
+ RSBrs = 160,
+ RSCSri = 161,
+ RSCSrs = 162,
+ RSCri = 163,
+ RSCrs = 164,
+ SBCSSri = 165,
+ SBCSSrr = 166,
+ SBCSSrs = 167,
+ SBCri = 168,
+ SBCrr = 169,
+ SBCrs = 170,
+ SBFX = 171,
+ SMLABB = 172,
+ SMLABT = 173,
+ SMLAL = 174,
+ SMLATB = 175,
+ SMLATT = 176,
+ SMLAWB = 177,
+ SMLAWT = 178,
+ SMMLA = 179,
+ SMMLS = 180,
+ SMMUL = 181,
+ SMULBB = 182,
+ SMULBT = 183,
+ SMULL = 184,
+ SMULTB = 185,
+ SMULTT = 186,
+ SMULWB = 187,
+ SMULWT = 188,
+ STM = 189,
+ STR = 190,
+ STRB = 191,
+ STRB_POST = 192,
+ STRB_PRE = 193,
+ STRD = 194,
+ STREX = 195,
+ STREXB = 196,
+ STREXD = 197,
+ STREXH = 198,
+ STRH = 199,
+ STRH_POST = 200,
+ STRH_PRE = 201,
+ STR_POST = 202,
+ STR_PRE = 203,
+ SUBSri = 204,
+ SUBSrr = 205,
+ SUBSrs = 206,
+ SUBri = 207,
+ SUBrr = 208,
+ SUBrs = 209,
+ SXTABrr = 210,
+ SXTABrr_rot = 211,
+ SXTAHrr = 212,
+ SXTAHrr_rot = 213,
+ SXTBr = 214,
+ SXTBr_rot = 215,
+ SXTHr = 216,
+ SXTHr_rot = 217,
+ TEQri = 218,
+ TEQrr = 219,
+ TEQrs = 220,
+ TPsoft = 221,
+ TSTri = 222,
+ TSTrr = 223,
+ TSTrs = 224,
+ UBFX = 225,
+ UMAAL = 226,
+ UMLAL = 227,
+ UMULL = 228,
+ UXTABrr = 229,
+ UXTABrr_rot = 230,
+ UXTAHrr = 231,
+ UXTAHrr_rot = 232,
+ UXTB16r = 233,
+ UXTB16r_rot = 234,
+ UXTBr = 235,
+ UXTBr_rot = 236,
+ UXTHr = 237,
+ UXTHr_rot = 238,
+ VABALsv2i64 = 239,
+ VABALsv4i32 = 240,
+ VABALsv8i16 = 241,
+ VABALuv2i64 = 242,
+ VABALuv4i32 = 243,
+ VABALuv8i16 = 244,
+ VABAsv16i8 = 245,
+ VABAsv2i32 = 246,
+ VABAsv4i16 = 247,
+ VABAsv4i32 = 248,
+ VABAsv8i16 = 249,
+ VABAsv8i8 = 250,
+ VABAuv16i8 = 251,
+ VABAuv2i32 = 252,
+ VABAuv4i16 = 253,
+ VABAuv4i32 = 254,
+ VABAuv8i16 = 255,
+ VABAuv8i8 = 256,
+ VABDLsv2i64 = 257,
+ VABDLsv4i32 = 258,
+ VABDLsv8i16 = 259,
+ VABDLuv2i64 = 260,
+ VABDLuv4i32 = 261,
+ VABDLuv8i16 = 262,
+ VABDfd = 263,
+ VABDfq = 264,
+ VABDsv16i8 = 265,
+ VABDsv2i32 = 266,
+ VABDsv4i16 = 267,
+ VABDsv4i32 = 268,
+ VABDsv8i16 = 269,
+ VABDsv8i8 = 270,
+ VABDuv16i8 = 271,
+ VABDuv2i32 = 272,
+ VABDuv4i16 = 273,
+ VABDuv4i32 = 274,
+ VABDuv8i16 = 275,
+ VABDuv8i8 = 276,
+ VABSD = 277,
+ VABSS = 278,
+ VABSfd = 279,
+ VABSfd_sfp = 280,
+ VABSfq = 281,
+ VABSv16i8 = 282,
+ VABSv2i32 = 283,
+ VABSv4i16 = 284,
+ VABSv4i32 = 285,
+ VABSv8i16 = 286,
+ VABSv8i8 = 287,
+ VACGEd = 288,
+ VACGEq = 289,
+ VACGTd = 290,
+ VACGTq = 291,
+ VADDD = 292,
+ VADDHNv2i32 = 293,
+ VADDHNv4i16 = 294,
+ VADDHNv8i8 = 295,
+ VADDLsv2i64 = 296,
+ VADDLsv4i32 = 297,
+ VADDLsv8i16 = 298,
+ VADDLuv2i64 = 299,
+ VADDLuv4i32 = 300,
+ VADDLuv8i16 = 301,
+ VADDS = 302,
+ VADDWsv2i64 = 303,
+ VADDWsv4i32 = 304,
+ VADDWsv8i16 = 305,
+ VADDWuv2i64 = 306,
+ VADDWuv4i32 = 307,
+ VADDWuv8i16 = 308,
+ VADDfd = 309,
+ VADDfd_sfp = 310,
+ VADDfq = 311,
+ VADDv16i8 = 312,
+ VADDv1i64 = 313,
+ VADDv2i32 = 314,
+ VADDv2i64 = 315,
+ VADDv4i16 = 316,
+ VADDv4i32 = 317,
+ VADDv8i16 = 318,
+ VADDv8i8 = 319,
+ VANDd = 320,
+ VANDq = 321,
+ VBICd = 322,
+ VBICq = 323,
+ VBSLd = 324,
+ VBSLq = 325,
+ VCEQfd = 326,
+ VCEQfq = 327,
+ VCEQv16i8 = 328,
+ VCEQv2i32 = 329,
+ VCEQv4i16 = 330,
+ VCEQv4i32 = 331,
+ VCEQv8i16 = 332,
+ VCEQv8i8 = 333,
+ VCGEfd = 334,
+ VCGEfq = 335,
+ VCGEsv16i8 = 336,
+ VCGEsv2i32 = 337,
+ VCGEsv4i16 = 338,
+ VCGEsv4i32 = 339,
+ VCGEsv8i16 = 340,
+ VCGEsv8i8 = 341,
+ VCGEuv16i8 = 342,
+ VCGEuv2i32 = 343,
+ VCGEuv4i16 = 344,
+ VCGEuv4i32 = 345,
+ VCGEuv8i16 = 346,
+ VCGEuv8i8 = 347,
+ VCGTfd = 348,
+ VCGTfq = 349,
+ VCGTsv16i8 = 350,
+ VCGTsv2i32 = 351,
+ VCGTsv4i16 = 352,
+ VCGTsv4i32 = 353,
+ VCGTsv8i16 = 354,
+ VCGTsv8i8 = 355,
+ VCGTuv16i8 = 356,
+ VCGTuv2i32 = 357,
+ VCGTuv4i16 = 358,
+ VCGTuv4i32 = 359,
+ VCGTuv8i16 = 360,
+ VCGTuv8i8 = 361,
+ VCLSv16i8 = 362,
+ VCLSv2i32 = 363,
+ VCLSv4i16 = 364,
+ VCLSv4i32 = 365,
+ VCLSv8i16 = 366,
+ VCLSv8i8 = 367,
+ VCLZv16i8 = 368,
+ VCLZv2i32 = 369,
+ VCLZv4i16 = 370,
+ VCLZv4i32 = 371,
+ VCLZv8i16 = 372,
+ VCLZv8i8 = 373,
+ VCMPED = 374,
+ VCMPES = 375,
+ VCMPEZD = 376,
+ VCMPEZS = 377,
+ VCNTd = 378,
+ VCNTq = 379,
+ VCVTDS = 380,
+ VCVTSD = 381,
+ VCVTf2sd = 382,
+ VCVTf2sd_sfp = 383,
+ VCVTf2sq = 384,
+ VCVTf2ud = 385,
+ VCVTf2ud_sfp = 386,
+ VCVTf2uq = 387,
+ VCVTf2xsd = 388,
+ VCVTf2xsq = 389,
+ VCVTf2xud = 390,
+ VCVTf2xuq = 391,
+ VCVTs2fd = 392,
+ VCVTs2fd_sfp = 393,
+ VCVTs2fq = 394,
+ VCVTu2fd = 395,
+ VCVTu2fd_sfp = 396,
+ VCVTu2fq = 397,
+ VCVTxs2fd = 398,
+ VCVTxs2fq = 399,
+ VCVTxu2fd = 400,
+ VCVTxu2fq = 401,
+ VDIVD = 402,
+ VDIVS = 403,
+ VDUP16d = 404,
+ VDUP16q = 405,
+ VDUP32d = 406,
+ VDUP32q = 407,
+ VDUP8d = 408,
+ VDUP8q = 409,
+ VDUPLN16d = 410,
+ VDUPLN16q = 411,
+ VDUPLN32d = 412,
+ VDUPLN32q = 413,
+ VDUPLN8d = 414,
+ VDUPLN8q = 415,
+ VDUPLNfd = 416,
+ VDUPLNfq = 417,
+ VDUPfd = 418,
+ VDUPfdf = 419,
+ VDUPfq = 420,
+ VDUPfqf = 421,
+ VEORd = 422,
+ VEORq = 423,
+ VEXTd16 = 424,
+ VEXTd32 = 425,
+ VEXTd8 = 426,
+ VEXTdf = 427,
+ VEXTq16 = 428,
+ VEXTq32 = 429,
+ VEXTq8 = 430,
+ VEXTqf = 431,
+ VGETLNi32 = 432,
+ VGETLNs16 = 433,
+ VGETLNs8 = 434,
+ VGETLNu16 = 435,
+ VGETLNu8 = 436,
+ VHADDsv16i8 = 437,
+ VHADDsv2i32 = 438,
+ VHADDsv4i16 = 439,
+ VHADDsv4i32 = 440,
+ VHADDsv8i16 = 441,
+ VHADDsv8i8 = 442,
+ VHADDuv16i8 = 443,
+ VHADDuv2i32 = 444,
+ VHADDuv4i16 = 445,
+ VHADDuv4i32 = 446,
+ VHADDuv8i16 = 447,
+ VHADDuv8i8 = 448,
+ VHSUBsv16i8 = 449,
+ VHSUBsv2i32 = 450,
+ VHSUBsv4i16 = 451,
+ VHSUBsv4i32 = 452,
+ VHSUBsv8i16 = 453,
+ VHSUBsv8i8 = 454,
+ VHSUBuv16i8 = 455,
+ VHSUBuv2i32 = 456,
+ VHSUBuv4i16 = 457,
+ VHSUBuv4i32 = 458,
+ VHSUBuv8i16 = 459,
+ VHSUBuv8i8 = 460,
+ VLD1d16 = 461,
+ VLD1d32 = 462,
+ VLD1d64 = 463,
+ VLD1d8 = 464,
+ VLD1df = 465,
+ VLD1q16 = 466,
+ VLD1q32 = 467,
+ VLD1q64 = 468,
+ VLD1q8 = 469,
+ VLD1qf = 470,
+ VLD2LNd16 = 471,
+ VLD2LNd32 = 472,
+ VLD2LNd8 = 473,
+ VLD2LNq16a = 474,
+ VLD2LNq16b = 475,
+ VLD2LNq32a = 476,
+ VLD2LNq32b = 477,
+ VLD2d16 = 478,
+ VLD2d32 = 479,
+ VLD2d64 = 480,
+ VLD2d8 = 481,
+ VLD2q16 = 482,
+ VLD2q32 = 483,
+ VLD2q8 = 484,
+ VLD3LNd16 = 485,
+ VLD3LNd32 = 486,
+ VLD3LNd8 = 487,
+ VLD3LNq16a = 488,
+ VLD3LNq16b = 489,
+ VLD3LNq32a = 490,
+ VLD3LNq32b = 491,
+ VLD3d16 = 492,
+ VLD3d32 = 493,
+ VLD3d64 = 494,
+ VLD3d8 = 495,
+ VLD3q16a = 496,
+ VLD3q16b = 497,
+ VLD3q32a = 498,
+ VLD3q32b = 499,
+ VLD3q8a = 500,
+ VLD3q8b = 501,
+ VLD4LNd16 = 502,
+ VLD4LNd32 = 503,
+ VLD4LNd8 = 504,
+ VLD4LNq16a = 505,
+ VLD4LNq16b = 506,
+ VLD4LNq32a = 507,
+ VLD4LNq32b = 508,
+ VLD4d16 = 509,
+ VLD4d32 = 510,
+ VLD4d64 = 511,
+ VLD4d8 = 512,
+ VLD4q16a = 513,
+ VLD4q16b = 514,
+ VLD4q32a = 515,
+ VLD4q32b = 516,
+ VLD4q8a = 517,
+ VLD4q8b = 518,
+ VLDMD = 519,
+ VLDMS = 520,
+ VLDRD = 521,
+ VLDRQ = 522,
+ VLDRS = 523,
+ VMAXfd = 524,
+ VMAXfq = 525,
+ VMAXsv16i8 = 526,
+ VMAXsv2i32 = 527,
+ VMAXsv4i16 = 528,
+ VMAXsv4i32 = 529,
+ VMAXsv8i16 = 530,
+ VMAXsv8i8 = 531,
+ VMAXuv16i8 = 532,
+ VMAXuv2i32 = 533,
+ VMAXuv4i16 = 534,
+ VMAXuv4i32 = 535,
+ VMAXuv8i16 = 536,
+ VMAXuv8i8 = 537,
+ VMINfd = 538,
+ VMINfq = 539,
+ VMINsv16i8 = 540,
+ VMINsv2i32 = 541,
+ VMINsv4i16 = 542,
+ VMINsv4i32 = 543,
+ VMINsv8i16 = 544,
+ VMINsv8i8 = 545,
+ VMINuv16i8 = 546,
+ VMINuv2i32 = 547,
+ VMINuv4i16 = 548,
+ VMINuv4i32 = 549,
+ VMINuv8i16 = 550,
+ VMINuv8i8 = 551,
+ VMLAD = 552,
+ VMLALslsv2i32 = 553,
+ VMLALslsv4i16 = 554,
+ VMLALsluv2i32 = 555,
+ VMLALsluv4i16 = 556,
+ VMLALsv2i64 = 557,
+ VMLALsv4i32 = 558,
+ VMLALsv8i16 = 559,
+ VMLALuv2i64 = 560,
+ VMLALuv4i32 = 561,
+ VMLALuv8i16 = 562,
+ VMLAS = 563,
+ VMLAfd = 564,
+ VMLAfq = 565,
+ VMLAslfd = 566,
+ VMLAslfq = 567,
+ VMLAslv2i32 = 568,
+ VMLAslv4i16 = 569,
+ VMLAslv4i32 = 570,
+ VMLAslv8i16 = 571,
+ VMLAv16i8 = 572,
+ VMLAv2i32 = 573,
+ VMLAv4i16 = 574,
+ VMLAv4i32 = 575,
+ VMLAv8i16 = 576,
+ VMLAv8i8 = 577,
+ VMLSD = 578,
+ VMLSLslsv2i32 = 579,
+ VMLSLslsv4i16 = 580,
+ VMLSLsluv2i32 = 581,
+ VMLSLsluv4i16 = 582,
+ VMLSLsv2i64 = 583,
+ VMLSLsv4i32 = 584,
+ VMLSLsv8i16 = 585,
+ VMLSLuv2i64 = 586,
+ VMLSLuv4i32 = 587,
+ VMLSLuv8i16 = 588,
+ VMLSS = 589,
+ VMLSfd = 590,
+ VMLSfq = 591,
+ VMLSslfd = 592,
+ VMLSslfq = 593,
+ VMLSslv2i32 = 594,
+ VMLSslv4i16 = 595,
+ VMLSslv4i32 = 596,
+ VMLSslv8i16 = 597,
+ VMLSv16i8 = 598,
+ VMLSv2i32 = 599,
+ VMLSv4i16 = 600,
+ VMLSv4i32 = 601,
+ VMLSv8i16 = 602,
+ VMLSv8i8 = 603,
+ VMOVD = 604,
+ VMOVDRR = 605,
+ VMOVDcc = 606,
+ VMOVDneon = 607,
+ VMOVLsv2i64 = 608,
+ VMOVLsv4i32 = 609,
+ VMOVLsv8i16 = 610,
+ VMOVLuv2i64 = 611,
+ VMOVLuv4i32 = 612,
+ VMOVLuv8i16 = 613,
+ VMOVNv2i32 = 614,
+ VMOVNv4i16 = 615,
+ VMOVNv8i8 = 616,
+ VMOVQ = 617,
+ VMOVRRD = 618,
+ VMOVRS = 619,
+ VMOVS = 620,
+ VMOVSR = 621,
+ VMOVScc = 622,
+ VMOVv16i8 = 623,
+ VMOVv1i64 = 624,
+ VMOVv2i32 = 625,
+ VMOVv2i64 = 626,
+ VMOVv4i16 = 627,
+ VMOVv4i32 = 628,
+ VMOVv8i16 = 629,
+ VMOVv8i8 = 630,
+ VMULD = 631,
+ VMULLp = 632,
+ VMULLslsv2i32 = 633,
+ VMULLslsv4i16 = 634,
+ VMULLsluv2i32 = 635,
+ VMULLsluv4i16 = 636,
+ VMULLsv2i64 = 637,
+ VMULLsv4i32 = 638,
+ VMULLsv8i16 = 639,
+ VMULLuv2i64 = 640,
+ VMULLuv4i32 = 641,
+ VMULLuv8i16 = 642,
+ VMULS = 643,
+ VMULfd = 644,
+ VMULfd_sfp = 645,
+ VMULfq = 646,
+ VMULpd = 647,
+ VMULpq = 648,
+ VMULslfd = 649,
+ VMULslfq = 650,
+ VMULslv2i32 = 651,
+ VMULslv4i16 = 652,
+ VMULslv4i32 = 653,
+ VMULslv8i16 = 654,
+ VMULv16i8 = 655,
+ VMULv2i32 = 656,
+ VMULv4i16 = 657,
+ VMULv4i32 = 658,
+ VMULv8i16 = 659,
+ VMULv8i8 = 660,
+ VMVNd = 661,
+ VMVNq = 662,
+ VNEGD = 663,
+ VNEGDcc = 664,
+ VNEGS = 665,
+ VNEGScc = 666,
+ VNEGf32d = 667,
+ VNEGf32d_sfp = 668,
+ VNEGf32q = 669,
+ VNEGs16d = 670,
+ VNEGs16q = 671,
+ VNEGs32d = 672,
+ VNEGs32q = 673,
+ VNEGs8d = 674,
+ VNEGs8q = 675,
+ VNMLAD = 676,
+ VNMLAS = 677,
+ VNMLSD = 678,
+ VNMLSS = 679,
+ VNMULD = 680,
+ VNMULS = 681,
+ VORNd = 682,
+ VORNq = 683,
+ VORRd = 684,
+ VORRq = 685,
+ VPADALsv16i8 = 686,
+ VPADALsv2i32 = 687,
+ VPADALsv4i16 = 688,
+ VPADALsv4i32 = 689,
+ VPADALsv8i16 = 690,
+ VPADALsv8i8 = 691,
+ VPADALuv16i8 = 692,
+ VPADALuv2i32 = 693,
+ VPADALuv4i16 = 694,
+ VPADALuv4i32 = 695,
+ VPADALuv8i16 = 696,
+ VPADALuv8i8 = 697,
+ VPADDLsv16i8 = 698,
+ VPADDLsv2i32 = 699,
+ VPADDLsv4i16 = 700,
+ VPADDLsv4i32 = 701,
+ VPADDLsv8i16 = 702,
+ VPADDLsv8i8 = 703,
+ VPADDLuv16i8 = 704,
+ VPADDLuv2i32 = 705,
+ VPADDLuv4i16 = 706,
+ VPADDLuv4i32 = 707,
+ VPADDLuv8i16 = 708,
+ VPADDLuv8i8 = 709,
+ VPADDf = 710,
+ VPADDi16 = 711,
+ VPADDi32 = 712,
+ VPADDi8 = 713,
+ VPMAXf = 714,
+ VPMAXs16 = 715,
+ VPMAXs32 = 716,
+ VPMAXs8 = 717,
+ VPMAXu16 = 718,
+ VPMAXu32 = 719,
+ VPMAXu8 = 720,
+ VPMINf = 721,
+ VPMINs16 = 722,
+ VPMINs32 = 723,
+ VPMINs8 = 724,
+ VPMINu16 = 725,
+ VPMINu32 = 726,
+ VPMINu8 = 727,
+ VQABSv16i8 = 728,
+ VQABSv2i32 = 729,
+ VQABSv4i16 = 730,
+ VQABSv4i32 = 731,
+ VQABSv8i16 = 732,
+ VQABSv8i8 = 733,
+ VQADDsv16i8 = 734,
+ VQADDsv1i64 = 735,
+ VQADDsv2i32 = 736,
+ VQADDsv2i64 = 737,
+ VQADDsv4i16 = 738,
+ VQADDsv4i32 = 739,
+ VQADDsv8i16 = 740,
+ VQADDsv8i8 = 741,
+ VQADDuv16i8 = 742,
+ VQADDuv1i64 = 743,
+ VQADDuv2i32 = 744,
+ VQADDuv2i64 = 745,
+ VQADDuv4i16 = 746,
+ VQADDuv4i32 = 747,
+ VQADDuv8i16 = 748,
+ VQADDuv8i8 = 749,
+ VQDMLALslv2i32 = 750,
+ VQDMLALslv4i16 = 751,
+ VQDMLALv2i64 = 752,
+ VQDMLALv4i32 = 753,
+ VQDMLSLslv2i32 = 754,
+ VQDMLSLslv4i16 = 755,
+ VQDMLSLv2i64 = 756,
+ VQDMLSLv4i32 = 757,
+ VQDMULHslv2i32 = 758,
+ VQDMULHslv4i16 = 759,
+ VQDMULHslv4i32 = 760,
+ VQDMULHslv8i16 = 761,
+ VQDMULHv2i32 = 762,
+ VQDMULHv4i16 = 763,
+ VQDMULHv4i32 = 764,
+ VQDMULHv8i16 = 765,
+ VQDMULLslv2i32 = 766,
+ VQDMULLslv4i16 = 767,
+ VQDMULLv2i64 = 768,
+ VQDMULLv4i32 = 769,
+ VQMOVNsuv2i32 = 770,
+ VQMOVNsuv4i16 = 771,
+ VQMOVNsuv8i8 = 772,
+ VQMOVNsv2i32 = 773,
+ VQMOVNsv4i16 = 774,
+ VQMOVNsv8i8 = 775,
+ VQMOVNuv2i32 = 776,
+ VQMOVNuv4i16 = 777,
+ VQMOVNuv8i8 = 778,
+ VQNEGv16i8 = 779,
+ VQNEGv2i32 = 780,
+ VQNEGv4i16 = 781,
+ VQNEGv4i32 = 782,
+ VQNEGv8i16 = 783,
+ VQNEGv8i8 = 784,
+ VQRDMULHslv2i32 = 785,
+ VQRDMULHslv4i16 = 786,
+ VQRDMULHslv4i32 = 787,
+ VQRDMULHslv8i16 = 788,
+ VQRDMULHv2i32 = 789,
+ VQRDMULHv4i16 = 790,
+ VQRDMULHv4i32 = 791,
+ VQRDMULHv8i16 = 792,
+ VQRSHLsv16i8 = 793,
+ VQRSHLsv1i64 = 794,
+ VQRSHLsv2i32 = 795,
+ VQRSHLsv2i64 = 796,
+ VQRSHLsv4i16 = 797,
+ VQRSHLsv4i32 = 798,
+ VQRSHLsv8i16 = 799,
+ VQRSHLsv8i8 = 800,
+ VQRSHLuv16i8 = 801,
+ VQRSHLuv1i64 = 802,
+ VQRSHLuv2i32 = 803,
+ VQRSHLuv2i64 = 804,
+ VQRSHLuv4i16 = 805,
+ VQRSHLuv4i32 = 806,
+ VQRSHLuv8i16 = 807,
+ VQRSHLuv8i8 = 808,
+ VQRSHRNsv2i32 = 809,
+ VQRSHRNsv4i16 = 810,
+ VQRSHRNsv8i8 = 811,
+ VQRSHRNuv2i32 = 812,
+ VQRSHRNuv4i16 = 813,
+ VQRSHRNuv8i8 = 814,
+ VQRSHRUNv2i32 = 815,
+ VQRSHRUNv4i16 = 816,
+ VQRSHRUNv8i8 = 817,
+ VQSHLsiv16i8 = 818,
+ VQSHLsiv1i64 = 819,
+ VQSHLsiv2i32 = 820,
+ VQSHLsiv2i64 = 821,
+ VQSHLsiv4i16 = 822,
+ VQSHLsiv4i32 = 823,
+ VQSHLsiv8i16 = 824,
+ VQSHLsiv8i8 = 825,
+ VQSHLsuv16i8 = 826,
+ VQSHLsuv1i64 = 827,
+ VQSHLsuv2i32 = 828,
+ VQSHLsuv2i64 = 829,
+ VQSHLsuv4i16 = 830,
+ VQSHLsuv4i32 = 831,
+ VQSHLsuv8i16 = 832,
+ VQSHLsuv8i8 = 833,
+ VQSHLsv16i8 = 834,
+ VQSHLsv1i64 = 835,
+ VQSHLsv2i32 = 836,
+ VQSHLsv2i64 = 837,
+ VQSHLsv4i16 = 838,
+ VQSHLsv4i32 = 839,
+ VQSHLsv8i16 = 840,
+ VQSHLsv8i8 = 841,
+ VQSHLuiv16i8 = 842,
+ VQSHLuiv1i64 = 843,
+ VQSHLuiv2i32 = 844,
+ VQSHLuiv2i64 = 845,
+ VQSHLuiv4i16 = 846,
+ VQSHLuiv4i32 = 847,
+ VQSHLuiv8i16 = 848,
+ VQSHLuiv8i8 = 849,
+ VQSHLuv16i8 = 850,
+ VQSHLuv1i64 = 851,
+ VQSHLuv2i32 = 852,
+ VQSHLuv2i64 = 853,
+ VQSHLuv4i16 = 854,
+ VQSHLuv4i32 = 855,
+ VQSHLuv8i16 = 856,
+ VQSHLuv8i8 = 857,
+ VQSHRNsv2i32 = 858,
+ VQSHRNsv4i16 = 859,
+ VQSHRNsv8i8 = 860,
+ VQSHRNuv2i32 = 861,
+ VQSHRNuv4i16 = 862,
+ VQSHRNuv8i8 = 863,
+ VQSHRUNv2i32 = 864,
+ VQSHRUNv4i16 = 865,
+ VQSHRUNv8i8 = 866,
+ VQSUBsv16i8 = 867,
+ VQSUBsv1i64 = 868,
+ VQSUBsv2i32 = 869,
+ VQSUBsv2i64 = 870,
+ VQSUBsv4i16 = 871,
+ VQSUBsv4i32 = 872,
+ VQSUBsv8i16 = 873,
+ VQSUBsv8i8 = 874,
+ VQSUBuv16i8 = 875,
+ VQSUBuv1i64 = 876,
+ VQSUBuv2i32 = 877,
+ VQSUBuv2i64 = 878,
+ VQSUBuv4i16 = 879,
+ VQSUBuv4i32 = 880,
+ VQSUBuv8i16 = 881,
+ VQSUBuv8i8 = 882,
+ VRADDHNv2i32 = 883,
+ VRADDHNv4i16 = 884,
+ VRADDHNv8i8 = 885,
+ VRECPEd = 886,
+ VRECPEfd = 887,
+ VRECPEfq = 888,
+ VRECPEq = 889,
+ VRECPSfd = 890,
+ VRECPSfq = 891,
+ VREV16d8 = 892,
+ VREV16q8 = 893,
+ VREV32d16 = 894,
+ VREV32d8 = 895,
+ VREV32q16 = 896,
+ VREV32q8 = 897,
+ VREV64d16 = 898,
+ VREV64d32 = 899,
+ VREV64d8 = 900,
+ VREV64df = 901,
+ VREV64q16 = 902,
+ VREV64q32 = 903,
+ VREV64q8 = 904,
+ VREV64qf = 905,
+ VRHADDsv16i8 = 906,
+ VRHADDsv2i32 = 907,
+ VRHADDsv4i16 = 908,
+ VRHADDsv4i32 = 909,
+ VRHADDsv8i16 = 910,
+ VRHADDsv8i8 = 911,
+ VRHADDuv16i8 = 912,
+ VRHADDuv2i32 = 913,
+ VRHADDuv4i16 = 914,
+ VRHADDuv4i32 = 915,
+ VRHADDuv8i16 = 916,
+ VRHADDuv8i8 = 917,
+ VRSHLsv16i8 = 918,
+ VRSHLsv1i64 = 919,
+ VRSHLsv2i32 = 920,
+ VRSHLsv2i64 = 921,
+ VRSHLsv4i16 = 922,
+ VRSHLsv4i32 = 923,
+ VRSHLsv8i16 = 924,
+ VRSHLsv8i8 = 925,
+ VRSHLuv16i8 = 926,
+ VRSHLuv1i64 = 927,
+ VRSHLuv2i32 = 928,
+ VRSHLuv2i64 = 929,
+ VRSHLuv4i16 = 930,
+ VRSHLuv4i32 = 931,
+ VRSHLuv8i16 = 932,
+ VRSHLuv8i8 = 933,
+ VRSHRNv2i32 = 934,
+ VRSHRNv4i16 = 935,
+ VRSHRNv8i8 = 936,
+ VRSHRsv16i8 = 937,
+ VRSHRsv1i64 = 938,
+ VRSHRsv2i32 = 939,
+ VRSHRsv2i64 = 940,
+ VRSHRsv4i16 = 941,
+ VRSHRsv4i32 = 942,
+ VRSHRsv8i16 = 943,
+ VRSHRsv8i8 = 944,
+ VRSHRuv16i8 = 945,
+ VRSHRuv1i64 = 946,
+ VRSHRuv2i32 = 947,
+ VRSHRuv2i64 = 948,
+ VRSHRuv4i16 = 949,
+ VRSHRuv4i32 = 950,
+ VRSHRuv8i16 = 951,
+ VRSHRuv8i8 = 952,
+ VRSQRTEd = 953,
+ VRSQRTEfd = 954,
+ VRSQRTEfq = 955,
+ VRSQRTEq = 956,
+ VRSQRTSfd = 957,
+ VRSQRTSfq = 958,
+ VRSRAsv16i8 = 959,
+ VRSRAsv1i64 = 960,
+ VRSRAsv2i32 = 961,
+ VRSRAsv2i64 = 962,
+ VRSRAsv4i16 = 963,
+ VRSRAsv4i32 = 964,
+ VRSRAsv8i16 = 965,
+ VRSRAsv8i8 = 966,
+ VRSRAuv16i8 = 967,
+ VRSRAuv1i64 = 968,
+ VRSRAuv2i32 = 969,
+ VRSRAuv2i64 = 970,
+ VRSRAuv4i16 = 971,
+ VRSRAuv4i32 = 972,
+ VRSRAuv8i16 = 973,
+ VRSRAuv8i8 = 974,
+ VRSUBHNv2i32 = 975,
+ VRSUBHNv4i16 = 976,
+ VRSUBHNv8i8 = 977,
+ VSETLNi16 = 978,
+ VSETLNi32 = 979,
+ VSETLNi8 = 980,
+ VSHLLi16 = 981,
+ VSHLLi32 = 982,
+ VSHLLi8 = 983,
+ VSHLLsv2i64 = 984,
+ VSHLLsv4i32 = 985,
+ VSHLLsv8i16 = 986,
+ VSHLLuv2i64 = 987,
+ VSHLLuv4i32 = 988,
+ VSHLLuv8i16 = 989,
+ VSHLiv16i8 = 990,
+ VSHLiv1i64 = 991,
+ VSHLiv2i32 = 992,
+ VSHLiv2i64 = 993,
+ VSHLiv4i16 = 994,
+ VSHLiv4i32 = 995,
+ VSHLiv8i16 = 996,
+ VSHLiv8i8 = 997,
+ VSHLsv16i8 = 998,
+ VSHLsv1i64 = 999,
+ VSHLsv2i32 = 1000,
+ VSHLsv2i64 = 1001,
+ VSHLsv4i16 = 1002,
+ VSHLsv4i32 = 1003,
+ VSHLsv8i16 = 1004,
+ VSHLsv8i8 = 1005,
+ VSHLuv16i8 = 1006,
+ VSHLuv1i64 = 1007,
+ VSHLuv2i32 = 1008,
+ VSHLuv2i64 = 1009,
+ VSHLuv4i16 = 1010,
+ VSHLuv4i32 = 1011,
+ VSHLuv8i16 = 1012,
+ VSHLuv8i8 = 1013,
+ VSHRNv2i32 = 1014,
+ VSHRNv4i16 = 1015,
+ VSHRNv8i8 = 1016,
+ VSHRsv16i8 = 1017,
+ VSHRsv1i64 = 1018,
+ VSHRsv2i32 = 1019,
+ VSHRsv2i64 = 1020,
+ VSHRsv4i16 = 1021,
+ VSHRsv4i32 = 1022,
+ VSHRsv8i16 = 1023,
+ VSHRsv8i8 = 1024,
+ VSHRuv16i8 = 1025,
+ VSHRuv1i64 = 1026,
+ VSHRuv2i32 = 1027,
+ VSHRuv2i64 = 1028,
+ VSHRuv4i16 = 1029,
+ VSHRuv4i32 = 1030,
+ VSHRuv8i16 = 1031,
+ VSHRuv8i8 = 1032,
+ VSITOD = 1033,
+ VSITOS = 1034,
+ VSLIv16i8 = 1035,
+ VSLIv1i64 = 1036,
+ VSLIv2i32 = 1037,
+ VSLIv2i64 = 1038,
+ VSLIv4i16 = 1039,
+ VSLIv4i32 = 1040,
+ VSLIv8i16 = 1041,
+ VSLIv8i8 = 1042,
+ VSQRTD = 1043,
+ VSQRTS = 1044,
+ VSRAsv16i8 = 1045,
+ VSRAsv1i64 = 1046,
+ VSRAsv2i32 = 1047,
+ VSRAsv2i64 = 1048,
+ VSRAsv4i16 = 1049,
+ VSRAsv4i32 = 1050,
+ VSRAsv8i16 = 1051,
+ VSRAsv8i8 = 1052,
+ VSRAuv16i8 = 1053,
+ VSRAuv1i64 = 1054,
+ VSRAuv2i32 = 1055,
+ VSRAuv2i64 = 1056,
+ VSRAuv4i16 = 1057,
+ VSRAuv4i32 = 1058,
+ VSRAuv8i16 = 1059,
+ VSRAuv8i8 = 1060,
+ VSRIv16i8 = 1061,
+ VSRIv1i64 = 1062,
+ VSRIv2i32 = 1063,
+ VSRIv2i64 = 1064,
+ VSRIv4i16 = 1065,
+ VSRIv4i32 = 1066,
+ VSRIv8i16 = 1067,
+ VSRIv8i8 = 1068,
+ VST1d16 = 1069,
+ VST1d32 = 1070,
+ VST1d64 = 1071,
+ VST1d8 = 1072,
+ VST1df = 1073,
+ VST1q16 = 1074,
+ VST1q32 = 1075,
+ VST1q64 = 1076,
+ VST1q8 = 1077,
+ VST1qf = 1078,
+ VST2LNd16 = 1079,
+ VST2LNd32 = 1080,
+ VST2LNd8 = 1081,
+ VST2LNq16a = 1082,
+ VST2LNq16b = 1083,
+ VST2LNq32a = 1084,
+ VST2LNq32b = 1085,
+ VST2d16 = 1086,
+ VST2d32 = 1087,
+ VST2d64 = 1088,
+ VST2d8 = 1089,
+ VST2q16 = 1090,
+ VST2q32 = 1091,
+ VST2q8 = 1092,
+ VST3LNd16 = 1093,
+ VST3LNd32 = 1094,
+ VST3LNd8 = 1095,
+ VST3LNq16a = 1096,
+ VST3LNq16b = 1097,
+ VST3LNq32a = 1098,
+ VST3LNq32b = 1099,
+ VST3d16 = 1100,
+ VST3d32 = 1101,
+ VST3d64 = 1102,
+ VST3d8 = 1103,
+ VST3q16a = 1104,
+ VST3q16b = 1105,
+ VST3q32a = 1106,
+ VST3q32b = 1107,
+ VST3q8a = 1108,
+ VST3q8b = 1109,
+ VST4LNd16 = 1110,
+ VST4LNd32 = 1111,
+ VST4LNd8 = 1112,
+ VST4LNq16a = 1113,
+ VST4LNq16b = 1114,
+ VST4LNq32a = 1115,
+ VST4LNq32b = 1116,
+ VST4d16 = 1117,
+ VST4d32 = 1118,
+ VST4d64 = 1119,
+ VST4d8 = 1120,
+ VST4q16a = 1121,
+ VST4q16b = 1122,
+ VST4q32a = 1123,
+ VST4q32b = 1124,
+ VST4q8a = 1125,
+ VST4q8b = 1126,
+ VSTMD = 1127,
+ VSTMS = 1128,
+ VSTRD = 1129,
+ VSTRQ = 1130,
+ VSTRS = 1131,
+ VSUBD = 1132,
+ VSUBHNv2i32 = 1133,
+ VSUBHNv4i16 = 1134,
+ VSUBHNv8i8 = 1135,
+ VSUBLsv2i64 = 1136,
+ VSUBLsv4i32 = 1137,
+ VSUBLsv8i16 = 1138,
+ VSUBLuv2i64 = 1139,
+ VSUBLuv4i32 = 1140,
+ VSUBLuv8i16 = 1141,
+ VSUBS = 1142,
+ VSUBWsv2i64 = 1143,
+ VSUBWsv4i32 = 1144,
+ VSUBWsv8i16 = 1145,
+ VSUBWuv2i64 = 1146,
+ VSUBWuv4i32 = 1147,
+ VSUBWuv8i16 = 1148,
+ VSUBfd = 1149,
+ VSUBfd_sfp = 1150,
+ VSUBfq = 1151,
+ VSUBv16i8 = 1152,
+ VSUBv1i64 = 1153,
+ VSUBv2i32 = 1154,
+ VSUBv2i64 = 1155,
+ VSUBv4i16 = 1156,
+ VSUBv4i32 = 1157,
+ VSUBv8i16 = 1158,
+ VSUBv8i8 = 1159,
+ VTBL1 = 1160,
+ VTBL2 = 1161,
+ VTBL3 = 1162,
+ VTBL4 = 1163,
+ VTBX1 = 1164,
+ VTBX2 = 1165,
+ VTBX3 = 1166,
+ VTBX4 = 1167,
+ VTOSIZD = 1168,
+ VTOSIZS = 1169,
+ VTOUIZD = 1170,
+ VTOUIZS = 1171,
+ VTRNd16 = 1172,
+ VTRNd32 = 1173,
+ VTRNd8 = 1174,
+ VTRNq16 = 1175,
+ VTRNq32 = 1176,
+ VTRNq8 = 1177,
+ VTSTv16i8 = 1178,
+ VTSTv2i32 = 1179,
+ VTSTv4i16 = 1180,
+ VTSTv4i32 = 1181,
+ VTSTv8i16 = 1182,
+ VTSTv8i8 = 1183,
+ VUITOD = 1184,
+ VUITOS = 1185,
+ VUZPd16 = 1186,
+ VUZPd32 = 1187,
+ VUZPd8 = 1188,
+ VUZPq16 = 1189,
+ VUZPq32 = 1190,
+ VUZPq8 = 1191,
+ VZIPd16 = 1192,
+ VZIPd32 = 1193,
+ VZIPd8 = 1194,
+ VZIPq16 = 1195,
+ VZIPq32 = 1196,
+ VZIPq8 = 1197,
+ t2ADCSri = 1198,
+ t2ADCSrr = 1199,
+ t2ADCSrs = 1200,
+ t2ADCri = 1201,
+ t2ADCrr = 1202,
+ t2ADCrs = 1203,
+ t2ADDSri = 1204,
+ t2ADDSrr = 1205,
+ t2ADDSrs = 1206,
+ t2ADDrSPi = 1207,
+ t2ADDrSPi12 = 1208,
+ t2ADDrSPs = 1209,
+ t2ADDri = 1210,
+ t2ADDri12 = 1211,
+ t2ADDrr = 1212,
+ t2ADDrs = 1213,
+ t2ANDri = 1214,
+ t2ANDrr = 1215,
+ t2ANDrs = 1216,
+ t2ASRri = 1217,
+ t2ASRrr = 1218,
+ t2B = 1219,
+ t2BFC = 1220,
+ t2BICri = 1221,
+ t2BICrr = 1222,
+ t2BICrs = 1223,
+ t2BR_JT = 1224,
+ t2Bcc = 1225,
+ t2CLZ = 1226,
+ t2CMNri = 1227,
+ t2CMNrr = 1228,
+ t2CMNrs = 1229,
+ t2CMNzri = 1230,
+ t2CMNzrr = 1231,
+ t2CMNzrs = 1232,
+ t2CMPri = 1233,
+ t2CMPrr = 1234,
+ t2CMPrs = 1235,
+ t2CMPzri = 1236,
+ t2CMPzrr = 1237,
+ t2CMPzrs = 1238,
+ t2EORri = 1239,
+ t2EORrr = 1240,
+ t2EORrs = 1241,
+ t2IT = 1242,
+ t2Int_MemBarrierV7 = 1243,
+ t2Int_SyncBarrierV7 = 1244,
+ t2Int_eh_sjlj_setjmp = 1245,
+ t2LDM = 1246,
+ t2LDM_RET = 1247,
+ t2LDRB_POST = 1248,
+ t2LDRB_PRE = 1249,
+ t2LDRBi12 = 1250,
+ t2LDRBi8 = 1251,
+ t2LDRBpci = 1252,
+ t2LDRBs = 1253,
+ t2LDRDi8 = 1254,
+ t2LDRDpci = 1255,
+ t2LDREX = 1256,
+ t2LDREXB = 1257,
+ t2LDREXD = 1258,
+ t2LDREXH = 1259,
+ t2LDRH_POST = 1260,
+ t2LDRH_PRE = 1261,
+ t2LDRHi12 = 1262,
+ t2LDRHi8 = 1263,
+ t2LDRHpci = 1264,
+ t2LDRHs = 1265,
+ t2LDRSB_POST = 1266,
+ t2LDRSB_PRE = 1267,
+ t2LDRSBi12 = 1268,
+ t2LDRSBi8 = 1269,
+ t2LDRSBpci = 1270,
+ t2LDRSBs = 1271,
+ t2LDRSH_POST = 1272,
+ t2LDRSH_PRE = 1273,
+ t2LDRSHi12 = 1274,
+ t2LDRSHi8 = 1275,
+ t2LDRSHpci = 1276,
+ t2LDRSHs = 1277,
+ t2LDR_POST = 1278,
+ t2LDR_PRE = 1279,
+ t2LDRi12 = 1280,
+ t2LDRi8 = 1281,
+ t2LDRpci = 1282,
+ t2LDRpci_pic = 1283,
+ t2LDRs = 1284,
+ t2LEApcrel = 1285,
+ t2LEApcrelJT = 1286,
+ t2LSLri = 1287,
+ t2LSLrr = 1288,
+ t2LSRri = 1289,
+ t2LSRrr = 1290,
+ t2MLA = 1291,
+ t2MLS = 1292,
+ t2MOVCCasr = 1293,
+ t2MOVCCi = 1294,
+ t2MOVCClsl = 1295,
+ t2MOVCClsr = 1296,
+ t2MOVCCr = 1297,
+ t2MOVCCror = 1298,
+ t2MOVTi16 = 1299,
+ t2MOVi = 1300,
+ t2MOVi16 = 1301,
+ t2MOVi32imm = 1302,
+ t2MOVr = 1303,
+ t2MOVrx = 1304,
+ t2MOVsra_flag = 1305,
+ t2MOVsrl_flag = 1306,
+ t2MUL = 1307,
+ t2MVNi = 1308,
+ t2MVNr = 1309,
+ t2MVNs = 1310,
+ t2ORNri = 1311,
+ t2ORNrr = 1312,
+ t2ORNrs = 1313,
+ t2ORRri = 1314,
+ t2ORRrr = 1315,
+ t2ORRrs = 1316,
+ t2PKHBT = 1317,
+ t2PKHTB = 1318,
+ t2REV = 1319,
+ t2REV16 = 1320,
+ t2REVSH = 1321,
+ t2RORri = 1322,
+ t2RORrr = 1323,
+ t2RSBSri = 1324,
+ t2RSBSrs = 1325,
+ t2RSBri = 1326,
+ t2RSBrs = 1327,
+ t2SBCSri = 1328,
+ t2SBCSrr = 1329,
+ t2SBCSrs = 1330,
+ t2SBCri = 1331,
+ t2SBCrr = 1332,
+ t2SBCrs = 1333,
+ t2SBFX = 1334,
+ t2SMLABB = 1335,
+ t2SMLABT = 1336,
+ t2SMLAL = 1337,
+ t2SMLATB = 1338,
+ t2SMLATT = 1339,
+ t2SMLAWB = 1340,
+ t2SMLAWT = 1341,
+ t2SMMLA = 1342,
+ t2SMMLS = 1343,
+ t2SMMUL = 1344,
+ t2SMULBB = 1345,
+ t2SMULBT = 1346,
+ t2SMULL = 1347,
+ t2SMULTB = 1348,
+ t2SMULTT = 1349,
+ t2SMULWB = 1350,
+ t2SMULWT = 1351,
+ t2STM = 1352,
+ t2STRB_POST = 1353,
+ t2STRB_PRE = 1354,
+ t2STRBi12 = 1355,
+ t2STRBi8 = 1356,
+ t2STRBs = 1357,
+ t2STRDi8 = 1358,
+ t2STREX = 1359,
+ t2STREXB = 1360,
+ t2STREXD = 1361,
+ t2STREXH = 1362,
+ t2STRH_POST = 1363,
+ t2STRH_PRE = 1364,
+ t2STRHi12 = 1365,
+ t2STRHi8 = 1366,
+ t2STRHs = 1367,
+ t2STR_POST = 1368,
+ t2STR_PRE = 1369,
+ t2STRi12 = 1370,
+ t2STRi8 = 1371,
+ t2STRs = 1372,
+ t2SUBSri = 1373,
+ t2SUBSrr = 1374,
+ t2SUBSrs = 1375,
+ t2SUBrSPi = 1376,
+ t2SUBrSPi12 = 1377,
+ t2SUBrSPi12_ = 1378,
+ t2SUBrSPi_ = 1379,
+ t2SUBrSPs = 1380,
+ t2SUBrSPs_ = 1381,
+ t2SUBri = 1382,
+ t2SUBri12 = 1383,
+ t2SUBrr = 1384,
+ t2SUBrs = 1385,
+ t2SXTABrr = 1386,
+ t2SXTABrr_rot = 1387,
+ t2SXTAHrr = 1388,
+ t2SXTAHrr_rot = 1389,
+ t2SXTBr = 1390,
+ t2SXTBr_rot = 1391,
+ t2SXTHr = 1392,
+ t2SXTHr_rot = 1393,
+ t2TBB = 1394,
+ t2TBH = 1395,
+ t2TEQri = 1396,
+ t2TEQrr = 1397,
+ t2TEQrs = 1398,
+ t2TPsoft = 1399,
+ t2TSTri = 1400,
+ t2TSTrr = 1401,
+ t2TSTrs = 1402,
+ t2UBFX = 1403,
+ t2UMAAL = 1404,
+ t2UMLAL = 1405,
+ t2UMULL = 1406,
+ t2UXTABrr = 1407,
+ t2UXTABrr_rot = 1408,
+ t2UXTAHrr = 1409,
+ t2UXTAHrr_rot = 1410,
+ t2UXTB16r = 1411,
+ t2UXTB16r_rot = 1412,
+ t2UXTBr = 1413,
+ t2UXTBr_rot = 1414,
+ t2UXTHr = 1415,
+ t2UXTHr_rot = 1416,
+ tADC = 1417,
+ tADDhirr = 1418,
+ tADDi3 = 1419,
+ tADDi8 = 1420,
+ tADDrPCi = 1421,
+ tADDrSP = 1422,
+ tADDrSPi = 1423,
+ tADDrr = 1424,
+ tADDspi = 1425,
+ tADDspr = 1426,
+ tADDspr_ = 1427,
+ tADJCALLSTACKDOWN = 1428,
+ tADJCALLSTACKUP = 1429,
+ tAND = 1430,
+ tANDsp = 1431,
+ tASRri = 1432,
+ tASRrr = 1433,
+ tB = 1434,
+ tBIC = 1435,
+ tBL = 1436,
+ tBLXi = 1437,
+ tBLXi_r9 = 1438,
+ tBLXr = 1439,
+ tBLXr_r9 = 1440,
+ tBLr9 = 1441,
+ tBRIND = 1442,
+ tBR_JTr = 1443,
+ tBX = 1444,
+ tBX_RET = 1445,
+ tBX_RET_vararg = 1446,
+ tBXr9 = 1447,
+ tBcc = 1448,
+ tBfar = 1449,
+ tCBNZ = 1450,
+ tCBZ = 1451,
+ tCMN = 1452,
+ tCMNZ = 1453,
+ tCMPhir = 1454,
+ tCMPi8 = 1455,
+ tCMPr = 1456,
+ tCMPzhir = 1457,
+ tCMPzi8 = 1458,
+ tCMPzr = 1459,
+ tEOR = 1460,
+ tInt_eh_sjlj_setjmp = 1461,
+ tLDM = 1462,
+ tLDR = 1463,
+ tLDRB = 1464,
+ tLDRH = 1465,
+ tLDRSB = 1466,
+ tLDRSH = 1467,
+ tLDRcp = 1468,
+ tLDRpci = 1469,
+ tLDRpci_pic = 1470,
+ tLDRspi = 1471,
+ tLEApcrel = 1472,
+ tLEApcrelJT = 1473,
+ tLSLri = 1474,
+ tLSLrr = 1475,
+ tLSRri = 1476,
+ tLSRrr = 1477,
+ tMOVCCi = 1478,
+ tMOVCCr = 1479,
+ tMOVCCr_pseudo = 1480,
+ tMOVSr = 1481,
+ tMOVgpr2gpr = 1482,
+ tMOVgpr2tgpr = 1483,
+ tMOVi8 = 1484,
+ tMOVr = 1485,
+ tMOVtgpr2gpr = 1486,
+ tMUL = 1487,
+ tMVN = 1488,
+ tORR = 1489,
+ tPICADD = 1490,
+ tPOP = 1491,
+ tPOP_RET = 1492,
+ tPUSH = 1493,
+ tREV = 1494,
+ tREV16 = 1495,
+ tREVSH = 1496,
+ tROR = 1497,
+ tRSB = 1498,
+ tRestore = 1499,
+ tSBC = 1500,
+ tSTM = 1501,
+ tSTR = 1502,
+ tSTRB = 1503,
+ tSTRH = 1504,
+ tSTRspi = 1505,
+ tSUBi3 = 1506,
+ tSUBi8 = 1507,
+ tSUBrr = 1508,
+ tSUBspi = 1509,
+ tSUBspi_ = 1510,
+ tSXTB = 1511,
+ tSXTH = 1512,
+ tSpill = 1513,
+ tTPsoft = 1514,
+ tTST = 1515,
+ tUXTB = 1516,
+ tUXTH = 1517,
+ INSTRUCTION_LIST_END = 1518
+ };
+}
+} // End llvm namespace
diff --git a/libclamav/c++/ARMGenRegisterInfo.h.inc b/libclamav/c++/ARMGenRegisterInfo.h.inc
new file mode 100644
index 0000000..1e26e88
--- /dev/null
+++ b/libclamav/c++/ARMGenRegisterInfo.h.inc
@@ -0,0 +1,111 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Register Information Header Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <string>
+
+namespace llvm {
+
+struct ARMGenRegisterInfo : public TargetRegisterInfo {
+ explicit ARMGenRegisterInfo(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
+ virtual int getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) const;
+ virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
+ virtual bool needsStackRealignment(const MachineFunction &) const
+ { return false; }
+ unsigned getSubReg(unsigned RegNo, unsigned Index) const;
+ unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
+};
+
+namespace ARM { // Register classes
+ enum {
+ CCRRegClassID = 1,
+ DPRRegClassID = 2,
+ DPR_8RegClassID = 3,
+ DPR_VFP2RegClassID = 4,
+ GPRRegClassID = 5,
+ QPRRegClassID = 6,
+ QPR_8RegClassID = 7,
+ QPR_VFP2RegClassID = 8,
+ SPRRegClassID = 9,
+ SPR_8RegClassID = 10,
+ SPR_INVALIDRegClassID = 11,
+ tGPRRegClassID = 12
+ };
+
+ struct CCRClass : public TargetRegisterClass {
+ CCRClass();
+ };
+ extern CCRClass CCRRegClass;
+ static TargetRegisterClass * const CCRRegisterClass = &CCRRegClass;
+ struct DPRClass : public TargetRegisterClass {
+ DPRClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern DPRClass DPRRegClass;
+ static TargetRegisterClass * const DPRRegisterClass = &DPRRegClass;
+ struct DPR_8Class : public TargetRegisterClass {
+ DPR_8Class();
+ };
+ extern DPR_8Class DPR_8RegClass;
+ static TargetRegisterClass * const DPR_8RegisterClass = &DPR_8RegClass;
+ struct DPR_VFP2Class : public TargetRegisterClass {
+ DPR_VFP2Class();
+ };
+ extern DPR_VFP2Class DPR_VFP2RegClass;
+ static TargetRegisterClass * const DPR_VFP2RegisterClass = &DPR_VFP2RegClass;
+ struct GPRClass : public TargetRegisterClass {
+ GPRClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GPRClass GPRRegClass;
+ static TargetRegisterClass * const GPRRegisterClass = &GPRRegClass;
+ struct QPRClass : public TargetRegisterClass {
+ QPRClass();
+ };
+ extern QPRClass QPRRegClass;
+ static TargetRegisterClass * const QPRRegisterClass = &QPRRegClass;
+ struct QPR_8Class : public TargetRegisterClass {
+ QPR_8Class();
+ };
+ extern QPR_8Class QPR_8RegClass;
+ static TargetRegisterClass * const QPR_8RegisterClass = &QPR_8RegClass;
+ struct QPR_VFP2Class : public TargetRegisterClass {
+ QPR_VFP2Class();
+ };
+ extern QPR_VFP2Class QPR_VFP2RegClass;
+ static TargetRegisterClass * const QPR_VFP2RegisterClass = &QPR_VFP2RegClass;
+ struct SPRClass : public TargetRegisterClass {
+ SPRClass();
+ };
+ extern SPRClass SPRRegClass;
+ static TargetRegisterClass * const SPRRegisterClass = &SPRRegClass;
+ struct SPR_8Class : public TargetRegisterClass {
+ SPR_8Class();
+ };
+ extern SPR_8Class SPR_8RegClass;
+ static TargetRegisterClass * const SPR_8RegisterClass = &SPR_8RegClass;
+ struct SPR_INVALIDClass : public TargetRegisterClass {
+ SPR_INVALIDClass();
+ };
+ extern SPR_INVALIDClass SPR_INVALIDRegClass;
+ static TargetRegisterClass * const SPR_INVALIDRegisterClass = &SPR_INVALIDRegClass;
+ struct tGPRClass : public TargetRegisterClass {
+ tGPRClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern tGPRClass tGPRRegClass;
+ static TargetRegisterClass * const tGPRRegisterClass = &tGPRRegClass;
+} // end of namespace ARM
+
+} // End llvm namespace
diff --git a/libclamav/c++/ARMGenRegisterInfo.inc b/libclamav/c++/ARMGenRegisterInfo.inc
new file mode 100644
index 0000000..c449225
--- /dev/null
+++ b/libclamav/c++/ARMGenRegisterInfo.inc
@@ -0,0 +1,3707 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Register Information Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace { // Register classes...
+ // CCR Register Class...
+ static const unsigned CCR[] = {
+ ARM::CPSR,
+ };
+
+ // DPR Register Class...
+ static const unsigned DPR[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31,
+ };
+
+ // DPR_8 Register Class...
+ static const unsigned DPR_8[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ };
+
+ // DPR_VFP2 Register Class...
+ static const unsigned DPR_VFP2[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
+ };
+
+ // GPR Register Class...
+ static const unsigned GPR[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R12, ARM::R11, ARM::LR, ARM::SP, ARM::PC,
+ };
+
+ // QPR Register Class...
+ static const unsigned QPR[] = {
+ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
+ };
+
+ // QPR_8 Register Class...
+ static const unsigned QPR_8[] = {
+ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
+ };
+
+ // QPR_VFP2 Register Class...
+ static const unsigned QPR_VFP2[] = {
+ ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
+ };
+
+ // SPR Register Class...
+ static const unsigned SPR[] = {
+ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31,
+ };
+
+ // SPR_8 Register Class...
+ static const unsigned SPR_8[] = {
+ ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
+ };
+
+ // SPR_INVALID Register Class...
+ static const unsigned SPR_INVALID[] = {
+ ARM::SDummy,
+ };
+
+ // tGPR Register Class...
+ static const unsigned tGPR[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ };
+
+ // CCRVTs Register Class Value Types...
+ static const EVT CCRVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // DPRVTs Register Class Value Types...
+ static const EVT DPRVTs[] = {
+ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::Other
+ };
+
+ // DPR_8VTs Register Class Value Types...
+ static const EVT DPR_8VTs[] = {
+ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::Other
+ };
+
+ // DPR_VFP2VTs Register Class Value Types...
+ static const EVT DPR_VFP2VTs[] = {
+ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::Other
+ };
+
+ // GPRVTs Register Class Value Types...
+ static const EVT GPRVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // QPRVTs Register Class Value Types...
+ static const EVT QPRVTs[] = {
+ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
+ };
+
+ // QPR_8VTs Register Class Value Types...
+ static const EVT QPR_8VTs[] = {
+ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
+ };
+
+ // QPR_VFP2VTs Register Class Value Types...
+ static const EVT QPR_VFP2VTs[] = {
+ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
+ };
+
+ // SPRVTs Register Class Value Types...
+ static const EVT SPRVTs[] = {
+ MVT::f32, MVT::Other
+ };
+
+ // SPR_8VTs Register Class Value Types...
+ static const EVT SPR_8VTs[] = {
+ MVT::f32, MVT::Other
+ };
+
+ // SPR_INVALIDVTs Register Class Value Types...
+ static const EVT SPR_INVALIDVTs[] = {
+ MVT::f32, MVT::Other
+ };
+
+ // tGPRVTs Register Class Value Types...
+ static const EVT tGPRVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+} // end anonymous namespace
+
+namespace ARM { // Register class instances
+ CCRClass CCRRegClass;
+ DPRClass DPRRegClass;
+ DPR_8Class DPR_8RegClass;
+ DPR_VFP2Class DPR_VFP2RegClass;
+ GPRClass GPRRegClass;
+ QPRClass QPRRegClass;
+ QPR_8Class QPR_8RegClass;
+ QPR_VFP2Class QPR_VFP2RegClass;
+ SPRClass SPRRegClass;
+ SPR_8Class SPR_8RegClass;
+ SPR_INVALIDClass SPR_INVALIDRegClass;
+ tGPRClass tGPRRegClass;
+
+ // CCR Sub-register Classes...
+ static const TargetRegisterClass* const CCRSubRegClasses[] = {
+ NULL
+ };
+
+ // DPR Sub-register Classes...
+ static const TargetRegisterClass* const DPRSubRegClasses[] = {
+ &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, NULL
+ };
+
+ // DPR_8 Sub-register Classes...
+ static const TargetRegisterClass* const DPR_8SubRegClasses[] = {
+ &ARM::SPR_8RegClass, &ARM::SPR_8RegClass, NULL
+ };
+
+ // DPR_VFP2 Sub-register Classes...
+ static const TargetRegisterClass* const DPR_VFP2SubRegClasses[] = {
+ &ARM::SPRRegClass, &ARM::SPRRegClass, NULL
+ };
+
+ // GPR Sub-register Classes...
+ static const TargetRegisterClass* const GPRSubRegClasses[] = {
+ NULL
+ };
+
+ // QPR Sub-register Classes...
+ static const TargetRegisterClass* const QPRSubRegClasses[] = {
+ &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, NULL
+ };
+
+ // QPR_8 Sub-register Classes...
+ static const TargetRegisterClass* const QPR_8SubRegClasses[] = {
+ &ARM::SPR_8RegClass, &ARM::SPR_8RegClass, &ARM::SPR_8RegClass, &ARM::SPR_8RegClass, &ARM::DPR_8RegClass, &ARM::DPR_8RegClass, NULL
+ };
+
+ // QPR_VFP2 Sub-register Classes...
+ static const TargetRegisterClass* const QPR_VFP2SubRegClasses[] = {
+ &ARM::SPRRegClass, &ARM::SPRRegClass, &ARM::SPRRegClass, &ARM::SPRRegClass, &ARM::DPR_VFP2RegClass, &ARM::DPR_VFP2RegClass, NULL
+ };
+
+ // SPR Sub-register Classes...
+ static const TargetRegisterClass* const SPRSubRegClasses[] = {
+ NULL
+ };
+
+ // SPR_8 Sub-register Classes...
+ static const TargetRegisterClass* const SPR_8SubRegClasses[] = {
+ NULL
+ };
+
+ // SPR_INVALID Sub-register Classes...
+ static const TargetRegisterClass* const SPR_INVALIDSubRegClasses[] = {
+ NULL
+ };
+
+ // tGPR Sub-register Classes...
+ static const TargetRegisterClass* const tGPRSubRegClasses[] = {
+ NULL
+ };
+
+ // CCR Super-register Classes...
+ static const TargetRegisterClass* const CCRSuperRegClasses[] = {
+ NULL
+ };
+
+ // DPR Super-register Classes...
+ static const TargetRegisterClass* const DPRSuperRegClasses[] = {
+ &ARM::QPRRegClass, NULL
+ };
+
+ // DPR_8 Super-register Classes...
+ static const TargetRegisterClass* const DPR_8SuperRegClasses[] = {
+ &ARM::QPR_8RegClass, NULL
+ };
+
+ // DPR_VFP2 Super-register Classes...
+ static const TargetRegisterClass* const DPR_VFP2SuperRegClasses[] = {
+ &ARM::QPR_VFP2RegClass, NULL
+ };
+
+ // GPR Super-register Classes...
+ static const TargetRegisterClass* const GPRSuperRegClasses[] = {
+ NULL
+ };
+
+ // QPR Super-register Classes...
+ static const TargetRegisterClass* const QPRSuperRegClasses[] = {
+ NULL
+ };
+
+ // QPR_8 Super-register Classes...
+ static const TargetRegisterClass* const QPR_8SuperRegClasses[] = {
+ NULL
+ };
+
+ // QPR_VFP2 Super-register Classes...
+ static const TargetRegisterClass* const QPR_VFP2SuperRegClasses[] = {
+ NULL
+ };
+
+ // SPR Super-register Classes...
+ static const TargetRegisterClass* const SPRSuperRegClasses[] = {
+ &ARM::DPR_VFP2RegClass, &ARM::QPR_VFP2RegClass, NULL
+ };
+
+ // SPR_8 Super-register Classes...
+ static const TargetRegisterClass* const SPR_8SuperRegClasses[] = {
+ &ARM::DPR_8RegClass, &ARM::QPR_8RegClass, NULL
+ };
+
+ // SPR_INVALID Super-register Classes...
+ static const TargetRegisterClass* const SPR_INVALIDSuperRegClasses[] = {
+ &ARM::DPRRegClass, &ARM::QPRRegClass, NULL
+ };
+
+ // tGPR Super-register Classes...
+ static const TargetRegisterClass* const tGPRSuperRegClasses[] = {
+ NULL
+ };
+
+ // CCR Register Class sub-classes...
+ static const TargetRegisterClass* const CCRSubclasses[] = {
+ NULL
+ };
+
+ // DPR Register Class sub-classes...
+ static const TargetRegisterClass* const DPRSubclasses[] = {
+ &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, NULL
+ };
+
+ // DPR_8 Register Class sub-classes...
+ static const TargetRegisterClass* const DPR_8Subclasses[] = {
+ NULL
+ };
+
+ // DPR_VFP2 Register Class sub-classes...
+ static const TargetRegisterClass* const DPR_VFP2Subclasses[] = {
+ &ARM::DPR_8RegClass, NULL
+ };
+
+ // GPR Register Class sub-classes...
+ static const TargetRegisterClass* const GPRSubclasses[] = {
+ &ARM::tGPRRegClass, NULL
+ };
+
+ // QPR Register Class sub-classes...
+ static const TargetRegisterClass* const QPRSubclasses[] = {
+ &ARM::QPR_8RegClass, &ARM::QPR_VFP2RegClass, NULL
+ };
+
+ // QPR_8 Register Class sub-classes...
+ static const TargetRegisterClass* const QPR_8Subclasses[] = {
+ NULL
+ };
+
+ // QPR_VFP2 Register Class sub-classes...
+ static const TargetRegisterClass* const QPR_VFP2Subclasses[] = {
+ &ARM::QPR_8RegClass, NULL
+ };
+
+ // SPR Register Class sub-classes...
+ static const TargetRegisterClass* const SPRSubclasses[] = {
+ &ARM::SPR_8RegClass, NULL
+ };
+
+ // SPR_8 Register Class sub-classes...
+ static const TargetRegisterClass* const SPR_8Subclasses[] = {
+ NULL
+ };
+
+ // SPR_INVALID Register Class sub-classes...
+ static const TargetRegisterClass* const SPR_INVALIDSubclasses[] = {
+ NULL
+ };
+
+ // tGPR Register Class sub-classes...
+ static const TargetRegisterClass* const tGPRSubclasses[] = {
+ NULL
+ };
+
+ // CCR Register Class super-classes...
+ static const TargetRegisterClass* const CCRSuperclasses[] = {
+ NULL
+ };
+
+ // DPR Register Class super-classes...
+ static const TargetRegisterClass* const DPRSuperclasses[] = {
+ NULL
+ };
+
+ // DPR_8 Register Class super-classes...
+ static const TargetRegisterClass* const DPR_8Superclasses[] = {
+ &ARM::DPRRegClass, &ARM::DPR_VFP2RegClass, NULL
+ };
+
+ // DPR_VFP2 Register Class super-classes...
+ static const TargetRegisterClass* const DPR_VFP2Superclasses[] = {
+ &ARM::DPRRegClass, NULL
+ };
+
+ // GPR Register Class super-classes...
+ static const TargetRegisterClass* const GPRSuperclasses[] = {
+ NULL
+ };
+
+ // QPR Register Class super-classes...
+ static const TargetRegisterClass* const QPRSuperclasses[] = {
+ NULL
+ };
+
+ // QPR_8 Register Class super-classes...
+ static const TargetRegisterClass* const QPR_8Superclasses[] = {
+ &ARM::QPRRegClass, &ARM::QPR_VFP2RegClass, NULL
+ };
+
+ // QPR_VFP2 Register Class super-classes...
+ static const TargetRegisterClass* const QPR_VFP2Superclasses[] = {
+ &ARM::QPRRegClass, NULL
+ };
+
+ // SPR Register Class super-classes...
+ static const TargetRegisterClass* const SPRSuperclasses[] = {
+ NULL
+ };
+
+ // SPR_8 Register Class super-classes...
+ static const TargetRegisterClass* const SPR_8Superclasses[] = {
+ &ARM::SPRRegClass, NULL
+ };
+
+ // SPR_INVALID Register Class super-classes...
+ static const TargetRegisterClass* const SPR_INVALIDSuperclasses[] = {
+ NULL
+ };
+
+ // tGPR Register Class super-classes...
+ static const TargetRegisterClass* const tGPRSuperclasses[] = {
+ &ARM::GPRRegClass, NULL
+ };
+
+
+CCRClass::CCRClass() : TargetRegisterClass(CCRRegClassID, "CCR", CCRVTs, CCRSubclasses, CCRSuperclasses, CCRSubRegClasses, CCRSuperRegClasses, 4, 4, 1, CCR, CCR + 1) {}
+
+ // VFP2
+ static const unsigned ARM_DPR_VFP2[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
+ // VFP3
+ static const unsigned ARM_DPR_VFP3[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ ARM::D12, ARM::D13, ARM::D14, ARM::D15,
+ ARM::D16, ARM::D17, ARM::D18, ARM::D19,
+ ARM::D20, ARM::D21, ARM::D22, ARM::D23,
+ ARM::D24, ARM::D25, ARM::D26, ARM::D27,
+ ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
+ DPRClass::iterator
+ DPRClass::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ if (Subtarget.hasVFP3())
+ return ARM_DPR_VFP3;
+ return ARM_DPR_VFP2;
+ }
+
+ DPRClass::iterator
+ DPRClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ if (Subtarget.hasVFP3())
+ return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
+ else
+ return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
+ }
+
+DPRClass::DPRClass() : TargetRegisterClass(DPRRegClassID, "DPR", DPRVTs, DPRSubclasses, DPRSuperclasses, DPRSubRegClasses, DPRSuperRegClasses, 8, 8, 1, DPR, DPR + 32) {}
+
+DPR_8Class::DPR_8Class() : TargetRegisterClass(DPR_8RegClassID, "DPR_8", DPR_8VTs, DPR_8Subclasses, DPR_8Superclasses, DPR_8SubRegClasses, DPR_8SuperRegClasses, 8, 8, 1, DPR_8, DPR_8 + 8) {}
+
+DPR_VFP2Class::DPR_VFP2Class() : TargetRegisterClass(DPR_VFP2RegClassID, "DPR_VFP2", DPR_VFP2VTs, DPR_VFP2Subclasses, DPR_VFP2Superclasses, DPR_VFP2SubRegClasses, DPR_VFP2SuperRegClasses, 8, 8, 1, DPR_VFP2, DPR_VFP2 + 16) {}
+
+ // FP is R11, R9 is available.
+ static const unsigned ARM_GPR_AO_1[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R9, ARM::R10,
+ ARM::R11 };
+ // FP is R11, R9 is not available.
+ static const unsigned ARM_GPR_AO_2[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R10,
+ ARM::R11 };
+ // FP is R7, R9 is available as non-callee-saved register.
+ // This is used by Darwin.
+ static const unsigned ARM_GPR_AO_3[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R9, ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
+ // FP is R7, R9 is not available.
+ static const unsigned ARM_GPR_AO_4[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R10,ARM::R11,
+ ARM::R7 };
+ // FP is R7, R9 is available as callee-saved register.
+ // This is used by non-Darwin platform in Thumb mode.
+ static const unsigned ARM_GPR_AO_5[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
+
+ // For Thumb1 mode, we don't want to allocate hi regs at all, as we
+ // don't know how to spill them. If we make our prologue/epilogue code
+ // smarter at some point, we can go back to using the above allocation
+ // orders for the Thumb1 instructions that know how to use hi regs.
+ static const unsigned THUMB_GPR_AO[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
+
+ GPRClass::iterator
+ GPRClass::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ if (Subtarget.isThumb1Only())
+ return THUMB_GPR_AO;
+ if (Subtarget.isTargetDarwin()) {
+ if (Subtarget.isR9Reserved())
+ return ARM_GPR_AO_4;
+ else
+ return ARM_GPR_AO_3;
+ } else {
+ if (Subtarget.isR9Reserved())
+ return ARM_GPR_AO_2;
+ else if (Subtarget.isThumb())
+ return ARM_GPR_AO_5;
+ else
+ return ARM_GPR_AO_1;
+ }
+ }
+
+ GPRClass::iterator
+ GPRClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ GPRClass::iterator I;
+
+ if (Subtarget.isThumb1Only()) {
+ I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
+ // Mac OS X requires FP not to be clobbered for backtracing purpose.
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+ }
+
+ if (Subtarget.isTargetDarwin()) {
+ if (Subtarget.isR9Reserved())
+ I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
+ else
+ I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
+ } else {
+ if (Subtarget.isR9Reserved())
+ I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
+ else if (Subtarget.isThumb())
+ I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
+ else
+ I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
+ }
+
+ // Mac OS X requires FP not to be clobbered for backtracing purpose.
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+ }
+
+GPRClass::GPRClass() : TargetRegisterClass(GPRRegClassID, "GPR", GPRVTs, GPRSubclasses, GPRSuperclasses, GPRSubRegClasses, GPRSuperRegClasses, 4, 4, 1, GPR, GPR + 16) {}
+
+QPRClass::QPRClass() : TargetRegisterClass(QPRRegClassID, "QPR", QPRVTs, QPRSubclasses, QPRSuperclasses, QPRSubRegClasses, QPRSuperRegClasses, 16, 16, 1, QPR, QPR + 16) {}
+
+QPR_8Class::QPR_8Class() : TargetRegisterClass(QPR_8RegClassID, "QPR_8", QPR_8VTs, QPR_8Subclasses, QPR_8Superclasses, QPR_8SubRegClasses, QPR_8SuperRegClasses, 16, 16, 1, QPR_8, QPR_8 + 4) {}
+
+QPR_VFP2Class::QPR_VFP2Class() : TargetRegisterClass(QPR_VFP2RegClassID, "QPR_VFP2", QPR_VFP2VTs, QPR_VFP2Subclasses, QPR_VFP2Superclasses, QPR_VFP2SubRegClasses, QPR_VFP2SuperRegClasses, 16, 16, 1, QPR_VFP2, QPR_VFP2 + 8) {}
+
+SPRClass::SPRClass() : TargetRegisterClass(SPRRegClassID, "SPR", SPRVTs, SPRSubclasses, SPRSuperclasses, SPRSubRegClasses, SPRSuperRegClasses, 4, 4, 1, SPR, SPR + 32) {}
+
+SPR_8Class::SPR_8Class() : TargetRegisterClass(SPR_8RegClassID, "SPR_8", SPR_8VTs, SPR_8Subclasses, SPR_8Superclasses, SPR_8SubRegClasses, SPR_8SuperRegClasses, 4, 4, 1, SPR_8, SPR_8 + 16) {}
+
+SPR_INVALIDClass::SPR_INVALIDClass() : TargetRegisterClass(SPR_INVALIDRegClassID, "SPR_INVALID", SPR_INVALIDVTs, SPR_INVALIDSubclasses, SPR_INVALIDSuperclasses, SPR_INVALIDSubRegClasses, SPR_INVALIDSuperRegClasses, 4, 4, -1, SPR_INVALID, SPR_INVALID + 1) {}
+
+ static const unsigned THUMB_tGPR_AO[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
+
+ // FP is R7, only low registers available.
+ tGPRClass::iterator
+ tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
+ return THUMB_tGPR_AO;
+ }
+
+ tGPRClass::iterator
+ tGPRClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ tGPRClass::iterator I =
+ THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
+ // Mac OS X requires FP not to be clobbered for backtracing purpose.
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+ }
+
+tGPRClass::tGPRClass() : TargetRegisterClass(tGPRRegClassID, "tGPR", tGPRVTs, tGPRSubclasses, tGPRSuperclasses, tGPRSubRegClasses, tGPRSuperRegClasses, 4, 4, 1, tGPR, tGPR + 8) {}
+}
+
+namespace {
+ const TargetRegisterClass* const RegisterClasses[] = {
+ &ARM::CCRRegClass,
+ &ARM::DPRRegClass,
+ &ARM::DPR_8RegClass,
+ &ARM::DPR_VFP2RegClass,
+ &ARM::GPRRegClass,
+ &ARM::QPRRegClass,
+ &ARM::QPR_8RegClass,
+ &ARM::QPR_VFP2RegClass,
+ &ARM::SPRRegClass,
+ &ARM::SPR_8RegClass,
+ &ARM::SPR_INVALIDRegClass,
+ &ARM::tGPRRegClass,
+ };
+
+
+ // Number of hash collisions: 6
+ const unsigned SubregHashTable[] = { ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S10,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D12, ARM::S24,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S23,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q15, ARM::D31,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q9, ARM::D19,
+ ARM::D5, ARM::S11,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D4, ARM::S9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S11,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D12, ARM::S25,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::D2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S24,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::D4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D6, ARM::S12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D13, ARM::S26,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q10, ARM::D20,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S25,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::D5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D6, ARM::S13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::D0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D13, ARM::S27,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q10, ARM::D21,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S26,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::D6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D7, ARM::S14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::D1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D14, ARM::S28,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q11, ARM::D22,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S27,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::D7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D7, ARM::S15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D14, ARM::S29,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q11, ARM::D23,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::D10,
+ ARM::Q7, ARM::S28,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::D8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D8, ARM::S16,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D1, ARM::S3,
+ ARM::Q4, ARM::S16,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q12, ARM::D24,
+ ARM::Q5, ARM::D11,
+ ARM::Q7, ARM::S29,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::D9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D8, ARM::S17,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::S3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S17,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D15, ARM::S30,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q12, ARM::D25,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::D12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D9, ARM::S18,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S18,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D15, ARM::S31,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q13, ARM::D26,
+ ARM::Q6, ARM::D13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q7, ARM::S30,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D9, ARM::S19,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D1, ARM::S2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S19,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q13, ARM::D27,
+ ARM::Q7, ARM::S31,
+ ARM::D2, ARM::S4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q7, ARM::D14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::S2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D10, ARM::S20,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q14, ARM::D28,
+ ARM::D2, ARM::S5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q7, ARM::D15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D0, ARM::S0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D10, ARM::S21,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S20,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q14, ARM::D29,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q8, ARM::D16,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D3, ARM::S6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D0, ARM::S1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::S0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D11, ARM::S22,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S21,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::D3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q8, ARM::D17,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D3, ARM::S7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::S1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D11, ARM::S23,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S22,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q15, ARM::D30,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q9, ARM::D18,
+ ARM::D5, ARM::S10,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D4, ARM::S8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ARM::NoRegister, ARM::NoRegister };
+ const unsigned SubregHashTableSize = 512;
+
+
+ // Number of hash collisions: 18
+ const unsigned SuperregHashTable[] = { ARM::D24, ARM::Q12,
+ ARM::D25, ARM::Q12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D26, ARM::Q13,
+ ARM::D27, ARM::Q13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D28, ARM::Q14,
+ ARM::D29, ARM::Q14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S4, ARM::D2,
+ ARM::S5, ARM::D2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S8, ARM::D4,
+ ARM::S9, ARM::D4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S10, ARM::D5,
+ ARM::D30, ARM::Q15,
+ ARM::D31, ARM::Q15,
+ ARM::S11, ARM::D5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S0, ARM::D0,
+ ARM::S1, ARM::D0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S12, ARM::D6,
+ ARM::D4, ARM::Q2,
+ ARM::D5, ARM::Q2,
+ ARM::S13, ARM::D6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S2, ARM::D1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S14, ARM::D7,
+ ARM::D6, ARM::Q3,
+ ARM::D7, ARM::Q3,
+ ARM::S11, ARM::Q2,
+ ARM::S10, ARM::Q2,
+ ARM::S3, ARM::D1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S15, ARM::D7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S8, ARM::Q2,
+ ARM::S9, ARM::Q2,
+ ARM::S20, ARM::D10,
+ ARM::S21, ARM::D10,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S16, ARM::D8,
+ ARM::D8, ARM::Q4,
+ ARM::D9, ARM::Q4,
+ ARM::S13, ARM::Q3,
+ ARM::S12, ARM::Q3,
+ ARM::S15, ARM::Q3,
+ ARM::S14, ARM::Q3,
+ ARM::S17, ARM::D8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D10, ARM::Q5,
+ ARM::D11, ARM::Q5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S22, ARM::D11,
+ ARM::S23, ARM::D11,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S18, ARM::D9,
+ ARM::S19, ARM::D9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S16, ARM::Q4,
+ ARM::S17, ARM::Q4,
+ ARM::S18, ARM::Q4,
+ ARM::S19, ARM::Q4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D12, ARM::Q6,
+ ARM::D13, ARM::Q6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S24, ARM::D12,
+ ARM::S25, ARM::D12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S20, ARM::Q5,
+ ARM::S21, ARM::Q5,
+ ARM::S22, ARM::Q5,
+ ARM::D14, ARM::Q7,
+ ARM::D15, ARM::Q7,
+ ARM::S23, ARM::Q5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S26, ARM::D13,
+ ARM::S27, ARM::D13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D0, ARM::Q0,
+ ARM::D1, ARM::Q0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S24, ARM::Q6,
+ ARM::D16, ARM::Q8,
+ ARM::D17, ARM::Q8,
+ ARM::S25, ARM::Q6,
+ ARM::S26, ARM::Q6,
+ ARM::S27, ARM::Q6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S28, ARM::D14,
+ ARM::S29, ARM::D14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D2, ARM::Q1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D18, ARM::Q9,
+ ARM::D19, ARM::Q9,
+ ARM::S29, ARM::Q7,
+ ARM::S28, ARM::Q7,
+ ARM::S30, ARM::Q7,
+ ARM::S31, ARM::Q7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D3, ARM::Q1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S0, ARM::Q0,
+ ARM::S1, ARM::Q0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S2, ARM::Q0,
+ ARM::S31, ARM::D15,
+ ARM::S30, ARM::D15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D20, ARM::Q10,
+ ARM::D21, ARM::Q10,
+ ARM::S3, ARM::Q0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D22, ARM::Q11,
+ ARM::D23, ARM::Q11,
+ ARM::S5, ARM::Q1,
+ ARM::S4, ARM::Q1,
+ ARM::S7, ARM::Q1,
+ ARM::S6, ARM::Q1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S6, ARM::D3,
+ ARM::S7, ARM::D3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ARM::NoRegister, ARM::NoRegister };
+ const unsigned SuperregHashTableSize = 512;
+
+
+ // Number of hash collisions: 38
+ const unsigned AliasesHashTable[] = { ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D12, ARM::S24,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S23,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q15, ARM::D31,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D12, ARM::S25,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S24,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::D4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D13, ARM::S26,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S25,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::D5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S8, ARM::D4,
+ ARM::S9, ARM::D4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::D0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D13, ARM::S27,
+ ARM::S11, ARM::D5,
+ ARM::S10, ARM::D5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S26,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::D6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S0, ARM::D0,
+ ARM::S1, ARM::D0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::D1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D14, ARM::S28,
+ ARM::S12, ARM::D6,
+ ARM::S13, ARM::D6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::S27,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::D7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S2, ARM::D1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D14, ARM::S29,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S14, ARM::D7,
+ ARM::Q5, ARM::D10,
+ ARM::Q7, ARM::S28,
+ ARM::S15, ARM::D7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S3, ARM::D1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::D8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D1, ARM::S3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S20, ARM::D10,
+ ARM::S21, ARM::D10,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::D11,
+ ARM::Q7, ARM::S29,
+ ARM::S17, ARM::D8,
+ ARM::S16, ARM::D8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::D9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::S3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S22, ARM::D11,
+ ARM::D15, ARM::S30,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S23, ARM::D11,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::D12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S18, ARM::D9,
+ ARM::S19, ARM::D9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D15, ARM::S31,
+ ARM::S24, ARM::D12,
+ ARM::S25, ARM::D12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q6, ARM::D13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q7, ARM::S30,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S26, ARM::D13,
+ ARM::Q7, ARM::S31,
+ ARM::D2, ARM::S4,
+ ARM::D0, ARM::Q0,
+ ARM::D1, ARM::Q0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S27, ARM::D13,
+ ARM::Q7, ARM::D14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D2, ARM::S5,
+ ARM::S29, ARM::D14,
+ ARM::Q7, ARM::D15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S28, ARM::D14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D0, ARM::S0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D2, ARM::Q1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D3, ARM::Q1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S0, ARM::Q0,
+ ARM::S1, ARM::Q0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q8, ARM::D16,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S2, ARM::Q0,
+ ARM::S31, ARM::D15,
+ ARM::S30, ARM::D15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D3, ARM::S6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D0, ARM::S1,
+ ARM::D20, ARM::Q10,
+ ARM::D21, ARM::Q10,
+ ARM::S3, ARM::Q0,
+ ARM::Q0, ARM::S0,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q8, ARM::D17,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D3, ARM::S7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q0, ARM::S1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D22, ARM::Q11,
+ ARM::D23, ARM::Q11,
+ ARM::S5, ARM::Q1,
+ ARM::S4, ARM::Q1,
+ ARM::S7, ARM::Q1,
+ ARM::S6, ARM::Q1,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::S7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q9, ARM::D18,
+ ARM::D5, ARM::S10,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D4, ARM::S8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D24, ARM::Q12,
+ ARM::D25, ARM::Q12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S10,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S8,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q9, ARM::D19,
+ ARM::D5, ARM::S11,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D4, ARM::S9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S11,
+ ARM::D26, ARM::Q13,
+ ARM::D27, ARM::Q13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::D2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q2, ARM::S9,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D6, ARM::S12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S12,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D28, ARM::Q14,
+ ARM::D29, ARM::Q14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q10, ARM::D20,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D6, ARM::S13,
+ ARM::S4, ARM::D2,
+ ARM::S5, ARM::D2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S13,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D30, ARM::Q15,
+ ARM::D31, ARM::Q15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q10, ARM::D21,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D7, ARM::S14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S14,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D4, ARM::Q2,
+ ARM::D5, ARM::Q2,
+ ARM::Q11, ARM::D22,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D7, ARM::S15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q3, ARM::S15,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q11, ARM::D23,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D6, ARM::Q3,
+ ARM::D7, ARM::Q3,
+ ARM::S11, ARM::Q2,
+ ARM::S10, ARM::Q2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D8, ARM::S16,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S16,
+ ARM::S9, ARM::Q2,
+ ARM::S8, ARM::Q2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q12, ARM::D24,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D8, ARM::Q4,
+ ARM::D9, ARM::Q4,
+ ARM::S13, ARM::Q3,
+ ARM::S12, ARM::Q3,
+ ARM::S15, ARM::Q3,
+ ARM::S14, ARM::Q3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D10, ARM::Q5,
+ ARM::D11, ARM::Q5,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D8, ARM::S17,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S17,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q12, ARM::D25,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S16, ARM::Q4,
+ ARM::S17, ARM::Q4,
+ ARM::S18, ARM::Q4,
+ ARM::S19, ARM::Q4,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D12, ARM::Q6,
+ ARM::D13, ARM::Q6,
+ ARM::D9, ARM::S18,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S18,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q13, ARM::D26,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S20, ARM::Q5,
+ ARM::S21, ARM::Q5,
+ ARM::S22, ARM::Q5,
+ ARM::D14, ARM::Q7,
+ ARM::D15, ARM::Q7,
+ ARM::D9, ARM::S19,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S23, ARM::Q5,
+ ARM::D1, ARM::S2,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q4, ARM::S19,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q13, ARM::D27,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S24, ARM::Q6,
+ ARM::D16, ARM::Q8,
+ ARM::D17, ARM::Q8,
+ ARM::Q0, ARM::S2,
+ ARM::S26, ARM::Q6,
+ ARM::S27, ARM::Q6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D10, ARM::S20,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S25, ARM::Q6,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q14, ARM::D28,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D18, ARM::Q9,
+ ARM::D19, ARM::Q9,
+ ARM::S29, ARM::Q7,
+ ARM::S28, ARM::Q7,
+ ARM::D10, ARM::S21,
+ ARM::S31, ARM::Q7,
+ ARM::S30, ARM::Q7,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S20,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q14, ARM::D29,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D11, ARM::S22,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S21,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q1, ARM::D3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::D11, ARM::S23,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q5, ARM::S22,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::Q15, ARM::D30,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::S6, ARM::D3,
+ ARM::S7, ARM::D3,
+ ARM::NoRegister, ARM::NoRegister,
+ ARM::NoRegister, ARM::NoRegister,
+ARM::NoRegister, ARM::NoRegister };
+ const unsigned AliasesHashTableSize = 1024;
+
+
+ // Register Alias Sets...
+ const unsigned Empty_AliasSet[] = { 0 };
+ const unsigned CPSR_AliasSet[] = { 0 };
+ const unsigned D0_AliasSet[] = { ARM::S0, ARM::S1, ARM::Q0, 0 };
+ const unsigned D1_AliasSet[] = { ARM::S2, ARM::S3, ARM::Q0, 0 };
+ const unsigned D10_AliasSet[] = { ARM::S20, ARM::S21, ARM::Q5, 0 };
+ const unsigned D11_AliasSet[] = { ARM::S22, ARM::S23, ARM::Q5, 0 };
+ const unsigned D12_AliasSet[] = { ARM::S24, ARM::S25, ARM::Q6, 0 };
+ const unsigned D13_AliasSet[] = { ARM::S26, ARM::S27, ARM::Q6, 0 };
+ const unsigned D14_AliasSet[] = { ARM::S28, ARM::S29, ARM::Q7, 0 };
+ const unsigned D15_AliasSet[] = { ARM::S30, ARM::S31, ARM::Q7, 0 };
+ const unsigned D16_AliasSet[] = { ARM::Q8, 0 };
+ const unsigned D17_AliasSet[] = { ARM::Q8, 0 };
+ const unsigned D18_AliasSet[] = { ARM::Q9, 0 };
+ const unsigned D19_AliasSet[] = { ARM::Q9, 0 };
+ const unsigned D2_AliasSet[] = { ARM::S4, ARM::S5, ARM::Q1, 0 };
+ const unsigned D20_AliasSet[] = { ARM::Q10, 0 };
+ const unsigned D21_AliasSet[] = { ARM::Q10, 0 };
+ const unsigned D22_AliasSet[] = { ARM::Q11, 0 };
+ const unsigned D23_AliasSet[] = { ARM::Q11, 0 };
+ const unsigned D24_AliasSet[] = { ARM::Q12, 0 };
+ const unsigned D25_AliasSet[] = { ARM::Q12, 0 };
+ const unsigned D26_AliasSet[] = { ARM::Q13, 0 };
+ const unsigned D27_AliasSet[] = { ARM::Q13, 0 };
+ const unsigned D28_AliasSet[] = { ARM::Q14, 0 };
+ const unsigned D29_AliasSet[] = { ARM::Q14, 0 };
+ const unsigned D3_AliasSet[] = { ARM::S6, ARM::S7, ARM::Q1, 0 };
+ const unsigned D30_AliasSet[] = { ARM::Q15, 0 };
+ const unsigned D31_AliasSet[] = { ARM::Q15, 0 };
+ const unsigned D4_AliasSet[] = { ARM::S8, ARM::S9, ARM::Q2, 0 };
+ const unsigned D5_AliasSet[] = { ARM::S10, ARM::S11, ARM::Q2, 0 };
+ const unsigned D6_AliasSet[] = { ARM::S12, ARM::S13, ARM::Q3, 0 };
+ const unsigned D7_AliasSet[] = { ARM::S14, ARM::S15, ARM::Q3, 0 };
+ const unsigned D8_AliasSet[] = { ARM::S16, ARM::S17, ARM::Q4, 0 };
+ const unsigned D9_AliasSet[] = { ARM::S18, ARM::S19, ARM::Q4, 0 };
+ const unsigned FPSCR_AliasSet[] = { 0 };
+ const unsigned LR_AliasSet[] = { 0 };
+ const unsigned PC_AliasSet[] = { 0 };
+ const unsigned Q0_AliasSet[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::D0, ARM::D1, 0 };
+ const unsigned Q1_AliasSet[] = { ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::D2, ARM::D3, 0 };
+ const unsigned Q10_AliasSet[] = { ARM::D20, ARM::D21, 0 };
+ const unsigned Q11_AliasSet[] = { ARM::D22, ARM::D23, 0 };
+ const unsigned Q12_AliasSet[] = { ARM::D24, ARM::D25, 0 };
+ const unsigned Q13_AliasSet[] = { ARM::D26, ARM::D27, 0 };
+ const unsigned Q14_AliasSet[] = { ARM::D28, ARM::D29, 0 };
+ const unsigned Q15_AliasSet[] = { ARM::D30, ARM::D31, 0 };
+ const unsigned Q2_AliasSet[] = { ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::D4, ARM::D5, 0 };
+ const unsigned Q3_AliasSet[] = { ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::D6, ARM::D7, 0 };
+ const unsigned Q4_AliasSet[] = { ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::D8, ARM::D9, 0 };
+ const unsigned Q5_AliasSet[] = { ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::D10, ARM::D11, 0 };
+ const unsigned Q6_AliasSet[] = { ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::D12, ARM::D13, 0 };
+ const unsigned Q7_AliasSet[] = { ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D14, ARM::D15, 0 };
+ const unsigned Q8_AliasSet[] = { ARM::D16, ARM::D17, 0 };
+ const unsigned Q9_AliasSet[] = { ARM::D18, ARM::D19, 0 };
+ const unsigned R0_AliasSet[] = { 0 };
+ const unsigned R1_AliasSet[] = { 0 };
+ const unsigned R10_AliasSet[] = { 0 };
+ const unsigned R11_AliasSet[] = { 0 };
+ const unsigned R12_AliasSet[] = { 0 };
+ const unsigned R2_AliasSet[] = { 0 };
+ const unsigned R3_AliasSet[] = { 0 };
+ const unsigned R4_AliasSet[] = { 0 };
+ const unsigned R5_AliasSet[] = { 0 };
+ const unsigned R6_AliasSet[] = { 0 };
+ const unsigned R7_AliasSet[] = { 0 };
+ const unsigned R8_AliasSet[] = { 0 };
+ const unsigned R9_AliasSet[] = { 0 };
+ const unsigned S0_AliasSet[] = { ARM::D0, ARM::Q0, 0 };
+ const unsigned S1_AliasSet[] = { ARM::D0, ARM::Q0, 0 };
+ const unsigned S10_AliasSet[] = { ARM::D5, ARM::Q2, 0 };
+ const unsigned S11_AliasSet[] = { ARM::D5, ARM::Q2, 0 };
+ const unsigned S12_AliasSet[] = { ARM::D6, ARM::Q3, 0 };
+ const unsigned S13_AliasSet[] = { ARM::D6, ARM::Q3, 0 };
+ const unsigned S14_AliasSet[] = { ARM::D7, ARM::Q3, 0 };
+ const unsigned S15_AliasSet[] = { ARM::D7, ARM::Q3, 0 };
+ const unsigned S16_AliasSet[] = { ARM::D8, ARM::Q4, 0 };
+ const unsigned S17_AliasSet[] = { ARM::D8, ARM::Q4, 0 };
+ const unsigned S18_AliasSet[] = { ARM::D9, ARM::Q4, 0 };
+ const unsigned S19_AliasSet[] = { ARM::D9, ARM::Q4, 0 };
+ const unsigned S2_AliasSet[] = { ARM::D1, ARM::Q0, 0 };
+ const unsigned S20_AliasSet[] = { ARM::D10, ARM::Q5, 0 };
+ const unsigned S21_AliasSet[] = { ARM::D10, ARM::Q5, 0 };
+ const unsigned S22_AliasSet[] = { ARM::D11, ARM::Q5, 0 };
+ const unsigned S23_AliasSet[] = { ARM::D11, ARM::Q5, 0 };
+ const unsigned S24_AliasSet[] = { ARM::D12, ARM::Q6, 0 };
+ const unsigned S25_AliasSet[] = { ARM::D12, ARM::Q6, 0 };
+ const unsigned S26_AliasSet[] = { ARM::D13, ARM::Q6, 0 };
+ const unsigned S27_AliasSet[] = { ARM::D13, ARM::Q6, 0 };
+ const unsigned S28_AliasSet[] = { ARM::D14, ARM::Q7, 0 };
+ const unsigned S29_AliasSet[] = { ARM::D14, ARM::Q7, 0 };
+ const unsigned S3_AliasSet[] = { ARM::D1, ARM::Q0, 0 };
+ const unsigned S30_AliasSet[] = { ARM::D15, ARM::Q7, 0 };
+ const unsigned S31_AliasSet[] = { ARM::D15, ARM::Q7, 0 };
+ const unsigned S4_AliasSet[] = { ARM::D2, ARM::Q1, 0 };
+ const unsigned S5_AliasSet[] = { ARM::D2, ARM::Q1, 0 };
+ const unsigned S6_AliasSet[] = { ARM::D3, ARM::Q1, 0 };
+ const unsigned S7_AliasSet[] = { ARM::D3, ARM::Q1, 0 };
+ const unsigned S8_AliasSet[] = { ARM::D4, ARM::Q2, 0 };
+ const unsigned S9_AliasSet[] = { ARM::D4, ARM::Q2, 0 };
+ const unsigned SDummy_AliasSet[] = { 0 };
+ const unsigned SP_AliasSet[] = { 0 };
+
+
+ // Register Sub-registers Sets...
+ const unsigned Empty_SubRegsSet[] = { 0 };
+ const unsigned CPSR_SubRegsSet[] = { 0 };
+ const unsigned D0_SubRegsSet[] = { ARM::S0, ARM::S1, 0 };
+ const unsigned D1_SubRegsSet[] = { ARM::S2, ARM::S3, 0 };
+ const unsigned D10_SubRegsSet[] = { ARM::S20, ARM::S21, 0 };
+ const unsigned D11_SubRegsSet[] = { ARM::S22, ARM::S23, 0 };
+ const unsigned D12_SubRegsSet[] = { ARM::S24, ARM::S25, 0 };
+ const unsigned D13_SubRegsSet[] = { ARM::S26, ARM::S27, 0 };
+ const unsigned D14_SubRegsSet[] = { ARM::S28, ARM::S29, 0 };
+ const unsigned D15_SubRegsSet[] = { ARM::S30, ARM::S31, 0 };
+ const unsigned D16_SubRegsSet[] = { 0 };
+ const unsigned D17_SubRegsSet[] = { 0 };
+ const unsigned D18_SubRegsSet[] = { 0 };
+ const unsigned D19_SubRegsSet[] = { 0 };
+ const unsigned D2_SubRegsSet[] = { ARM::S4, ARM::S5, 0 };
+ const unsigned D20_SubRegsSet[] = { 0 };
+ const unsigned D21_SubRegsSet[] = { 0 };
+ const unsigned D22_SubRegsSet[] = { 0 };
+ const unsigned D23_SubRegsSet[] = { 0 };
+ const unsigned D24_SubRegsSet[] = { 0 };
+ const unsigned D25_SubRegsSet[] = { 0 };
+ const unsigned D26_SubRegsSet[] = { 0 };
+ const unsigned D27_SubRegsSet[] = { 0 };
+ const unsigned D28_SubRegsSet[] = { 0 };
+ const unsigned D29_SubRegsSet[] = { 0 };
+ const unsigned D3_SubRegsSet[] = { ARM::S6, ARM::S7, 0 };
+ const unsigned D30_SubRegsSet[] = { 0 };
+ const unsigned D31_SubRegsSet[] = { 0 };
+ const unsigned D4_SubRegsSet[] = { ARM::S8, ARM::S9, 0 };
+ const unsigned D5_SubRegsSet[] = { ARM::S10, ARM::S11, 0 };
+ const unsigned D6_SubRegsSet[] = { ARM::S12, ARM::S13, 0 };
+ const unsigned D7_SubRegsSet[] = { ARM::S14, ARM::S15, 0 };
+ const unsigned D8_SubRegsSet[] = { ARM::S16, ARM::S17, 0 };
+ const unsigned D9_SubRegsSet[] = { ARM::S18, ARM::S19, 0 };
+ const unsigned FPSCR_SubRegsSet[] = { 0 };
+ const unsigned LR_SubRegsSet[] = { 0 };
+ const unsigned PC_SubRegsSet[] = { 0 };
+ const unsigned Q0_SubRegsSet[] = { ARM::S0, ARM::S1, ARM::D1, ARM::S2, ARM::S3, ARM::D0, 0 };
+ const unsigned Q1_SubRegsSet[] = { ARM::S4, ARM::S5, ARM::D3, ARM::S6, ARM::S7, ARM::D2, 0 };
+ const unsigned Q10_SubRegsSet[] = { ARM::D20, ARM::D21, 0 };
+ const unsigned Q11_SubRegsSet[] = { ARM::D22, ARM::D23, 0 };
+ const unsigned Q12_SubRegsSet[] = { ARM::D24, ARM::D25, 0 };
+ const unsigned Q13_SubRegsSet[] = { ARM::D26, ARM::D27, 0 };
+ const unsigned Q14_SubRegsSet[] = { ARM::D28, ARM::D29, 0 };
+ const unsigned Q15_SubRegsSet[] = { ARM::D30, ARM::D31, 0 };
+ const unsigned Q2_SubRegsSet[] = { ARM::S8, ARM::S9, ARM::D5, ARM::S10, ARM::S11, ARM::D4, 0 };
+ const unsigned Q3_SubRegsSet[] = { ARM::S12, ARM::S13, ARM::D7, ARM::S14, ARM::S15, ARM::D6, 0 };
+ const unsigned Q4_SubRegsSet[] = { ARM::S16, ARM::S17, ARM::D9, ARM::S18, ARM::S19, ARM::D8, 0 };
+ const unsigned Q5_SubRegsSet[] = { ARM::S20, ARM::S21, ARM::D11, ARM::S22, ARM::S23, ARM::D10, 0 };
+ const unsigned Q6_SubRegsSet[] = { ARM::S24, ARM::S25, ARM::D13, ARM::S26, ARM::S27, ARM::D12, 0 };
+ const unsigned Q7_SubRegsSet[] = { ARM::S28, ARM::S29, ARM::D15, ARM::S30, ARM::S31, ARM::D14, 0 };
+ const unsigned Q8_SubRegsSet[] = { ARM::D16, ARM::D17, 0 };
+ const unsigned Q9_SubRegsSet[] = { ARM::D18, ARM::D19, 0 };
+ const unsigned R0_SubRegsSet[] = { 0 };
+ const unsigned R1_SubRegsSet[] = { 0 };
+ const unsigned R10_SubRegsSet[] = { 0 };
+ const unsigned R11_SubRegsSet[] = { 0 };
+ const unsigned R12_SubRegsSet[] = { 0 };
+ const unsigned R2_SubRegsSet[] = { 0 };
+ const unsigned R3_SubRegsSet[] = { 0 };
+ const unsigned R4_SubRegsSet[] = { 0 };
+ const unsigned R5_SubRegsSet[] = { 0 };
+ const unsigned R6_SubRegsSet[] = { 0 };
+ const unsigned R7_SubRegsSet[] = { 0 };
+ const unsigned R8_SubRegsSet[] = { 0 };
+ const unsigned R9_SubRegsSet[] = { 0 };
+ const unsigned S0_SubRegsSet[] = { 0 };
+ const unsigned S1_SubRegsSet[] = { 0 };
+ const unsigned S10_SubRegsSet[] = { 0 };
+ const unsigned S11_SubRegsSet[] = { 0 };
+ const unsigned S12_SubRegsSet[] = { 0 };
+ const unsigned S13_SubRegsSet[] = { 0 };
+ const unsigned S14_SubRegsSet[] = { 0 };
+ const unsigned S15_SubRegsSet[] = { 0 };
+ const unsigned S16_SubRegsSet[] = { 0 };
+ const unsigned S17_SubRegsSet[] = { 0 };
+ const unsigned S18_SubRegsSet[] = { 0 };
+ const unsigned S19_SubRegsSet[] = { 0 };
+ const unsigned S2_SubRegsSet[] = { 0 };
+ const unsigned S20_SubRegsSet[] = { 0 };
+ const unsigned S21_SubRegsSet[] = { 0 };
+ const unsigned S22_SubRegsSet[] = { 0 };
+ const unsigned S23_SubRegsSet[] = { 0 };
+ const unsigned S24_SubRegsSet[] = { 0 };
+ const unsigned S25_SubRegsSet[] = { 0 };
+ const unsigned S26_SubRegsSet[] = { 0 };
+ const unsigned S27_SubRegsSet[] = { 0 };
+ const unsigned S28_SubRegsSet[] = { 0 };
+ const unsigned S29_SubRegsSet[] = { 0 };
+ const unsigned S3_SubRegsSet[] = { 0 };
+ const unsigned S30_SubRegsSet[] = { 0 };
+ const unsigned S31_SubRegsSet[] = { 0 };
+ const unsigned S4_SubRegsSet[] = { 0 };
+ const unsigned S5_SubRegsSet[] = { 0 };
+ const unsigned S6_SubRegsSet[] = { 0 };
+ const unsigned S7_SubRegsSet[] = { 0 };
+ const unsigned S8_SubRegsSet[] = { 0 };
+ const unsigned S9_SubRegsSet[] = { 0 };
+ const unsigned SDummy_SubRegsSet[] = { 0 };
+ const unsigned SP_SubRegsSet[] = { 0 };
+
+
+ // Register Super-registers Sets...
+ const unsigned Empty_SuperRegsSet[] = { 0 };
+ const unsigned CPSR_SuperRegsSet[] = { 0 };
+ const unsigned D0_SuperRegsSet[] = { ARM::Q0, 0 };
+ const unsigned D1_SuperRegsSet[] = { ARM::Q0, 0 };
+ const unsigned D10_SuperRegsSet[] = { ARM::Q5, 0 };
+ const unsigned D11_SuperRegsSet[] = { ARM::Q5, 0 };
+ const unsigned D12_SuperRegsSet[] = { ARM::Q6, 0 };
+ const unsigned D13_SuperRegsSet[] = { ARM::Q6, 0 };
+ const unsigned D14_SuperRegsSet[] = { ARM::Q7, 0 };
+ const unsigned D15_SuperRegsSet[] = { ARM::Q7, 0 };
+ const unsigned D16_SuperRegsSet[] = { ARM::Q8, 0 };
+ const unsigned D17_SuperRegsSet[] = { ARM::Q8, 0 };
+ const unsigned D18_SuperRegsSet[] = { ARM::Q9, 0 };
+ const unsigned D19_SuperRegsSet[] = { ARM::Q9, 0 };
+ const unsigned D2_SuperRegsSet[] = { ARM::Q1, 0 };
+ const unsigned D20_SuperRegsSet[] = { ARM::Q10, 0 };
+ const unsigned D21_SuperRegsSet[] = { ARM::Q10, 0 };
+ const unsigned D22_SuperRegsSet[] = { ARM::Q11, 0 };
+ const unsigned D23_SuperRegsSet[] = { ARM::Q11, 0 };
+ const unsigned D24_SuperRegsSet[] = { ARM::Q12, 0 };
+ const unsigned D25_SuperRegsSet[] = { ARM::Q12, 0 };
+ const unsigned D26_SuperRegsSet[] = { ARM::Q13, 0 };
+ const unsigned D27_SuperRegsSet[] = { ARM::Q13, 0 };
+ const unsigned D28_SuperRegsSet[] = { ARM::Q14, 0 };
+ const unsigned D29_SuperRegsSet[] = { ARM::Q14, 0 };
+ const unsigned D3_SuperRegsSet[] = { ARM::Q1, 0 };
+ const unsigned D30_SuperRegsSet[] = { ARM::Q15, 0 };
+ const unsigned D31_SuperRegsSet[] = { ARM::Q15, 0 };
+ const unsigned D4_SuperRegsSet[] = { ARM::Q2, 0 };
+ const unsigned D5_SuperRegsSet[] = { ARM::Q2, 0 };
+ const unsigned D6_SuperRegsSet[] = { ARM::Q3, 0 };
+ const unsigned D7_SuperRegsSet[] = { ARM::Q3, 0 };
+ const unsigned D8_SuperRegsSet[] = { ARM::Q4, 0 };
+ const unsigned D9_SuperRegsSet[] = { ARM::Q4, 0 };
+ const unsigned FPSCR_SuperRegsSet[] = { 0 };
+ const unsigned LR_SuperRegsSet[] = { 0 };
+ const unsigned PC_SuperRegsSet[] = { 0 };
+ const unsigned Q0_SuperRegsSet[] = { 0 };
+ const unsigned Q1_SuperRegsSet[] = { 0 };
+ const unsigned Q10_SuperRegsSet[] = { 0 };
+ const unsigned Q11_SuperRegsSet[] = { 0 };
+ const unsigned Q12_SuperRegsSet[] = { 0 };
+ const unsigned Q13_SuperRegsSet[] = { 0 };
+ const unsigned Q14_SuperRegsSet[] = { 0 };
+ const unsigned Q15_SuperRegsSet[] = { 0 };
+ const unsigned Q2_SuperRegsSet[] = { 0 };
+ const unsigned Q3_SuperRegsSet[] = { 0 };
+ const unsigned Q4_SuperRegsSet[] = { 0 };
+ const unsigned Q5_SuperRegsSet[] = { 0 };
+ const unsigned Q6_SuperRegsSet[] = { 0 };
+ const unsigned Q7_SuperRegsSet[] = { 0 };
+ const unsigned Q8_SuperRegsSet[] = { 0 };
+ const unsigned Q9_SuperRegsSet[] = { 0 };
+ const unsigned R0_SuperRegsSet[] = { 0 };
+ const unsigned R1_SuperRegsSet[] = { 0 };
+ const unsigned R10_SuperRegsSet[] = { 0 };
+ const unsigned R11_SuperRegsSet[] = { 0 };
+ const unsigned R12_SuperRegsSet[] = { 0 };
+ const unsigned R2_SuperRegsSet[] = { 0 };
+ const unsigned R3_SuperRegsSet[] = { 0 };
+ const unsigned R4_SuperRegsSet[] = { 0 };
+ const unsigned R5_SuperRegsSet[] = { 0 };
+ const unsigned R6_SuperRegsSet[] = { 0 };
+ const unsigned R7_SuperRegsSet[] = { 0 };
+ const unsigned R8_SuperRegsSet[] = { 0 };
+ const unsigned R9_SuperRegsSet[] = { 0 };
+ const unsigned S0_SuperRegsSet[] = { ARM::Q0, ARM::D0, 0 };
+ const unsigned S1_SuperRegsSet[] = { ARM::Q0, ARM::D0, 0 };
+ const unsigned S10_SuperRegsSet[] = { ARM::Q2, ARM::D5, 0 };
+ const unsigned S11_SuperRegsSet[] = { ARM::Q2, ARM::D5, 0 };
+ const unsigned S12_SuperRegsSet[] = { ARM::Q3, ARM::D6, 0 };
+ const unsigned S13_SuperRegsSet[] = { ARM::Q3, ARM::D6, 0 };
+ const unsigned S14_SuperRegsSet[] = { ARM::Q3, ARM::D7, 0 };
+ const unsigned S15_SuperRegsSet[] = { ARM::Q3, ARM::D7, 0 };
+ const unsigned S16_SuperRegsSet[] = { ARM::Q4, ARM::D8, 0 };
+ const unsigned S17_SuperRegsSet[] = { ARM::Q4, ARM::D8, 0 };
+ const unsigned S18_SuperRegsSet[] = { ARM::Q4, ARM::D9, 0 };
+ const unsigned S19_SuperRegsSet[] = { ARM::Q4, ARM::D9, 0 };
+ const unsigned S2_SuperRegsSet[] = { ARM::Q0, ARM::D1, 0 };
+ const unsigned S20_SuperRegsSet[] = { ARM::Q5, ARM::D10, 0 };
+ const unsigned S21_SuperRegsSet[] = { ARM::Q5, ARM::D10, 0 };
+ const unsigned S22_SuperRegsSet[] = { ARM::Q5, ARM::D11, 0 };
+ const unsigned S23_SuperRegsSet[] = { ARM::Q5, ARM::D11, 0 };
+ const unsigned S24_SuperRegsSet[] = { ARM::Q6, ARM::D12, 0 };
+ const unsigned S25_SuperRegsSet[] = { ARM::Q6, ARM::D12, 0 };
+ const unsigned S26_SuperRegsSet[] = { ARM::Q6, ARM::D13, 0 };
+ const unsigned S27_SuperRegsSet[] = { ARM::Q6, ARM::D13, 0 };
+ const unsigned S28_SuperRegsSet[] = { ARM::Q7, ARM::D14, 0 };
+ const unsigned S29_SuperRegsSet[] = { ARM::Q7, ARM::D14, 0 };
+ const unsigned S3_SuperRegsSet[] = { ARM::Q0, ARM::D1, 0 };
+ const unsigned S30_SuperRegsSet[] = { ARM::Q7, ARM::D15, 0 };
+ const unsigned S31_SuperRegsSet[] = { ARM::Q7, ARM::D15, 0 };
+ const unsigned S4_SuperRegsSet[] = { ARM::Q1, ARM::D2, 0 };
+ const unsigned S5_SuperRegsSet[] = { ARM::Q1, ARM::D2, 0 };
+ const unsigned S6_SuperRegsSet[] = { ARM::Q1, ARM::D3, 0 };
+ const unsigned S7_SuperRegsSet[] = { ARM::Q1, ARM::D3, 0 };
+ const unsigned S8_SuperRegsSet[] = { ARM::Q2, ARM::D4, 0 };
+ const unsigned S9_SuperRegsSet[] = { ARM::Q2, ARM::D4, 0 };
+ const unsigned SDummy_SuperRegsSet[] = { 0 };
+ const unsigned SP_SuperRegsSet[] = { 0 };
+
+ const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors
+ { "NOREG", 0, 0, 0 },
+ { "CPSR", CPSR_AliasSet, CPSR_SubRegsSet, CPSR_SuperRegsSet },
+ { "D0", D0_AliasSet, D0_SubRegsSet, D0_SuperRegsSet },
+ { "D1", D1_AliasSet, D1_SubRegsSet, D1_SuperRegsSet },
+ { "D10", D10_AliasSet, D10_SubRegsSet, D10_SuperRegsSet },
+ { "D11", D11_AliasSet, D11_SubRegsSet, D11_SuperRegsSet },
+ { "D12", D12_AliasSet, D12_SubRegsSet, D12_SuperRegsSet },
+ { "D13", D13_AliasSet, D13_SubRegsSet, D13_SuperRegsSet },
+ { "D14", D14_AliasSet, D14_SubRegsSet, D14_SuperRegsSet },
+ { "D15", D15_AliasSet, D15_SubRegsSet, D15_SuperRegsSet },
+ { "D16", D16_AliasSet, D16_SubRegsSet, D16_SuperRegsSet },
+ { "D17", D17_AliasSet, D17_SubRegsSet, D17_SuperRegsSet },
+ { "D18", D18_AliasSet, D18_SubRegsSet, D18_SuperRegsSet },
+ { "D19", D19_AliasSet, D19_SubRegsSet, D19_SuperRegsSet },
+ { "D2", D2_AliasSet, D2_SubRegsSet, D2_SuperRegsSet },
+ { "D20", D20_AliasSet, D20_SubRegsSet, D20_SuperRegsSet },
+ { "D21", D21_AliasSet, D21_SubRegsSet, D21_SuperRegsSet },
+ { "D22", D22_AliasSet, D22_SubRegsSet, D22_SuperRegsSet },
+ { "D23", D23_AliasSet, D23_SubRegsSet, D23_SuperRegsSet },
+ { "D24", D24_AliasSet, D24_SubRegsSet, D24_SuperRegsSet },
+ { "D25", D25_AliasSet, D25_SubRegsSet, D25_SuperRegsSet },
+ { "D26", D26_AliasSet, D26_SubRegsSet, D26_SuperRegsSet },
+ { "D27", D27_AliasSet, D27_SubRegsSet, D27_SuperRegsSet },
+ { "D28", D28_AliasSet, D28_SubRegsSet, D28_SuperRegsSet },
+ { "D29", D29_AliasSet, D29_SubRegsSet, D29_SuperRegsSet },
+ { "D3", D3_AliasSet, D3_SubRegsSet, D3_SuperRegsSet },
+ { "D30", D30_AliasSet, D30_SubRegsSet, D30_SuperRegsSet },
+ { "D31", D31_AliasSet, D31_SubRegsSet, D31_SuperRegsSet },
+ { "D4", D4_AliasSet, D4_SubRegsSet, D4_SuperRegsSet },
+ { "D5", D5_AliasSet, D5_SubRegsSet, D5_SuperRegsSet },
+ { "D6", D6_AliasSet, D6_SubRegsSet, D6_SuperRegsSet },
+ { "D7", D7_AliasSet, D7_SubRegsSet, D7_SuperRegsSet },
+ { "D8", D8_AliasSet, D8_SubRegsSet, D8_SuperRegsSet },
+ { "D9", D9_AliasSet, D9_SubRegsSet, D9_SuperRegsSet },
+ { "FPSCR", FPSCR_AliasSet, FPSCR_SubRegsSet, FPSCR_SuperRegsSet },
+ { "LR", LR_AliasSet, LR_SubRegsSet, LR_SuperRegsSet },
+ { "PC", PC_AliasSet, PC_SubRegsSet, PC_SuperRegsSet },
+ { "Q0", Q0_AliasSet, Q0_SubRegsSet, Q0_SuperRegsSet },
+ { "Q1", Q1_AliasSet, Q1_SubRegsSet, Q1_SuperRegsSet },
+ { "Q10", Q10_AliasSet, Q10_SubRegsSet, Q10_SuperRegsSet },
+ { "Q11", Q11_AliasSet, Q11_SubRegsSet, Q11_SuperRegsSet },
+ { "Q12", Q12_AliasSet, Q12_SubRegsSet, Q12_SuperRegsSet },
+ { "Q13", Q13_AliasSet, Q13_SubRegsSet, Q13_SuperRegsSet },
+ { "Q14", Q14_AliasSet, Q14_SubRegsSet, Q14_SuperRegsSet },
+ { "Q15", Q15_AliasSet, Q15_SubRegsSet, Q15_SuperRegsSet },
+ { "Q2", Q2_AliasSet, Q2_SubRegsSet, Q2_SuperRegsSet },
+ { "Q3", Q3_AliasSet, Q3_SubRegsSet, Q3_SuperRegsSet },
+ { "Q4", Q4_AliasSet, Q4_SubRegsSet, Q4_SuperRegsSet },
+ { "Q5", Q5_AliasSet, Q5_SubRegsSet, Q5_SuperRegsSet },
+ { "Q6", Q6_AliasSet, Q6_SubRegsSet, Q6_SuperRegsSet },
+ { "Q7", Q7_AliasSet, Q7_SubRegsSet, Q7_SuperRegsSet },
+ { "Q8", Q8_AliasSet, Q8_SubRegsSet, Q8_SuperRegsSet },
+ { "Q9", Q9_AliasSet, Q9_SubRegsSet, Q9_SuperRegsSet },
+ { "R0", R0_AliasSet, R0_SubRegsSet, R0_SuperRegsSet },
+ { "R1", R1_AliasSet, R1_SubRegsSet, R1_SuperRegsSet },
+ { "R10", R10_AliasSet, R10_SubRegsSet, R10_SuperRegsSet },
+ { "R11", R11_AliasSet, R11_SubRegsSet, R11_SuperRegsSet },
+ { "R12", R12_AliasSet, R12_SubRegsSet, R12_SuperRegsSet },
+ { "R2", R2_AliasSet, R2_SubRegsSet, R2_SuperRegsSet },
+ { "R3", R3_AliasSet, R3_SubRegsSet, R3_SuperRegsSet },
+ { "R4", R4_AliasSet, R4_SubRegsSet, R4_SuperRegsSet },
+ { "R5", R5_AliasSet, R5_SubRegsSet, R5_SuperRegsSet },
+ { "R6", R6_AliasSet, R6_SubRegsSet, R6_SuperRegsSet },
+ { "R7", R7_AliasSet, R7_SubRegsSet, R7_SuperRegsSet },
+ { "R8", R8_AliasSet, R8_SubRegsSet, R8_SuperRegsSet },
+ { "R9", R9_AliasSet, R9_SubRegsSet, R9_SuperRegsSet },
+ { "S0", S0_AliasSet, S0_SubRegsSet, S0_SuperRegsSet },
+ { "S1", S1_AliasSet, S1_SubRegsSet, S1_SuperRegsSet },
+ { "S10", S10_AliasSet, S10_SubRegsSet, S10_SuperRegsSet },
+ { "S11", S11_AliasSet, S11_SubRegsSet, S11_SuperRegsSet },
+ { "S12", S12_AliasSet, S12_SubRegsSet, S12_SuperRegsSet },
+ { "S13", S13_AliasSet, S13_SubRegsSet, S13_SuperRegsSet },
+ { "S14", S14_AliasSet, S14_SubRegsSet, S14_SuperRegsSet },
+ { "S15", S15_AliasSet, S15_SubRegsSet, S15_SuperRegsSet },
+ { "S16", S16_AliasSet, S16_SubRegsSet, S16_SuperRegsSet },
+ { "S17", S17_AliasSet, S17_SubRegsSet, S17_SuperRegsSet },
+ { "S18", S18_AliasSet, S18_SubRegsSet, S18_SuperRegsSet },
+ { "S19", S19_AliasSet, S19_SubRegsSet, S19_SuperRegsSet },
+ { "S2", S2_AliasSet, S2_SubRegsSet, S2_SuperRegsSet },
+ { "S20", S20_AliasSet, S20_SubRegsSet, S20_SuperRegsSet },
+ { "S21", S21_AliasSet, S21_SubRegsSet, S21_SuperRegsSet },
+ { "S22", S22_AliasSet, S22_SubRegsSet, S22_SuperRegsSet },
+ { "S23", S23_AliasSet, S23_SubRegsSet, S23_SuperRegsSet },
+ { "S24", S24_AliasSet, S24_SubRegsSet, S24_SuperRegsSet },
+ { "S25", S25_AliasSet, S25_SubRegsSet, S25_SuperRegsSet },
+ { "S26", S26_AliasSet, S26_SubRegsSet, S26_SuperRegsSet },
+ { "S27", S27_AliasSet, S27_SubRegsSet, S27_SuperRegsSet },
+ { "S28", S28_AliasSet, S28_SubRegsSet, S28_SuperRegsSet },
+ { "S29", S29_AliasSet, S29_SubRegsSet, S29_SuperRegsSet },
+ { "S3", S3_AliasSet, S3_SubRegsSet, S3_SuperRegsSet },
+ { "S30", S30_AliasSet, S30_SubRegsSet, S30_SuperRegsSet },
+ { "S31", S31_AliasSet, S31_SubRegsSet, S31_SuperRegsSet },
+ { "S4", S4_AliasSet, S4_SubRegsSet, S4_SuperRegsSet },
+ { "S5", S5_AliasSet, S5_SubRegsSet, S5_SuperRegsSet },
+ { "S6", S6_AliasSet, S6_SubRegsSet, S6_SuperRegsSet },
+ { "S7", S7_AliasSet, S7_SubRegsSet, S7_SuperRegsSet },
+ { "S8", S8_AliasSet, S8_SubRegsSet, S8_SuperRegsSet },
+ { "S9", S9_AliasSet, S9_SubRegsSet, S9_SuperRegsSet },
+ { "SDummy", SDummy_AliasSet, SDummy_SubRegsSet, SDummy_SuperRegsSet },
+ { "SP", SP_AliasSet, SP_SubRegsSet, SP_SuperRegsSet },
+ };
+}
+
+unsigned ARMGenRegisterInfo::getSubReg(unsigned RegNo, unsigned Index) const {
+ switch (RegNo) {
+ default:
+ return 0;
+ case ARM::D0:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S0;
+ case 2: return ARM::S1;
+ };
+ break;
+ case ARM::D1:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S2;
+ case 2: return ARM::S3;
+ };
+ break;
+ case ARM::D2:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S4;
+ case 2: return ARM::S5;
+ };
+ break;
+ case ARM::D3:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S6;
+ case 2: return ARM::S7;
+ };
+ break;
+ case ARM::D4:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S8;
+ case 2: return ARM::S9;
+ };
+ break;
+ case ARM::D5:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S10;
+ case 2: return ARM::S11;
+ };
+ break;
+ case ARM::D6:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S12;
+ case 2: return ARM::S13;
+ };
+ break;
+ case ARM::D7:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S14;
+ case 2: return ARM::S15;
+ };
+ break;
+ case ARM::D8:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S16;
+ case 2: return ARM::S17;
+ };
+ break;
+ case ARM::D9:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S18;
+ case 2: return ARM::S19;
+ };
+ break;
+ case ARM::D10:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S20;
+ case 2: return ARM::S21;
+ };
+ break;
+ case ARM::D11:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S22;
+ case 2: return ARM::S23;
+ };
+ break;
+ case ARM::D12:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S24;
+ case 2: return ARM::S25;
+ };
+ break;
+ case ARM::D13:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S26;
+ case 2: return ARM::S27;
+ };
+ break;
+ case ARM::D14:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S28;
+ case 2: return ARM::S29;
+ };
+ break;
+ case ARM::D15:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S30;
+ case 2: return ARM::S31;
+ };
+ break;
+ case ARM::Q0:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S0;
+ case 2: return ARM::S1;
+ case 3: return ARM::S2;
+ case 4: return ARM::S3;
+ case 5: return ARM::D0;
+ case 6: return ARM::D1;
+ };
+ break;
+ case ARM::Q1:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S4;
+ case 2: return ARM::S5;
+ case 3: return ARM::S6;
+ case 4: return ARM::S7;
+ case 5: return ARM::D2;
+ case 6: return ARM::D3;
+ };
+ break;
+ case ARM::Q2:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S8;
+ case 2: return ARM::S9;
+ case 3: return ARM::S10;
+ case 4: return ARM::S11;
+ case 5: return ARM::D4;
+ case 6: return ARM::D5;
+ };
+ break;
+ case ARM::Q3:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S12;
+ case 2: return ARM::S13;
+ case 3: return ARM::S14;
+ case 4: return ARM::S15;
+ case 5: return ARM::D6;
+ case 6: return ARM::D7;
+ };
+ break;
+ case ARM::Q4:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S16;
+ case 2: return ARM::S17;
+ case 3: return ARM::S18;
+ case 4: return ARM::S19;
+ case 5: return ARM::D8;
+ case 6: return ARM::D9;
+ };
+ break;
+ case ARM::Q5:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S20;
+ case 2: return ARM::S21;
+ case 3: return ARM::S22;
+ case 4: return ARM::S23;
+ case 5: return ARM::D10;
+ case 6: return ARM::D11;
+ };
+ break;
+ case ARM::Q6:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S24;
+ case 2: return ARM::S25;
+ case 3: return ARM::S26;
+ case 4: return ARM::S27;
+ case 5: return ARM::D12;
+ case 6: return ARM::D13;
+ };
+ break;
+ case ARM::Q7:
+ switch (Index) {
+ default: return 0;
+ case 1: return ARM::S28;
+ case 2: return ARM::S29;
+ case 3: return ARM::S30;
+ case 4: return ARM::S31;
+ case 5: return ARM::D14;
+ case 6: return ARM::D15;
+ };
+ break;
+ case ARM::Q8:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D16;
+ case 6: return ARM::D17;
+ };
+ break;
+ case ARM::Q9:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D18;
+ case 6: return ARM::D19;
+ };
+ break;
+ case ARM::Q10:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D20;
+ case 6: return ARM::D21;
+ };
+ break;
+ case ARM::Q11:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D22;
+ case 6: return ARM::D23;
+ };
+ break;
+ case ARM::Q12:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D24;
+ case 6: return ARM::D25;
+ };
+ break;
+ case ARM::Q13:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D26;
+ case 6: return ARM::D27;
+ };
+ break;
+ case ARM::Q14:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D28;
+ case 6: return ARM::D29;
+ };
+ break;
+ case ARM::Q15:
+ switch (Index) {
+ default: return 0;
+ case 5: return ARM::D30;
+ case 6: return ARM::D31;
+ };
+ break;
+ };
+ return 0;
+}
+
+unsigned ARMGenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
+ switch (RegNo) {
+ default:
+ return 0;
+ case ARM::D0:
+ if (SubRegNo == ARM::S0) return 1;
+ if (SubRegNo == ARM::S1) return 2;
+ return 0;
+ case ARM::D1:
+ if (SubRegNo == ARM::S2) return 1;
+ if (SubRegNo == ARM::S3) return 2;
+ return 0;
+ case ARM::D2:
+ if (SubRegNo == ARM::S4) return 1;
+ if (SubRegNo == ARM::S5) return 2;
+ return 0;
+ case ARM::D3:
+ if (SubRegNo == ARM::S6) return 1;
+ if (SubRegNo == ARM::S7) return 2;
+ return 0;
+ case ARM::D4:
+ if (SubRegNo == ARM::S8) return 1;
+ if (SubRegNo == ARM::S9) return 2;
+ return 0;
+ case ARM::D5:
+ if (SubRegNo == ARM::S10) return 1;
+ if (SubRegNo == ARM::S11) return 2;
+ return 0;
+ case ARM::D6:
+ if (SubRegNo == ARM::S12) return 1;
+ if (SubRegNo == ARM::S13) return 2;
+ return 0;
+ case ARM::D7:
+ if (SubRegNo == ARM::S14) return 1;
+ if (SubRegNo == ARM::S15) return 2;
+ return 0;
+ case ARM::D8:
+ if (SubRegNo == ARM::S16) return 1;
+ if (SubRegNo == ARM::S17) return 2;
+ return 0;
+ case ARM::D9:
+ if (SubRegNo == ARM::S18) return 1;
+ if (SubRegNo == ARM::S19) return 2;
+ return 0;
+ case ARM::D10:
+ if (SubRegNo == ARM::S20) return 1;
+ if (SubRegNo == ARM::S21) return 2;
+ return 0;
+ case ARM::D11:
+ if (SubRegNo == ARM::S22) return 1;
+ if (SubRegNo == ARM::S23) return 2;
+ return 0;
+ case ARM::D12:
+ if (SubRegNo == ARM::S24) return 1;
+ if (SubRegNo == ARM::S25) return 2;
+ return 0;
+ case ARM::D13:
+ if (SubRegNo == ARM::S26) return 1;
+ if (SubRegNo == ARM::S27) return 2;
+ return 0;
+ case ARM::D14:
+ if (SubRegNo == ARM::S28) return 1;
+ if (SubRegNo == ARM::S29) return 2;
+ return 0;
+ case ARM::D15:
+ if (SubRegNo == ARM::S30) return 1;
+ if (SubRegNo == ARM::S31) return 2;
+ return 0;
+ case ARM::Q0:
+ if (SubRegNo == ARM::S0) return 1;
+ if (SubRegNo == ARM::S1) return 2;
+ if (SubRegNo == ARM::S2) return 3;
+ if (SubRegNo == ARM::S3) return 4;
+ if (SubRegNo == ARM::D0) return 5;
+ if (SubRegNo == ARM::D1) return 6;
+ return 0;
+ case ARM::Q1:
+ if (SubRegNo == ARM::S4) return 1;
+ if (SubRegNo == ARM::S5) return 2;
+ if (SubRegNo == ARM::S6) return 3;
+ if (SubRegNo == ARM::S7) return 4;
+ if (SubRegNo == ARM::D2) return 5;
+ if (SubRegNo == ARM::D3) return 6;
+ return 0;
+ case ARM::Q2:
+ if (SubRegNo == ARM::S8) return 1;
+ if (SubRegNo == ARM::S9) return 2;
+ if (SubRegNo == ARM::S10) return 3;
+ if (SubRegNo == ARM::S11) return 4;
+ if (SubRegNo == ARM::D4) return 5;
+ if (SubRegNo == ARM::D5) return 6;
+ return 0;
+ case ARM::Q3:
+ if (SubRegNo == ARM::S12) return 1;
+ if (SubRegNo == ARM::S13) return 2;
+ if (SubRegNo == ARM::S14) return 3;
+ if (SubRegNo == ARM::S15) return 4;
+ if (SubRegNo == ARM::D6) return 5;
+ if (SubRegNo == ARM::D7) return 6;
+ return 0;
+ case ARM::Q4:
+ if (SubRegNo == ARM::S16) return 1;
+ if (SubRegNo == ARM::S17) return 2;
+ if (SubRegNo == ARM::S18) return 3;
+ if (SubRegNo == ARM::S19) return 4;
+ if (SubRegNo == ARM::D8) return 5;
+ if (SubRegNo == ARM::D9) return 6;
+ return 0;
+ case ARM::Q5:
+ if (SubRegNo == ARM::S20) return 1;
+ if (SubRegNo == ARM::S21) return 2;
+ if (SubRegNo == ARM::S22) return 3;
+ if (SubRegNo == ARM::S23) return 4;
+ if (SubRegNo == ARM::D10) return 5;
+ if (SubRegNo == ARM::D11) return 6;
+ return 0;
+ case ARM::Q6:
+ if (SubRegNo == ARM::S24) return 1;
+ if (SubRegNo == ARM::S25) return 2;
+ if (SubRegNo == ARM::S26) return 3;
+ if (SubRegNo == ARM::S27) return 4;
+ if (SubRegNo == ARM::D12) return 5;
+ if (SubRegNo == ARM::D13) return 6;
+ return 0;
+ case ARM::Q7:
+ if (SubRegNo == ARM::S28) return 1;
+ if (SubRegNo == ARM::S29) return 2;
+ if (SubRegNo == ARM::S30) return 3;
+ if (SubRegNo == ARM::S31) return 4;
+ if (SubRegNo == ARM::D14) return 5;
+ if (SubRegNo == ARM::D15) return 6;
+ return 0;
+ case ARM::Q8:
+ if (SubRegNo == ARM::D16) return 5;
+ if (SubRegNo == ARM::D17) return 6;
+ return 0;
+ case ARM::Q9:
+ if (SubRegNo == ARM::D18) return 5;
+ if (SubRegNo == ARM::D19) return 6;
+ return 0;
+ case ARM::Q10:
+ if (SubRegNo == ARM::D20) return 5;
+ if (SubRegNo == ARM::D21) return 6;
+ return 0;
+ case ARM::Q11:
+ if (SubRegNo == ARM::D22) return 5;
+ if (SubRegNo == ARM::D23) return 6;
+ return 0;
+ case ARM::Q12:
+ if (SubRegNo == ARM::D24) return 5;
+ if (SubRegNo == ARM::D25) return 6;
+ return 0;
+ case ARM::Q13:
+ if (SubRegNo == ARM::D26) return 5;
+ if (SubRegNo == ARM::D27) return 6;
+ return 0;
+ case ARM::Q14:
+ if (SubRegNo == ARM::D28) return 5;
+ if (SubRegNo == ARM::D29) return 6;
+ return 0;
+ case ARM::Q15:
+ if (SubRegNo == ARM::D30) return 5;
+ if (SubRegNo == ARM::D31) return 6;
+ return 0;
+ };
+ return 0;
+}
+
+ARMGenRegisterInfo::ARMGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
+ : TargetRegisterInfo(RegisterDescriptors, 100, RegisterClasses, RegisterClasses+12,
+ CallFrameSetupOpcode, CallFrameDestroyOpcode,
+ SubregHashTable, SubregHashTableSize,
+ SuperregHashTable, SuperregHashTableSize,
+ AliasesHashTable, AliasesHashTableSize) {
+}
+
+int ARMGenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) const {
+ switch (Flavour) {
+ default:
+ assert(0 && "Unknown DWARF flavour");
+ return -1;
+ case 0:
+ switch (RegNum) {
+ default:
+ assert(0 && "Invalid RegNum");
+ return -1;
+ case ARM::CPSR:
+ return -1;
+ case ARM::D0:
+ return -1;
+ case ARM::D1:
+ return -1;
+ case ARM::D10:
+ return -1;
+ case ARM::D11:
+ return -1;
+ case ARM::D12:
+ return -1;
+ case ARM::D13:
+ return -1;
+ case ARM::D14:
+ return -1;
+ case ARM::D15:
+ return -1;
+ case ARM::D16:
+ return -1;
+ case ARM::D17:
+ return -1;
+ case ARM::D18:
+ return -1;
+ case ARM::D19:
+ return -1;
+ case ARM::D2:
+ return -1;
+ case ARM::D20:
+ return -1;
+ case ARM::D21:
+ return -1;
+ case ARM::D22:
+ return -1;
+ case ARM::D23:
+ return -1;
+ case ARM::D24:
+ return -1;
+ case ARM::D25:
+ return -1;
+ case ARM::D26:
+ return -1;
+ case ARM::D27:
+ return -1;
+ case ARM::D28:
+ return -1;
+ case ARM::D29:
+ return -1;
+ case ARM::D3:
+ return -1;
+ case ARM::D30:
+ return -1;
+ case ARM::D31:
+ return -1;
+ case ARM::D4:
+ return -1;
+ case ARM::D5:
+ return -1;
+ case ARM::D6:
+ return -1;
+ case ARM::D7:
+ return -1;
+ case ARM::D8:
+ return -1;
+ case ARM::D9:
+ return -1;
+ case ARM::FPSCR:
+ return -1;
+ case ARM::LR:
+ return 14;
+ case ARM::PC:
+ return 15;
+ case ARM::Q0:
+ return -1;
+ case ARM::Q1:
+ return -1;
+ case ARM::Q10:
+ return -1;
+ case ARM::Q11:
+ return -1;
+ case ARM::Q12:
+ return -1;
+ case ARM::Q13:
+ return -1;
+ case ARM::Q14:
+ return -1;
+ case ARM::Q15:
+ return -1;
+ case ARM::Q2:
+ return -1;
+ case ARM::Q3:
+ return -1;
+ case ARM::Q4:
+ return -1;
+ case ARM::Q5:
+ return -1;
+ case ARM::Q6:
+ return -1;
+ case ARM::Q7:
+ return -1;
+ case ARM::Q8:
+ return -1;
+ case ARM::Q9:
+ return -1;
+ case ARM::R0:
+ return 0;
+ case ARM::R1:
+ return 1;
+ case ARM::R10:
+ return 10;
+ case ARM::R11:
+ return 11;
+ case ARM::R12:
+ return 12;
+ case ARM::R2:
+ return 2;
+ case ARM::R3:
+ return 3;
+ case ARM::R4:
+ return 4;
+ case ARM::R5:
+ return 5;
+ case ARM::R6:
+ return 6;
+ case ARM::R7:
+ return 7;
+ case ARM::R8:
+ return 8;
+ case ARM::R9:
+ return 9;
+ case ARM::S0:
+ return -1;
+ case ARM::S1:
+ return -1;
+ case ARM::S10:
+ return -1;
+ case ARM::S11:
+ return -1;
+ case ARM::S12:
+ return -1;
+ case ARM::S13:
+ return -1;
+ case ARM::S14:
+ return -1;
+ case ARM::S15:
+ return -1;
+ case ARM::S16:
+ return -1;
+ case ARM::S17:
+ return -1;
+ case ARM::S18:
+ return -1;
+ case ARM::S19:
+ return -1;
+ case ARM::S2:
+ return -1;
+ case ARM::S20:
+ return -1;
+ case ARM::S21:
+ return -1;
+ case ARM::S22:
+ return -1;
+ case ARM::S23:
+ return -1;
+ case ARM::S24:
+ return -1;
+ case ARM::S25:
+ return -1;
+ case ARM::S26:
+ return -1;
+ case ARM::S27:
+ return -1;
+ case ARM::S28:
+ return -1;
+ case ARM::S29:
+ return -1;
+ case ARM::S3:
+ return -1;
+ case ARM::S30:
+ return -1;
+ case ARM::S31:
+ return -1;
+ case ARM::S4:
+ return -1;
+ case ARM::S5:
+ return -1;
+ case ARM::S6:
+ return -1;
+ case ARM::S7:
+ return -1;
+ case ARM::S8:
+ return -1;
+ case ARM::S9:
+ return -1;
+ case ARM::SDummy:
+ return -1;
+ case ARM::SP:
+ return 13;
+ };
+ };
+}
+
+} // End llvm namespace
diff --git a/libclamav/c++/ARMGenRegisterNames.inc b/libclamav/c++/ARMGenRegisterNames.inc
new file mode 100644
index 0000000..17ad868
--- /dev/null
+++ b/libclamav/c++/ARMGenRegisterNames.inc
@@ -0,0 +1,116 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Register Enum Values
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace ARM {
+ enum {
+ NoRegister,
+ CPSR, // 1
+ D0, // 2
+ D1, // 3
+ D10, // 4
+ D11, // 5
+ D12, // 6
+ D13, // 7
+ D14, // 8
+ D15, // 9
+ D16, // 10
+ D17, // 11
+ D18, // 12
+ D19, // 13
+ D2, // 14
+ D20, // 15
+ D21, // 16
+ D22, // 17
+ D23, // 18
+ D24, // 19
+ D25, // 20
+ D26, // 21
+ D27, // 22
+ D28, // 23
+ D29, // 24
+ D3, // 25
+ D30, // 26
+ D31, // 27
+ D4, // 28
+ D5, // 29
+ D6, // 30
+ D7, // 31
+ D8, // 32
+ D9, // 33
+ FPSCR, // 34
+ LR, // 35
+ PC, // 36
+ Q0, // 37
+ Q1, // 38
+ Q10, // 39
+ Q11, // 40
+ Q12, // 41
+ Q13, // 42
+ Q14, // 43
+ Q15, // 44
+ Q2, // 45
+ Q3, // 46
+ Q4, // 47
+ Q5, // 48
+ Q6, // 49
+ Q7, // 50
+ Q8, // 51
+ Q9, // 52
+ R0, // 53
+ R1, // 54
+ R10, // 55
+ R11, // 56
+ R12, // 57
+ R2, // 58
+ R3, // 59
+ R4, // 60
+ R5, // 61
+ R6, // 62
+ R7, // 63
+ R8, // 64
+ R9, // 65
+ S0, // 66
+ S1, // 67
+ S10, // 68
+ S11, // 69
+ S12, // 70
+ S13, // 71
+ S14, // 72
+ S15, // 73
+ S16, // 74
+ S17, // 75
+ S18, // 76
+ S19, // 77
+ S2, // 78
+ S20, // 79
+ S21, // 80
+ S22, // 81
+ S23, // 82
+ S24, // 83
+ S25, // 84
+ S26, // 85
+ S27, // 86
+ S28, // 87
+ S29, // 88
+ S3, // 89
+ S30, // 90
+ S31, // 91
+ S4, // 92
+ S5, // 93
+ S6, // 94
+ S7, // 95
+ S8, // 96
+ S9, // 97
+ SDummy, // 98
+ SP, // 99
+ NUM_TARGET_REGS // 100
+ };
+}
+} // End llvm namespace
diff --git a/libclamav/c++/ARMGenSubtarget.inc b/libclamav/c++/ARMGenSubtarget.inc
new file mode 100644
index 0000000..186cb6a
--- /dev/null
+++ b/libclamav/c++/ARMGenSubtarget.inc
@@ -0,0 +1,703 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Subtarget Enumeration Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/SubtargetFeature.h"
+#include "llvm/Target/TargetInstrItineraries.h"
+
+enum {
+ FU_Issue = 1 << 0,
+ FU_LdSt0 = 1 << 1,
+ FU_LdSt1 = 1 << 2,
+ FU_NLSPipe = 1 << 3,
+ FU_NPipe = 1 << 4,
+ FU_Pipe0 = 1 << 5,
+ FU_Pipe1 = 1 << 6
+};
+
+enum {
+ ArchV4T = 1 << 0,
+ ArchV5T = 1 << 1,
+ ArchV5TE = 1 << 2,
+ ArchV6 = 1 << 3,
+ ArchV6T2 = 1 << 4,
+ ArchV7A = 1 << 5,
+ FeatureNEON = 1 << 6,
+ FeatureThumb2 = 1 << 7,
+ FeatureVFP2 = 1 << 8,
+ FeatureVFP3 = 1 << 9
+};
+
+// Sorted (by key) array of values for CPU features.
+static const llvm::SubtargetFeatureKV FeatureKV[] = {
+ { "neon", "Enable NEON instructions", FeatureNEON, 0 },
+ { "thumb2", "Enable Thumb2 instructions", FeatureThumb2, 0 },
+ { "v4t", "ARM v4T", ArchV4T, 0 },
+ { "v5t", "ARM v5T", ArchV5T, 0 },
+ { "v5te", "ARM v5TE, v5TEj, v5TExp", ArchV5TE, 0 },
+ { "v6", "ARM v6", ArchV6, 0 },
+ { "v6t2", "ARM v6t2", ArchV6T2, 0 },
+ { "v7a", "ARM v7A", ArchV7A, 0 },
+ { "vfp2", "Enable VFP2 instructions", FeatureVFP2, 0 },
+ { "vfp3", "Enable VFP3 instructions", FeatureVFP3, 0 }
+};
+
+enum {
+ FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)
+};
+
+// Sorted (by key) array of values for CPU subtype.
+static const llvm::SubtargetFeatureKV SubTypeKV[] = {
+ { "arm1020e", "Select the arm1020e processor", ArchV5TE, 0 },
+ { "arm1020t", "Select the arm1020t processor", ArchV5T, 0 },
+ { "arm1022e", "Select the arm1022e processor", ArchV5TE, 0 },
+ { "arm10e", "Select the arm10e processor", ArchV5TE, 0 },
+ { "arm10tdmi", "Select the arm10tdmi processor", ArchV5T, 0 },
+ { "arm1136j-s", "Select the arm1136j-s processor", ArchV6, 0 },
+ { "arm1136jf-s", "Select the arm1136jf-s processor", ArchV6 | FeatureVFP2, 0 },
+ { "arm1156t2-s", "Select the arm1156t2-s processor", ArchV6T2 | FeatureThumb2, 0 },
+ { "arm1156t2f-s", "Select the arm1156t2f-s processor", ArchV6T2 | FeatureThumb2 | FeatureVFP2, 0 },
+ { "arm1176jz-s", "Select the arm1176jz-s processor", ArchV6, 0 },
+ { "arm1176jzf-s", "Select the arm1176jzf-s processor", ArchV6 | FeatureVFP2, 0 },
+ { "arm710t", "Select the arm710t processor", ArchV4T, 0 },
+ { "arm720t", "Select the arm720t processor", ArchV4T, 0 },
+ { "arm7tdmi", "Select the arm7tdmi processor", ArchV4T, 0 },
+ { "arm7tdmi-s", "Select the arm7tdmi-s processor", ArchV4T, 0 },
+ { "arm8", "Select the arm8 processor", 0, 0 },
+ { "arm810", "Select the arm810 processor", 0, 0 },
+ { "arm9", "Select the arm9 processor", ArchV4T, 0 },
+ { "arm920", "Select the arm920 processor", ArchV4T, 0 },
+ { "arm920t", "Select the arm920t processor", ArchV4T, 0 },
+ { "arm922t", "Select the arm922t processor", ArchV4T, 0 },
+ { "arm926ej-s", "Select the arm926ej-s processor", ArchV5TE, 0 },
+ { "arm940t", "Select the arm940t processor", ArchV4T, 0 },
+ { "arm946e-s", "Select the arm946e-s processor", ArchV5TE, 0 },
+ { "arm966e-s", "Select the arm966e-s processor", ArchV5TE, 0 },
+ { "arm968e-s", "Select the arm968e-s processor", ArchV5TE, 0 },
+ { "arm9e", "Select the arm9e processor", ArchV5TE, 0 },
+ { "arm9tdmi", "Select the arm9tdmi processor", ArchV4T, 0 },
+ { "cortex-a8", "Select the cortex-a8 processor", ArchV7A | FeatureThumb2 | FeatureNEON, 0 },
+ { "cortex-a9", "Select the cortex-a9 processor", ArchV7A | FeatureThumb2 | FeatureNEON, 0 },
+ { "ep9312", "Select the ep9312 processor", ArchV4T, 0 },
+ { "generic", "Select the generic processor", 0, 0 },
+ { "iwmmxt", "Select the iwmmxt processor", ArchV5TE, 0 },
+ { "mpcore", "Select the mpcore processor", ArchV6 | FeatureVFP2, 0 },
+ { "mpcorenovfp", "Select the mpcorenovfp processor", ArchV6, 0 },
+ { "strongarm", "Select the strongarm processor", 0, 0 },
+ { "strongarm110", "Select the strongarm110 processor", 0, 0 },
+ { "strongarm1100", "Select the strongarm1100 processor", 0, 0 },
+ { "strongarm1110", "Select the strongarm1110 processor", 0, 0 },
+ { "xscale", "Select the xscale processor", ArchV5TE, 0 }
+};
+
+enum {
+ SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)
+};
+
+
+enum {
+ ItinClassesSize = 129
+};
+static const llvm::InstrStage Stages[] = {
+ { 0, 0, 0 }, // No itinerary
+ { 1, FU_Pipe0, -1 }, // 1
+ { 2, FU_Pipe0, -1 }, // 2
+ { 3, FU_Pipe0, -1 }, // 3
+ { 15, FU_Pipe0, -1 }, // 4
+ { 29, FU_Pipe0, -1 }, // 5
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, // 6
+ { 1, FU_Pipe1, 0 }, { 2, FU_Pipe0, -1 }, // 7
+ { 2, FU_Pipe1, 0 }, { 3, FU_Pipe0, -1 }, // 8
+ { 1, FU_Issue, 0 }, { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_LdSt0, -1 }, // 9
+ { 2, FU_Issue, 0 }, { 1, FU_Pipe0, 0 }, { 1, FU_Pipe1, -1 }, { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_LdSt0, -1 }, // 10
+ { 2, FU_Issue, 0 }, { 2, FU_Pipe0, 0 }, { 2, FU_Pipe1, -1 }, { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_LdSt0, -1 }, // 11
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_NLSPipe, -1 }, // 12
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_NPipe, -1 }, // 13
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 4, FU_NPipe, 0 }, { 4, FU_NLSPipe, -1 }, // 14
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 7, FU_NPipe, 0 }, { 7, FU_NLSPipe, -1 }, // 15
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 5, FU_NPipe, 0 }, { 5, FU_NLSPipe, -1 }, // 16
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 8, FU_NPipe, 0 }, { 8, FU_NLSPipe, -1 }, // 17
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 9, FU_NPipe, 0 }, { 9, FU_NLSPipe, -1 }, // 18
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 11, FU_NPipe, 0 }, { 11, FU_NLSPipe, -1 }, // 19
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 19, FU_NPipe, 0 }, { 19, FU_NLSPipe, -1 }, // 20
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 20, FU_NPipe, 0 }, { 20, FU_NLSPipe, -1 }, // 21
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 29, FU_NPipe, 0 }, { 29, FU_NLSPipe, -1 }, // 22
+ { 1, FU_Issue, 0 }, { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_LdSt0, 0 }, { 1, FU_NLSPipe, -1 }, // 23
+ { 2, FU_Issue, 0 }, { 1, FU_Pipe0, 0 }, { 1, FU_Pipe1, -1 }, { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_LdSt0, 0 }, { 1, FU_NLSPipe, -1 }, // 24
+ { 3, FU_Issue, 0 }, { 2, FU_Pipe0, 0 }, { 2, FU_Pipe1, -1 }, { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_LdSt0, 0 }, { 1, FU_NLSPipe, -1 }, // 25
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 2, FU_NPipe, -1 }, // 26
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 2, FU_NLSPipe, -1 }, // 27
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_NLSPipe, -1 }, { 1, FU_NPipe, 0 }, { 2, FU_NLSPipe, -1 }, // 28
+ { 1, FU_Pipe0 | FU_Pipe1, -1 }, { 1, FU_NPipe, -1 }, { 2, FU_NLSPipe, 0 }, { 3, FU_NPipe, -1 }, // 29
+ { 0, 0, 0 } // End itinerary
+};
+static const unsigned OperandCycles[] = {
+ 0, // No itinerary
+ 2, 2, // 1
+ 2, 2, 2, // 2
+ 2, 2, 1, // 3
+ 3, 3, 2, 1, // 4
+ 2, 1, // 5
+ 3, 2, 1, // 6
+ 2, // 7
+ 3, // 8
+ 3, 2, // 9
+ 3, 1, // 10
+ 4, 2, 1, // 11
+ 4, 1, 1, // 12
+ 4, 1, 1, 2, // 13
+ 5, 1, 1, // 14
+ 5, 1, 1, 2, // 15
+ 6, 1, 1, // 16
+ 6, 1, 1, 2, // 17
+ 4, 1, // 18
+ 5, 2, 1, // 19
+ 4, 2, 1, 1, // 20
+ 5, 2, 2, 1, // 21
+ 2, 1, 1, // 22
+ 2, 2, 1, 1, // 23
+ 2, 2, 2, 1, // 24
+ 5, 2, // 25
+ 9, 2, // 26
+ 9, 2, 2, // 27
+ 9, 2, 2, 2, // 28
+ 20, 2, 2, // 29
+ 34, 2, 2, // 30
+ 5, 2, 2, // 31
+ 1, // 32
+ 1, 1, // 33
+ 1, 1, 1, // 34
+ 6, 1, 1, 4, // 35
+ 6, 6, 1, 1, // 36
+ 3, 1, 1, // 37
+ 3, 2, 1, 1, // 38
+ 4, 3, 1, 1, // 39
+ 2, 3, 1, // 40
+ 2, 3, 1, 1, // 41
+ 3, 3, 1, 1, // 42
+ 7, 1, // 43
+ 5, 1, // 44
+ 8, 1, // 45
+ 7, 1, 1, // 46
+ 9, 1, 1, // 47
+ 11, 1, 1, // 48
+ 7, 2, 1, 1, // 49
+ 19, 2, 1, 1, // 50
+ 20, 1, 1, // 51
+ 29, 1, 1, // 52
+ 19, 1, // 53
+ 29, 1, // 54
+ 2, 2, 2, 2, 1, // 55
+ 6, 2, // 56
+ 6, 2, 2, // 57
+ 20, 1, // 58
+ 20, 20, 1, // 59
+ 4, 4, 1, 1, // 60
+ 9, 2, 2, 3, // 61
+ 10, 2, 2, 3, // 62
+ 10, 2, 2, // 63
+ 3, 2, 2, // 64
+ 4, 2, 2, // 65
+ 4, 2, // 66
+ 6, 3, 2, 1, // 67
+ 7, 3, 2, 1, // 68
+ 7, 2, 1, // 69
+ 7, 2, 2, // 70
+ 9, 2, 1, // 71
+ 6, 2, 2, 3, // 72
+ 7, 2, 1, 3, // 73
+ 7, 2, 2, 3, // 74
+ 9, 2, 1, 3, // 75
+ 3, 2, 2, 1, // 76
+ 4, 2, 2, 3, 1, // 77
+ 4, 2, 2, 3, 3, 1, // 78
+ 3, 1, 2, 1, // 79
+ 3, 1, 2, 2, 1, // 80
+ 4, 1, 2, 2, 3, 1, // 81
+ 4, 1, 2, 2, 3, 3, 1, // 82
+ 0 // End itinerary
+};
+
+enum {
+ StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),
+ OperandCyclesSize = sizeof(OperandCycles)/sizeof(unsigned)
+};
+
+static const llvm::InstrItinerary ARMV6Itineraries[] = {
+ { 1, 2, 0, 0 }, // 0
+ { 0, 0, 0, 0 }, // 1
+ { 0, 0, 0, 0 }, // 2
+ { 0, 0, 0, 0 }, // 3
+ { 0, 0, 0, 0 }, // 4
+ { 0, 0, 0, 0 }, // 5
+ { 0, 0, 0, 0 }, // 6
+ { 0, 0, 0, 0 }, // 7
+ { 0, 0, 0, 0 }, // 8
+ { 0, 0, 0, 0 }, // 9
+ { 0, 0, 0, 0 }, // 10
+ { 0, 0, 0, 0 }, // 11
+ { 0, 0, 0, 0 }, // 12
+ { 0, 0, 0, 0 }, // 13
+ { 0, 0, 0, 0 }, // 14
+ { 0, 0, 0, 0 }, // 15
+ { 0, 0, 0, 0 }, // 16
+ { 0, 0, 0, 0 }, // 17
+ { 0, 0, 0, 0 }, // 18
+ { 0, 0, 0, 0 }, // 19
+ { 0, 0, 0, 0 }, // 20
+ { 0, 0, 0, 0 }, // 21
+ { 0, 0, 0, 0 }, // 22
+ { 0, 0, 0, 0 }, // 23
+ { 0, 0, 0, 0 }, // 24
+ { 0, 0, 0, 0 }, // 25
+ { 0, 0, 0, 0 }, // 26
+ { 0, 0, 0, 0 }, // 27
+ { 0, 0, 0, 0 }, // 28
+ { 0, 0, 0, 0 }, // 29
+ { 0, 0, 0, 0 }, // 30
+ { 0, 0, 0, 0 }, // 31
+ { 0, 0, 0, 0 }, // 32
+ { 0, 0, 0, 0 }, // 33
+ { 0, 0, 0, 0 }, // 34
+ { 0, 0, 0, 0 }, // 35
+ { 0, 0, 0, 0 }, // 36
+ { 0, 0, 0, 0 }, // 37
+ { 0, 0, 0, 0 }, // 38
+ { 0, 0, 0, 0 }, // 39
+ { 0, 0, 0, 0 }, // 40
+ { 0, 0, 0, 0 }, // 41
+ { 0, 0, 0, 0 }, // 42
+ { 0, 0, 0, 0 }, // 43
+ { 0, 0, 0, 0 }, // 44
+ { 0, 0, 0, 0 }, // 45
+ { 0, 0, 0, 0 }, // 46
+ { 0, 0, 0, 0 }, // 47
+ { 0, 0, 0, 0 }, // 48
+ { 0, 0, 0, 0 }, // 49
+ { 0, 0, 0, 0 }, // 50
+ { 0, 0, 0, 0 }, // 51
+ { 0, 0, 0, 0 }, // 52
+ { 0, 0, 0, 0 }, // 53
+ { 0, 0, 0, 0 }, // 54
+ { 0, 0, 0, 0 }, // 55
+ { 0, 0, 0, 0 }, // 56
+ { 0, 0, 0, 0 }, // 57
+ { 0, 0, 0, 0 }, // 58
+ { 0, 0, 0, 0 }, // 59
+ { 0, 0, 0, 0 }, // 60
+ { 1, 2, 76, 79 }, // 61
+ { 1, 2, 76, 79 }, // 62
+ { 1, 2, 1, 3 }, // 63
+ { 1, 2, 1, 3 }, // 64
+ { 1, 2, 74, 76 }, // 65
+ { 1, 2, 72, 74 }, // 66
+ { 1, 2, 74, 76 }, // 67
+ { 1, 2, 74, 76 }, // 68
+ { 1, 2, 72, 74 }, // 69
+ { 1, 2, 74, 76 }, // 70
+ { 4, 5, 83, 86 }, // 71
+ { 5, 6, 86, 89 }, // 72
+ { 1, 2, 89, 92 }, // 73
+ { 1, 2, 89, 92 }, // 74
+ { 3, 4, 0, 0 }, // 75
+ { 1, 2, 79, 83 }, // 76
+ { 2, 3, 79, 83 }, // 77
+ { 1, 2, 76, 79 }, // 78
+ { 2, 3, 76, 79 }, // 79
+ { 4, 5, 83, 86 }, // 80
+ { 5, 6, 86, 89 }, // 81
+ { 1, 2, 19, 20 }, // 82
+ { 1, 2, 3, 6 }, // 83
+ { 1, 2, 3, 6 }, // 84
+ { 3, 4, 0, 0 }, // 85
+ { 1, 2, 72, 74 }, // 86
+ { 1, 2, 72, 74 }, // 87
+ { 1, 2, 1, 3 }, // 88
+ { 1, 2, 3, 6 }, // 89
+ { 1, 2, 6, 9 }, // 90
+ { 2, 3, 9, 13 }, // 91
+ { 1, 2, 0, 0 }, // 92
+ { 1, 2, 19, 20 }, // 93
+ { 1, 2, 20, 22 }, // 94
+ { 1, 2, 22, 24 }, // 95
+ { 1, 2, 24, 27 }, // 96
+ { 1, 2, 18, 19 }, // 97
+ { 1, 2, 1, 3 }, // 98
+ { 1, 2, 13, 15 }, // 99
+ { 2, 3, 15, 18 }, // 100
+ { 1, 2, 48, 50 }, // 101
+ { 1, 2, 24, 27 }, // 102
+ { 3, 4, 0, 0 }, // 103
+ { 1, 2, 27, 30 }, // 104
+ { 1, 2, 53, 57 }, // 105
+ { 2, 3, 50, 53 }, // 106
+ { 2, 3, 57, 61 }, // 107
+ { 1, 2, 30, 34 }, // 108
+ { 2, 3, 37, 41 }, // 109
+ { 3, 4, 44, 48 }, // 110
+ { 1, 2, 18, 19 }, // 111
+ { 1, 2, 1, 3 }, // 112
+ { 1, 2, 13, 15 }, // 113
+ { 2, 3, 15, 18 }, // 114
+ { 1, 2, 27, 30 }, // 115
+ { 2, 3, 34, 37 }, // 116
+ { 3, 4, 41, 44 }, // 117
+ { 1, 2, 13, 15 }, // 118
+ { 1, 2, 6, 9 }, // 119
+ { 3, 4, 0, 0 }, // 120
+ { 1, 2, 61, 64 }, // 121
+ { 1, 2, 64, 68 }, // 122
+ { 2, 3, 6, 9 }, // 123
+ { 2, 3, 68, 72 }, // 124
+ { 1, 2, 1, 3 }, // 125
+ { 1, 2, 13, 15 }, // 126
+ { 2, 3, 15, 18 }, // 127
+ { 0, 0, 0, 0 }, // 128
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+static const llvm::InstrItinerary CortexA8Itineraries[] = {
+ { 6, 7, 0, 0 }, // 0
+ { 26, 28, 89, 92 }, // 1
+ { 71, 73, 168, 171 }, // 2
+ { 26, 28, 24, 27 }, // 3
+ { 26, 28, 24, 27 }, // 4
+ { 26, 28, 191, 194 }, // 5
+ { 26, 28, 191, 194 }, // 6
+ { 26, 28, 191, 194 }, // 7
+ { 71, 73, 194, 197 }, // 8
+ { 24, 26, 61, 64 }, // 9
+ { 73, 75, 106, 109 }, // 10
+ { 55, 59, 0, 0 }, // 11
+ { 55, 59, 6, 9 }, // 12
+ { 55, 59, 68, 72 }, // 13
+ { 55, 59, 161, 166 }, // 14
+ { 26, 28, 180, 184 }, // 15
+ { 71, 73, 184, 188 }, // 16
+ { 26, 28, 216, 220 }, // 17
+ { 71, 73, 224, 228 }, // 18
+ { 71, 73, 220, 224 }, // 19
+ { 79, 83, 228, 232 }, // 20
+ { 24, 26, 13, 15 }, // 21
+ { 24, 26, 173, 176 }, // 22
+ { 24, 26, 61, 64 }, // 23
+ { 24, 26, 13, 15 }, // 24
+ { 73, 75, 106, 109 }, // 25
+ { 26, 28, 19, 20 }, // 26
+ { 73, 75, 22, 24 }, // 27
+ { 24, 26, 171, 173 }, // 28
+ { 26, 28, 168, 171 }, // 29
+ { 71, 73, 210, 213 }, // 30
+ { 71, 73, 207, 210 }, // 31
+ { 79, 83, 213, 216 }, // 32
+ { 26, 28, 199, 203 }, // 33
+ { 71, 73, 203, 207 }, // 34
+ { 24, 26, 64, 68 }, // 35
+ { 73, 75, 124, 128 }, // 36
+ { 75, 79, 176, 180 }, // 37
+ { 26, 28, 48, 50 }, // 38
+ { 26, 28, 48, 50 }, // 39
+ { 26, 28, 76, 79 }, // 40
+ { 71, 73, 188, 191 }, // 41
+ { 26, 28, 27, 30 }, // 42
+ { 71, 73, 34, 37 }, // 43
+ { 26, 28, 106, 109 }, // 44
+ { 71, 73, 27, 30 }, // 45
+ { 55, 59, 0, 0 }, // 46
+ { 26, 28, 15, 18 }, // 47
+ { 26, 28, 15, 18 }, // 48
+ { 73, 75, 15, 18 }, // 49
+ { 73, 75, 232, 236 }, // 50
+ { 75, 79, 236, 241 }, // 51
+ { 75, 79, 241, 247 }, // 52
+ { 73, 75, 247, 251 }, // 53
+ { 73, 75, 251, 256 }, // 54
+ { 75, 79, 256, 262 }, // 55
+ { 75, 79, 262, 269 }, // 56
+ { 26, 28, 72, 74 }, // 57
+ { 71, 73, 166, 168 }, // 58
+ { 26, 28, 197, 199 }, // 59
+ { 26, 28, 197, 199 }, // 60
+ { 26, 28, 134, 137 }, // 61
+ { 40, 43, 137, 140 }, // 62
+ { 26, 28, 93, 95 }, // 63
+ { 28, 31, 48, 50 }, // 64
+ { 37, 40, 132, 134 }, // 65
+ { 34, 37, 130, 132 }, // 66
+ { 37, 40, 132, 134 }, // 67
+ { 26, 28, 128, 130 }, // 68
+ { 31, 34, 128, 130 }, // 69
+ { 26, 28, 128, 130 }, // 70
+ { 49, 52, 151, 154 }, // 71
+ { 52, 55, 154, 157 }, // 72
+ { 55, 59, 0, 0 }, // 73
+ { 59, 65, 0, 0 }, // 74
+ { 65, 71, 0, 0 }, // 75
+ { 26, 28, 143, 147 }, // 76
+ { 46, 49, 147, 151 }, // 77
+ { 26, 28, 134, 137 }, // 78
+ { 43, 46, 140, 143 }, // 79
+ { 46, 49, 157, 159 }, // 80
+ { 52, 55, 159, 161 }, // 81
+ { 24, 26, 0, 0 }, // 82
+ { 55, 59, 0, 0 }, // 83
+ { 59, 65, 0, 0 }, // 84
+ { 65, 71, 0, 0 }, // 85
+ { 26, 28, 128, 130 }, // 86
+ { 28, 31, 48, 50 }, // 87
+ { 6, 7, 1, 3 }, // 88
+ { 6, 7, 3, 6 }, // 89
+ { 6, 7, 6, 9 }, // 90
+ { 6, 7, 64, 68 }, // 91
+ { 6, 7, 0, 0 }, // 92
+ { 6, 7, 18, 19 }, // 93
+ { 6, 7, 13, 15 }, // 94
+ { 6, 7, 13, 15 }, // 95
+ { 6, 7, 61, 64 }, // 96
+ { 6, 7, 18, 19 }, // 97
+ { 6, 7, 1, 3 }, // 98
+ { 6, 7, 13, 15 }, // 99
+ { 6, 7, 61, 64 }, // 100
+ { 11, 14, 22, 24 }, // 101
+ { 11, 14, 15, 18 }, // 102
+ { 19, 24, 0, 0 }, // 103
+ { 11, 14, 106, 109 }, // 104
+ { 11, 14, 109, 113 }, // 105
+ { 14, 19, 27, 30 }, // 106
+ { 14, 19, 113, 117 }, // 107
+ { 7, 9, 98, 102 }, // 108
+ { 7, 9, 98, 102 }, // 109
+ { 9, 11, 102, 106 }, // 110
+ { 6, 7, 92, 93 }, // 111
+ { 6, 7, 93, 95 }, // 112
+ { 6, 7, 93, 95 }, // 113
+ { 6, 7, 95, 98 }, // 114
+ { 1, 2, 34, 37 }, // 115
+ { 7, 9, 41, 44 }, // 116
+ { 9, 11, 102, 106 }, // 117
+ { 11, 14, 22, 24 }, // 118
+ { 11, 14, 117, 120 }, // 119
+ { 19, 24, 0, 0 }, // 120
+ { 11, 14, 106, 109 }, // 121
+ { 11, 14, 120, 124 }, // 122
+ { 14, 19, 106, 109 }, // 123
+ { 14, 19, 124, 128 }, // 124
+ { 6, 7, 1, 3 }, // 125
+ { 6, 7, 13, 15 }, // 126
+ { 6, 7, 61, 64 }, // 127
+ { 0, 0, 0, 0 }, // 128
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+static const llvm::InstrItinerary GenericItineraries[] = {
+ { 0, 0, 0, 0 }, // 0
+ { 0, 0, 0, 0 }, // 1
+ { 0, 0, 0, 0 }, // 2
+ { 0, 0, 0, 0 }, // 3
+ { 0, 0, 0, 0 }, // 4
+ { 0, 0, 0, 0 }, // 5
+ { 0, 0, 0, 0 }, // 6
+ { 0, 0, 0, 0 }, // 7
+ { 0, 0, 0, 0 }, // 8
+ { 0, 0, 0, 0 }, // 9
+ { 0, 0, 0, 0 }, // 10
+ { 0, 0, 0, 0 }, // 11
+ { 0, 0, 0, 0 }, // 12
+ { 0, 0, 0, 0 }, // 13
+ { 0, 0, 0, 0 }, // 14
+ { 0, 0, 0, 0 }, // 15
+ { 0, 0, 0, 0 }, // 16
+ { 0, 0, 0, 0 }, // 17
+ { 0, 0, 0, 0 }, // 18
+ { 0, 0, 0, 0 }, // 19
+ { 0, 0, 0, 0 }, // 20
+ { 0, 0, 0, 0 }, // 21
+ { 0, 0, 0, 0 }, // 22
+ { 0, 0, 0, 0 }, // 23
+ { 0, 0, 0, 0 }, // 24
+ { 0, 0, 0, 0 }, // 25
+ { 0, 0, 0, 0 }, // 26
+ { 0, 0, 0, 0 }, // 27
+ { 0, 0, 0, 0 }, // 28
+ { 0, 0, 0, 0 }, // 29
+ { 0, 0, 0, 0 }, // 30
+ { 0, 0, 0, 0 }, // 31
+ { 0, 0, 0, 0 }, // 32
+ { 0, 0, 0, 0 }, // 33
+ { 0, 0, 0, 0 }, // 34
+ { 0, 0, 0, 0 }, // 35
+ { 0, 0, 0, 0 }, // 36
+ { 0, 0, 0, 0 }, // 37
+ { 0, 0, 0, 0 }, // 38
+ { 0, 0, 0, 0 }, // 39
+ { 0, 0, 0, 0 }, // 40
+ { 0, 0, 0, 0 }, // 41
+ { 0, 0, 0, 0 }, // 42
+ { 0, 0, 0, 0 }, // 43
+ { 0, 0, 0, 0 }, // 44
+ { 0, 0, 0, 0 }, // 45
+ { 0, 0, 0, 0 }, // 46
+ { 0, 0, 0, 0 }, // 47
+ { 0, 0, 0, 0 }, // 48
+ { 0, 0, 0, 0 }, // 49
+ { 0, 0, 0, 0 }, // 50
+ { 0, 0, 0, 0 }, // 51
+ { 0, 0, 0, 0 }, // 52
+ { 0, 0, 0, 0 }, // 53
+ { 0, 0, 0, 0 }, // 54
+ { 0, 0, 0, 0 }, // 55
+ { 0, 0, 0, 0 }, // 56
+ { 0, 0, 0, 0 }, // 57
+ { 0, 0, 0, 0 }, // 58
+ { 0, 0, 0, 0 }, // 59
+ { 0, 0, 0, 0 }, // 60
+ { 0, 0, 0, 0 }, // 61
+ { 0, 0, 0, 0 }, // 62
+ { 0, 0, 0, 0 }, // 63
+ { 0, 0, 0, 0 }, // 64
+ { 0, 0, 0, 0 }, // 65
+ { 0, 0, 0, 0 }, // 66
+ { 0, 0, 0, 0 }, // 67
+ { 0, 0, 0, 0 }, // 68
+ { 0, 0, 0, 0 }, // 69
+ { 0, 0, 0, 0 }, // 70
+ { 0, 0, 0, 0 }, // 71
+ { 0, 0, 0, 0 }, // 72
+ { 0, 0, 0, 0 }, // 73
+ { 0, 0, 0, 0 }, // 74
+ { 0, 0, 0, 0 }, // 75
+ { 0, 0, 0, 0 }, // 76
+ { 0, 0, 0, 0 }, // 77
+ { 0, 0, 0, 0 }, // 78
+ { 0, 0, 0, 0 }, // 79
+ { 0, 0, 0, 0 }, // 80
+ { 0, 0, 0, 0 }, // 81
+ { 0, 0, 0, 0 }, // 82
+ { 0, 0, 0, 0 }, // 83
+ { 0, 0, 0, 0 }, // 84
+ { 0, 0, 0, 0 }, // 85
+ { 0, 0, 0, 0 }, // 86
+ { 0, 0, 0, 0 }, // 87
+ { 0, 0, 0, 0 }, // 88
+ { 0, 0, 0, 0 }, // 89
+ { 0, 0, 0, 0 }, // 90
+ { 0, 0, 0, 0 }, // 91
+ { 0, 0, 0, 0 }, // 92
+ { 0, 0, 0, 0 }, // 93
+ { 0, 0, 0, 0 }, // 94
+ { 0, 0, 0, 0 }, // 95
+ { 0, 0, 0, 0 }, // 96
+ { 0, 0, 0, 0 }, // 97
+ { 0, 0, 0, 0 }, // 98
+ { 0, 0, 0, 0 }, // 99
+ { 0, 0, 0, 0 }, // 100
+ { 0, 0, 0, 0 }, // 101
+ { 0, 0, 0, 0 }, // 102
+ { 0, 0, 0, 0 }, // 103
+ { 0, 0, 0, 0 }, // 104
+ { 0, 0, 0, 0 }, // 105
+ { 0, 0, 0, 0 }, // 106
+ { 0, 0, 0, 0 }, // 107
+ { 0, 0, 0, 0 }, // 108
+ { 0, 0, 0, 0 }, // 109
+ { 0, 0, 0, 0 }, // 110
+ { 0, 0, 0, 0 }, // 111
+ { 0, 0, 0, 0 }, // 112
+ { 0, 0, 0, 0 }, // 113
+ { 0, 0, 0, 0 }, // 114
+ { 0, 0, 0, 0 }, // 115
+ { 0, 0, 0, 0 }, // 116
+ { 0, 0, 0, 0 }, // 117
+ { 0, 0, 0, 0 }, // 118
+ { 0, 0, 0, 0 }, // 119
+ { 0, 0, 0, 0 }, // 120
+ { 0, 0, 0, 0 }, // 121
+ { 0, 0, 0, 0 }, // 122
+ { 0, 0, 0, 0 }, // 123
+ { 0, 0, 0, 0 }, // 124
+ { 0, 0, 0, 0 }, // 125
+ { 0, 0, 0, 0 }, // 126
+ { 0, 0, 0, 0 }, // 127
+ { 0, 0, 0, 0 }, // 128
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+// Sorted (by key) array of itineraries for CPU subtype.
+static const llvm::SubtargetInfoKV ProcItinKV[] = {
+ { "arm1020e", (void *)&GenericItineraries },
+ { "arm1020t", (void *)&GenericItineraries },
+ { "arm1022e", (void *)&GenericItineraries },
+ { "arm10e", (void *)&GenericItineraries },
+ { "arm10tdmi", (void *)&GenericItineraries },
+ { "arm1136j-s", (void *)&ARMV6Itineraries },
+ { "arm1136jf-s", (void *)&ARMV6Itineraries },
+ { "arm1156t2-s", (void *)&ARMV6Itineraries },
+ { "arm1156t2f-s", (void *)&ARMV6Itineraries },
+ { "arm1176jz-s", (void *)&ARMV6Itineraries },
+ { "arm1176jzf-s", (void *)&ARMV6Itineraries },
+ { "arm710t", (void *)&GenericItineraries },
+ { "arm720t", (void *)&GenericItineraries },
+ { "arm7tdmi", (void *)&GenericItineraries },
+ { "arm7tdmi-s", (void *)&GenericItineraries },
+ { "arm8", (void *)&GenericItineraries },
+ { "arm810", (void *)&GenericItineraries },
+ { "arm9", (void *)&GenericItineraries },
+ { "arm920", (void *)&GenericItineraries },
+ { "arm920t", (void *)&GenericItineraries },
+ { "arm922t", (void *)&GenericItineraries },
+ { "arm926ej-s", (void *)&GenericItineraries },
+ { "arm940t", (void *)&GenericItineraries },
+ { "arm946e-s", (void *)&GenericItineraries },
+ { "arm966e-s", (void *)&GenericItineraries },
+ { "arm968e-s", (void *)&GenericItineraries },
+ { "arm9e", (void *)&GenericItineraries },
+ { "arm9tdmi", (void *)&GenericItineraries },
+ { "cortex-a8", (void *)&CortexA8Itineraries },
+ { "cortex-a9", (void *)&GenericItineraries },
+ { "ep9312", (void *)&GenericItineraries },
+ { "generic", (void *)&GenericItineraries },
+ { "iwmmxt", (void *)&GenericItineraries },
+ { "mpcore", (void *)&ARMV6Itineraries },
+ { "mpcorenovfp", (void *)&ARMV6Itineraries },
+ { "strongarm", (void *)&GenericItineraries },
+ { "strongarm110", (void *)&GenericItineraries },
+ { "strongarm1100", (void *)&GenericItineraries },
+ { "strongarm1110", (void *)&GenericItineraries },
+ { "xscale", (void *)&GenericItineraries }
+};
+
+enum {
+ ProcItinKVSize = sizeof(ProcItinKV)/sizeof(llvm::SubtargetInfoKV)
+};
+
+// ParseSubtargetFeatures - Parses features string setting specified
+// subtarget options.
+std::string llvm::ARMSubtarget::ParseSubtargetFeatures(const std::string &FS,
+ const std::string &CPU) {
+ DEBUG(errs() << "\nFeatures:" << FS);
+ DEBUG(errs() << "\nCPU:" << CPU);
+ SubtargetFeatures Features(FS);
+ Features.setCPUIfNone(CPU);
+ uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,
+ FeatureKV, FeatureKVSize);
+ if ((Bits & ArchV4T) != 0 && ARMArchVersion < V4T) ARMArchVersion = V4T;
+ if ((Bits & ArchV5T) != 0 && ARMArchVersion < V5T) ARMArchVersion = V5T;
+ if ((Bits & ArchV5TE) != 0 && ARMArchVersion < V5TE) ARMArchVersion = V5TE;
+ if ((Bits & ArchV6) != 0 && ARMArchVersion < V6) ARMArchVersion = V6;
+ if ((Bits & ArchV6T2) != 0 && ARMArchVersion < V6T2) ARMArchVersion = V6T2;
+ if ((Bits & ArchV7A) != 0 && ARMArchVersion < V7A) ARMArchVersion = V7A;
+ if ((Bits & FeatureNEON) != 0 && ARMFPUType < NEON) ARMFPUType = NEON;
+ if ((Bits & FeatureThumb2) != 0 && ThumbMode < Thumb2) ThumbMode = Thumb2;
+ if ((Bits & FeatureVFP2) != 0 && ARMFPUType < VFPv2) ARMFPUType = VFPv2;
+ if ((Bits & FeatureVFP3) != 0 && ARMFPUType < VFPv3) ARMFPUType = VFPv3;
+
+ InstrItinerary *Itinerary = (InstrItinerary *)Features.getInfo(ProcItinKV, ProcItinKVSize);
+ InstrItins = InstrItineraryData(Stages, OperandCycles, Itinerary);
+ return Features.getCPU();
+}
diff --git a/libclamav/c++/Makefile.am b/libclamav/c++/Makefile.am
index d20952f..ae441f1 100644
--- a/libclamav/c++/Makefile.am
+++ b/libclamav/c++/Makefile.am
@@ -37,7 +37,7 @@ endif
#libclamavcxx_la_CPPFLAGS = $(AM_CPPFLAGS) $(LLVM_INCLUDES) $(LLVM_DEFS)
#libclamavcxx_la_DEPENDENCIES = $(LLVM_DEPS)
-noinst_LTLIBRARIES = libclamavcxx.la libllvmsupport.la libllvmsystem.la\
+noinst_LTLIBRARIES = libclamavcxx.la libllvmsystem.la\
libllvmcodegen.la libllvmjit.la
lli_LDADD=libllvmbitreader.la libllvmfullcodegen.la libllvmjit.la
libclamavcxx_la_LIBADD=libllvmjit.la
@@ -68,7 +68,14 @@ libclamavcxx_la_LIBADD+=libllvmcodegen.la libllvmsystem.la
LLVM_CXXFLAGS=-Woverloaded-virtual -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-variadic-macros
-EXTRA_DIST=$(top_srcdir)/llvm llvmdejagnu.sh
+TBLGENFILES=llvm/include/llvm/Intrinsics.gen X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc X86GenInstrNames.inc X86GenInstrInfo.inc\
+ X86GenAsmWriter.inc X86GenAsmWriter1.inc X86GenAsmMatcher.inc X86GenDAGISel.inc X86GenFastISel.inc X86GenCallingConv.inc\
+ X86GenSubtarget.inc PPCGenInstrNames.inc PPCGenRegisterNames.inc PPCGenAsmWriter.inc PPCGenCodeEmitter.inc PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc\
+ PPCGenInstrInfo.inc PPCGenDAGISel.inc PPCGenCallingConv.inc PPCGenSubtarget.inc ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc ARMGenRegisterInfo.inc ARMGenInstrNames.inc ARMGenInstrInfo.inc ARMGenCodeEmitter.inc\
+ ARMGenAsmWriter.inc ARMGenDAGISel.inc ARMGenCallingConv.inc ARMGenSubtarget.inc
+
+BUILT_SOURCES=
+EXTRA_DIST=$(top_srcdir)/llvm llvmdejagnu.sh $(TBLGENFILES)
libllvmsystem_la_LDFLAGS=-pthread
libllvmsystem_la_LIBADD=
@@ -135,6 +142,9 @@ libllvmsupport_la_SOURCES=\
llvm/lib/Support/regfree.c\
llvm/lib/Support/regstrlcpy.c
+if MAINTAINER_MODE
+BUILT_SOURCES+=$(TBLGENFILES)
+noinst_PROGRAMS = tblgen
tblgen_CXXFLAGS=$(LLVM_CXXFLAGS)
tblgen_LDADD=libllvmsupport.la libllvmsystem.la
#TODO: if VERSIONSCRIPT
@@ -169,12 +179,10 @@ TBLGEN=$(top_builddir)/tblgen
TBLGEN_V=$(AM_V_GEN)$(TBLGEN)
TBLGEN_FLAGS=-I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
-BUILT_SOURCES=llvm/include/llvm/Intrinsics.gen
llvm/include/llvm/Intrinsics.gen: llvm/include/llvm/Intrinsics.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS) -gen-intrinsic -o $@ $<
# X86 Target
-if BUILD_X86
TBLGEN_FLAGS_X86= $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/X86
X86GenRegisterInfo.h.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-desc-header -o $@ $<
@@ -212,36 +220,6 @@ X86GenCallingConv.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
X86GenSubtarget.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-subtarget -o $@ $<
-libllvmx86codegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
-BUILT_SOURCES+=X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc X86GenInstrNames.inc X86GenInstrInfo.inc\
- X86GenAsmWriter.inc X86GenAsmWriter1.inc X86GenAsmMatcher.inc X86GenDAGISel.inc X86GenFastISel.inc X86GenCallingConv.inc\
- X86GenSubtarget.inc
-
-libllvmx86codegen_la_SOURCES=\
- llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
- llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
- llvm/lib/MC/MCAsmInfoCOFF.cpp\
- llvm/lib/MC/MCCodeEmitter.cpp\
- llvm/lib/Target/TargetELFWriterInfo.cpp\
- llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp\
- llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp\
- llvm/lib/Target/X86/X86CodeEmitter.cpp\
- llvm/lib/Target/X86/X86ELFWriterInfo.cpp\
- llvm/lib/Target/X86/X86FastISel.cpp\
- llvm/lib/Target/X86/X86FloatingPoint.cpp\
- llvm/lib/Target/X86/X86FloatingPointRegKill.cpp\
- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp\
- llvm/lib/Target/X86/X86ISelLowering.cpp\
- llvm/lib/Target/X86/X86InstrInfo.cpp\
- llvm/lib/Target/X86/X86JITInfo.cpp\
- llvm/lib/Target/X86/X86MCAsmInfo.cpp\
- llvm/lib/Target/X86/X86RegisterInfo.cpp\
- llvm/lib/Target/X86/X86Subtarget.cpp\
- llvm/lib/Target/X86/X86TargetMachine.cpp\
- llvm/lib/Target/X86/X86TargetObjectFile.cpp
-endif
-
-if BUILD_PPC
# PPC Target
TBLGEN_FLAGS_PPC= $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/PowerPC
PPCGenInstrNames.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
@@ -277,30 +255,6 @@ PPCGenCallingConv.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
PPCGenSubtarget.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-subtarget -o $@ $<
-libllvmpowerpccodegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/PowerPC
-BUILT_SOURCES += PPCGenInstrNames.inc PPCGenRegisterNames.inc PPCGenAsmWriter.inc PPCGenCodeEmitter.inc PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc\
- PPCGenInstrInfo.inc PPCGenDAGISel.inc PPCGenCallingConv.inc PPCGenSubtarget.inc
-
-libllvmpowerpccodegen_la_SOURCES=\
- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp\
- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp\
- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp\
- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp\
- llvm/lib/Target/PowerPC/PPCISelLowering.cpp\
- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp\
- llvm/lib/Target/PowerPC/PPCJITInfo.cpp\
- llvm/lib/Target/PowerPC/PPCMCAsmInfo.cpp\
- llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp\
- llvm/lib/Target/PowerPC/PPCPredicates.cpp\
- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp\
- llvm/lib/Target/PowerPC/PPCSubtarget.cpp\
- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp\
- llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp\
- llvm/lib/Target/TargetMachOWriterInfo.cpp
-
-endif
-
-if BUILD_ARM
# ARM Target
TBLGEN_FLAGS_ARM= $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
ARMGenRegisterInfo.h.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
@@ -332,11 +286,57 @@ ARMGenCallingConv.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
ARMGenSubtarget.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-subtarget -o $@ $<
+endif
-libllvmarmcodegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/ARM
-BUILT_SOURCES += ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc ARMGenRegisterInfo.inc ARMGenInstrNames.inc ARMGenInstrInfo.inc ARMGenCodeEmitter.inc\
- ARMGenAsmWriter.inc ARMGenDAGISel.inc ARMGenCallingConv.inc ARMGenSubtarget.inc
+if BUILD_X86
+libllvmx86codegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
+libllvmx86codegen_la_SOURCES=\
+ llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
+ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
+ llvm/lib/MC/MCAsmInfoCOFF.cpp\
+ llvm/lib/MC/MCCodeEmitter.cpp\
+ llvm/lib/Target/TargetELFWriterInfo.cpp\
+ llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp\
+ llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp\
+ llvm/lib/Target/X86/X86CodeEmitter.cpp\
+ llvm/lib/Target/X86/X86ELFWriterInfo.cpp\
+ llvm/lib/Target/X86/X86FastISel.cpp\
+ llvm/lib/Target/X86/X86FloatingPoint.cpp\
+ llvm/lib/Target/X86/X86FloatingPointRegKill.cpp\
+ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp\
+ llvm/lib/Target/X86/X86ISelLowering.cpp\
+ llvm/lib/Target/X86/X86InstrInfo.cpp\
+ llvm/lib/Target/X86/X86JITInfo.cpp\
+ llvm/lib/Target/X86/X86MCAsmInfo.cpp\
+ llvm/lib/Target/X86/X86RegisterInfo.cpp\
+ llvm/lib/Target/X86/X86Subtarget.cpp\
+ llvm/lib/Target/X86/X86TargetMachine.cpp\
+ llvm/lib/Target/X86/X86TargetObjectFile.cpp
+endif
+
+if BUILD_PPC
+libllvmpowerpccodegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/PowerPC
+libllvmpowerpccodegen_la_SOURCES=\
+ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp\
+ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp\
+ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp\
+ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp\
+ llvm/lib/Target/PowerPC/PPCISelLowering.cpp\
+ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp\
+ llvm/lib/Target/PowerPC/PPCJITInfo.cpp\
+ llvm/lib/Target/PowerPC/PPCMCAsmInfo.cpp\
+ llvm/lib/Target/PowerPC/PPCMachOWriterInfo.cpp\
+ llvm/lib/Target/PowerPC/PPCPredicates.cpp\
+ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp\
+ llvm/lib/Target/PowerPC/PPCSubtarget.cpp\
+ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp\
+ llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp\
+ llvm/lib/Target/TargetMachOWriterInfo.cpp
+endif
+
+if BUILD_ARM
+libllvmarmcodegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/ARM
libllvmarmcodegen_la_SOURCES=\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp\
@@ -687,7 +687,7 @@ FileCheck_CXXFLAGS=$(LLVM_CXXFLAGS)
FileCheck_LDADD=libllvmsupport.la libllvmsystem.la
FileCheck_SOURCES=llvm/utils/FileCheck/FileCheck.cpp
-check_LTLIBRARIES=libllvmbitreader.la libllvmfullcodegen.la libllvmasmprinter.la libllvmbitwriter.la libllvmasmparser.la libgoogletest.la libllvminterpreter.la
+check_LTLIBRARIES=libllvmbitreader.la libllvmsupport.la libllvmfullcodegen.la libllvmasmprinter.la libllvmbitwriter.la libllvmasmparser.la libgoogletest.la libllvminterpreter.la
check_PROGRAMS=count not lli llc llvm-as llvm-dis llvmunittest_ADT llvmunittest_Support llvmunittest_VMCore llvmunittest_ExecutionEngine llvmunittest_JIT FileCheck
check_SCRIPTS=llvmdejagnu.sh
TESTS_ENVIRONMENT=export GMAKE=@GMAKE@;
@@ -769,7 +769,6 @@ llvm_dis_LDADD=libllvmasmparser.la libllvmbitreader.la libllvmjit.la libllvmsupp
llvm_dis_SOURCES=\
llvm/tools/llvm-dis/llvm-dis.cpp
-noinst_PROGRAMS = tblgen
#bytecode2llvm.cpp: build-llvm
build-llvm:
@@ -783,8 +782,10 @@ build-llvm-for-check:
clean-local:
rm -rf `find llvm/test -name Output -type d -print`
rm -rf llvm/Release llvm/Debug
+if MAINTAINER_MODE
rm -f *.inc
rm -f llvm/include/llvm/Intrinsics.gen
+endif
rm -f llvm/test/site.exp llvm/test/site.bak llvm/test/*.out llvm/test/*.sum llvm/test/*.log
distclean-local:
@@ -814,6 +815,5 @@ dist-hook:
make -C llvm dist-hook
rm -f $(distdir)/llvm/include/llvm/Config/*.h $(distdir)/llvm/include/llvm/Config/*.def $(distdir)/llvm/Makefile.config $(distdir)/llvm/llvm.spec
rm -f $(distdir)/llvm/docs/doxygen.cfg $(distdir)/llvm/tools/llvmc/plugins/Base/Base.td $(distdir)/llvm/tools/llvm-config/llvm-config.in
- rm -f $(distdir)/llvm/include/llvm/Intrinsics.gen
rm -f $(distdir)/llvm/include/llvm/Support/DataTypes.h $(distdir)/llvm/config.log $(distdir)/llvm/config.status
diff --git a/libclamav/c++/Makefile.in b/libclamav/c++/Makefile.in
index e5b40b4..9d8d7f6 100644
--- a/libclamav/c++/Makefile.in
+++ b/libclamav/c++/Makefile.in
@@ -63,16 +63,8 @@ target_triplet = @target@
@BUILD_ARM_TRUE at am__append_10 = libllvmarmcodegen.la
@BUILD_ARM_TRUE at am__append_11 = libllvmarmcodegen.la
@BUILD_ARM_TRUE at am__append_12 = libllvmarmcodegen.la
- at BUILD_X86_TRUE@am__append_13 = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc X86GenInstrNames.inc X86GenInstrInfo.inc\
- at BUILD_X86_TRUE@ X86GenAsmWriter.inc X86GenAsmWriter1.inc X86GenAsmMatcher.inc X86GenDAGISel.inc X86GenFastISel.inc X86GenCallingConv.inc\
- at BUILD_X86_TRUE@ X86GenSubtarget.inc
-
- at BUILD_PPC_TRUE@am__append_14 = PPCGenInstrNames.inc PPCGenRegisterNames.inc PPCGenAsmWriter.inc PPCGenCodeEmitter.inc PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc\
- at BUILD_PPC_TRUE@ PPCGenInstrInfo.inc PPCGenDAGISel.inc PPCGenCallingConv.inc PPCGenSubtarget.inc
-
- at BUILD_ARM_TRUE@am__append_15 = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc ARMGenRegisterInfo.inc ARMGenInstrNames.inc ARMGenInstrInfo.inc ARMGenCodeEmitter.inc\
- at BUILD_ARM_TRUE@ ARMGenAsmWriter.inc ARMGenDAGISel.inc ARMGenCallingConv.inc ARMGenSubtarget.inc
-
+ at MAINTAINER_MODE_TRUE@am__append_13 = $(TBLGENFILES)
+ at MAINTAINER_MODE_TRUE@noinst_PROGRAMS = tblgen$(EXEEXT)
check_PROGRAMS = count$(EXEEXT) not$(EXEEXT) lli$(EXEEXT) llc$(EXEEXT) \
llvm-as$(EXEEXT) llvm-dis$(EXEEXT) llvmunittest_ADT$(EXEEXT) \
llvmunittest_Support$(EXEEXT) llvmunittest_VMCore$(EXEEXT) \
@@ -82,19 +74,18 @@ TESTS = llvmunittest_ADT$(EXEEXT) llvmunittest_Support$(EXEEXT) \
llvmunittest_VMCore$(EXEEXT) \
llvmunittest_ExecutionEngine$(EXEEXT) \
llvmunittest_JIT$(EXEEXT)
- at BUILD_X86_TRUE@am__append_16 = llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp\
+ at BUILD_X86_TRUE@am__append_14 = llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
- at BUILD_PPC_TRUE@am__append_17 = llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
- at BUILD_ARM_TRUE@am__append_18 = llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp \
+ at BUILD_PPC_TRUE@am__append_15 = llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+ at BUILD_ARM_TRUE@am__append_16 = llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp \
@BUILD_ARM_TRUE@ llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp\
@BUILD_ARM_TRUE@ llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
-noinst_PROGRAMS = tblgen$(EXEEXT)
subdir = .
DIST_COMMON = $(am__configure_deps) $(srcdir)/Makefile.am \
$(srcdir)/Makefile.in $(srcdir)/clamavcxx-config.h.in \
@@ -516,28 +507,58 @@ not_DEPENDENCIES = libllvmsystem.la
not_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) \
$(LIBTOOLFLAGS) --mode=link $(CXXLD) $(not_CXXFLAGS) \
$(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
-am_tblgen_OBJECTS = tblgen-AsmMatcherEmitter.$(OBJEXT) \
- tblgen-AsmWriterEmitter.$(OBJEXT) \
- tblgen-CallingConvEmitter.$(OBJEXT) \
- tblgen-ClangDiagnosticsEmitter.$(OBJEXT) \
- tblgen-CodeEmitterGen.$(OBJEXT) \
- tblgen-CodeGenDAGPatterns.$(OBJEXT) \
- tblgen-CodeGenInstruction.$(OBJEXT) \
- tblgen-CodeGenTarget.$(OBJEXT) \
- tblgen-DisassemblerEmitter.$(OBJEXT) \
- tblgen-DAGISelEmitter.$(OBJEXT) \
- tblgen-FastISelEmitter.$(OBJEXT) \
- tblgen-InstrEnumEmitter.$(OBJEXT) \
- tblgen-InstrInfoEmitter.$(OBJEXT) \
- tblgen-IntrinsicEmitter.$(OBJEXT) \
- tblgen-LLVMCConfigurationEmitter.$(OBJEXT) \
- tblgen-OptParserEmitter.$(OBJEXT) tblgen-Record.$(OBJEXT) \
- tblgen-RegisterInfoEmitter.$(OBJEXT) \
- tblgen-SubtargetEmitter.$(OBJEXT) tblgen-TGLexer.$(OBJEXT) \
- tblgen-TGParser.$(OBJEXT) tblgen-TGValueTypes.$(OBJEXT) \
- tblgen-TableGen.$(OBJEXT) tblgen-TableGenBackend.$(OBJEXT)
+am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
+ llvm/utils/TableGen/AsmWriterEmitter.cpp \
+ llvm/utils/TableGen/CallingConvEmitter.cpp \
+ llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp \
+ llvm/utils/TableGen/CodeEmitterGen.cpp \
+ llvm/utils/TableGen/CodeGenDAGPatterns.cpp \
+ llvm/utils/TableGen/CodeGenInstruction.cpp \
+ llvm/utils/TableGen/CodeGenTarget.cpp \
+ llvm/utils/TableGen/DisassemblerEmitter.cpp \
+ llvm/utils/TableGen/DAGISelEmitter.cpp \
+ llvm/utils/TableGen/FastISelEmitter.cpp \
+ llvm/utils/TableGen/InstrEnumEmitter.cpp \
+ llvm/utils/TableGen/InstrInfoEmitter.cpp \
+ llvm/utils/TableGen/IntrinsicEmitter.cpp \
+ llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp \
+ llvm/utils/TableGen/OptParserEmitter.cpp \
+ llvm/utils/TableGen/Record.cpp \
+ llvm/utils/TableGen/RegisterInfoEmitter.cpp \
+ llvm/utils/TableGen/SubtargetEmitter.cpp \
+ llvm/utils/TableGen/TGLexer.cpp \
+ llvm/utils/TableGen/TGParser.cpp \
+ llvm/utils/TableGen/TGValueTypes.cpp \
+ llvm/utils/TableGen/TableGen.cpp \
+ llvm/utils/TableGen/TableGenBackend.cpp
+ at MAINTAINER_MODE_TRUE@am_tblgen_OBJECTS = \
+ at MAINTAINER_MODE_TRUE@ tblgen-AsmMatcherEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-AsmWriterEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-CallingConvEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-ClangDiagnosticsEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-CodeEmitterGen.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-CodeGenDAGPatterns.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-CodeGenInstruction.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-CodeGenTarget.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DAGISelEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-FastISelEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-InstrEnumEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-InstrInfoEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-IntrinsicEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-LLVMCConfigurationEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-OptParserEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Record.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-RegisterInfoEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-SubtargetEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TGLexer.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TGParser.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TGValueTypes.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TableGen.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TableGenBackend.$(OBJEXT)
tblgen_OBJECTS = $(am_tblgen_OBJECTS)
-tblgen_DEPENDENCIES = libllvmsupport.la libllvmsystem.la
+ at MAINTAINER_MODE_TRUE@tblgen_DEPENDENCIES = libllvmsupport.la \
+ at MAINTAINER_MODE_TRUE@ libllvmsystem.la
tblgen_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) \
$(LIBTOOLFLAGS) --mode=link $(CXXLD) $(tblgen_CXXFLAGS) \
$(CXXFLAGS) $(tblgen_LDFLAGS) $(LDFLAGS) -o $@
@@ -615,7 +636,7 @@ DIST_SOURCES = $(libclamavcxx_la_SOURCES) $(libgoogletest_la_SOURCES) \
$(llvmunittest_ExecutionEngine_SOURCES) \
$(llvmunittest_JIT_SOURCES) $(llvmunittest_Support_SOURCES) \
$(llvmunittest_VMCore_SOURCES) $(not_SOURCES) \
- $(tblgen_SOURCES)
+ $(am__tblgen_SOURCES_DIST)
ETAGS = etags
CTAGS = ctags
# If stdout is a non-dumb tty, use colors. If test -t is not supported,
@@ -789,9 +810,9 @@ ACLOCAL_AMFLAGS = -I m4
#libclamavcxx_la_LDFLAGS = `$(LLVM_CONFIG) --ldflags --libs jit nativecodegen`
#libclamavcxx_la_CPPFLAGS = $(AM_CPPFLAGS) $(LLVM_INCLUDES) $(LLVM_DEFS)
#libclamavcxx_la_DEPENDENCIES = $(LLVM_DEPS)
-noinst_LTLIBRARIES = libclamavcxx.la libllvmsupport.la \
- libllvmsystem.la libllvmcodegen.la libllvmjit.la \
- $(am__append_4) $(am__append_8) $(am__append_12)
+noinst_LTLIBRARIES = libclamavcxx.la libllvmsystem.la \
+ libllvmcodegen.la libllvmjit.la $(am__append_4) \
+ $(am__append_8) $(am__append_12)
lli_LDADD = libllvmbitreader.la libllvmfullcodegen.la libllvmjit.la \
$(am__append_3) $(am__append_7) $(am__append_11) \
libllvmfullcodegen.la libllvmcodegen.la libllvmjit.la \
@@ -805,7 +826,17 @@ libclamavcxx_la_LDFLAGS = -no-undefined
libclamavcxx_la_CXXFLAGS = $(LLVM_CXXFLAGS)
libclamavcxx_la_SOURCES = bytecode2llvm.cpp
LLVM_CXXFLAGS = -Woverloaded-virtual -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-variadic-macros
-EXTRA_DIST = $(top_srcdir)/llvm llvmdejagnu.sh
+TBLGENFILES = llvm/include/llvm/Intrinsics.gen X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc X86GenInstrNames.inc X86GenInstrInfo.inc\
+ X86GenAsmWriter.inc X86GenAsmWriter1.inc X86GenAsmMatcher.inc X86GenDAGISel.inc X86GenFastISel.inc X86GenCallingConv.inc\
+ X86GenSubtarget.inc PPCGenInstrNames.inc PPCGenRegisterNames.inc PPCGenAsmWriter.inc PPCGenCodeEmitter.inc PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc\
+ PPCGenInstrInfo.inc PPCGenDAGISel.inc PPCGenCallingConv.inc PPCGenSubtarget.inc ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc ARMGenRegisterInfo.inc ARMGenInstrNames.inc ARMGenInstrInfo.inc ARMGenCodeEmitter.inc\
+ ARMGenAsmWriter.inc ARMGenDAGISel.inc ARMGenCallingConv.inc ARMGenSubtarget.inc
+
+
+# Rule to rerun LLVM's configure if it changed, before building anything else
+# LLVM
+BUILT_SOURCES = $(am__append_13) llvm/config.status
+EXTRA_DIST = $(top_srcdir)/llvm llvmdejagnu.sh $(TBLGENFILES)
libllvmsystem_la_LDFLAGS = -pthread
libllvmsystem_la_LIBADD =
libllvmsystem_la_SOURCES = llvm/lib/System/Alarm.cpp \
@@ -862,47 +893,48 @@ libllvmsupport_la_SOURCES = \
llvm/lib/Support/regfree.c\
llvm/lib/Support/regstrlcpy.c
-tblgen_CXXFLAGS = $(LLVM_CXXFLAGS)
-tblgen_LDADD = libllvmsupport.la libllvmsystem.la
+ at MAINTAINER_MODE_TRUE@tblgen_CXXFLAGS = $(LLVM_CXXFLAGS)
+ at MAINTAINER_MODE_TRUE@tblgen_LDADD = libllvmsupport.la libllvmsystem.la
#TODO: if VERSIONSCRIPT
-tblgen_LDFLAGS = -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMap.map
-tblgen_SOURCES = \
- llvm/utils/TableGen/AsmMatcherEmitter.cpp\
- llvm/utils/TableGen/AsmWriterEmitter.cpp\
- llvm/utils/TableGen/CallingConvEmitter.cpp\
- llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp\
- llvm/utils/TableGen/CodeEmitterGen.cpp\
- llvm/utils/TableGen/CodeGenDAGPatterns.cpp\
- llvm/utils/TableGen/CodeGenInstruction.cpp\
- llvm/utils/TableGen/CodeGenTarget.cpp\
- llvm/utils/TableGen/DisassemblerEmitter.cpp\
- llvm/utils/TableGen/DAGISelEmitter.cpp\
- llvm/utils/TableGen/FastISelEmitter.cpp\
- llvm/utils/TableGen/InstrEnumEmitter.cpp\
- llvm/utils/TableGen/InstrInfoEmitter.cpp\
- llvm/utils/TableGen/IntrinsicEmitter.cpp\
- llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp\
- llvm/utils/TableGen/OptParserEmitter.cpp\
- llvm/utils/TableGen/Record.cpp\
- llvm/utils/TableGen/RegisterInfoEmitter.cpp\
- llvm/utils/TableGen/SubtargetEmitter.cpp\
- llvm/utils/TableGen/TGLexer.cpp\
- llvm/utils/TableGen/TGParser.cpp\
- llvm/utils/TableGen/TGValueTypes.cpp\
- llvm/utils/TableGen/TableGen.cpp\
- llvm/utils/TableGen/TableGenBackend.cpp
-
-TBLGEN = $(top_builddir)/tblgen
-TBLGEN_V = $(AM_V_GEN)$(TBLGEN)
-TBLGEN_FLAGS = -I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
-
-# Rule to rerun LLVM's configure if it changed, before building anything else
-# LLVM
-BUILT_SOURCES = llvm/include/llvm/Intrinsics.gen $(am__append_13) \
- $(am__append_14) $(am__append_15) llvm/config.status
+ at MAINTAINER_MODE_TRUE@tblgen_LDFLAGS = -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMap.map
+ at MAINTAINER_MODE_TRUE@tblgen_SOURCES = \
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmMatcherEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmWriterEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CallingConvEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeEmitterGen.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenDAGPatterns.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenInstruction.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenTarget.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/FastISelEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/InstrEnumEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/InstrInfoEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/IntrinsicEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/LLVMCConfigurationEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/OptParserEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/Record.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/RegisterInfoEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/SubtargetEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TGLexer.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TGParser.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TGValueTypes.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGen.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGenBackend.cpp
+
+ at MAINTAINER_MODE_TRUE@TBLGEN = $(top_builddir)/tblgen
+ at MAINTAINER_MODE_TRUE@TBLGEN_V = $(AM_V_GEN)$(TBLGEN)
+ at MAINTAINER_MODE_TRUE@TBLGEN_FLAGS = -I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
# X86 Target
- at BUILD_X86_TRUE@TBLGEN_FLAGS_X86 = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/X86
+ at MAINTAINER_MODE_TRUE@TBLGEN_FLAGS_X86 = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/X86
+
+# PPC Target
+ at MAINTAINER_MODE_TRUE@TBLGEN_FLAGS_PPC = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/PowerPC
+
+# ARM Target
+ at MAINTAINER_MODE_TRUE@TBLGEN_FLAGS_ARM = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_X86_TRUE at libllvmx86codegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
@BUILD_X86_TRUE at libllvmx86codegen_la_SOURCES = \
@BUILD_X86_TRUE@ llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
@@ -927,9 +959,6 @@ BUILT_SOURCES = llvm/include/llvm/Intrinsics.gen $(am__append_13) \
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86TargetMachine.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86TargetObjectFile.cpp
-
-# PPC Target
- at BUILD_PPC_TRUE@TBLGEN_FLAGS_PPC = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/PowerPC
@BUILD_PPC_TRUE at libllvmpowerpccodegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/PowerPC
@BUILD_PPC_TRUE at libllvmpowerpccodegen_la_SOURCES = \
@BUILD_PPC_TRUE@ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp\
@@ -948,9 +977,6 @@ BUILT_SOURCES = llvm/include/llvm/Intrinsics.gen $(am__append_13) \
@BUILD_PPC_TRUE@ llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp\
@BUILD_PPC_TRUE@ llvm/lib/Target/TargetMachOWriterInfo.cpp
-
-# ARM Target
- at BUILD_ARM_TRUE@TBLGEN_FLAGS_ARM = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_ARM_TRUE at libllvmarmcodegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_ARM_TRUE at libllvmarmcodegen_la_SOURCES = \
@BUILD_ARM_TRUE@ llvm/lib/CodeGen/IfConversion.cpp\
@@ -1300,7 +1326,7 @@ FileCheck_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS)
FileCheck_CXXFLAGS = $(LLVM_CXXFLAGS)
FileCheck_LDADD = libllvmsupport.la libllvmsystem.la
FileCheck_SOURCES = llvm/utils/FileCheck/FileCheck.cpp
-check_LTLIBRARIES = libllvmbitreader.la libllvmfullcodegen.la libllvmasmprinter.la libllvmbitwriter.la libllvmasmparser.la libgoogletest.la libllvminterpreter.la
+check_LTLIBRARIES = libllvmbitreader.la libllvmsupport.la libllvmfullcodegen.la libllvmasmprinter.la libllvmbitwriter.la libllvmasmparser.la libgoogletest.la libllvminterpreter.la
check_SCRIPTS = llvmdejagnu.sh
TESTS_ENVIRONMENT = export GMAKE=@GMAKE@;
# Disable LLVM make check for now, there are some things to fix first:
@@ -1316,8 +1342,8 @@ libllvmasmprinter_la_SOURCES = \
llvm/lib/CodeGen/ELFCodeEmitter.cpp \
llvm/lib/CodeGen/ELFWriter.cpp \
llvm/lib/CodeGen/MachOCodeEmitter.cpp \
- llvm/lib/CodeGen/MachOWriter.cpp $(am__append_16) \
- $(am__append_17) $(am__append_18)
+ llvm/lib/CodeGen/MachOWriter.cpp $(am__append_14) \
+ $(am__append_15) $(am__append_16)
libllvmfullcodegen_la_SOURCES = \
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
@@ -6326,104 +6352,106 @@ uninstall-am:
mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
tags uninstall uninstall-am
-llvm/include/llvm/Intrinsics.gen: llvm/include/llvm/Intrinsics.td $(TBLGEN)
- $(TBLGEN_V) $(TBLGEN_FLAGS) -gen-intrinsic -o $@ $<
- at BUILD_X86_TRUE@X86GenRegisterInfo.h.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-desc-header -o $@ $<
- at BUILD_X86_TRUE@X86GenRegisterNames.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-enums -o $@ $<
+ at MAINTAINER_MODE_TRUE@llvm/include/llvm/Intrinsics.gen: llvm/include/llvm/Intrinsics.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS) -gen-intrinsic -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenRegisterInfo.h.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-desc-header -o $@ $<
+
+ at MAINTAINER_MODE_TRUE@X86GenRegisterNames.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-enums -o $@ $<
+
+ at MAINTAINER_MODE_TRUE@X86GenRegisterInfo.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-desc -o $@ $<
- at BUILD_X86_TRUE@X86GenRegisterInfo.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-register-desc -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenInstrNames.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-instr-enums -o $@ $<
- at BUILD_X86_TRUE@X86GenInstrNames.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-instr-enums -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenInstrInfo.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-instr-desc -o $@ $<
- at BUILD_X86_TRUE@X86GenInstrInfo.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-instr-desc -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenAsmWriter.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-asm-writer -o $@ $<
- at BUILD_X86_TRUE@X86GenAsmWriter.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-asm-writer -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenAsmWriter1.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-asm-writer -asmwriternum=1 -o $@ $<
- at BUILD_X86_TRUE@X86GenAsmWriter1.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-asm-writer -asmwriternum=1 -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenAsmMatcher.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-asm-matcher -o $@ $<
- at BUILD_X86_TRUE@X86GenAsmMatcher.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-asm-matcher -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenDAGISel.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-dag-isel -o $@ $<
- at BUILD_X86_TRUE@X86GenDAGISel.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-dag-isel -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenFastISel.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-fast-isel -o $@ $<
- at BUILD_X86_TRUE@X86GenFastISel.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-fast-isel -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenCallingConv.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-callingconv -o $@ $<
- at BUILD_X86_TRUE@X86GenCallingConv.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-callingconv -o $@ $<
+ at MAINTAINER_MODE_TRUE@X86GenSubtarget.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-subtarget -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenInstrNames.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-instr-enums -o $@ $<
- at BUILD_X86_TRUE@X86GenSubtarget.inc: llvm/lib/Target/X86/X86.td $(TBLGEN)
- at BUILD_X86_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_X86) -gen-subtarget -o $@ $<
- at BUILD_PPC_TRUE@PPCGenInstrNames.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-instr-enums -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenRegisterNames.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-enums -o $@ $<
- at BUILD_PPC_TRUE@PPCGenRegisterNames.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-enums -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenAsmWriter.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-asm-writer -o $@ $<
- at BUILD_PPC_TRUE@PPCGenAsmWriter.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-asm-writer -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenCodeEmitter.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-emitter -o $@ $<
- at BUILD_PPC_TRUE@PPCGenCodeEmitter.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-emitter -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCRegisterInfo.h.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-desc-header -o $@ $<
- at BUILD_PPC_TRUE@PPCRegisterInfo.h.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-desc-header -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenRegisterInfo.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-desc -o $@ $<
- at BUILD_PPC_TRUE@PPCGenRegisterInfo.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-desc -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenRegisterInfo.h.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-desc-header -o $@ $<
- at BUILD_PPC_TRUE@PPCGenRegisterInfo.h.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-register-desc-header -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenInstrInfo.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-instr-desc -o $@ $<
- at BUILD_PPC_TRUE@PPCGenInstrInfo.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-instr-desc -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenDAGISel.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-dag-isel -o $@ $<
- at BUILD_PPC_TRUE@PPCGenDAGISel.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-dag-isel -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenCallingConv.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-callingconv -o $@ $<
- at BUILD_PPC_TRUE@PPCGenCallingConv.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-callingconv -o $@ $<
+ at MAINTAINER_MODE_TRUE@PPCGenSubtarget.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-subtarget -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenRegisterInfo.h.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-register-desc-header -o $@ $<
- at BUILD_PPC_TRUE@PPCGenSubtarget.inc: llvm/lib/Target/PowerPC/PPC.td $(TBLGEN)
- at BUILD_PPC_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_PPC) -gen-subtarget -o $@ $<
- at BUILD_ARM_TRUE@ARMGenRegisterInfo.h.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-register-desc-header -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenRegisterNames.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-register-enums -o $@ $<
- at BUILD_ARM_TRUE@ARMGenRegisterNames.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-register-enums -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenRegisterInfo.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-register-desc -o $@ $<
- at BUILD_ARM_TRUE@ARMGenRegisterInfo.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-register-desc -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenInstrNames.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-instr-enums -o $@ $<
- at BUILD_ARM_TRUE@ARMGenInstrNames.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-instr-enums -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenInstrInfo.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-instr-desc -o $@ $<
- at BUILD_ARM_TRUE@ARMGenInstrInfo.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-instr-desc -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenCodeEmitter.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-emitter -o $@ $<
- at BUILD_ARM_TRUE@ARMGenCodeEmitter.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-emitter -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenAsmWriter.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-asm-writer -o $@ $<
- at BUILD_ARM_TRUE@ARMGenAsmWriter.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-asm-writer -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenDAGISel.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-dag-isel -o $@ $<
- at BUILD_ARM_TRUE@ARMGenDAGISel.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-dag-isel -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenCallingConv.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-callingconv -o $@ $<
- at BUILD_ARM_TRUE@ARMGenCallingConv.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-callingconv -o $@ $<
+ at MAINTAINER_MODE_TRUE@ARMGenSubtarget.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
+ at MAINTAINER_MODE_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-subtarget -o $@ $<
- at BUILD_ARM_TRUE@ARMGenSubtarget.inc: llvm/lib/Target/ARM/ARM.td $(TBLGEN)
- at BUILD_ARM_TRUE@ $(TBLGEN_V) $(TBLGEN_FLAGS_ARM) -gen-subtarget -o $@ $<
#bytecode2llvm.cpp: build-llvm
build-llvm:
@@ -6437,8 +6465,8 @@ build-llvm-for-check:
clean-local:
rm -rf `find llvm/test -name Output -type d -print`
rm -rf llvm/Release llvm/Debug
- rm -f *.inc
- rm -f llvm/include/llvm/Intrinsics.gen
+ at MAINTAINER_MODE_TRUE@ rm -f *.inc
+ at MAINTAINER_MODE_TRUE@ rm -f llvm/include/llvm/Intrinsics.gen
rm -f llvm/test/site.exp llvm/test/site.bak llvm/test/*.out llvm/test/*.sum llvm/test/*.log
distclean-local:
@@ -6463,7 +6491,6 @@ dist-hook:
make -C llvm dist-hook
rm -f $(distdir)/llvm/include/llvm/Config/*.h $(distdir)/llvm/include/llvm/Config/*.def $(distdir)/llvm/Makefile.config $(distdir)/llvm/llvm.spec
rm -f $(distdir)/llvm/docs/doxygen.cfg $(distdir)/llvm/tools/llvmc/plugins/Base/Base.td $(distdir)/llvm/tools/llvm-config/llvm-config.in
- rm -f $(distdir)/llvm/include/llvm/Intrinsics.gen
rm -f $(distdir)/llvm/include/llvm/Support/DataTypes.h $(distdir)/llvm/config.log $(distdir)/llvm/config.status
# Tell versions [3.59,3.63) of GNU make to not export all variables.
diff --git a/libclamav/c++/PPCGenAsmWriter.inc b/libclamav/c++/PPCGenAsmWriter.inc
new file mode 100644
index 0000000..7dab0d0
--- /dev/null
+++ b/libclamav/c++/PPCGenAsmWriter.inc
@@ -0,0 +1,1407 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Assembly Writer Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
+ static const unsigned OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // DBG_LABEL
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 1U, // ADD4
+ 6U, // ADD8
+ 11U, // ADDC
+ 11U, // ADDC8
+ 17U, // ADDE
+ 17U, // ADDE8
+ 4119U, // ADDI
+ 4119U, // ADDI8
+ 4125U, // ADDIC
+ 4125U, // ADDIC8
+ 4132U, // ADDICo
+ 8236U, // ADDIS
+ 8236U, // ADDIS8
+ 32819U, // ADDME
+ 32819U, // ADDME8
+ 32826U, // ADDZE
+ 32826U, // ADDZE8
+ 272629825U, // ADJCALLSTACKDOWN
+ 276824129U, // ADJCALLSTACKUP
+ 66U, // AND
+ 66U, // AND8
+ 71U, // ANDC
+ 71U, // ANDC8
+ 12365U, // ANDISo
+ 12365U, // ANDISo8
+ 12373U, // ANDIo
+ 12373U, // ANDIo8
+ 281018433U, // ATOMIC_CMP_SWAP_I16
+ 285212737U, // ATOMIC_CMP_SWAP_I32
+ 289407041U, // ATOMIC_CMP_SWAP_I64
+ 293601345U, // ATOMIC_CMP_SWAP_I8
+ 297795649U, // ATOMIC_LOAD_ADD_I16
+ 301989953U, // ATOMIC_LOAD_ADD_I32
+ 306184257U, // ATOMIC_LOAD_ADD_I64
+ 310378561U, // ATOMIC_LOAD_ADD_I8
+ 314572865U, // ATOMIC_LOAD_AND_I16
+ 318767169U, // ATOMIC_LOAD_AND_I32
+ 322961473U, // ATOMIC_LOAD_AND_I64
+ 327155777U, // ATOMIC_LOAD_AND_I8
+ 331350081U, // ATOMIC_LOAD_NAND_I16
+ 335544385U, // ATOMIC_LOAD_NAND_I32
+ 339738689U, // ATOMIC_LOAD_NAND_I64
+ 343932993U, // ATOMIC_LOAD_NAND_I8
+ 348127297U, // ATOMIC_LOAD_OR_I16
+ 352321601U, // ATOMIC_LOAD_OR_I32
+ 356515905U, // ATOMIC_LOAD_OR_I64
+ 360710209U, // ATOMIC_LOAD_OR_I8
+ 364904513U, // ATOMIC_LOAD_SUB_I16
+ 369098817U, // ATOMIC_LOAD_SUB_I32
+ 373293121U, // ATOMIC_LOAD_SUB_I64
+ 377487425U, // ATOMIC_LOAD_SUB_I8
+ 381681729U, // ATOMIC_LOAD_XOR_I16
+ 385876033U, // ATOMIC_LOAD_XOR_I32
+ 390070337U, // ATOMIC_LOAD_XOR_I64
+ 394264641U, // ATOMIC_LOAD_XOR_I8
+ 398458945U, // ATOMIC_SWAP_I16
+ 402653249U, // ATOMIC_SWAP_I32
+ 406847553U, // ATOMIC_SWAP_I64
+ 411041857U, // ATOMIC_SWAP_I8
+ 536871004U, // B
+ 952369247U, // BCC
+ 1073741921U, // BCTR
+ 1073741926U, // BCTRL8_Darwin
+ 1073741926U, // BCTRL8_ELF
+ 1073741926U, // BCTRL_Darwin
+ 1073741926U, // BCTRL_SVR4
+ 1493172332U, // BL8_Darwin
+ 1493172332U, // BL8_ELF
+ 1761607792U, // BLA8_Darwin
+ 1761607792U, // BLA8_ELF
+ 1761607792U, // BLA_Darwin
+ 1761607792U, // BLA_SVR4
+ 960495711U, // BLR
+ 1493172332U, // BL_Darwin
+ 1493172332U, // BL_SVR4
+ 117U, // CMPD
+ 4219U, // CMPDI
+ 130U, // CMPLD
+ 12425U, // CMPLDI
+ 145U, // CMPLW
+ 12440U, // CMPLWI
+ 160U, // CMPW
+ 4262U, // CMPWI
+ 32941U, // CNTLZD
+ 32949U, // CNTLZW
+ 189U, // CREQV
+ 196U, // CROR
+ 524477U, // CRSET
+ 1879048394U, // DCBA
+ 1879048400U, // DCBF
+ 1879048406U, // DCBI
+ 1879048412U, // DCBST
+ 1879048419U, // DCBT
+ 1879048425U, // DCBTST
+ 1879048433U, // DCBZ
+ 1879048439U, // DCBZL
+ 254U, // DIVD
+ 260U, // DIVDU
+ 267U, // DIVW
+ 273U, // DIVWU
+ 2147483928U, // DSS
+ 1073742109U, // DSSALL
+ 2415919396U, // DST
+ 2415919396U, // DST64
+ 2415919401U, // DSTST
+ 2415919401U, // DSTST64
+ 2415919408U, // DSTSTT
+ 2415919408U, // DSTSTT64
+ 2415919416U, // DSTT
+ 2415919416U, // DSTT64
+ 427819073U, // DYNALLOC
+ 432013377U, // DYNALLOC8
+ 318U, // EQV
+ 318U, // EQV8
+ 33091U, // EXTSB
+ 33091U, // EXTSB8
+ 33098U, // EXTSH
+ 33098U, // EXTSH8
+ 33105U, // EXTSW
+ 33105U, // EXTSW_32
+ 33105U, // EXTSW_32_64
+ 33112U, // FABSD
+ 33112U, // FABSS
+ 350U, // FADD
+ 356U, // FADDS
+ 350U, // FADDrtz
+ 33131U, // FCFID
+ 370U, // FCMPUD
+ 370U, // FCMPUS
+ 33145U, // FCTIDZ
+ 33153U, // FCTIWZ
+ 393U, // FDIV
+ 399U, // FDIVS
+ 406U, // FMADD
+ 413U, // FMADDS
+ 33189U, // FMRD
+ 33189U, // FMRS
+ 33189U, // FMRSD
+ 426U, // FMSUB
+ 433U, // FMSUBS
+ 441U, // FMUL
+ 447U, // FMULS
+ 33222U, // FNABSD
+ 33222U, // FNABSS
+ 33229U, // FNEGD
+ 33229U, // FNEGS
+ 467U, // FNMADD
+ 475U, // FNMADDS
+ 484U, // FNMSUB
+ 492U, // FNMSUBS
+ 33269U, // FRSP
+ 507U, // FSELD
+ 507U, // FSELS
+ 33281U, // FSQRT
+ 33288U, // FSQRTS
+ 528U, // FSUB
+ 534U, // FSUBS
+ 852509U, // LA
+ 1049121U, // LBZ
+ 1049121U, // LBZ8
+ 1311270U, // LBZU
+ 1311270U, // LBZU8
+ 1573420U, // LBZX
+ 1573420U, // LBZX8
+ 1835570U, // LD
+ 1573430U, // LDARX
+ 2097725U, // LDU
+ 1573442U, // LDX
+ 2359858U, // LDtoc
+ 1049159U, // LFD
+ 1311303U, // LFDU
+ 1573452U, // LFDX
+ 1049170U, // LFS
+ 1311314U, // LFSU
+ 1573463U, // LFSX
+ 1049181U, // LHA
+ 1049181U, // LHA8
+ 1311330U, // LHAU
+ 885346U, // LHAU8
+ 1573480U, // LHAX
+ 1573480U, // LHAX8
+ 1573486U, // LHBRX
+ 1049205U, // LHZ
+ 1049205U, // LHZ8
+ 1311354U, // LHZU
+ 1311354U, // LHZU8
+ 1573504U, // LHZX
+ 1573504U, // LHZX8
+ 2622086U, // LI
+ 2622086U, // LI8
+ 2884234U, // LIS
+ 2884234U, // LIS8
+ 1573519U, // LVEBX
+ 1573526U, // LVEHX
+ 1573533U, // LVEWX
+ 1573540U, // LVSL
+ 1573546U, // LVSR
+ 1573552U, // LVX
+ 1573557U, // LVXL
+ 1835707U, // LWA
+ 1573568U, // LWARX
+ 1573575U, // LWAX
+ 1573581U, // LWBRX
+ 1049300U, // LWZ
+ 1049300U, // LWZ8
+ 1311449U, // LWZU
+ 1311449U, // LWZU8
+ 1573599U, // LWZX
+ 1573599U, // LWZX8
+ 33509U, // MCRF
+ 150995691U, // MFCR
+ 150995697U, // MFCTR
+ 150995697U, // MFCTR8
+ 150995704U, // MFFS
+ 150995710U, // MFLR
+ 150995710U, // MFLR8
+ 3146475U, // MFOCRF
+ 167772932U, // MFVRSAVE
+ 150995723U, // MFVSCR
+ 2684355347U, // MTCRF
+ 150995738U, // MTCTR
+ 150995738U, // MTCTR8
+ 2952790817U, // MTFSB0
+ 2952790825U, // MTFSB1
+ 3393192753U, // MTFSF
+ 150995768U, // MTLR
+ 150995768U, // MTLR8
+ 150995774U, // MTVRSAVE
+ 150995786U, // MTVSCR
+ 850U, // MULHD
+ 857U, // MULHDU
+ 865U, // MULHW
+ 872U, // MULHWU
+ 880U, // MULLD
+ 4983U, // MULLI
+ 894U, // MULLW
+ 3489661036U, // MovePCtoLR
+ 3489661036U, // MovePCtoLR8
+ 901U, // NAND
+ 901U, // NAND8
+ 33675U, // NEG
+ 33675U, // NEG8
+ 1073742736U, // NOP
+ 916U, // NOR
+ 916U, // NOR8
+ 921U, // OR
+ 921U, // OR4To8
+ 921U, // OR8
+ 921U, // OR8To4
+ 925U, // ORC
+ 925U, // ORC8
+ 13218U, // ORI
+ 13218U, // ORI8
+ 13223U, // ORIS
+ 13223U, // ORIS8
+ 941U, // RLDCL
+ 17332U, // RLDICL
+ 17340U, // RLDICR
+ 3539908U, // RLDIMI
+ 3572684U, // RLWIMI
+ 21460U, // RLWINM
+ 21468U, // RLWINMo
+ 997U, // RLWNM
+ 444596289U, // SELECT_CC_F4
+ 444596289U, // SELECT_CC_F8
+ 444596289U, // SELECT_CC_I4
+ 444596289U, // SELECT_CC_I8
+ 444596289U, // SELECT_CC_VRRC
+ 1004U, // SLD
+ 1009U, // SLW
+ 448790593U, // SPILL_CR
+ 1014U, // SRAD
+ 17404U, // SRADI
+ 1027U, // SRAW
+ 21513U, // SRAWI
+ 1040U, // SRD
+ 1045U, // SRW
+ 1049626U, // STB
+ 1049626U, // STB8
+ 3405775903U, // STBU
+ 3405775903U, // STBU8
+ 1573925U, // STBX
+ 1573925U, // STBX8
+ 1836075U, // STD
+ 1573936U, // STDCX
+ 3409970232U, // STDU
+ 1573950U, // STDUX
+ 1573957U, // STDX
+ 1573957U, // STDX_32
+ 1836075U, // STD_32
+ 1049675U, // STFD
+ 3405775953U, // STFDU
+ 1573976U, // STFDX
+ 1573983U, // STFIWX
+ 1049703U, // STFS
+ 3405775981U, // STFSU
+ 1574004U, // STFSX
+ 1049723U, // STH
+ 1049723U, // STH8
+ 1574016U, // STHBRX
+ 3405776008U, // STHU
+ 3405776008U, // STHU8
+ 1574030U, // STHX
+ 1574030U, // STHX8
+ 1574036U, // STVEBX
+ 1574044U, // STVEHX
+ 1574052U, // STVEWX
+ 1574060U, // STVX
+ 1574066U, // STVXL
+ 1049785U, // STW
+ 1049785U, // STW8
+ 1574078U, // STWBRX
+ 1574086U, // STWCX
+ 3405776078U, // STWU
+ 3405776078U, // STWU8
+ 1236U, // STWUX
+ 1574107U, // STWX
+ 1574107U, // STWX8
+ 1249U, // SUBF
+ 1249U, // SUBF8
+ 1255U, // SUBFC
+ 1255U, // SUBFC8
+ 1262U, // SUBFE
+ 1262U, // SUBFE8
+ 5365U, // SUBFIC
+ 5365U, // SUBFIC8
+ 34045U, // SUBFME
+ 34045U, // SUBFME8
+ 34053U, // SUBFZE
+ 34053U, // SUBFZE8
+ 1073743117U, // SYNC
+ 1493172316U, // TAILB
+ 1493172316U, // TAILB8
+ 1761608978U, // TAILBA
+ 1761608978U, // TAILBA8
+ 1073741921U, // TAILBCTR
+ 1073741921U, // TAILBCTR8
+ 1757447446U, // TCRETURNai
+ 1757447459U, // TCRETURNai8
+ 1489012017U, // TCRETURNdi
+ 1489012030U, // TCRETURNdi8
+ 146834764U, // TCRETURNri
+ 146834777U, // TCRETURNri8
+ 1073743207U, // TRAP
+ 34156U, // UPDATE_VRSAVE
+ 1403U, // VADDCUW
+ 1412U, // VADDFP
+ 1420U, // VADDSBS
+ 1429U, // VADDSHS
+ 1438U, // VADDSWS
+ 1447U, // VADDUBM
+ 1456U, // VADDUBS
+ 1465U, // VADDUHM
+ 1474U, // VADDUHS
+ 1483U, // VADDUWM
+ 1492U, // VADDUWS
+ 1501U, // VAND
+ 1507U, // VANDC
+ 1514U, // VAVGSB
+ 1522U, // VAVGSH
+ 1530U, // VAVGSW
+ 1538U, // VAVGUB
+ 1546U, // VAVGUH
+ 1554U, // VAVGUW
+ 3606042U, // VCFSX
+ 3606049U, // VCFUX
+ 1576U, // VCMPBFP
+ 1585U, // VCMPBFPo
+ 1595U, // VCMPEQFP
+ 1605U, // VCMPEQFPo
+ 1616U, // VCMPEQUB
+ 1626U, // VCMPEQUBo
+ 1637U, // VCMPEQUH
+ 1647U, // VCMPEQUHo
+ 1658U, // VCMPEQUW
+ 1668U, // VCMPEQUWo
+ 1679U, // VCMPGEFP
+ 1689U, // VCMPGEFPo
+ 1700U, // VCMPGTFP
+ 1710U, // VCMPGTFPo
+ 1721U, // VCMPGTSB
+ 1731U, // VCMPGTSBo
+ 1742U, // VCMPGTSH
+ 1752U, // VCMPGTSHo
+ 1763U, // VCMPGTSW
+ 1773U, // VCMPGTSWo
+ 1784U, // VCMPGTUB
+ 1794U, // VCMPGTUBo
+ 1805U, // VCMPGTUH
+ 1815U, // VCMPGTUHo
+ 1826U, // VCMPGTUW
+ 1836U, // VCMPGTUWo
+ 3606327U, // VCTSXS
+ 3606335U, // VCTUXS
+ 34631U, // VEXPTEFP
+ 34641U, // VLOGEFP
+ 1882U, // VMADDFP
+ 1891U, // VMAXFP
+ 1899U, // VMAXSB
+ 1907U, // VMAXSH
+ 1915U, // VMAXSW
+ 1923U, // VMAXUB
+ 1931U, // VMAXUH
+ 1939U, // VMAXUW
+ 1947U, // VMHADDSHS
+ 1958U, // VMHRADDSHS
+ 1970U, // VMINFP
+ 1978U, // VMINSB
+ 1986U, // VMINSH
+ 1994U, // VMINSW
+ 2002U, // VMINUB
+ 2010U, // VMINUH
+ 2018U, // VMINUW
+ 2026U, // VMLADDUHM
+ 2037U, // VMRGHB
+ 2045U, // VMRGHH
+ 2053U, // VMRGHW
+ 2061U, // VMRGLB
+ 2069U, // VMRGLH
+ 2077U, // VMRGLW
+ 2085U, // VMSUMMBM
+ 2095U, // VMSUMSHM
+ 2105U, // VMSUMSHS
+ 2115U, // VMSUMUBM
+ 2125U, // VMSUMUHM
+ 2135U, // VMSUMUHS
+ 2145U, // VMULESB
+ 2154U, // VMULESH
+ 2163U, // VMULEUB
+ 2172U, // VMULEUH
+ 2181U, // VMULOSB
+ 2190U, // VMULOSH
+ 2199U, // VMULOUB
+ 2208U, // VMULOUH
+ 2217U, // VNMSUBFP
+ 2227U, // VNOR
+ 2233U, // VOR
+ 2238U, // VPERM
+ 2245U, // VPKPX
+ 2252U, // VPKSHSS
+ 2261U, // VPKSHUS
+ 2270U, // VPKSWSS
+ 2279U, // VPKSWUS
+ 2288U, // VPKUHUM
+ 2297U, // VPKUHUS
+ 2306U, // VPKUWUM
+ 2315U, // VPKUWUS
+ 35092U, // VREFP
+ 35099U, // VRFIM
+ 35106U, // VRFIN
+ 35113U, // VRFIP
+ 35120U, // VRFIZ
+ 2359U, // VRLB
+ 2365U, // VRLH
+ 2371U, // VRLW
+ 35145U, // VRSQRTEFP
+ 2388U, // VSEL
+ 2394U, // VSL
+ 2399U, // VSLB
+ 2405U, // VSLDOI
+ 2413U, // VSLH
+ 2419U, // VSLO
+ 2425U, // VSLW
+ 3606911U, // VSPLTB
+ 3606919U, // VSPLTH
+ 3672463U, // VSPLTISB
+ 3672473U, // VSPLTISH
+ 3672483U, // VSPLTISW
+ 3606957U, // VSPLTW
+ 2485U, // VSR
+ 2490U, // VSRAB
+ 2497U, // VSRAH
+ 2504U, // VSRAW
+ 2511U, // VSRB
+ 2517U, // VSRH
+ 2523U, // VSRO
+ 2529U, // VSRW
+ 2535U, // VSUBCUW
+ 2544U, // VSUBFP
+ 2552U, // VSUBSBS
+ 2561U, // VSUBSHS
+ 2570U, // VSUBSWS
+ 2579U, // VSUBUBM
+ 2588U, // VSUBUBS
+ 2597U, // VSUBUHM
+ 2606U, // VSUBUHS
+ 2615U, // VSUBUWM
+ 2624U, // VSUBUWS
+ 2633U, // VSUM2SWS
+ 2643U, // VSUM4SBS
+ 2653U, // VSUM4SHS
+ 2663U, // VSUM4UBS
+ 2673U, // VSUMSWS
+ 35450U, // VUPKHPX
+ 35459U, // VUPKHSB
+ 35468U, // VUPKHSH
+ 35477U, // VUPKLPX
+ 35486U, // VUPKLSB
+ 35495U, // VUPKLSH
+ 2736U, // VXOR
+ 527024U, // V_SET0
+ 2742U, // XOR
+ 2742U, // XOR8
+ 15035U, // XORI
+ 15035U, // XORI8
+ 15041U, // XORIS
+ 15041U, // XORIS8
+ 0U
+ };
+
+ const char *AsmStrs =
+ "add \000add \000addc \000adde \000addi \000addic \000addic. \000addis \000"
+ "addme \000addze \000\000and \000andc \000andis. \000andi. \000b \000b\000"
+ "bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000cmpldi \000"
+ "cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000creqv \000"
+ "cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst \000dcbz "
+ "\000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000dssall\000d"
+ "st \000dstst \000dststt \000dstt \000eqv \000extsb \000extsh \000extsw "
+ "\000fabs \000fadd \000fadds \000fcfid \000fcmpu \000fctidz \000fctiwz \000"
+ "fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fmsubs \000fm"
+ "ul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000fnmsub \000f"
+ "nmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000fsubs \000la"
+ " \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx \000lfd \000"
+ "lfdx \000lfs \000lfsx \000lha \000lhau \000lhax \000lhbrx \000lhz \000l"
+ "hzu \000lhzx \000li \000lis \000lvebx \000lvehx \000lvewx \000lvsl \000"
+ "lvsr \000lvx \000lvxl \000lwa \000lwarx \000lwax \000lwbrx \000lwz \000"
+ "lwzu \000lwzx \000mcrf \000mfcr \000mfctr \000mffs \000mflr \000mfspr \000"
+ "mfvscr \000mtcrf \000mtctr \000mtfsb0 \000mtfsb1 \000mtfsf \000mtlr \000"
+ "mtspr 256, \000mtvscr \000mulhd \000mulhdu \000mulhw \000mulhwu \000mul"
+ "ld \000mulli \000mullw \000nand \000neg \000nop\000nor \000or \000orc \000"
+ "ori \000oris \000rldcl \000rldicl \000rldicr \000rldimi \000rlwimi \000"
+ "rlwinm \000rlwinm. \000rlwnm \000sld \000slw \000srad \000sradi \000sra"
+ "w \000srawi \000srd \000srw \000stb \000stbu \000stbx \000std \000stdcx"
+ ". \000stdu \000stdux \000stdx \000stfd \000stfdu \000stfdx \000stfiwx \000"
+ "stfs \000stfsu \000stfsx \000sth \000sthbrx \000sthu \000sthx \000stveb"
+ "x \000stvehx \000stvewx \000stvx \000stvxl \000stw \000stwbrx \000stwcx"
+ ". \000stwu \000stwux \000stwx \000subf \000subfc \000subfe \000subfic \000"
+ "subfme \000subfze \000sync\000ba \000#TC_RETURNa \000#TC_RETURNa8 \000#"
+ "TC_RETURNd \000#TC_RETURNd8 \000#TC_RETURNr \000#TC_RETURNr8 \000trap\000"
+ "UPDATE_VRSAVE \000vaddcuw \000vaddfp \000vaddsbs \000vaddshs \000vaddsw"
+ "s \000vaddubm \000vaddubs \000vadduhm \000vadduhs \000vadduwm \000vaddu"
+ "ws \000vand \000vandc \000vavgsb \000vavgsh \000vavgsw \000vavgub \000v"
+ "avguh \000vavguw \000vcfsx \000vcfux \000vcmpbfp \000vcmpbfp. \000vcmpe"
+ "qfp \000vcmpeqfp. \000vcmpequb \000vcmpequb. \000vcmpequh \000vcmpequh."
+ " \000vcmpequw \000vcmpequw. \000vcmpgefp \000vcmpgefp. \000vcmpgtfp \000"
+ "vcmpgtfp. \000vcmpgtsb \000vcmpgtsb. \000vcmpgtsh \000vcmpgtsh. \000vcm"
+ "pgtsw \000vcmpgtsw. \000vcmpgtub \000vcmpgtub. \000vcmpgtuh \000vcmpgtu"
+ "h. \000vcmpgtuw \000vcmpgtuw. \000vctsxs \000vctuxs \000vexptefp \000vl"
+ "ogefp \000vmaddfp \000vmaxfp \000vmaxsb \000vmaxsh \000vmaxsw \000vmaxu"
+ "b \000vmaxuh \000vmaxuw \000vmhaddshs \000vmhraddshs \000vminfp \000vmi"
+ "nsb \000vminsh \000vminsw \000vminub \000vminuh \000vminuw \000vmladduh"
+ "m \000vmrghb \000vmrghh \000vmrghw \000vmrglb \000vmrglh \000vmrglw \000"
+ "vmsummbm \000vmsumshm \000vmsumshs \000vmsumubm \000vmsumuhm \000vmsumu"
+ "hs \000vmulesb \000vmulesh \000vmuleub \000vmuleuh \000vmulosb \000vmul"
+ "osh \000vmuloub \000vmulouh \000vnmsubfp \000vnor \000vor \000vperm \000"
+ "vpkpx \000vpkshss \000vpkshus \000vpkswss \000vpkswus \000vpkuhum \000v"
+ "pkuhus \000vpkuwum \000vpkuwus \000vrefp \000vrfim \000vrfin \000vrfip "
+ "\000vrfiz \000vrlb \000vrlh \000vrlw \000vrsqrtefp \000vsel \000vsl \000"
+ "vslb \000vsldoi \000vslh \000vslo \000vslw \000vspltb \000vsplth \000vs"
+ "pltisb \000vspltish \000vspltisw \000vspltw \000vsr \000vsrab \000vsrah"
+ " \000vsraw \000vsrb \000vsrh \000vsro \000vsrw \000vsubcuw \000vsubfp \000"
+ "vsubsbs \000vsubshs \000vsubsws \000vsububm \000vsububs \000vsubuhm \000"
+ "vsubuhs \000vsubuwm \000vsubuws \000vsum2sws \000vsum4sbs \000vsum4shs "
+ "\000vsum4ubs \000vsumsws \000vupkhpx \000vupkhsb \000vupkhsh \000vupklp"
+ "x \000vupklsb \000vupklsh \000vxor \000xor \000xori \000xoris \000";
+
+
+#ifndef NO_ASM_WRITER_BOILERPLATE
+ if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+ printInlineAsm(MI);
+ return;
+ } else if (MI->isLabel()) {
+ printLabel(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ printImplicitDef(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
+ printKill(MI);
+ return;
+ }
+
+
+#endif
+ O << "\t";
+
+ // Emit the opcode for the instruction.
+ unsigned Bits = OpInfo[MI->getOpcode()];
+ assert(Bits != 0 && "Cannot print this instruction.");
+ O << AsmStrs+(Bits & 4095)-1;
+
+
+ // Fragment 0 encoded into 4 bits for 14 unique commands.
+ switch ((Bits >> 28) & 15) {
+ default: // unreachable.
+ case 0:
+ // ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
+ printOperand(MI, 0);
+ break;
+ case 1:
+ // ADJCALLSTACKDOWN, ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP...
+ PrintSpecial(MI, "comment");
+ break;
+ case 2:
+ // B
+ printBranchOperand(MI, 0);
+ return;
+ break;
+ case 3:
+ // BCC, BLR
+ printPredicateOperand(MI, 0, "cc");
+ break;
+ case 4:
+ // BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, DSSALL, NOP...
+ return;
+ break;
+ case 5:
+ // BL8_Darwin, BL8_ELF, BL_Darwin, BL_SVR4, TAILB, TAILB8, TCRETURNdi, TC...
+ printCallOperand(MI, 0);
+ break;
+ case 6:
+ // BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, TAILBA, TAILBA8, TCRETURN...
+ printAbsAddrOperand(MI, 0);
+ break;
+ case 7:
+ // DCBA, DCBF, DCBI, DCBST, DCBT, DCBTST, DCBZ, DCBZL
+ printMemRegReg(MI, 0);
+ return;
+ break;
+ case 8:
+ // DSS
+ printU5ImmOperand(MI, 1);
+ return;
+ break;
+ case 9:
+ // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 3);
+ O << ", ";
+ printU5ImmOperand(MI, 1);
+ return;
+ break;
+ case 10:
+ // MTCRF
+ printcrbitm(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 11:
+ // MTFSB0, MTFSB1
+ printU5ImmOperand(MI, 0);
+ return;
+ break;
+ case 12:
+ // MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU, STWU8
+ printOperand(MI, 1);
+ O << ", ";
+ break;
+ case 13:
+ // MovePCtoLR, MovePCtoLR8
+ printPICLabel(MI, 0);
+ return;
+ break;
+ }
+
+
+ // Fragment 1 encoded into 6 bits for 46 unique commands.
+ switch ((Bits >> 22) & 63) {
+ default: // unreachable.
+ case 0:
+ // ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
+ O << ", ";
+ break;
+ case 1:
+ // ADJCALLSTACKDOWN
+ O << " ADJCALLSTACKDOWN";
+ return;
+ break;
+ case 2:
+ // ADJCALLSTACKUP
+ O << " ADJCALLSTACKUP";
+ return;
+ break;
+ case 3:
+ // ATOMIC_CMP_SWAP_I16
+ O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
+ return;
+ break;
+ case 4:
+ // ATOMIC_CMP_SWAP_I32
+ O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
+ return;
+ break;
+ case 5:
+ // ATOMIC_CMP_SWAP_I64
+ O << " ATOMIC_CMP_SWAP_I64 PSEUDO!";
+ return;
+ break;
+ case 6:
+ // ATOMIC_CMP_SWAP_I8
+ O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
+ return;
+ break;
+ case 7:
+ // ATOMIC_LOAD_ADD_I16
+ O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
+ return;
+ break;
+ case 8:
+ // ATOMIC_LOAD_ADD_I32
+ O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
+ return;
+ break;
+ case 9:
+ // ATOMIC_LOAD_ADD_I64
+ O << " ATOMIC_LOAD_ADD_I64 PSEUDO!";
+ return;
+ break;
+ case 10:
+ // ATOMIC_LOAD_ADD_I8
+ O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
+ return;
+ break;
+ case 11:
+ // ATOMIC_LOAD_AND_I16
+ O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
+ return;
+ break;
+ case 12:
+ // ATOMIC_LOAD_AND_I32
+ O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
+ return;
+ break;
+ case 13:
+ // ATOMIC_LOAD_AND_I64
+ O << " ATOMIC_LOAD_AND_I64 PSEUDO!";
+ return;
+ break;
+ case 14:
+ // ATOMIC_LOAD_AND_I8
+ O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
+ return;
+ break;
+ case 15:
+ // ATOMIC_LOAD_NAND_I16
+ O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
+ return;
+ break;
+ case 16:
+ // ATOMIC_LOAD_NAND_I32
+ O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
+ return;
+ break;
+ case 17:
+ // ATOMIC_LOAD_NAND_I64
+ O << " ATOMIC_LOAD_NAND_I64 PSEUDO!";
+ return;
+ break;
+ case 18:
+ // ATOMIC_LOAD_NAND_I8
+ O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
+ return;
+ break;
+ case 19:
+ // ATOMIC_LOAD_OR_I16
+ O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
+ return;
+ break;
+ case 20:
+ // ATOMIC_LOAD_OR_I32
+ O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
+ return;
+ break;
+ case 21:
+ // ATOMIC_LOAD_OR_I64
+ O << " ATOMIC_LOAD_OR_I64 PSEUDO!";
+ return;
+ break;
+ case 22:
+ // ATOMIC_LOAD_OR_I8
+ O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
+ return;
+ break;
+ case 23:
+ // ATOMIC_LOAD_SUB_I16
+ O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
+ return;
+ break;
+ case 24:
+ // ATOMIC_LOAD_SUB_I32
+ O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
+ return;
+ break;
+ case 25:
+ // ATOMIC_LOAD_SUB_I64
+ O << " ATOMIC_LOAD_SUB_I64 PSEUDO!";
+ return;
+ break;
+ case 26:
+ // ATOMIC_LOAD_SUB_I8
+ O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
+ return;
+ break;
+ case 27:
+ // ATOMIC_LOAD_XOR_I16
+ O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
+ return;
+ break;
+ case 28:
+ // ATOMIC_LOAD_XOR_I32
+ O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
+ return;
+ break;
+ case 29:
+ // ATOMIC_LOAD_XOR_I64
+ O << " ATOMIC_LOAD_XOR_I64 PSEUDO!";
+ return;
+ break;
+ case 30:
+ // ATOMIC_LOAD_XOR_I8
+ O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
+ return;
+ break;
+ case 31:
+ // ATOMIC_SWAP_I16
+ O << " ATOMIC_SWAP_I16 PSEUDO!";
+ return;
+ break;
+ case 32:
+ // ATOMIC_SWAP_I32
+ O << " ATOMIC_SWAP_I32 PSEUDO!";
+ return;
+ break;
+ case 33:
+ // ATOMIC_SWAP_I64
+ O << " ATOMIC_SWAP_I64 PSEUDO!";
+ return;
+ break;
+ case 34:
+ // ATOMIC_SWAP_I8
+ O << " ATOMIC_SWAP_I8 PSEUDO!";
+ return;
+ break;
+ case 35:
+ // BCC, TCRETURNai, TCRETURNai8, TCRETURNdi, TCRETURNdi8, TCRETURNri, TCR...
+ O << ' ';
+ break;
+ case 36:
+ // BL8_Darwin, BL8_ELF, BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, BL_D...
+ return;
+ break;
+ case 37:
+ // BLR
+ O << "lr ";
+ printPredicateOperand(MI, 0, "reg");
+ return;
+ break;
+ case 38:
+ // DYNALLOC
+ O << " DYNALLOC ";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printMemRegImm(MI, 2);
+ return;
+ break;
+ case 39:
+ // DYNALLOC8
+ O << " DYNALLOC8 ";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printMemRegImm(MI, 2);
+ return;
+ break;
+ case 40:
+ // MFVRSAVE
+ O << ", 256";
+ return;
+ break;
+ case 41:
+ // MTFSF
+ printOperand(MI, 2);
+ return;
+ break;
+ case 42:
+ // SELECT_CC_F4, SELECT_CC_F8, SELECT_CC_I4, SELECT_CC_I8, SELECT_CC_VRRC
+ O << " SELECT_CC PSEUDO!";
+ return;
+ break;
+ case 43:
+ // SPILL_CR
+ O << " SPILL_CR ";
+ printOperand(MI, 0);
+ O << ' ';
+ printMemRegImm(MI, 1);
+ return;
+ break;
+ case 44:
+ // STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU, STWU8
+ printSymbolLo(MI, 2);
+ O << '(';
+ printOperand(MI, 3);
+ O << ')';
+ return;
+ break;
+ case 45:
+ // STDU
+ printS16X4ImmOperand(MI, 2);
+ O << '(';
+ printOperand(MI, 3);
+ O << ')';
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 4 bits for 15 unique commands.
+ switch ((Bits >> 18) & 15) {
+ default: // unreachable.
+ case 0:
+ // ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
+ printOperand(MI, 1);
+ break;
+ case 1:
+ // BCC
+ printPredicateOperand(MI, 0, "reg");
+ O << ", ";
+ printBranchOperand(MI, 2);
+ return;
+ break;
+ case 2:
+ // CRSET, V_SET0
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 3:
+ // LA, LHAU8
+ printSymbolLo(MI, 2);
+ O << '(';
+ break;
+ case 4:
+ // LBZ, LBZ8, LFD, LFS, LHA, LHA8, LHZ, LHZ8, LWZ, LWZ8, STB, STB8, STFD,...
+ printMemRegImm(MI, 1);
+ return;
+ break;
+ case 5:
+ // LBZU, LBZU8, LFDU, LFSU, LHAU, LHZU, LHZU8, LWZU, LWZU8
+ printMemRegImm(MI, 2);
+ return;
+ break;
+ case 6:
+ // LBZX, LBZX8, LDARX, LDX, LFDX, LFSX, LHAX, LHAX8, LHBRX, LHZX, LHZX8, ...
+ printMemRegReg(MI, 1);
+ return;
+ break;
+ case 7:
+ // LD, LWA, STD, STD_32
+ printMemRegImmShifted(MI, 1);
+ return;
+ break;
+ case 8:
+ // LDU
+ printMemRegImmShifted(MI, 2);
+ return;
+ break;
+ case 9:
+ // LDtoc
+ printTOCEntryLabel(MI, 1);
+ O << '(';
+ printOperand(MI, 2);
+ O << ')';
+ return;
+ break;
+ case 10:
+ // LI, LI8
+ printSymbolLo(MI, 1);
+ return;
+ break;
+ case 11:
+ // LIS, LIS8
+ printSymbolHi(MI, 1);
+ return;
+ break;
+ case 12:
+ // MFOCRF
+ printcrbitm(MI, 1);
+ return;
+ break;
+ case 13:
+ // RLDIMI, RLWIMI, VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
+ printOperand(MI, 2);
+ O << ", ";
+ break;
+ case 14:
+ // VSPLTISB, VSPLTISH, VSPLTISW
+ printS5ImmOperand(MI, 1);
+ return;
+ break;
+ }
+
+
+ // Fragment 3 encoded into 3 bits for 7 unique commands.
+ switch ((Bits >> 15) & 7) {
+ default: // unreachable.
+ case 0:
+ // ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
+ O << ", ";
+ break;
+ case 1:
+ // ADDME, ADDME8, ADDZE, ADDZE8, CNTLZD, CNTLZW, EXTSB, EXTSB8, EXTSH, EX...
+ return;
+ break;
+ case 2:
+ // LA
+ printOperand(MI, 1);
+ O << ')';
+ return;
+ break;
+ case 3:
+ // LHAU8
+ printOperand(MI, 3);
+ O << ')';
+ return;
+ break;
+ case 4:
+ // RLDIMI
+ printU6ImmOperand(MI, 3);
+ O << ", ";
+ printU6ImmOperand(MI, 4);
+ return;
+ break;
+ case 5:
+ // RLWIMI
+ printU5ImmOperand(MI, 3);
+ O << ", ";
+ printU5ImmOperand(MI, 4);
+ O << ", ";
+ printU5ImmOperand(MI, 5);
+ return;
+ break;
+ case 6:
+ // VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
+ printU5ImmOperand(MI, 1);
+ return;
+ break;
+ }
+
+
+ // Fragment 4 encoded into 3 bits for 6 unique commands.
+ switch ((Bits >> 12) & 7) {
+ default: // unreachable.
+ case 0:
+ // ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, AND, AND8, ANDC, ANDC8, CMPD, CM...
+ printOperand(MI, 2);
+ break;
+ case 1:
+ // ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, CMPDI, CMPWI, MULLI, SUBFIC, SUBFI...
+ printS16ImmOperand(MI, 2);
+ return;
+ break;
+ case 2:
+ // ADDIS, ADDIS8
+ printSymbolHi(MI, 2);
+ return;
+ break;
+ case 3:
+ // ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
+ printU16ImmOperand(MI, 2);
+ return;
+ break;
+ case 4:
+ // RLDICL, RLDICR, SRADI
+ printU6ImmOperand(MI, 2);
+ break;
+ case 5:
+ // RLWINM, RLWINMo, SRAWI
+ printU5ImmOperand(MI, 2);
+ break;
+ }
+
+ switch (MI->getOpcode()) {
+ case PPC::ADD4:
+ case PPC::ADD8:
+ case PPC::ADDC:
+ case PPC::ADDC8:
+ case PPC::ADDE:
+ case PPC::ADDE8:
+ case PPC::AND:
+ case PPC::AND8:
+ case PPC::ANDC:
+ case PPC::ANDC8:
+ case PPC::CMPD:
+ case PPC::CMPLD:
+ case PPC::CMPLW:
+ case PPC::CMPW:
+ case PPC::CREQV:
+ case PPC::CROR:
+ case PPC::DIVD:
+ case PPC::DIVDU:
+ case PPC::DIVW:
+ case PPC::DIVWU:
+ case PPC::EQV:
+ case PPC::EQV8:
+ case PPC::FADD:
+ case PPC::FADDS:
+ case PPC::FADDrtz:
+ case PPC::FCMPUD:
+ case PPC::FCMPUS:
+ case PPC::FDIV:
+ case PPC::FDIVS:
+ case PPC::FMUL:
+ case PPC::FMULS:
+ case PPC::FSUB:
+ case PPC::FSUBS:
+ case PPC::MULHD:
+ case PPC::MULHDU:
+ case PPC::MULHW:
+ case PPC::MULHWU:
+ case PPC::MULLD:
+ case PPC::MULLW:
+ case PPC::NAND:
+ case PPC::NAND8:
+ case PPC::NOR:
+ case PPC::NOR8:
+ case PPC::OR:
+ case PPC::OR4To8:
+ case PPC::OR8:
+ case PPC::OR8To4:
+ case PPC::ORC:
+ case PPC::ORC8:
+ case PPC::SLD:
+ case PPC::SLW:
+ case PPC::SRAD:
+ case PPC::SRADI:
+ case PPC::SRAW:
+ case PPC::SRAWI:
+ case PPC::SRD:
+ case PPC::SRW:
+ case PPC::STWUX:
+ case PPC::SUBF:
+ case PPC::SUBF8:
+ case PPC::SUBFC:
+ case PPC::SUBFC8:
+ case PPC::SUBFE:
+ case PPC::SUBFE8:
+ case PPC::VADDCUW:
+ case PPC::VADDFP:
+ case PPC::VADDSBS:
+ case PPC::VADDSHS:
+ case PPC::VADDSWS:
+ case PPC::VADDUBM:
+ case PPC::VADDUBS:
+ case PPC::VADDUHM:
+ case PPC::VADDUHS:
+ case PPC::VADDUWM:
+ case PPC::VADDUWS:
+ case PPC::VAND:
+ case PPC::VANDC:
+ case PPC::VAVGSB:
+ case PPC::VAVGSH:
+ case PPC::VAVGSW:
+ case PPC::VAVGUB:
+ case PPC::VAVGUH:
+ case PPC::VAVGUW:
+ case PPC::VCMPBFP:
+ case PPC::VCMPBFPo:
+ case PPC::VCMPEQFP:
+ case PPC::VCMPEQFPo:
+ case PPC::VCMPEQUB:
+ case PPC::VCMPEQUBo:
+ case PPC::VCMPEQUH:
+ case PPC::VCMPEQUHo:
+ case PPC::VCMPEQUW:
+ case PPC::VCMPEQUWo:
+ case PPC::VCMPGEFP:
+ case PPC::VCMPGEFPo:
+ case PPC::VCMPGTFP:
+ case PPC::VCMPGTFPo:
+ case PPC::VCMPGTSB:
+ case PPC::VCMPGTSBo:
+ case PPC::VCMPGTSH:
+ case PPC::VCMPGTSHo:
+ case PPC::VCMPGTSW:
+ case PPC::VCMPGTSWo:
+ case PPC::VCMPGTUB:
+ case PPC::VCMPGTUBo:
+ case PPC::VCMPGTUH:
+ case PPC::VCMPGTUHo:
+ case PPC::VCMPGTUW:
+ case PPC::VCMPGTUWo:
+ case PPC::VMAXFP:
+ case PPC::VMAXSB:
+ case PPC::VMAXSH:
+ case PPC::VMAXSW:
+ case PPC::VMAXUB:
+ case PPC::VMAXUH:
+ case PPC::VMAXUW:
+ case PPC::VMINFP:
+ case PPC::VMINSB:
+ case PPC::VMINSH:
+ case PPC::VMINSW:
+ case PPC::VMINUB:
+ case PPC::VMINUH:
+ case PPC::VMINUW:
+ case PPC::VMRGHB:
+ case PPC::VMRGHH:
+ case PPC::VMRGHW:
+ case PPC::VMRGLB:
+ case PPC::VMRGLH:
+ case PPC::VMRGLW:
+ case PPC::VMULESB:
+ case PPC::VMULESH:
+ case PPC::VMULEUB:
+ case PPC::VMULEUH:
+ case PPC::VMULOSB:
+ case PPC::VMULOSH:
+ case PPC::VMULOUB:
+ case PPC::VMULOUH:
+ case PPC::VNOR:
+ case PPC::VOR:
+ case PPC::VPKPX:
+ case PPC::VPKSHSS:
+ case PPC::VPKSHUS:
+ case PPC::VPKSWSS:
+ case PPC::VPKSWUS:
+ case PPC::VPKUHUM:
+ case PPC::VPKUHUS:
+ case PPC::VPKUWUM:
+ case PPC::VPKUWUS:
+ case PPC::VRLB:
+ case PPC::VRLH:
+ case PPC::VRLW:
+ case PPC::VSL:
+ case PPC::VSLB:
+ case PPC::VSLH:
+ case PPC::VSLO:
+ case PPC::VSLW:
+ case PPC::VSR:
+ case PPC::VSRAB:
+ case PPC::VSRAH:
+ case PPC::VSRAW:
+ case PPC::VSRB:
+ case PPC::VSRH:
+ case PPC::VSRO:
+ case PPC::VSRW:
+ case PPC::VSUBCUW:
+ case PPC::VSUBFP:
+ case PPC::VSUBSBS:
+ case PPC::VSUBSHS:
+ case PPC::VSUBSWS:
+ case PPC::VSUBUBM:
+ case PPC::VSUBUBS:
+ case PPC::VSUBUHM:
+ case PPC::VSUBUHS:
+ case PPC::VSUBUWM:
+ case PPC::VSUBUWS:
+ case PPC::VSUM2SWS:
+ case PPC::VSUM4SBS:
+ case PPC::VSUM4SHS:
+ case PPC::VSUM4UBS:
+ case PPC::VSUMSWS:
+ case PPC::VXOR:
+ case PPC::XOR:
+ case PPC::XOR8:
+ return;
+ break;
+ case PPC::FMADD:
+ case PPC::FMADDS:
+ case PPC::FMSUB:
+ case PPC::FMSUBS:
+ case PPC::FNMADD:
+ case PPC::FNMADDS:
+ case PPC::FNMSUB:
+ case PPC::FNMSUBS:
+ case PPC::FSELD:
+ case PPC::FSELS:
+ case PPC::RLDCL:
+ case PPC::RLDICL:
+ case PPC::RLDICR:
+ case PPC::VMADDFP:
+ case PPC::VMHADDSHS:
+ case PPC::VMHRADDSHS:
+ case PPC::VMLADDUHM:
+ case PPC::VMSUMMBM:
+ case PPC::VMSUMSHM:
+ case PPC::VMSUMSHS:
+ case PPC::VMSUMUBM:
+ case PPC::VMSUMUHM:
+ case PPC::VMSUMUHS:
+ case PPC::VNMSUBFP:
+ case PPC::VPERM:
+ case PPC::VSEL:
+ case PPC::VSLDOI:
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case PPC::FMADD:
+ case PPC::FMADDS:
+ case PPC::FMSUB:
+ case PPC::FMSUBS:
+ case PPC::FNMADD:
+ case PPC::FNMADDS:
+ case PPC::FNMSUB:
+ case PPC::FNMSUBS:
+ case PPC::FSELD:
+ case PPC::FSELS:
+ case PPC::VMADDFP:
+ case PPC::VMHADDSHS:
+ case PPC::VMHRADDSHS:
+ case PPC::VMLADDUHM:
+ case PPC::VMSUMMBM:
+ case PPC::VMSUMSHM:
+ case PPC::VMSUMSHS:
+ case PPC::VMSUMUBM:
+ case PPC::VMSUMUHM:
+ case PPC::VMSUMUHS:
+ case PPC::VNMSUBFP:
+ case PPC::VPERM:
+ case PPC::VSEL: printOperand(MI, 3); break;
+ case PPC::RLDCL:
+ case PPC::RLDICL:
+ case PPC::RLDICR: printU6ImmOperand(MI, 3); break;
+ case PPC::VSLDOI: printU5ImmOperand(MI, 3); break;
+ }
+ return;
+ break;
+ case PPC::RLWINM:
+ case PPC::RLWINMo:
+ case PPC::RLWNM:
+ O << ", ";
+ printU5ImmOperand(MI, 3);
+ O << ", ";
+ printU5ImmOperand(MI, 4);
+ return;
+ break;
+ }
+ return;
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
+ assert(RegNo && RegNo < 176 && "Invalid register number!");
+
+ static const unsigned RegAsmOffset[] = {
+ 0, 3, 7, 9, 11, 13, 15, 19, 21, 23, 25, 27, 31, 34,
+ 36, 38, 41, 45, 48, 51, 54, 57, 61, 64, 67, 70, 73, 77,
+ 80, 83, 86, 89, 93, 96, 99, 102, 105, 109, 112, 115, 118, 121,
+ 121, 125, 128, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171,
+ 174, 178, 182, 186, 190, 194, 198, 202, 206, 210, 214, 217, 221, 225,
+ 228, 231, 234, 237, 240, 243, 243, 246, 249, 252, 256, 260, 264, 268,
+ 272, 276, 280, 284, 288, 292, 295, 299, 303, 307, 311, 315, 319, 323,
+ 327, 331, 335, 338, 342, 346, 349, 352, 355, 358, 361, 364, 382, 385,
+ 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 431, 435, 439,
+ 443, 447, 451, 455, 459, 463, 467, 471, 474, 478, 482, 485, 488, 491,
+ 494, 497, 500, 246, 249, 252, 256, 260, 264, 268, 272, 276, 280, 284,
+ 288, 292, 295, 299, 303, 307, 311, 315, 319, 323, 327, 331, 335, 338,
+ 342, 346, 349, 352, 355, 358, 361, 0
+ };
+
+ const char *AsmStrs =
+ "ca\000cr0\0002\0001\0000\0003\000cr1\0006\0005\0004\0007\000cr2\00010\000"
+ "9\0008\00011\000cr3\00014\00013\00012\00015\000cr4\00018\00017\00016\000"
+ "19\000cr5\00022\00021\00020\00023\000cr6\00026\00025\00024\00027\000cr7"
+ "\00030\00029\00028\00031\000ctr\000f0\000f1\000f10\000f11\000f12\000f13"
+ "\000f14\000f15\000f16\000f17\000f18\000f19\000f2\000f20\000f21\000f22\000"
+ "f23\000f24\000f25\000f26\000f27\000f28\000f29\000f3\000f30\000f31\000f4"
+ "\000f5\000f6\000f7\000f8\000f9\000lr\000r0\000r1\000r10\000r11\000r12\000"
+ "r13\000r14\000r15\000r16\000r17\000r18\000r19\000r2\000r20\000r21\000r2"
+ "2\000r23\000r24\000r25\000r26\000r27\000r28\000r29\000r3\000r30\000r31\000"
+ "r4\000r5\000r6\000r7\000r8\000r9\000**ROUNDING MODE**\000v0\000v1\000v1"
+ "0\000v11\000v12\000v13\000v14\000v15\000v16\000v17\000v18\000v19\000v2\000"
+ "v20\000v21\000v22\000v23\000v24\000v25\000v26\000v27\000v28\000v29\000v"
+ "3\000v30\000v31\000v4\000v5\000v6\000v7\000v8\000v9\000VRsave\000";
+ return AsmStrs+RegAsmOffset[RegNo-1];
+}
diff --git a/libclamav/c++/PPCGenCallingConv.inc b/libclamav/c++/PPCGenCallingConv.inc
new file mode 100644
index 0000000..da7d05e
--- /dev/null
+++ b/libclamav/c++/PPCGenCallingConv.inc
@@ -0,0 +1,204 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Calling Convention Implementation Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+static bool CC_PPC_SVR4(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_PPC_SVR4_ByVal(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_PPC_SVR4_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_PPC_SVR4_VarArg(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_PPC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+
+
+static bool CC_PPC_SVR4(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v4f32) {
+ static const unsigned RegList1[] = {
+ PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 12)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!CC_PPC_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_PPC_SVR4_ByVal(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
+ return false;
+ }
+
+ if (CC_PPC_SVR4_Custom_Dummy(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_PPC_SVR4_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i32) {
+ if (ArgFlags.isSplit()) {
+ if (CC_PPC_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ if (!ArgFlags.isInReg()) {
+ static const unsigned RegList1[] = {
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (ArgFlags.isSplit()) {
+ if (CC_PPC_SVR4_Custom_AlignFPArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ static const unsigned RegList2[] = {
+ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ if (ArgFlags.isSplit()) {
+ unsigned Offset3 = State.AllocateStack(4, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ unsigned Offset4 = State.AllocateStack(4, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ unsigned Offset5 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v4f32) {
+ unsigned Offset6 = State.AllocateStack(16, 16);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_PPC_SVR4_VarArg(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (!CC_PPC_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_PPC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList2[] = {
+ PPC::X3, PPC::X4, PPC::X5, PPC::X6
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ if (unsigned Reg = State.AllocateReg(PPC::F1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const unsigned RegList3[] = {
+ PPC::F1, PPC::F2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v4f32) {
+ if (unsigned Reg = State.AllocateReg(PPC::V2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
diff --git a/libclamav/c++/PPCGenCodeEmitter.inc b/libclamav/c++/PPCGenCodeEmitter.inc
new file mode 100644
index 0000000..0c3fab2
--- /dev/null
+++ b/libclamav/c++/PPCGenCodeEmitter.inc
@@ -0,0 +1,1053 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Machine Code Emitter
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
+ static const unsigned InstBits[] = {
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 2080375316U, // ADD4
+ 2080375316U, // ADD8
+ 2080374804U, // ADDC
+ 2080374804U, // ADDC8
+ 2080375060U, // ADDE
+ 2080375060U, // ADDE8
+ 939524096U, // ADDI
+ 939524096U, // ADDI8
+ 805306368U, // ADDIC
+ 805306368U, // ADDIC8
+ 872415232U, // ADDICo
+ 1006632960U, // ADDIS
+ 1006632960U, // ADDIS8
+ 2080375252U, // ADDME
+ 2080375252U, // ADDME8
+ 2080375188U, // ADDZE
+ 2080375188U, // ADDZE8
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 2080374840U, // AND
+ 2080374840U, // AND8
+ 2080374904U, // ANDC
+ 2080374904U, // ANDC8
+ 1946157056U, // ANDISo
+ 1946157056U, // ANDISo8
+ 1879048192U, // ANDIo
+ 1879048192U, // ANDIo8
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I8
+ 1207959552U, // B
+ 1073741824U, // BCC
+ 1317012512U, // BCTR
+ 1317012513U, // BCTRL8_Darwin
+ 1317012513U, // BCTRL8_ELF
+ 1317012513U, // BCTRL_Darwin
+ 1317012513U, // BCTRL_SVR4
+ 1207959553U, // BL8_Darwin
+ 1207959553U, // BL8_ELF
+ 1207959555U, // BLA8_Darwin
+ 1207959555U, // BLA8_ELF
+ 1207959555U, // BLA_Darwin
+ 1207959555U, // BLA_SVR4
+ 1275068448U, // BLR
+ 1207959553U, // BL_Darwin
+ 1207959553U, // BL_SVR4
+ 2082471936U, // CMPD
+ 740294656U, // CMPDI
+ 2082472000U, // CMPLD
+ 673185792U, // CMPLDI
+ 2080374848U, // CMPLW
+ 671088640U, // CMPLWI
+ 2080374784U, // CMPW
+ 738197504U, // CMPWI
+ 2080374900U, // CNTLZD
+ 2080374836U, // CNTLZW
+ 1275068994U, // CREQV
+ 1275069314U, // CROR
+ 1275068994U, // CRSET
+ 2080376300U, // DCBA
+ 2080374956U, // DCBF
+ 2080375724U, // DCBI
+ 2080374892U, // DCBST
+ 2080375340U, // DCBT
+ 2080375276U, // DCBTST
+ 2080376812U, // DCBZ
+ 2082473964U, // DCBZL
+ 2080375762U, // DIVD
+ 2080375698U, // DIVDU
+ 2080375766U, // DIVW
+ 2080375702U, // DIVWU
+ 2080376428U, // DSS
+ 2080376428U, // DSSALL
+ 2080375468U, // DST
+ 2080375468U, // DST64
+ 2080375532U, // DSTST
+ 2080375532U, // DSTST64
+ 2080375532U, // DSTSTT
+ 2080375532U, // DSTSTT64
+ 2080375468U, // DSTT
+ 2080375468U, // DSTT64
+ 0U, // DYNALLOC
+ 0U, // DYNALLOC8
+ 2080375352U, // EQV
+ 2080375352U, // EQV8
+ 2080376692U, // EXTSB
+ 2080376692U, // EXTSB8
+ 2080376628U, // EXTSH
+ 2080376628U, // EXTSH8
+ 2080376756U, // EXTSW
+ 2080376756U, // EXTSW_32
+ 2080376756U, // EXTSW_32_64
+ 4227858960U, // FABSD
+ 4227858960U, // FABSS
+ 4227858474U, // FADD
+ 3959423018U, // FADDS
+ 4227858474U, // FADDrtz
+ 4227860124U, // FCFID
+ 4227858432U, // FCMPUD
+ 4227858432U, // FCMPUS
+ 4227860062U, // FCTIDZ
+ 4227858462U, // FCTIWZ
+ 4227858468U, // FDIV
+ 3959423012U, // FDIVS
+ 4227858490U, // FMADD
+ 3959423034U, // FMADDS
+ 4227858576U, // FMRD
+ 4227858576U, // FMRS
+ 4227858576U, // FMRSD
+ 4227858488U, // FMSUB
+ 3959423032U, // FMSUBS
+ 4227858482U, // FMUL
+ 3959423026U, // FMULS
+ 4227858704U, // FNABSD
+ 4227858704U, // FNABSS
+ 4227858512U, // FNEGD
+ 4227858512U, // FNEGS
+ 4227858494U, // FNMADD
+ 3959423038U, // FNMADDS
+ 4227858492U, // FNMSUB
+ 3959423036U, // FNMSUBS
+ 4227858456U, // FRSP
+ 4227858478U, // FSELD
+ 4227858478U, // FSELS
+ 4227858476U, // FSQRT
+ 3959423020U, // FSQRTS
+ 4227858472U, // FSUB
+ 3959423016U, // FSUBS
+ 939524096U, // LA
+ 2281701376U, // LBZ
+ 2281701376U, // LBZ8
+ 2348810240U, // LBZU
+ 2348810240U, // LBZU8
+ 2080374958U, // LBZX
+ 2080374958U, // LBZX8
+ 3892314112U, // LD
+ 2080374952U, // LDARX
+ 3892314113U, // LDU
+ 2080374826U, // LDX
+ 3892314112U, // LDtoc
+ 3355443200U, // LFD
+ 3422552064U, // LFDU
+ 2080375982U, // LFDX
+ 3221225472U, // LFS
+ 3288334336U, // LFSU
+ 2080375854U, // LFSX
+ 2818572288U, // LHA
+ 2818572288U, // LHA8
+ 2885681152U, // LHAU
+ 2885681152U, // LHAU8
+ 2080375470U, // LHAX
+ 2080375470U, // LHAX8
+ 2080376364U, // LHBRX
+ 2684354560U, // LHZ
+ 2684354560U, // LHZ8
+ 2751463424U, // LHZU
+ 2751463424U, // LHZU8
+ 2080375342U, // LHZX
+ 2080375342U, // LHZX8
+ 939524096U, // LI
+ 939524096U, // LI8
+ 1006632960U, // LIS
+ 1006632960U, // LIS8
+ 2080374798U, // LVEBX
+ 2080374862U, // LVEHX
+ 2080374926U, // LVEWX
+ 2080374796U, // LVSL
+ 2080374860U, // LVSR
+ 2080374990U, // LVX
+ 2080375502U, // LVXL
+ 3892314114U, // LWA
+ 2080374824U, // LWARX
+ 2080375466U, // LWAX
+ 2080375852U, // LWBRX
+ 2147483648U, // LWZ
+ 2147483648U, // LWZ8
+ 2214592512U, // LWZU
+ 2214592512U, // LWZU8
+ 2080374830U, // LWZX
+ 2080374830U, // LWZX8
+ 1275068416U, // MCRF
+ 2080374822U, // MFCR
+ 2080965286U, // MFCTR
+ 2080965286U, // MFCTR8
+ 4227859598U, // MFFS
+ 2080899750U, // MFLR
+ 2080899750U, // MFLR8
+ 2081423398U, // MFOCRF
+ 2080391846U, // MFVRSAVE
+ 268436996U, // MFVSCR
+ 2080375072U, // MTCRF
+ 2080965542U, // MTCTR
+ 2080965542U, // MTCTR8
+ 4227858572U, // MTFSB0
+ 4227858508U, // MTFSB1
+ 4227859854U, // MTFSF
+ 2080900006U, // MTLR
+ 2080900006U, // MTLR8
+ 2080392102U, // MTVRSAVE
+ 268437060U, // MTVSCR
+ 2080374930U, // MULHD
+ 2080374802U, // MULHDU
+ 2080374934U, // MULHW
+ 2080374806U, // MULHWU
+ 2080375250U, // MULLD
+ 469762048U, // MULLI
+ 2080375254U, // MULLW
+ 0U, // MovePCtoLR
+ 0U, // MovePCtoLR8
+ 2080375736U, // NAND
+ 2080375736U, // NAND8
+ 2080374992U, // NEG
+ 2080374992U, // NEG8
+ 1610612736U, // NOP
+ 2080375032U, // NOR
+ 2080375032U, // NOR8
+ 2080375672U, // OR
+ 2080375672U, // OR4To8
+ 2080375672U, // OR8
+ 2080375672U, // OR8To4
+ 2080375608U, // ORC
+ 2080375608U, // ORC8
+ 1610612736U, // ORI
+ 1610612736U, // ORI8
+ 1677721600U, // ORIS
+ 1677721600U, // ORIS8
+ 2013265920U, // RLDCL
+ 2013265920U, // RLDICL
+ 2013265924U, // RLDICR
+ 2013265932U, // RLDIMI
+ 1342177280U, // RLWIMI
+ 1409286144U, // RLWINM
+ 1409286145U, // RLWINMo
+ 1543503872U, // RLWNM
+ 0U, // SELECT_CC_F4
+ 0U, // SELECT_CC_F8
+ 0U, // SELECT_CC_I4
+ 0U, // SELECT_CC_I8
+ 0U, // SELECT_CC_VRRC
+ 2080374838U, // SLD
+ 2080374832U, // SLW
+ 0U, // SPILL_CR
+ 2080376372U, // SRAD
+ 2080376436U, // SRADI
+ 2080376368U, // SRAW
+ 2080376432U, // SRAWI
+ 2080375862U, // SRD
+ 2080375856U, // SRW
+ 2550136832U, // STB
+ 2550136832U, // STB8
+ 2617245696U, // STBU
+ 2550136832U, // STBU8
+ 2080375214U, // STBX
+ 2080375214U, // STBX8
+ 4160749568U, // STD
+ 2080375213U, // STDCX
+ 4160749569U, // STDU
+ 2080375146U, // STDUX
+ 2080375082U, // STDX
+ 2080375082U, // STDX_32
+ 4160749568U, // STD_32
+ 3623878656U, // STFD
+ 2483027968U, // STFDU
+ 2080376238U, // STFDX
+ 2080376750U, // STFIWX
+ 3489660928U, // STFS
+ 2483027968U, // STFSU
+ 2080376110U, // STFSX
+ 2952790016U, // STH
+ 2952790016U, // STH8
+ 2080376620U, // STHBRX
+ 3019898880U, // STHU
+ 3019898880U, // STHU8
+ 2080375598U, // STHX
+ 2080375598U, // STHX8
+ 2080375054U, // STVEBX
+ 2080375118U, // STVEHX
+ 2080375182U, // STVEWX
+ 2080375246U, // STVX
+ 2080375758U, // STVXL
+ 2415919104U, // STW
+ 2415919104U, // STW8
+ 2080376108U, // STWBRX
+ 2080375085U, // STWCX
+ 2483027968U, // STWU
+ 2483027968U, // STWU8
+ 2080375150U, // STWUX
+ 2080375086U, // STWX
+ 2080375086U, // STWX8
+ 2080374864U, // SUBF
+ 2080374864U, // SUBF8
+ 2080374800U, // SUBFC
+ 2080374800U, // SUBFC8
+ 2080375056U, // SUBFE
+ 2080375056U, // SUBFE8
+ 536870912U, // SUBFIC
+ 536870912U, // SUBFIC8
+ 2080375248U, // SUBFME
+ 2080375248U, // SUBFME8
+ 2080375184U, // SUBFZE
+ 2080375184U, // SUBFZE8
+ 2080375980U, // SYNC
+ 1207959552U, // TAILB
+ 1207959552U, // TAILB8
+ 1207959552U, // TAILBA
+ 1207959552U, // TAILBA8
+ 1317012512U, // TAILBCTR
+ 1317012512U, // TAILBCTR8
+ 0U, // TCRETURNai
+ 0U, // TCRETURNai8
+ 0U, // TCRETURNdi
+ 0U, // TCRETURNdi8
+ 0U, // TCRETURNri
+ 0U, // TCRETURNri8
+ 2145386504U, // TRAP
+ 0U, // UPDATE_VRSAVE
+ 268435840U, // VADDCUW
+ 268435466U, // VADDFP
+ 268436224U, // VADDSBS
+ 268436288U, // VADDSHS
+ 268436352U, // VADDSWS
+ 268435456U, // VADDUBM
+ 268435968U, // VADDUBS
+ 268435520U, // VADDUHM
+ 268436032U, // VADDUHS
+ 268435584U, // VADDUWM
+ 268436096U, // VADDUWS
+ 268436484U, // VAND
+ 268436548U, // VANDC
+ 268436738U, // VAVGSB
+ 268436802U, // VAVGSH
+ 268436866U, // VAVGSW
+ 268436482U, // VAVGUB
+ 268436546U, // VAVGUH
+ 268436610U, // VAVGUW
+ 268436298U, // VCFSX
+ 268436234U, // VCFUX
+ 268436422U, // VCMPBFP
+ 268437446U, // VCMPBFPo
+ 268435654U, // VCMPEQFP
+ 268436678U, // VCMPEQFPo
+ 268435462U, // VCMPEQUB
+ 268436486U, // VCMPEQUBo
+ 268435526U, // VCMPEQUH
+ 268436550U, // VCMPEQUHo
+ 268435590U, // VCMPEQUW
+ 268436614U, // VCMPEQUWo
+ 268435910U, // VCMPGEFP
+ 268436934U, // VCMPGEFPo
+ 268436166U, // VCMPGTFP
+ 268437190U, // VCMPGTFPo
+ 268436230U, // VCMPGTSB
+ 268437254U, // VCMPGTSBo
+ 268436294U, // VCMPGTSH
+ 268437318U, // VCMPGTSHo
+ 268436358U, // VCMPGTSW
+ 268437382U, // VCMPGTSWo
+ 268435974U, // VCMPGTUB
+ 268436998U, // VCMPGTUBo
+ 268436038U, // VCMPGTUH
+ 268437062U, // VCMPGTUHo
+ 268436102U, // VCMPGTUW
+ 268437126U, // VCMPGTUWo
+ 268436426U, // VCTSXS
+ 268436362U, // VCTUXS
+ 268435850U, // VEXPTEFP
+ 268435914U, // VLOGEFP
+ 268435502U, // VMADDFP
+ 268436490U, // VMAXFP
+ 268435714U, // VMAXSB
+ 268435778U, // VMAXSH
+ 268435842U, // VMAXSW
+ 268435458U, // VMAXUB
+ 268435522U, // VMAXUH
+ 268435586U, // VMAXUW
+ 268435488U, // VMHADDSHS
+ 268435489U, // VMHRADDSHS
+ 268436554U, // VMINFP
+ 268436226U, // VMINSB
+ 268436290U, // VMINSH
+ 268436354U, // VMINSW
+ 268435970U, // VMINUB
+ 268436034U, // VMINUH
+ 268436098U, // VMINUW
+ 268435490U, // VMLADDUHM
+ 268435468U, // VMRGHB
+ 268435532U, // VMRGHH
+ 268435596U, // VMRGHW
+ 268435724U, // VMRGLB
+ 268435788U, // VMRGLH
+ 268435852U, // VMRGLW
+ 268435493U, // VMSUMMBM
+ 268435496U, // VMSUMSHM
+ 268435497U, // VMSUMSHS
+ 268435492U, // VMSUMUBM
+ 268435494U, // VMSUMUHM
+ 268435495U, // VMSUMUHS
+ 268436232U, // VMULESB
+ 268436296U, // VMULESH
+ 268435976U, // VMULEUB
+ 268436040U, // VMULEUH
+ 268435720U, // VMULOSB
+ 268435784U, // VMULOSH
+ 268435464U, // VMULOUB
+ 268435528U, // VMULOUH
+ 268435503U, // VNMSUBFP
+ 268436740U, // VNOR
+ 268436612U, // VOR
+ 268435499U, // VPERM
+ 268436238U, // VPKPX
+ 268435854U, // VPKSHSS
+ 268435726U, // VPKSHUS
+ 268435918U, // VPKSWSS
+ 268435790U, // VPKSWUS
+ 268435470U, // VPKUHUM
+ 268435598U, // VPKUHUS
+ 268435534U, // VPKUWUM
+ 268435662U, // VPKUWUS
+ 268435722U, // VREFP
+ 268436170U, // VRFIM
+ 268435978U, // VRFIN
+ 268436106U, // VRFIP
+ 268436042U, // VRFIZ
+ 268435460U, // VRLB
+ 268435524U, // VRLH
+ 268435588U, // VRLW
+ 268435786U, // VRSQRTEFP
+ 268435498U, // VSEL
+ 268435908U, // VSL
+ 268435716U, // VSLB
+ 268435500U, // VSLDOI
+ 268435780U, // VSLH
+ 268436492U, // VSLO
+ 268435844U, // VSLW
+ 268435980U, // VSPLTB
+ 268436044U, // VSPLTH
+ 268436236U, // VSPLTISB
+ 268436300U, // VSPLTISH
+ 268436364U, // VSPLTISW
+ 268436108U, // VSPLTW
+ 268436164U, // VSR
+ 268436228U, // VSRAB
+ 268436292U, // VSRAH
+ 268436356U, // VSRAW
+ 268435972U, // VSRB
+ 268436036U, // VSRH
+ 268436556U, // VSRO
+ 268436100U, // VSRW
+ 268435530U, // VSUBCUW
+ 268435530U, // VSUBFP
+ 268437248U, // VSUBSBS
+ 268437312U, // VSUBSHS
+ 268437376U, // VSUBSWS
+ 268436480U, // VSUBUBM
+ 268436992U, // VSUBUBS
+ 268436544U, // VSUBUHM
+ 268437056U, // VSUBUHS
+ 268436608U, // VSUBUWM
+ 268437120U, // VSUBUWS
+ 268437128U, // VSUM2SWS
+ 268437128U, // VSUM4SBS
+ 268437064U, // VSUM4SHS
+ 268437000U, // VSUM4UBS
+ 268437384U, // VSUMSWS
+ 268436302U, // VUPKHPX
+ 268435982U, // VUPKHSB
+ 268436046U, // VUPKHSH
+ 268436430U, // VUPKLPX
+ 268436110U, // VUPKLSB
+ 268436174U, // VUPKLSH
+ 268436676U, // VXOR
+ 268436676U, // V_SET0
+ 2080375416U, // XOR
+ 2080375416U, // XOR8
+ 1744830464U, // XORI
+ 1744830464U, // XORI8
+ 1811939328U, // XORIS
+ 1811939328U, // XORIS8
+ 0U
+ };
+ const unsigned opcode = MI.getOpcode();
+ unsigned Value = InstBits[opcode];
+ unsigned op = 0;
+ op = op; // suppress warning
+ switch (opcode) {
+ case PPC::ADD4:
+ case PPC::ADD8:
+ case PPC::ADDC:
+ case PPC::ADDC8:
+ case PPC::ADDE:
+ case PPC::ADDE8:
+ case PPC::ADDI:
+ case PPC::ADDI8:
+ case PPC::ADDIC:
+ case PPC::ADDIC8:
+ case PPC::ADDICo:
+ case PPC::ADDIS:
+ case PPC::ADDIS8:
+ case PPC::ADDME:
+ case PPC::ADDME8:
+ case PPC::ADDZE:
+ case PPC::ADDZE8:
+ case PPC::ADJCALLSTACKDOWN:
+ case PPC::ADJCALLSTACKUP:
+ case PPC::AND:
+ case PPC::AND8:
+ case PPC::ANDC:
+ case PPC::ANDC8:
+ case PPC::ANDISo:
+ case PPC::ANDISo8:
+ case PPC::ANDIo:
+ case PPC::ANDIo8:
+ case PPC::ATOMIC_CMP_SWAP_I16:
+ case PPC::ATOMIC_CMP_SWAP_I32:
+ case PPC::ATOMIC_CMP_SWAP_I64:
+ case PPC::ATOMIC_CMP_SWAP_I8:
+ case PPC::ATOMIC_LOAD_ADD_I16:
+ case PPC::ATOMIC_LOAD_ADD_I32:
+ case PPC::ATOMIC_LOAD_ADD_I64:
+ case PPC::ATOMIC_LOAD_ADD_I8:
+ case PPC::ATOMIC_LOAD_AND_I16:
+ case PPC::ATOMIC_LOAD_AND_I32:
+ case PPC::ATOMIC_LOAD_AND_I64:
+ case PPC::ATOMIC_LOAD_AND_I8:
+ case PPC::ATOMIC_LOAD_NAND_I16:
+ case PPC::ATOMIC_LOAD_NAND_I32:
+ case PPC::ATOMIC_LOAD_NAND_I64:
+ case PPC::ATOMIC_LOAD_NAND_I8:
+ case PPC::ATOMIC_LOAD_OR_I16:
+ case PPC::ATOMIC_LOAD_OR_I32:
+ case PPC::ATOMIC_LOAD_OR_I64:
+ case PPC::ATOMIC_LOAD_OR_I8:
+ case PPC::ATOMIC_LOAD_SUB_I16:
+ case PPC::ATOMIC_LOAD_SUB_I32:
+ case PPC::ATOMIC_LOAD_SUB_I64:
+ case PPC::ATOMIC_LOAD_SUB_I8:
+ case PPC::ATOMIC_LOAD_XOR_I16:
+ case PPC::ATOMIC_LOAD_XOR_I32:
+ case PPC::ATOMIC_LOAD_XOR_I64:
+ case PPC::ATOMIC_LOAD_XOR_I8:
+ case PPC::ATOMIC_SWAP_I16:
+ case PPC::ATOMIC_SWAP_I32:
+ case PPC::ATOMIC_SWAP_I64:
+ case PPC::ATOMIC_SWAP_I8:
+ case PPC::B:
+ case PPC::BCC:
+ case PPC::BCTR:
+ case PPC::BCTRL8_Darwin:
+ case PPC::BCTRL8_ELF:
+ case PPC::BCTRL_Darwin:
+ case PPC::BCTRL_SVR4:
+ case PPC::BL8_Darwin:
+ case PPC::BL8_ELF:
+ case PPC::BLA8_Darwin:
+ case PPC::BLA8_ELF:
+ case PPC::BLA_Darwin:
+ case PPC::BLA_SVR4:
+ case PPC::BLR:
+ case PPC::BL_Darwin:
+ case PPC::BL_SVR4:
+ case PPC::CMPD:
+ case PPC::CMPDI:
+ case PPC::CMPLD:
+ case PPC::CMPLDI:
+ case PPC::CMPLW:
+ case PPC::CMPLWI:
+ case PPC::CMPW:
+ case PPC::CMPWI:
+ case PPC::CNTLZD:
+ case PPC::CNTLZW:
+ case PPC::CREQV:
+ case PPC::CROR:
+ case PPC::CRSET:
+ case PPC::DCBA:
+ case PPC::DCBF:
+ case PPC::DCBI:
+ case PPC::DCBST:
+ case PPC::DCBT:
+ case PPC::DCBTST:
+ case PPC::DCBZ:
+ case PPC::DCBZL:
+ case PPC::DIVD:
+ case PPC::DIVDU:
+ case PPC::DIVW:
+ case PPC::DIVWU:
+ case PPC::DSS:
+ case PPC::DSSALL:
+ case PPC::DST:
+ case PPC::DST64:
+ case PPC::DSTST:
+ case PPC::DSTST64:
+ case PPC::DSTSTT:
+ case PPC::DSTSTT64:
+ case PPC::DSTT:
+ case PPC::DSTT64:
+ case PPC::DYNALLOC:
+ case PPC::DYNALLOC8:
+ case PPC::EQV:
+ case PPC::EQV8:
+ case PPC::EXTSB:
+ case PPC::EXTSB8:
+ case PPC::EXTSH:
+ case PPC::EXTSH8:
+ case PPC::EXTSW:
+ case PPC::EXTSW_32:
+ case PPC::EXTSW_32_64:
+ case PPC::FABSD:
+ case PPC::FABSS:
+ case PPC::FADD:
+ case PPC::FADDS:
+ case PPC::FADDrtz:
+ case PPC::FCFID:
+ case PPC::FCMPUD:
+ case PPC::FCMPUS:
+ case PPC::FCTIDZ:
+ case PPC::FCTIWZ:
+ case PPC::FDIV:
+ case PPC::FDIVS:
+ case PPC::FMADD:
+ case PPC::FMADDS:
+ case PPC::FMRD:
+ case PPC::FMRS:
+ case PPC::FMRSD:
+ case PPC::FMSUB:
+ case PPC::FMSUBS:
+ case PPC::FMUL:
+ case PPC::FMULS:
+ case PPC::FNABSD:
+ case PPC::FNABSS:
+ case PPC::FNEGD:
+ case PPC::FNEGS:
+ case PPC::FNMADD:
+ case PPC::FNMADDS:
+ case PPC::FNMSUB:
+ case PPC::FNMSUBS:
+ case PPC::FRSP:
+ case PPC::FSELD:
+ case PPC::FSELS:
+ case PPC::FSQRT:
+ case PPC::FSQRTS:
+ case PPC::FSUB:
+ case PPC::FSUBS:
+ case PPC::LA:
+ case PPC::LBZ:
+ case PPC::LBZ8:
+ case PPC::LBZU:
+ case PPC::LBZU8:
+ case PPC::LBZX:
+ case PPC::LBZX8:
+ case PPC::LD:
+ case PPC::LDARX:
+ case PPC::LDU:
+ case PPC::LDX:
+ case PPC::LDtoc:
+ case PPC::LFD:
+ case PPC::LFDU:
+ case PPC::LFDX:
+ case PPC::LFS:
+ case PPC::LFSU:
+ case PPC::LFSX:
+ case PPC::LHA:
+ case PPC::LHA8:
+ case PPC::LHAU:
+ case PPC::LHAU8:
+ case PPC::LHAX:
+ case PPC::LHAX8:
+ case PPC::LHBRX:
+ case PPC::LHZ:
+ case PPC::LHZ8:
+ case PPC::LHZU:
+ case PPC::LHZU8:
+ case PPC::LHZX:
+ case PPC::LHZX8:
+ case PPC::LI:
+ case PPC::LI8:
+ case PPC::LIS:
+ case PPC::LIS8:
+ case PPC::LVEBX:
+ case PPC::LVEHX:
+ case PPC::LVEWX:
+ case PPC::LVSL:
+ case PPC::LVSR:
+ case PPC::LVX:
+ case PPC::LVXL:
+ case PPC::LWA:
+ case PPC::LWARX:
+ case PPC::LWAX:
+ case PPC::LWBRX:
+ case PPC::LWZ:
+ case PPC::LWZ8:
+ case PPC::LWZU:
+ case PPC::LWZU8:
+ case PPC::LWZX:
+ case PPC::LWZX8:
+ case PPC::MCRF:
+ case PPC::MFCR:
+ case PPC::MFCTR:
+ case PPC::MFCTR8:
+ case PPC::MFFS:
+ case PPC::MFLR:
+ case PPC::MFLR8:
+ case PPC::MFOCRF:
+ case PPC::MFVRSAVE:
+ case PPC::MFVSCR:
+ case PPC::MTCRF:
+ case PPC::MTCTR:
+ case PPC::MTCTR8:
+ case PPC::MTFSB0:
+ case PPC::MTFSB1:
+ case PPC::MTFSF:
+ case PPC::MTLR:
+ case PPC::MTLR8:
+ case PPC::MTVRSAVE:
+ case PPC::MTVSCR:
+ case PPC::MULHD:
+ case PPC::MULHDU:
+ case PPC::MULHW:
+ case PPC::MULHWU:
+ case PPC::MULLD:
+ case PPC::MULLI:
+ case PPC::MULLW:
+ case PPC::MovePCtoLR:
+ case PPC::MovePCtoLR8:
+ case PPC::NAND:
+ case PPC::NAND8:
+ case PPC::NEG:
+ case PPC::NEG8:
+ case PPC::NOP:
+ case PPC::NOR:
+ case PPC::NOR8:
+ case PPC::OR:
+ case PPC::OR4To8:
+ case PPC::OR8:
+ case PPC::OR8To4:
+ case PPC::ORC:
+ case PPC::ORC8:
+ case PPC::ORI:
+ case PPC::ORI8:
+ case PPC::ORIS:
+ case PPC::ORIS8:
+ case PPC::RLDCL:
+ case PPC::RLDICL:
+ case PPC::RLDICR:
+ case PPC::RLDIMI:
+ case PPC::RLWIMI:
+ case PPC::RLWINM:
+ case PPC::RLWINMo:
+ case PPC::RLWNM:
+ case PPC::SELECT_CC_F4:
+ case PPC::SELECT_CC_F8:
+ case PPC::SELECT_CC_I4:
+ case PPC::SELECT_CC_I8:
+ case PPC::SELECT_CC_VRRC:
+ case PPC::SLD:
+ case PPC::SLW:
+ case PPC::SPILL_CR:
+ case PPC::SRAD:
+ case PPC::SRADI:
+ case PPC::SRAW:
+ case PPC::SRAWI:
+ case PPC::SRD:
+ case PPC::SRW:
+ case PPC::STB:
+ case PPC::STB8:
+ case PPC::STBU:
+ case PPC::STBU8:
+ case PPC::STBX:
+ case PPC::STBX8:
+ case PPC::STD:
+ case PPC::STDCX:
+ case PPC::STDU:
+ case PPC::STDUX:
+ case PPC::STDX:
+ case PPC::STDX_32:
+ case PPC::STD_32:
+ case PPC::STFD:
+ case PPC::STFDU:
+ case PPC::STFDX:
+ case PPC::STFIWX:
+ case PPC::STFS:
+ case PPC::STFSU:
+ case PPC::STFSX:
+ case PPC::STH:
+ case PPC::STH8:
+ case PPC::STHBRX:
+ case PPC::STHU:
+ case PPC::STHU8:
+ case PPC::STHX:
+ case PPC::STHX8:
+ case PPC::STVEBX:
+ case PPC::STVEHX:
+ case PPC::STVEWX:
+ case PPC::STVX:
+ case PPC::STVXL:
+ case PPC::STW:
+ case PPC::STW8:
+ case PPC::STWBRX:
+ case PPC::STWCX:
+ case PPC::STWU:
+ case PPC::STWU8:
+ case PPC::STWUX:
+ case PPC::STWX:
+ case PPC::STWX8:
+ case PPC::SUBF:
+ case PPC::SUBF8:
+ case PPC::SUBFC:
+ case PPC::SUBFC8:
+ case PPC::SUBFE:
+ case PPC::SUBFE8:
+ case PPC::SUBFIC:
+ case PPC::SUBFIC8:
+ case PPC::SUBFME:
+ case PPC::SUBFME8:
+ case PPC::SUBFZE:
+ case PPC::SUBFZE8:
+ case PPC::SYNC:
+ case PPC::TAILB:
+ case PPC::TAILB8:
+ case PPC::TAILBA:
+ case PPC::TAILBA8:
+ case PPC::TAILBCTR:
+ case PPC::TAILBCTR8:
+ case PPC::TCRETURNai:
+ case PPC::TCRETURNai8:
+ case PPC::TCRETURNdi:
+ case PPC::TCRETURNdi8:
+ case PPC::TCRETURNri:
+ case PPC::TCRETURNri8:
+ case PPC::TRAP:
+ case PPC::UPDATE_VRSAVE:
+ case PPC::VADDCUW:
+ case PPC::VADDFP:
+ case PPC::VADDSBS:
+ case PPC::VADDSHS:
+ case PPC::VADDSWS:
+ case PPC::VADDUBM:
+ case PPC::VADDUBS:
+ case PPC::VADDUHM:
+ case PPC::VADDUHS:
+ case PPC::VADDUWM:
+ case PPC::VADDUWS:
+ case PPC::VAND:
+ case PPC::VANDC:
+ case PPC::VAVGSB:
+ case PPC::VAVGSH:
+ case PPC::VAVGSW:
+ case PPC::VAVGUB:
+ case PPC::VAVGUH:
+ case PPC::VAVGUW:
+ case PPC::VCFSX:
+ case PPC::VCFUX:
+ case PPC::VCMPBFP:
+ case PPC::VCMPBFPo:
+ case PPC::VCMPEQFP:
+ case PPC::VCMPEQFPo:
+ case PPC::VCMPEQUB:
+ case PPC::VCMPEQUBo:
+ case PPC::VCMPEQUH:
+ case PPC::VCMPEQUHo:
+ case PPC::VCMPEQUW:
+ case PPC::VCMPEQUWo:
+ case PPC::VCMPGEFP:
+ case PPC::VCMPGEFPo:
+ case PPC::VCMPGTFP:
+ case PPC::VCMPGTFPo:
+ case PPC::VCMPGTSB:
+ case PPC::VCMPGTSBo:
+ case PPC::VCMPGTSH:
+ case PPC::VCMPGTSHo:
+ case PPC::VCMPGTSW:
+ case PPC::VCMPGTSWo:
+ case PPC::VCMPGTUB:
+ case PPC::VCMPGTUBo:
+ case PPC::VCMPGTUH:
+ case PPC::VCMPGTUHo:
+ case PPC::VCMPGTUW:
+ case PPC::VCMPGTUWo:
+ case PPC::VCTSXS:
+ case PPC::VCTUXS:
+ case PPC::VEXPTEFP:
+ case PPC::VLOGEFP:
+ case PPC::VMADDFP:
+ case PPC::VMAXFP:
+ case PPC::VMAXSB:
+ case PPC::VMAXSH:
+ case PPC::VMAXSW:
+ case PPC::VMAXUB:
+ case PPC::VMAXUH:
+ case PPC::VMAXUW:
+ case PPC::VMHADDSHS:
+ case PPC::VMHRADDSHS:
+ case PPC::VMINFP:
+ case PPC::VMINSB:
+ case PPC::VMINSH:
+ case PPC::VMINSW:
+ case PPC::VMINUB:
+ case PPC::VMINUH:
+ case PPC::VMINUW:
+ case PPC::VMLADDUHM:
+ case PPC::VMRGHB:
+ case PPC::VMRGHH:
+ case PPC::VMRGHW:
+ case PPC::VMRGLB:
+ case PPC::VMRGLH:
+ case PPC::VMRGLW:
+ case PPC::VMSUMMBM:
+ case PPC::VMSUMSHM:
+ case PPC::VMSUMSHS:
+ case PPC::VMSUMUBM:
+ case PPC::VMSUMUHM:
+ case PPC::VMSUMUHS:
+ case PPC::VMULESB:
+ case PPC::VMULESH:
+ case PPC::VMULEUB:
+ case PPC::VMULEUH:
+ case PPC::VMULOSB:
+ case PPC::VMULOSH:
+ case PPC::VMULOUB:
+ case PPC::VMULOUH:
+ case PPC::VNMSUBFP:
+ case PPC::VNOR:
+ case PPC::VOR:
+ case PPC::VPERM:
+ case PPC::VPKPX:
+ case PPC::VPKSHSS:
+ case PPC::VPKSHUS:
+ case PPC::VPKSWSS:
+ case PPC::VPKSWUS:
+ case PPC::VPKUHUM:
+ case PPC::VPKUHUS:
+ case PPC::VPKUWUM:
+ case PPC::VPKUWUS:
+ case PPC::VREFP:
+ case PPC::VRFIM:
+ case PPC::VRFIN:
+ case PPC::VRFIP:
+ case PPC::VRFIZ:
+ case PPC::VRLB:
+ case PPC::VRLH:
+ case PPC::VRLW:
+ case PPC::VRSQRTEFP:
+ case PPC::VSEL:
+ case PPC::VSL:
+ case PPC::VSLB:
+ case PPC::VSLDOI:
+ case PPC::VSLH:
+ case PPC::VSLO:
+ case PPC::VSLW:
+ case PPC::VSPLTB:
+ case PPC::VSPLTH:
+ case PPC::VSPLTISB:
+ case PPC::VSPLTISH:
+ case PPC::VSPLTISW:
+ case PPC::VSPLTW:
+ case PPC::VSR:
+ case PPC::VSRAB:
+ case PPC::VSRAH:
+ case PPC::VSRAW:
+ case PPC::VSRB:
+ case PPC::VSRH:
+ case PPC::VSRO:
+ case PPC::VSRW:
+ case PPC::VSUBCUW:
+ case PPC::VSUBFP:
+ case PPC::VSUBSBS:
+ case PPC::VSUBSHS:
+ case PPC::VSUBSWS:
+ case PPC::VSUBUBM:
+ case PPC::VSUBUBS:
+ case PPC::VSUBUHM:
+ case PPC::VSUBUHS:
+ case PPC::VSUBUWM:
+ case PPC::VSUBUWS:
+ case PPC::VSUM2SWS:
+ case PPC::VSUM4SBS:
+ case PPC::VSUM4SHS:
+ case PPC::VSUM4UBS:
+ case PPC::VSUMSWS:
+ case PPC::VUPKHPX:
+ case PPC::VUPKHSB:
+ case PPC::VUPKHSH:
+ case PPC::VUPKLPX:
+ case PPC::VUPKLSB:
+ case PPC::VUPKLSH:
+ case PPC::VXOR:
+ case PPC::V_SET0:
+ case PPC::XOR:
+ case PPC::XOR8:
+ case PPC::XORI:
+ case PPC::XORI8:
+ case PPC::XORIS:
+ case PPC::XORIS8: {
+ break;
+ }
+ default:
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Not supported instr: " << MI;
+ llvm_report_error(Msg.str());
+ }
+ return Value;
+}
+
diff --git a/libclamav/c++/PPCGenDAGISel.inc b/libclamav/c++/PPCGenDAGISel.inc
new file mode 100644
index 0000000..f5fcdd3
--- /dev/null
+++ b/libclamav/c++/PPCGenDAGISel.inc
@@ -0,0 +1,9525 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// DAG Instruction Selector for the PPC target
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+// *** NOTE: This file is #included into the middle of the target
+// *** instruction selector class. These functions are really methods.
+
+// Include standard, target-independent definitions and methods used
+// by the instruction selector.
+#include "llvm/CodeGen/DAGISelHeader.h"
+
+
+// Node transformations.
+inline SDValue Transform_HA16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: shift the immediate value down into the low bits.
+ signed int Val = N->getZExtValue();
+ return getI32Imm((Val - (signed short)Val) >> 16);
+
+}
+inline SDValue Transform_HI16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: shift the immediate value down into the low bits.
+ return getI32Imm((unsigned)N->getZExtValue() >> 16);
+
+}
+inline SDValue Transform_HI32_48(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: shift the immediate value down into the low bits.
+ return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
+
+}
+inline SDValue Transform_HI48_64(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: shift the immediate value down into the low bits.
+ return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
+
+}
+inline SDValue Transform_LO16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: get the low 16 bits.
+ return getI32Imm((unsigned short)N->getZExtValue());
+
+}
+inline SDValue Transform_MB(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: get the start bit of a mask
+ unsigned mb = 0, me;
+ (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
+ return getI32Imm(mb);
+
+}
+inline SDValue Transform_ME(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: get the end bit of a mask
+ unsigned mb, me = 0;
+ (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
+ return getI32Imm(me);
+
+}
+inline SDValue Transform_SHL32(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: 31 - imm
+ return getI32Imm(31 - N->getZExtValue());
+
+}
+inline SDValue Transform_SHL64(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: 63 - imm
+ return getI32Imm(63 - N->getZExtValue());
+
+}
+inline SDValue Transform_SRL32(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: 32 - imm
+ return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
+
+}
+inline SDValue Transform_SRL64(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: 64 - imm
+ return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
+
+}
+inline SDValue Transform_VSLDOI_get_imm(SDNode *N) {
+
+ return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
+
+}
+inline SDValue Transform_VSLDOI_unary_get_imm(SDNode *N) {
+
+ return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
+
+}
+inline SDValue Transform_VSPLTB_get_imm(SDNode *N) {
+
+ return getI32Imm(PPC::getVSPLTImmediate(N, 1));
+
+}
+inline SDValue Transform_VSPLTH_get_imm(SDNode *N) {
+
+ return getI32Imm(PPC::getVSPLTImmediate(N, 2));
+
+}
+inline SDValue Transform_VSPLTISB_get_imm(SDNode *N) {
+
+ return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
+
+}
+inline SDValue Transform_VSPLTISH_get_imm(SDNode *N) {
+
+ return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
+
+}
+inline SDValue Transform_VSPLTISW_get_imm(SDNode *N) {
+
+ return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
+
+}
+inline SDValue Transform_VSPLTW_get_imm(SDNode *N) {
+
+ return getI32Imm(PPC::getVSPLTImmediate(N, 4));
+
+}
+
+// Predicate functions.
+inline bool Predicate_V_immneg0(SDNode *N) {
+
+ return PPC::isAllNegativeZeroVector(N);
+
+}
+inline bool Predicate_atomic_cmp_swap_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_cmp_swap_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_cmp_swap_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_cmp_swap_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_add_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_add_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_add_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_add_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_and_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_and_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_and_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_and_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_max_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_max_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_max_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_max_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_min_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_min_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_min_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_min_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_nand_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_nand_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_nand_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_nand_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_or_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_or_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_or_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_or_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_sub_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_sub_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_sub_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_sub_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_umax_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_umax_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_umax_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_umax_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_umin_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_umin_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_umin_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_umin_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_xor_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_xor_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_xor_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_xor_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_swap_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_swap_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_swap_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_swap_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_cvtff(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
+
+}
+inline bool Predicate_cvtfs(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
+
+}
+inline bool Predicate_cvtfu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
+
+}
+inline bool Predicate_cvtsf(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
+
+}
+inline bool Predicate_cvtss(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
+
+}
+inline bool Predicate_cvtsu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
+
+}
+inline bool Predicate_cvtuf(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
+
+}
+inline bool Predicate_cvtus(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
+
+}
+inline bool Predicate_cvtuu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
+
+}
+inline bool Predicate_extload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
+
+}
+inline bool Predicate_extloadf32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_extloadf64(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
+
+}
+inline bool Predicate_extloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_extloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_extloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_extloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_imm16ShiftedSExt(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
+ // immediate are set. Used by instructions like 'addis'. Identical to
+ // imm16ShiftedZExt in 32-bit mode.
+ if (N->getZExtValue() & 0xFFFF) return false;
+ if (N->getValueType(0) == MVT::i32)
+ return true;
+ // For 64-bit, make sure it is sext right.
+ return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
+
+}
+inline bool Predicate_imm16ShiftedZExt(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
+ // immediate are set. Used by instructions like 'xoris'.
+ return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
+
+}
+inline bool Predicate_immAllOnes(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+ return N->isAllOnesValue();
+}
+inline bool Predicate_immAllOnesV(SDNode *N) {
+
+ return ISD::isBuildVectorAllOnes(N);
+
+}
+inline bool Predicate_immAllOnesV_bc(SDNode *N) {
+
+ return ISD::isBuildVectorAllOnes(N);
+
+}
+inline bool Predicate_immAllZerosV(SDNode *N) {
+
+ return ISD::isBuildVectorAllZeros(N);
+
+}
+inline bool Predicate_immAllZerosV_bc(SDNode *N) {
+
+ return ISD::isBuildVectorAllZeros(N);
+
+}
+inline bool Predicate_immSExt16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
+ // field. Used by instructions like 'addi'.
+ if (N->getValueType(0) == MVT::i32)
+ return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
+ else
+ return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
+
+}
+inline bool Predicate_immZExt16(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
+ // field. Used by instructions like 'ori'.
+ return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
+
+}
+inline bool Predicate_istore(SDNode *N) {
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_itruncstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_load(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
+
+}
+inline bool Predicate_maskimm32(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // maskImm predicate - True if immediate is a run of ones.
+ unsigned mb, me;
+ if (N->getValueType(0) == MVT::i32)
+ return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
+ else
+ return false;
+
+}
+inline bool Predicate_post_store(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
+
+}
+inline bool Predicate_post_truncst(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
+
+}
+inline bool Predicate_post_truncstf32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_post_truncsti1(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_post_truncsti16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_post_truncsti32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_post_truncsti8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_pre_store(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+
+}
+inline bool Predicate_pre_truncst(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+
+}
+inline bool Predicate_pre_truncstf32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_pre_truncsti1(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_pre_truncsti16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_pre_truncsti32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_pre_truncsti8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_sextload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
+
+}
+inline bool Predicate_sextloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_sextloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_sextloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_sextloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_store(SDNode *N) {
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_truncstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_truncstoref32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_truncstoref64(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
+
+}
+inline bool Predicate_truncstorei16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_truncstorei32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_truncstorei8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_unindexedload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+}
+inline bool Predicate_unindexedstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+}
+inline bool Predicate_vecspltisb(SDNode *N) {
+
+ return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vecspltish(SDNode *N) {
+
+ return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vecspltisw(SDNode *N) {
+
+ return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
+
+}
+inline bool Predicate_vmrghb_shuffle(SDNode *N) {
+
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
+
+}
+inline bool Predicate_vmrghb_unary_shuffle(SDNode *N) {
+
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
+
+}
+inline bool Predicate_vmrghh_shuffle(SDNode *N) {
+
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
+
+}
+inline bool Predicate_vmrghh_unary_shuffle(SDNode *N) {
+
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
+
+}
+inline bool Predicate_vmrghw_shuffle(SDNode *N) {
+
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
+
+}
+inline bool Predicate_vmrghw_unary_shuffle(SDNode *N) {
+
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
+
+}
+inline bool Predicate_vmrglb_shuffle(SDNode *N) {
+
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
+
+}
+inline bool Predicate_vmrglb_unary_shuffle(SDNode *N) {
+
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
+
+}
+inline bool Predicate_vmrglh_shuffle(SDNode *N) {
+
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
+
+}
+inline bool Predicate_vmrglh_unary_shuffle(SDNode *N) {
+
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
+
+}
+inline bool Predicate_vmrglw_shuffle(SDNode *N) {
+
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
+
+}
+inline bool Predicate_vmrglw_unary_shuffle(SDNode *N) {
+
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
+
+}
+inline bool Predicate_vpkuhum_shuffle(SDNode *N) {
+
+ return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
+
+}
+inline bool Predicate_vpkuhum_unary_shuffle(SDNode *N) {
+
+ return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
+
+}
+inline bool Predicate_vpkuwum_shuffle(SDNode *N) {
+
+ return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
+
+}
+inline bool Predicate_vpkuwum_unary_shuffle(SDNode *N) {
+
+ return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
+
+}
+inline bool Predicate_vsldoi_shuffle(SDNode *N) {
+
+ return PPC::isVSLDOIShuffleMask(N, false) != -1;
+
+}
+inline bool Predicate_vsldoi_unary_shuffle(SDNode *N) {
+
+ return PPC::isVSLDOIShuffleMask(N, true) != -1;
+
+}
+inline bool Predicate_vspltb_shuffle(SDNode *N) {
+
+ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
+
+}
+inline bool Predicate_vsplth_shuffle(SDNode *N) {
+
+ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
+
+}
+inline bool Predicate_vspltw_shuffle(SDNode *N) {
+
+ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
+
+}
+inline bool Predicate_vtFP(SDNode *inN) {
+ VTSDNode *N = cast<VTSDNode>(inN);
+ return N->getVT().isFloatingPoint();
+}
+inline bool Predicate_vtInt(SDNode *inN) {
+ VTSDNode *N = cast<VTSDNode>(inN);
+ return N->getVT().isInteger();
+}
+inline bool Predicate_zextload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
+
+}
+inline bool Predicate_zextloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_zextloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_zextloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_zextloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+
+
+DISABLE_INLINE SDNode *Emit_0(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_1(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_HI16(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N10);
+}
+DISABLE_INLINE SDNode *Emit_3(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1);
+}
+DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = Transform_HA16(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N00);
+}
+SDNode *Select_ISD_ADD_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i32 GPRC:i32:$rA, (PPClo:i32 (tglobaladdr:i32):$sym, 0:i32))
+ // Emits: (LA:i32 GPRC:i32:$rA, (tglobaladdr:i32):$sym)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N1.getOpcode() == PPCISD::Lo) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::LA, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == PPCISD::Hi) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tglobaladdr:i32):$g, 0:i32))
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tglobaladdr:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tconstpool:i32):$g, 0:i32))
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tconstpool:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tjumptable:i32):$g, 0:i32))
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tjumptable:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tblockaddress:i32):$g, 0:i32))
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tblockaddress:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (PPClo:i32 (tglobaladdr:i32):$sym, 0:i32), GPRC:i32:$rA)
+ // Emits: (LA:i32 GPRC:i32:$rA, (tglobaladdr:i32):$sym)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N0.getOpcode() == PPCISD::Lo) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::LA, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == PPCISD::Hi) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (PPChi:i32 (tglobaladdr:i32):$g, 0:i32), GPRC:i32:$in)
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tglobaladdr:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (PPChi:i32 (tconstpool:i32):$g, 0:i32), GPRC:i32:$in)
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tconstpool:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (PPChi:i32 (tjumptable:i32):$g, 0:i32), GPRC:i32:$in)
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tjumptable:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (PPChi:i32 (tblockaddress:i32):$g, 0:i32), GPRC:i32:$in)
+ // Emits: (ADDIS:i32 GPRC:i32:$in, (tblockaddress:i32):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
+ // Emits: (ADDI:i32 GPRC:i32:$rA, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immSExt16(N1.getNode())) {
+ SDNode *Result = Emit_0(N, PPC::ADDI, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm)
+ // Emits: (ADDIS:i32 GPRC:i32:$rA, (HI16:i32 (imm:i32):$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedSExt(N1.getNode())) {
+ SDNode *Result = Emit_1(N, PPC::ADDIS, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Emits: (ADDIS:i32 (ADDI:i32 GPRC:i32:$in, (LO16:i32 (imm:i32):$imm)), (HA16:i32 (imm:i32):$imm))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDNode *Result = Emit_4(N, PPC::ADDI, PPC::ADDIS, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Emits: (ADD4:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::ADD4, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_6(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_7(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDValue Tmp2 = Transform_HI16(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+SDNode *Select_ISD_ADD_i64(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == PPCISD::Hi) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tglobaladdr:i64):$g, 0:i64))
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tglobaladdr:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tconstpool:i64):$g, 0:i64))
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tconstpool:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tjumptable:i64):$g, 0:i64))
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tjumptable:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tblockaddress:i64):$g, 0:i64))
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tblockaddress:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == PPCISD::Hi) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i64 (PPChi:i64 (tglobaladdr:i64):$g, 0:i64), G8RC:i64:$in)
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tglobaladdr:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 (PPChi:i64 (tconstpool:i64):$g, 0:i64), G8RC:i64:$in)
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tconstpool:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 (PPChi:i64 (tjumptable:i64):$g, 0:i64), G8RC:i64:$in)
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tjumptable:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 (PPChi:i64 (tblockaddress:i64):$g, 0:i64), G8RC:i64:$in)
+ // Emits: (ADDIS8:i64 G8RC:i64:$in, (tblockaddress:i64):$g)
+ // Pattern complexity = 14 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immSExt16>>:$imm)
+ // Emits: (ADDI8:i64 G8RC:i64:$rA, (imm:i64):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immSExt16(N1.getNode())) {
+ SDNode *Result = Emit_6(N, PPC::ADDI8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (add:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm)
+ // Emits: (ADDIS8:i64 G8RC:i64:$rA, (HI16:i64 (imm:i64):$imm))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedSExt(N1.getNode())) {
+ SDNode *Result = Emit_7(N, PPC::ADDIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Emits: (ADD8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::ADD8, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VADDUBM, MVT::v16i8);
+ return Result;
+}
+
+SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VADDUHM, MVT::v8i16);
+ return Result;
+}
+
+SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VADDUWM, MVT::v4i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_8(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_9(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
+
+ // Pattern: (addc:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
+ // Emits: (ADDIC:i32 GPRC:i32:$rA, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immSExt16(N1.getNode())) {
+ SDNode *Result = Emit_8(N, PPC::ADDIC, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Emits: (ADDC:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_9(N, PPC::ADDC, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_10(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
+
+ // Pattern: (addc:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immSExt16>>:$imm)
+ // Emits: (ADDIC8:i64 G8RC:i64:$rA, (imm:i64):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immSExt16(N1.getNode())) {
+ SDNode *Result = Emit_10(N, PPC::ADDIC8, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Emits: (ADDC8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_9(N, PPC::ADDC8, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_11(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_12(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (adde:i32 GPRC:i32:$rA, 0:i32)
+ // Emits: (ADDZE:i32 GPRC:i32:$rA)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_12(N, PPC::ADDZE, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (adde:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (ADDME:i32 GPRC:i32:$rA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_12(N, PPC::ADDME, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Emits: (ADDE:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_11(N, PPC::ADDE, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (adde:i64 G8RC:i64:$rA, 0:i64)
+ // Emits: (ADDZE8:i64 G8RC:i64:$rA)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_12(N, PPC::ADDZE8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (adde:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immAllOnes>>)
+ // Emits: (ADDME8:i64 G8RC:i64:$rA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_12(N, PPC::ADDME8, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Emits: (ADDE8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_11(N, PPC::ADDE8, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_13(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_14(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp3 = Transform_MB(Tmp2.getNode());
+ SDValue Tmp4 = Transform_ME(Tmp2.getNode());
+ SDValue Ops0[] = { N00, N01, Tmp3, Tmp4 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_AND_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i32 GPRC:i32:$rS, (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (ANDC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_2(N, PPC::ANDC, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (rotl:i32 GPRC:i32:$in, GPRC:i32:$sh), (imm:i32)<<P:Predicate_maskimm32>>:$imm)
+ // Emits: (RLWNM:i32 GPRC:i32:$in, GPRC:i32:$sh, (MB:i32 (imm:i32)<<P:Predicate_maskimm32>>:$imm), (ME:i32 (imm:i32)<<P:Predicate_maskimm32>>:$imm))
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::ROTL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_maskimm32(N1.getNode()) &&
+ N01.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_14(N, PPC::RLWNM, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rS)
+ // Emits: (ANDC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_5(N, PPC::ANDC, MVT::i32);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
+ // Emits: (ANDIo:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immZExt16(N1.getNode())) {
+ SDNode *Result = Emit_13(N, PPC::ANDIo, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
+ // Emits: (ANDISo:i32 GPRC:i32:$src1, (HI16:i32 (imm:i32):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedZExt(N1.getNode())) {
+ SDNode *Result = Emit_1(N, PPC::ANDISo, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Emits: (AND:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::AND, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_15(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+SDNode *Select_ISD_AND_i64(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i64 G8RC:i64:$rS, (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>))
+ // Emits: (ANDC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_2(N, PPC::ANDC8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i64 (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rS)
+ // Emits: (ANDC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_5(N, PPC::ANDC8, MVT::i64);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
+ // Emits: (ANDIo8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immZExt16(N1.getNode())) {
+ SDNode *Result = Emit_15(N, PPC::ANDIo8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (and:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
+ // Emits: (ANDISo8:i64 G8RC:i64:$src1, (HI16:i32 (imm:i64):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedZExt(N1.getNode())) {
+ SDNode *Result = Emit_7(N, PPC::ANDISo8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Emits: (AND8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::AND8, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_16(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N11);
+}
+DISABLE_INLINE SDNode *Emit_17(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N01);
+}
+SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ {
+ SDValue N11 = N1.getOperand(1);
+
+ // Pattern: (and:v4i32 VRRC:v4i32:$vA, (xor:v4i32 VRRC:v4i32:$vB, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>))
+ // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_2(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (and:v4i32 VRRC:v4i32:$A, (xor:v4i32 VRRC:v4i32:$B, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
+ // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N11.getNode())) {
+ SDNode *Result = Emit_2(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v4i32 VRRC:v4i32:$vA, (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vB))
+ // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_16(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v4i32 (xor:v4i32 VRRC:v4i32:$vB, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VRRC:v4i32:$vA)
+ // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDNode *Result = Emit_5(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v4i32 (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vB), VRRC:v4i32:$vA)
+ // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDNode *Result = Emit_17(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v4i32 VRRC:v4i32:$A, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$B))
+ // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N10.getNode())) {
+ SDNode *Result = Emit_16(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v4i32 (xor:v4i32 VRRC:v4i32:$B, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), VRRC:v4i32:$A)
+ // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N01.getNode())) {
+ SDNode *Result = Emit_5(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$B), VRRC:v4i32:$A)
+ // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N00.getNode())) {
+ SDNode *Result = Emit_17(N, PPC::VANDC, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VAND:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::VAND, MVT::v4i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_18(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
+}
+SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_18(N, PPC::OR4To8, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_19(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, N2, N3, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 5);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_8>>
+ // Emits: (ATOMIC_CMP_SWAP_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_cmp_swap_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_16>>
+ // Emits: (ATOMIC_CMP_SWAP_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_cmp_swap_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_32>>
+ // Emits: (ATOMIC_CMP_SWAP_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_cmp_swap_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_CMP_SWAP_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_cmp_swap_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_20(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, N2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_8>>
+ // Emits: (ATOMIC_LOAD_ADD_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_add_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_16>>
+ // Emits: (ATOMIC_LOAD_ADD_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_add_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_32>>
+ // Emits: (ATOMIC_LOAD_ADD_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_add_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_add_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_8>>
+ // Emits: (ATOMIC_LOAD_AND_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_and_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_16>>
+ // Emits: (ATOMIC_LOAD_AND_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_and_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_32>>
+ // Emits: (ATOMIC_LOAD_AND_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_and_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_and_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_8>>
+ // Emits: (ATOMIC_LOAD_NAND_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_nand_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_16>>
+ // Emits: (ATOMIC_LOAD_NAND_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_nand_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_32>>
+ // Emits: (ATOMIC_LOAD_NAND_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_nand_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_nand_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_8>>
+ // Emits: (ATOMIC_LOAD_OR_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_or_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_16>>
+ // Emits: (ATOMIC_LOAD_OR_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_or_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_32>>
+ // Emits: (ATOMIC_LOAD_OR_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_or_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_or_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_8>>
+ // Emits: (ATOMIC_LOAD_SUB_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_sub_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_16>>
+ // Emits: (ATOMIC_LOAD_SUB_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_sub_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_32>>
+ // Emits: (ATOMIC_LOAD_SUB_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_sub_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_SUB_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_sub_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_8>>
+ // Emits: (ATOMIC_LOAD_XOR_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_xor_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_16>>
+ // Emits: (ATOMIC_LOAD_XOR_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_xor_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_32>>
+ // Emits: (ATOMIC_LOAD_XOR_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_load_xor_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_xor_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+
+ // Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_8>>
+ // Emits: (ATOMIC_SWAP_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_swap_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_16>>
+ // Emits: (ATOMIC_SWAP_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_swap_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_32>>
+ // Emits: (ATOMIC_SWAP_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
+ // Pattern complexity = 13 cost = 11 size = 0
+ if (Predicate_atomic_swap_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_swap_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_21(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ReplaceUses(N, N0);
+ return NULL;
+}
+SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v16i8 VRRC:v8i16:$src)
+ // Emits: VRRC:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 VRRC:v4i32:$src)
+ // Emits: VRRC:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 VRRC:v4f32:$src)
+ // Emits: VRRC:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v8i16 VRRC:v16i8:$src)
+ // Emits: VRRC:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 VRRC:v4i32:$src)
+ // Emits: VRRC:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 VRRC:v4f32:$src)
+ // Emits: VRRC:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4i32 VRRC:v16i8:$src)
+ // Emits: VRRC:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 VRRC:v8i16:$src)
+ // Emits: VRRC:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 VRRC:v4f32:$src)
+ // Emits: VRRC:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4f32 VRRC:v16i8:$src)
+ // Emits: VRRC:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 VRRC:v8i16:$src)
+ // Emits: VRRC:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 VRRC:v4i32:$src)
+ // Emits: VRRC:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_21(N);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_22(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
+}
+SDNode *Select_ISD_BR(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BasicBlock) {
+ SDNode *Result = Emit_22(N, PPC::B);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VSPLTISB_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
+ if (Predicate_vecspltisb(N.getNode())) {
+ SDNode *Result = Emit_23(N, PPC::VSPLTISB, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_24(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VSPLTISH_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
+ if (Predicate_vecspltish(N.getNode())) {
+ SDNode *Result = Emit_24(N, PPC::VSPLTISH, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_25(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VSPLTISW_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
+
+ // Pattern: (build_vector:v4i32)<<P:Predicate_vecspltisw>><<X:VSPLTISW_get_imm>>:$SIMM
+ // Emits: (VSPLTISW:v4i32 (VSPLTISW_get_imm:i32 (build_vector:v4i32):$SIMM))
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vecspltisw(N.getNode())) {
+ SDNode *Result = Emit_25(N, PPC::VSPLTISW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (build_vector:v4i32)<<P:Predicate_immAllZerosV>>
+ // Emits: (V_SET0:v4i32)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_26(N, PPC::V_SET0, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { N1, N2, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_27(N, PPC::ADJCALLSTACKUP);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain);
+ Chain = SDValue(ResNode, 0);
+ SDValue InFlag(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_28(N, PPC::ADJCALLSTACKDOWN);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_29(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+}
+SDNode *Select_ISD_CTLZ_i32(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::CNTLZW, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_CTLZ_i64(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::CNTLZD, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_30(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+}
+DISABLE_INLINE SDNode *Emit_31(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_32(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Tmp1), 0);
+ SDValue Tmp3 = Transform_LO16(Tmp0.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
+}
+SDNode *Select_ISD_Constant_i32(const SDValue &N) {
+
+ // Pattern: (imm:i32)<<P:Predicate_immSExt16>>:$imm
+ // Emits: (LI:i32 (imm:i32):$imm)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_immSExt16(N.getNode())) {
+ SDNode *Result = Emit_30(N, PPC::LI, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm
+ // Emits: (LIS:i32 (HI16:i32 (imm:i32):$imm))
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_imm16ShiftedSExt(N.getNode())) {
+ SDNode *Result = Emit_31(N, PPC::LIS, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32):$imm
+ // Emits: (ORI:i32 (LIS:i32 (HI16:i32 (imm:i32):$imm)), (LO16:i32 (imm:i32):$imm))
+ // Pattern complexity = 3 cost = 2 size = 0
+ SDNode *Result = Emit_32(N, PPC::LIS, PPC::ORI, MVT::i32, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_33(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+}
+DISABLE_INLINE SDNode *Emit_34(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
+ SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+}
+SDNode *Select_ISD_Constant_i64(const SDValue &N) {
+
+ // Pattern: (imm:i64)<<P:Predicate_immSExt16>>:$imm
+ // Emits: (LI8:i64 (imm:i64):$imm)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_immSExt16(N.getNode())) {
+ SDNode *Result = Emit_33(N, PPC::LI8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (imm:i64)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm
+ // Emits: (LIS8:i64 (HI16:i64 (imm:i64):$imm))
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_imm16ShiftedSExt(N.getNode())) {
+ SDNode *Result = Emit_34(N, PPC::LIS8, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FABS_f32(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FABSS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FABS_f64(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FABSD, MVT::f64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_35(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N01, N1);
+}
+DISABLE_INLINE SDNode *Emit_36(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N11, N0);
+}
+SDNode *Select_ISD_FADD_f32(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB)
+ // Emits: (FMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_35(N, PPC::FMADDS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fadd:f32 F4RC:f32:$FRB, (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC))
+ // Emits: (FMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_36(N, PPC::FMADDS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
+ // Emits: (FADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::FADDS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FADD_f64(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB)
+ // Emits: (FMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_35(N, PPC::FMADD, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fadd:f64 F8RC:f64:$FRB, (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC))
+ // Emits: (FMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_36(N, PPC::FMADD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
+ // Emits: (FADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::FADD, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:v4f32 (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC), VRRC:v4f32:$vB)
+ // Emits: (VMADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_35(N, PPC::VMADDFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (fadd:v4f32 VRRC:v4f32:$vB, (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC))
+ // Emits: (VMADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_36(N, PPC::VMADDFP, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Emits: (VADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::VADDFP, MVT::v4f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::FDIVS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::FDIV, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::FMULS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::FMUL, MVT::f64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_37(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, N1, Tmp2);
+}
+SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
+ SDNode *Result = Emit_37(N, PPC::V_SET0, PPC::VMADDFP, MVT::v4i32, MVT::v4f32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_38(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
+}
+DISABLE_INLINE SDNode *Emit_39(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, N001, N01);
+}
+DISABLE_INLINE SDNode *Emit_40(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N010, N011, N00);
+}
+SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fneg:f32 (fadd:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB))
+ // Emits: (FNMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_39(N, PPC::FNMADDS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f32 (fsub:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB))
+ // Emits: (FNMSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FSUB) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_39(N, PPC::FNMSUBS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f32 (fadd:f32 F4RC:f32:$FRB, (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC)))
+ // Emits: (FNMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_40(N, PPC::FNMADDS, MVT::f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fneg:f32 (fabs:f32 F4RC:f32:$frB))
+ // Emits: (FNABSS:f32 F4RC:f32:$frB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::FABS) {
+ SDNode *Result = Emit_38(N, PPC::FNABSS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f32 F4RC:f32:$frB)
+ // Emits: (FNEGS:f32 F4RC:f32:$frB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_29(N, PPC::FNEGS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fneg:f64 (fadd:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB))
+ // Emits: (FNMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_39(N, PPC::FNMADD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f64 (fsub:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB))
+ // Emits: (FNMSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FSUB) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_39(N, PPC::FNMSUB, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f64 (fadd:f64 F8RC:f64:$FRB, (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC)))
+ // Emits: (FNMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_40(N, PPC::FNMADD, MVT::f64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (fneg:f64 (fabs:f64 F8RC:f64:$frB))
+ // Emits: (FNABSD:f64 F8RC:f64:$frB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::FABS) {
+ SDNode *Result = Emit_38(N, PPC::FNABSD, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fneg:f64 F8RC:f64:$frB)
+ // Emits: (FNEGD:f64 F8RC:f64:$frB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_29(N, PPC::FNEGD, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_29(N, PPC::FMRSD, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_29(N, PPC::FRSP, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FSQRTS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FSQRT, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fsub:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB)
+ // Emits: (FMSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_35(N, PPC::FMSUBS, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 F4RC:f32:$B, (fmul:f32 F4RC:f32:$A, F4RC:f32:$C))
+ // Emits: (FNMSUBS:f32 F4RC:f32:$A, F4RC:f32:$C, F4RC:f32:$B)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_36(N, PPC::FNMSUBS, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
+ // Emits: (FSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::FSUBS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fsub:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB)
+ // Emits: (FMSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_35(N, PPC::FMSUB, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fsub:f64 F8RC:f64:$B, (fmul:f64 F8RC:f64:$A, F8RC:f64:$C))
+ // Emits: (FNMSUB:f64 F8RC:f64:$A, F8RC:f64:$C, F8RC:f64:$B)
+ // Pattern complexity = 6 cost = 1 size = 0
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_36(N, PPC::FNMSUB, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
+ // Emits: (FSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::FSUB, MVT::f64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_41(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100, N101, N11);
+}
+SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
+
+ // Pattern: (fsub:v4f32 (build_vector:v4f32)<<P:Predicate_V_immneg0>>, (fsub:v4f32 (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC), VRRC:v4f32:$vB))
+ // Emits: (VNMSUBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if ((!NoExcessFPPrecision)) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_V_immneg0(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::FSUB) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::FMUL) {
+ SDNode *Result = Emit_41(N, PPC::VNMSUBFP, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Emits: (VSUBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::VSUBFP, MVT::v4f32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_42(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
+}
+DISABLE_INLINE SDNode *Emit_43(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+DISABLE_INLINE SDNode *Emit_44(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N2, Chain);
+}
+DISABLE_INLINE SDNode *Emit_45(const SDValue &N, unsigned Opc0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Ops0[] = { N2, CPTmpN3_0, CPTmpN3_1, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_46(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Ops0[] = { Tmp2, Tmp3, Tmp4, Tmp5, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_47(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Ops0[] = { Tmp2, Tmp3, Tmp4, Tmp5, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_48(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
+ SDValue Ops0[] = { Tmp2, Tmp3, N2, N3, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_49(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
+ SDValue Ops0[] = { Tmp2, Tmp3, N2, N3, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+}
+SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_void:isVoid 339:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBA:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(339)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBA, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 340:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBF:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(340)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBF, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 341:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBI:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(341)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBI, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 342:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBST:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(342)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBST, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 343:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBT:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(343)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBT, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 344:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBTST:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(344)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBTST, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 345:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBZ:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(345)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBZ, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 346:iPTR, xoaddr:iPTR:$dst)
+ // Emits: (DCBZL:isVoid xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(346)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_42(N, PPC::DCBZL, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 207:iPTR, VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STVEBX:isVoid VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(207)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
+ SDNode *Result = Emit_45(N, PPC::STVEBX, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 208:iPTR, VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STVEHX:isVoid VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(208)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
+ SDNode *Result = Emit_45(N, PPC::STVEHX, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 209:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STVEWX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(209)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
+ SDNode *Result = Emit_45(N, PPC::STVEWX, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 210:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STVX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(210)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
+ SDNode *Result = Emit_45(N, PPC::STVX, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 211:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STVXL:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(211)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ SDValue CPTmpN3_1;
+ if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
+ SDNode *Result = Emit_45(N, PPC::STVXL, CPTmpN3_0, CPTmpN3_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 192:iPTR, (imm:i32):$STRM)
+ // Emits: (DSS:isVoid 0:i32, (imm:i32):$STRM, 0:i32, 0:i32)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(192)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_47(N, PPC::DSS);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 194:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(194)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_48(N, PPC::DST);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 197:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(197)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_49(N, PPC::DSTT);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 195:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DSTST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(195)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_48(N, PPC::DSTST);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 196:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DSTSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(196)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_49(N, PPC::DSTSTT);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 194:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(194)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_48(N, PPC::DST64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 197:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(197)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_49(N, PPC::DSTT64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 195:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DSTST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(195)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_48(N, PPC::DSTST64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 196:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Emits: (DSTSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(196)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_49(N, PPC::DSTSTT64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 347:iPTR)
+ // Emits: (SYNC:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(347)) {
+ SDNode *Result = Emit_43(N, PPC::SYNC);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 206:iPTR, VRRC:v4i32:$vB)
+ // Emits: (MTVSCR:isVoid VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(206)) {
+ SDNode *Result = Emit_44(N, PPC::MTVSCR);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 193:iPTR)
+ // Emits: (DSSALL:isVoid 1:i32, 0:i32, 0:i32, 0:i32)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(193)) {
+ SDNode *Result = Emit_46(N, PPC::DSSALL);
+ return Result;
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_50(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, CPTmpN1_0, CPTmpN1_1);
+}
+DISABLE_INLINE SDNode *Emit_51(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 201:iPTR, xoaddr:iPTR:$src)
+ // Emits: (LVSL:v16i8 xoaddr:iPTR:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(201)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_50(N, PPC::LVSL, MVT::v16i8, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 202:iPTR, xoaddr:iPTR:$src)
+ // Emits: (LVSR:v16i8 xoaddr:iPTR:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(202)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_50(N, PPC::LVSR, MVT::v16i8, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 213:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VADDSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(213)) {
+ SDNode *Result = Emit_51(N, PPC::VADDSBS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 216:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VADDUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(216)) {
+ SDNode *Result = Emit_51(N, PPC::VADDUBS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 219:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VAVGSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(219)) {
+ SDNode *Result = Emit_51(N, PPC::VAVGSB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 222:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VAVGUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(222)) {
+ SDNode *Result = Emit_51(N, PPC::VAVGUB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 259:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMAXSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(259)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXSB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 262:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMAXUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(262)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXUB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 268:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMINSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(268)) {
+ SDNode *Result = Emit_51(N, PPC::VMINSB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 271:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMINUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(271)) {
+ SDNode *Result = Emit_51(N, PPC::VMINUB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 322:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VSUBSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(322)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBSBS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 325:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VSUBUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(325)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBUBS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 303:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VRLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(303)) {
+ SDNode *Result = Emit_51(N, PPC::VRLB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 309:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VSLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(309)) {
+ SDNode *Result = Emit_51(N, PPC::VSLB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 314:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VSRAB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(314)) {
+ SDNode *Result = Emit_51(N, PPC::VSRAB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 317:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VSRB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(317)) {
+ SDNode *Result = Emit_51(N, PPC::VSRB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 292:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VPKSHSS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(292)) {
+ SDNode *Result = Emit_51(N, PPC::VPKSHSS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 293:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VPKSHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(293)) {
+ SDNode *Result = Emit_51(N, PPC::VPKSHUS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 294:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VPKSWSS:v16i8 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(294)) {
+ SDNode *Result = Emit_51(N, PPC::VPKSWSS, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 296:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VPKUHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(296)) {
+ SDNode *Result = Emit_51(N, PPC::VPKUHUS, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_52(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, N3);
+}
+DISABLE_INLINE SDNode *Emit_53(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 265:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Emits: (VMHADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(265)) {
+ SDNode *Result = Emit_52(N, PPC::VMHADDSHS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 266:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Emits: (VMHRADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(266)) {
+ SDNode *Result = Emit_52(N, PPC::VMHRADDSHS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 274:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Emits: (VMLADDUHM:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(274)) {
+ SDNode *Result = Emit_52(N, PPC::VMLADDUHM, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 214:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(214)) {
+ SDNode *Result = Emit_51(N, PPC::VADDSHS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 217:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VADDUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(217)) {
+ SDNode *Result = Emit_51(N, PPC::VADDUHS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 220:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VAVGSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(220)) {
+ SDNode *Result = Emit_51(N, PPC::VAVGSH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 223:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VAVGUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(223)) {
+ SDNode *Result = Emit_51(N, PPC::VAVGUH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 260:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMAXSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(260)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXSH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 263:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMAXUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(263)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXUH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 269:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMINSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(269)) {
+ SDNode *Result = Emit_51(N, PPC::VMINSH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 272:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMINUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(272)) {
+ SDNode *Result = Emit_51(N, PPC::VMINUH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 281:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMULESB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(281)) {
+ SDNode *Result = Emit_51(N, PPC::VMULESB, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 283:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMULEUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(283)) {
+ SDNode *Result = Emit_51(N, PPC::VMULEUB, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 285:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMULOSB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(285)) {
+ SDNode *Result = Emit_51(N, PPC::VMULOSB, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 287:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Emits: (VMULOUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(287)) {
+ SDNode *Result = Emit_51(N, PPC::VMULOUB, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 323:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VSUBSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(323)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBSHS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 326:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VSUBUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(326)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBUHS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 304:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VRLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(304)) {
+ SDNode *Result = Emit_51(N, PPC::VRLH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 310:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VSLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(310)) {
+ SDNode *Result = Emit_51(N, PPC::VSLH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 315:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VSRAH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(315)) {
+ SDNode *Result = Emit_51(N, PPC::VSRAH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 318:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VSRH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(318)) {
+ SDNode *Result = Emit_51(N, PPC::VSRH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 291:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VPKPX:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(291)) {
+ SDNode *Result = Emit_51(N, PPC::VPKPX, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 295:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VPKSWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(295)) {
+ SDNode *Result = Emit_51(N, PPC::VPKSWUS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 297:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VPKUWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(297)) {
+ SDNode *Result = Emit_51(N, PPC::VPKUWUS, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 334:iPTR, VRRC:v16i8:$vB)
+ // Emits: (VUPKHSB:v8i16 VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(334)) {
+ SDNode *Result = Emit_53(N, PPC::VUPKHSB, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 337:iPTR, VRRC:v16i8:$vB)
+ // Emits: (VUPKLSB:v8i16 VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(337)) {
+ SDNode *Result = Emit_53(N, PPC::VUPKLSB, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_54(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp2, N1);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 253:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
+ // Emits: (VCTSXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(253)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_54(N, PPC::VCTSXS, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 254:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
+ // Emits: (VCTUXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(254)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_54(N, PPC::VCTUXS, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 290:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
+ // Emits: (VPERM:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(290)) {
+ SDNode *Result = Emit_52(N, PPC::VPERM, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 307:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
+ // Emits: (VSEL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(307)) {
+ SDNode *Result = Emit_52(N, PPC::VSEL, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 212:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VADDCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(212)) {
+ SDNode *Result = Emit_51(N, PPC::VADDCUW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 215:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VADDSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(215)) {
+ SDNode *Result = Emit_51(N, PPC::VADDSWS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 218:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VADDUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(218)) {
+ SDNode *Result = Emit_51(N, PPC::VADDUWS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 221:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VAVGSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(221)) {
+ SDNode *Result = Emit_51(N, PPC::VAVGSW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 224:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VAVGUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(224)) {
+ SDNode *Result = Emit_51(N, PPC::VAVGUW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 261:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VMAXSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(261)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXSW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 264:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VMAXUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(264)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXUW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 270:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VMINSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(270)) {
+ SDNode *Result = Emit_51(N, PPC::VMINSW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 273:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VMINUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(273)) {
+ SDNode *Result = Emit_51(N, PPC::VMINUW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 275:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Emits: (VMSUMMBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(275)) {
+ SDNode *Result = Emit_52(N, PPC::VMSUMMBM, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 276:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Emits: (VMSUMSHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(276)) {
+ SDNode *Result = Emit_52(N, PPC::VMSUMSHM, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 277:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Emits: (VMSUMSHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(277)) {
+ SDNode *Result = Emit_52(N, PPC::VMSUMSHS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 278:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Emits: (VMSUMUBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(278)) {
+ SDNode *Result = Emit_52(N, PPC::VMSUMUBM, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 279:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Emits: (VMSUMUHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(279)) {
+ SDNode *Result = Emit_52(N, PPC::VMSUMUHM, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 280:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Emits: (VMSUMUHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(280)) {
+ SDNode *Result = Emit_52(N, PPC::VMSUMUHS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 282:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMULESH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(282)) {
+ SDNode *Result = Emit_51(N, PPC::VMULESH, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 284:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMULEUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(284)) {
+ SDNode *Result = Emit_51(N, PPC::VMULEUH, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 286:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMULOSH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(286)) {
+ SDNode *Result = Emit_51(N, PPC::VMULOSH, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 288:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Emits: (VMULOUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(288)) {
+ SDNode *Result = Emit_51(N, PPC::VMULOUH, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 321:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUBCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(321)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBCUW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 324:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUBSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(324)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBSWS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 327:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUBUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(327)) {
+ SDNode *Result = Emit_51(N, PPC::VSUBUWS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 332:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUMSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(332)) {
+ SDNode *Result = Emit_51(N, PPC::VSUMSWS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 328:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUM2SWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(328)) {
+ SDNode *Result = Emit_51(N, PPC::VSUM2SWS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 329:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUM4SBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(329)) {
+ SDNode *Result = Emit_51(N, PPC::VSUM4SBS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 330:iPTR, VRRC:v8i16:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUM4SHS:v4i32 VRRC:v8i16:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(330)) {
+ SDNode *Result = Emit_51(N, PPC::VSUM4SHS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 331:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSUM4UBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(331)) {
+ SDNode *Result = Emit_51(N, PPC::VSUM4UBS, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 305:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VRLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(305)) {
+ SDNode *Result = Emit_51(N, PPC::VRLW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 308:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(308)) {
+ SDNode *Result = Emit_51(N, PPC::VSL, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 311:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSLO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(311)) {
+ SDNode *Result = Emit_51(N, PPC::VSLO, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 312:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(312)) {
+ SDNode *Result = Emit_51(N, PPC::VSLW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 313:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(313)) {
+ SDNode *Result = Emit_51(N, PPC::VSR, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 319:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSRO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(319)) {
+ SDNode *Result = Emit_51(N, PPC::VSRO, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 316:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSRAW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(316)) {
+ SDNode *Result = Emit_51(N, PPC::VSRAW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 320:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VSRW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(320)) {
+ SDNode *Result = Emit_51(N, PPC::VSRW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 333:iPTR, VRRC:v8i16:$vB)
+ // Emits: (VUPKHPX:v4i32 VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(333)) {
+ SDNode *Result = Emit_53(N, PPC::VUPKHPX, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 335:iPTR, VRRC:v8i16:$vB)
+ // Emits: (VUPKHSH:v4i32 VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(335)) {
+ SDNode *Result = Emit_53(N, PPC::VUPKHSH, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 336:iPTR, VRRC:v8i16:$vB)
+ // Emits: (VUPKLPX:v4i32 VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(336)) {
+ SDNode *Result = Emit_53(N, PPC::VUPKLPX, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 338:iPTR, VRRC:v8i16:$vB)
+ // Emits: (VUPKLSH:v4i32 VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(338)) {
+ SDNode *Result = Emit_53(N, PPC::VUPKLSH, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 225:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
+ // Emits: (VCFSX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(225)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_54(N, PPC::VCFSX, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 226:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
+ // Emits: (VCFUX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (CN1 == INT64_C(226)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_54(N, PPC::VCFUX, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 255:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VEXPTEFP:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(255)) {
+ SDNode *Result = Emit_53(N, PPC::VEXPTEFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 256:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VLOGEFP:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(256)) {
+ SDNode *Result = Emit_53(N, PPC::VLOGEFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 258:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Emits: (VMAXFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(258)) {
+ SDNode *Result = Emit_51(N, PPC::VMAXFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 267:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Emits: (VMINFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(267)) {
+ SDNode *Result = Emit_51(N, PPC::VMINFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 298:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VREFP:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(298)) {
+ SDNode *Result = Emit_53(N, PPC::VREFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 299:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VRFIM:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(299)) {
+ SDNode *Result = Emit_53(N, PPC::VRFIM, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 300:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VRFIN:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(300)) {
+ SDNode *Result = Emit_53(N, PPC::VRFIN, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 301:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VRFIP:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(301)) {
+ SDNode *Result = Emit_53(N, PPC::VRFIP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 302:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VRFIZ:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(302)) {
+ SDNode *Result = Emit_53(N, PPC::VRFIZ, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 306:iPTR, VRRC:v4f32:$vB)
+ // Emits: (VRSQRTEFP:v4f32 VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(306)) {
+ SDNode *Result = Emit_53(N, PPC::VRSQRTEFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 257:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
+ // Emits: (VMADDFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(257)) {
+ SDNode *Result = Emit_52(N, PPC::VMADDFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 289:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
+ // Emits: (VNMSUBFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(289)) {
+ SDNode *Result = Emit_52(N, PPC::VNMSUBFP, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_55(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
+}
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(198)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_55(N, PPC::LVEBX, MVT::v16i8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_56(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Chain);
+}
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_w_chain:v8i16 199:iPTR, xoaddr:iPTR:$src)
+ // Emits: (LVEHX:v8i16 xoaddr:iPTR:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(199)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_55(N, PPC::LVEHX, MVT::v8i16, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_w_chain:v8i16 205:iPTR)
+ // Emits: (MFVSCR:v8i16)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(205)) {
+ SDNode *Result = Emit_56(N, PPC::MFVSCR, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_w_chain:v4i32 200:iPTR, xoaddr:iPTR:$src)
+ // Emits: (LVEWX:v4i32 xoaddr:iPTR:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(200)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_55(N, PPC::LVEWX, MVT::v4i32, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_w_chain:v4i32 203:iPTR, xoaddr:iPTR:$src)
+ // Emits: (LVX:v4i32 xoaddr:iPTR:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(203)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_55(N, PPC::LVX, MVT::v4i32, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_w_chain:v4i32 204:iPTR, xoaddr:iPTR:$src)
+ // Emits: (LVXL:v4i32 xoaddr:iPTR:$src)
+ // Pattern complexity = 17 cost = 1 size = 0
+ if (CN1 == INT64_C(204)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_55(N, PPC::LVXL, MVT::v4i32, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_57(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (LBZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (LHA:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_sextload(N.getNode()) &&
+ Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHA, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (LHZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LWZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (LBZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (LHAX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_sextload(N.getNode()) &&
+ Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHAX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (LHZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LWZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (LBZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (LBZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (LBZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (LBZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (LBZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (LBZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (LHZ:i32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (LHZX:i32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (LHA8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHA8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 ixaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
+ // Emits: (LWA:i64 ixaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_sextloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWA, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (LHAX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHAX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
+ // Emits: (LWAX:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_sextloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWAX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (LBZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (LHZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
+ // Emits: (LWZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (LBZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (LHZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
+ // Emits: (LWZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_zextloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i64 ixaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LD:i64 ixaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LD, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LDX:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LDX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (LBZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (LBZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (LBZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (LBZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (LBZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (LBZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (LHZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (LHZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LHZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
+ // Emits: (LWZ8:i64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
+ // Emits: (LWZX8:i64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LWZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:f32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LFS:f32 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LFS, MVT::f32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:f32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LFSX:f32 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LFSX, MVT::f32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_58(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain), 0);
+ Chain = SDValue(Tmp1.getNode(), 1);
+ MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
+ MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDNode *ResNode = CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
+ ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ return ResNode;
+}
+SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:f64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LFD:f64 iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LFD, MVT::f64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:f64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (LFDX:f64 xaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LFDX, MVT::f64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode()) &&
+ Predicate_extloadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+
+ // Pattern: (ld:f64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (FMRSD:f64 (LFS:f32 iaddr:iPTR:$src))
+ // Pattern complexity = 13 cost = 2 size = 0
+ if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_58(N, PPC::LFS, PPC::FMRSD, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (ld:f64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (FMRSD:f64 (LFSX:f32 xaddr:iPTR:$src))
+ // Pattern complexity = 13 cost = 2 size = 0
+ if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_58(N, PPC::LFSX, PPC::FMRSD, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_57(N, PPC::LVX, MVT::v4i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_59(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant) {
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_59(N, PPC::SYNC);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_i32(const SDValue &N) {
+
+ // Pattern: (mul:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
+ // Emits: (MULLI:i32 GPRC:i32:$rA, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immSExt16(N1.getNode())) {
+ SDNode *Result = Emit_0(N, PPC::MULLI, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (mul:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Emits: (MULLW:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::MULLW, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_MUL_i64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::MULLD, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_MULHS_i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::MULHW, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_MULHS_i64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::MULHD, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_MULHU_i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::MULHWU, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_MULHU_i64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::MULHDU, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_60(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = Transform_HI16(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3, Tmp4);
+}
+SDNode *Select_ISD_OR_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i32 GPRC:i32:$rS, (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (ORC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_2(N, PPC::ORC, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rS)
+ // Emits: (ORC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_5(N, PPC::ORC, MVT::i32);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
+ // Emits: (ORI:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immZExt16(N1.getNode())) {
+ SDNode *Result = Emit_13(N, PPC::ORI, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
+ // Emits: (ORIS:i32 GPRC:i32:$src1, (HI16:i32 (imm:i32):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedZExt(N1.getNode())) {
+ SDNode *Result = Emit_1(N, PPC::ORIS, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Emits: (ORIS:i32 (ORI:i32 GPRC:i32:$in, (LO16:i32 (imm:i32):$imm)), (HI16:i32 (imm:i32):$imm))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDNode *Result = Emit_60(N, PPC::ORI, PPC::ORIS, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Emits: (OR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::OR, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_OR_i64(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i64 G8RC:i64:$rS, (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>))
+ // Emits: (ORC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_2(N, PPC::ORC8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rS)
+ // Emits: (ORC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_5(N, PPC::ORC8, MVT::i64);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
+ // Emits: (ORI8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immZExt16(N1.getNode())) {
+ SDNode *Result = Emit_15(N, PPC::ORI8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (or:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
+ // Emits: (ORIS8:i64 G8RC:i64:$src1, (HI16:i32 (imm:i64):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedZExt(N1.getNode())) {
+ SDNode *Result = Emit_7(N, PPC::ORIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Emits: (OR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::OR8, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VOR, MVT::v4i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_61(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
+ SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_62(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotl:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Emits: (RLWINM:i32 GPRC:i32:$in, (imm:i32):$imm, 0:i32, 31:i32)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_62(N, PPC::RLWINM, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (rotl:i32 GPRC:i32:$in, GPRC:i32:$sh)
+ // Emits: (RLWNM:i32 GPRC:i32:$in, GPRC:i32:$sh, 0:i32, 31:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_61(N, PPC::RLWNM, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_63(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_64(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+}
+SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotl:i64 G8RC:i64:$in, (imm:i32):$imm)
+ // Emits: (RLDICL:i64 G8RC:i64:$in, (imm:i32):$imm, 0:i32)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_64(N, PPC::RLDICL, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (rotl:i64 G8RC:i64:$in, GPRC:i32:$sh)
+ // Emits: (RLDCL:i64 G8RC:i64:$in, GPRC:i32:$sh, 0:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_63(N, PPC::RLDCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SDIV_i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::DIVW, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_SDIV_i64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::DIVD, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_65(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp3 = Transform_SHL32(Tmp1.getNode());
+ SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_SHL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Emits: (RLWINM:i32 GPRC:i32:$in, (imm:i32):$imm, 0:i32, (SHL32:i32 (imm:i32):$imm))
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_65(N, PPC::RLWINM, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (shl:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Emits: (SLW:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SLW, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_66(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_SHL64(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+}
+SDNode *Select_ISD_SHL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i64 G8RC:i64:$in, (imm:i32):$imm)
+ // Emits: (RLDICR:i64 G8RC:i64:$in, (imm:i32):$imm, (SHL64:i32 (imm:i32):$imm))
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_66(N, PPC::RLDICR, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (shl:i64 G8RC:i64:$rS, GPRC:i32:$rB)
+ // Emits: (SLD:i64 G8RC:i64:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SLD, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_3(N, PPC::VSLB, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_3(N, PPC::VSLH, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_3(N, PPC::VSLW, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_29(N, PPC::EXTSW_32_64, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_67(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+}
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i32 GPRC:i32:$rS, i8:Other)
+ // Emits: (EXTSB:i32 GPRC:i32:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_67(N, PPC::EXTSB, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i32 GPRC:i32:$rS, i16:Other)
+ // Emits: (EXTSH:i32 GPRC:i32:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_67(N, PPC::EXTSH, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i64 G8RC:i64:$rS, i8:Other)
+ // Emits: (EXTSB8:i64 G8RC:i64:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_67(N, PPC::EXTSB8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i64 G8RC:i64:$rS, i16:Other)
+ // Emits: (EXTSH8:i64 G8RC:i64:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_67(N, PPC::EXTSH8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i64 G8RC:i64:$rS, i32:Other)
+ // Emits: (EXTSW:i64 G8RC:i64:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_67(N, PPC::EXTSW, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i32 GPRC:i32:$rS, (imm:i32):$SH)
+ // Emits: (SRAWI:i32 GPRC:i32:$rS, (imm:i32):$SH)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_0(N, PPC::SRAWI, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sra:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Emits: (SRAW:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRAW, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i64 G8RC:i64:$rS, (imm:i32):$SH)
+ // Emits: (SRADI:i64 G8RC:i64:$rS, (imm:i32):$SH)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_0(N, PPC::SRADI, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sra:i64 G8RC:i64:$rS, GPRC:i32:$rB)
+ // Emits: (SRAD:i64 G8RC:i64:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRAD, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_3(N, PPC::VSRAB, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_3(N, PPC::VSRAH, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_3(N, PPC::VSRAW, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_68(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_SRL32(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp1, Tmp3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_ISD_SRL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Emits: (RLWINM:i32 GPRC:i32:$in, (SRL32:i32 (imm:i32):$imm), (imm:i32):$imm, 31:i32)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_68(N, PPC::RLWINM, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (srl:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Emits: (SRW:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRW, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_69(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_SRL64(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2, Tmp1);
+}
+SDNode *Select_ISD_SRL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i64 G8RC:i64:$in, (imm:i32):$imm)
+ // Emits: (RLDICL:i64 G8RC:i64:$in, (SRL64:i32 (imm:i32):$imm), (imm:i32):$imm)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_69(N, PPC::RLDICL, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (srl:i64 G8RC:i64:$rS, GPRC:i32:$rB)
+ // Emits: (SRD:i64 G8RC:i64:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRD, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_3(N, PPC::VSRB, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_3(N, PPC::VSRH, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_3(N, PPC::VSRW, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_70(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_STORE(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (STB:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_70(N, PPC::STB, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (STH:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_70(N, PPC::STH, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+
+ // Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STW:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_70(N, PPC::STW, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid F4RC:f32:$rS, iaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STFS:isVoid F4RC:f32:$rS, iaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_70(N, PPC::STFS, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid F8RC:f64:$rS, iaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STFD:isVoid F8RC:f64:$rS, iaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_70(N, PPC::STFD, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (STBX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_70(N, PPC::STBX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (STHX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_70(N, PPC::STHX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+
+ // Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STWX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_70(N, PPC::STWX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid F4RC:f32:$frS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STFSX:isVoid F4RC:f32:$frS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_70(N, PPC::STFSX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid F8RC:f64:$frS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STFDX:isVoid F8RC:f64:$frS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_70(N, PPC::STFDX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (STB8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STB8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (STH8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STH8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>
+ // Emits: (STW8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STW8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
+ // Emits: (STBX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STBX8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (STHX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STHX8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>
+ // Emits: (STWX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (Predicate_truncstorei32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STWX8, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, ixaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STD:isVoid G8RC:i64:$rS, ixaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrImmShift(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STD, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STDX:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_70(N, PPC::STDX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (STVX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 13 cost = 1 size = 0
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_70(N, PPC::STVX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_71(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN3_0, N2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_itruncstore(N.getNode()) &&
+ Predicate_pre_truncst(N.getNode())) {
+
+ // Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
+ // Emits: (STBU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_truncsti8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, PPC::STBU, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
+ // Emits: (STHU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_truncsti16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, PPC::STHU, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_istore(N.getNode()) &&
+ Predicate_pre_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectAddrImmOffs(N, N3, CPTmpN3_0)) {
+
+ // Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (STWU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, PPC::STWU, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+
+ // Pattern: (ist:iPTR F4RC:f32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (STFSU:iPTR F4RC:f32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, PPC::STFSU, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+
+ // Pattern: (ist:iPTR F8RC:f64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (STFDU:iPTR F8RC:f64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, PPC::STFDU, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_itruncstore(N.getNode()) &&
+ Predicate_pre_truncst(N.getNode())) {
+
+ // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
+ // Emits: (STBU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_truncsti8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, PPC::STBU8, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
+ // Emits: (STHU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (Predicate_pre_truncsti16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, PPC::STHU8, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_istore(N.getNode()) &&
+ Predicate_pre_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue CPTmpN3_0;
+ if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
+ N1.getValueType() == MVT::i64) {
+
+ // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (STWU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_71(N, PPC::STWU8, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+
+ // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
+ // Emits: (STDU:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
+ // Pattern complexity = 10 cost = 1 size = 0
+ SDNode *Result = Emit_71(N, PPC::STDU, MVT::iPTR, CPTmpN3_0);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_72(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N0);
+}
+DISABLE_INLINE SDNode *Emit_73(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp1);
+}
+SDNode *Select_ISD_SUB_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i32 0:i32, GPRC:i32:$rA)
+ // Emits: (NEG:i32 GPRC:i32:$rA)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_53(N, PPC::NEG, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:i32 (imm:i32)<<P:Predicate_immSExt16>>:$imm, GPRC:i32:$in)
+ // Emits: (SUBFIC:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_immSExt16(N0.getNode())) {
+ SDNode *Result = Emit_73(N, PPC::SUBFIC, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 GPRC:i32:$rB, GPRC:i32:$rA)
+ // Emits: (SUBF:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_72(N, PPC::SUBF, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_i64(const SDValue &N) {
+
+ // Pattern: (sub:i64 0:i64, G8RC:i64:$rA)
+ // Emits: (NEG8:i64 G8RC:i64:$rA)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_53(N, PPC::NEG8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:i64 G8RC:i64:$rB, G8RC:i64:$rA)
+ // Emits: (SUBF8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_72(N, PPC::SUBF8, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VSUBUBM, MVT::v16i8);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VSUBUHM, MVT::v8i16);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::VSUBUWM, MVT::v4i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_74(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_75(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, N0);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
+
+ // Pattern: (subc:i32 (imm:i32)<<P:Predicate_immSExt16>>:$imm, GPRC:i32:$rA)
+ // Emits: (SUBFIC:i32 GPRC:i32:$rA, (imm:i32):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_immSExt16(N0.getNode())) {
+ SDNode *Result = Emit_74(N, PPC::SUBFIC, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 GPRC:i32:$rB, GPRC:i32:$rA)
+ // Emits: (SUBFC:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_75(N, PPC::SUBFC, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i64);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
+
+ // Pattern: (subc:i64 (imm:i64)<<P:Predicate_immSExt16>>:$imm, G8RC:i64:$rA)
+ // Emits: (SUBFIC8:i64 G8RC:i64:$rA, (imm:i64):$imm)
+ // Pattern complexity = 7 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_immSExt16(N0.getNode())) {
+ SDNode *Result = Emit_76(N, PPC::SUBFIC8, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i64 G8RC:i64:$rB, G8RC:i64:$rA)
+ // Emits: (SUBFC8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_75(N, PPC::SUBFC8, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, N0, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_78(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sube:i32 0:i32, GPRC:i32:$rA)
+ // Emits: (SUBFZE:i32 GPRC:i32:$rA)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_78(N, PPC::SUBFZE, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sube:i32 (imm:i32)<<P:Predicate_immAllOnes>>, GPRC:i32:$rA)
+ // Emits: (SUBFME:i32 GPRC:i32:$rA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N0.getNode())) {
+ SDNode *Result = Emit_78(N, PPC::SUBFME, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GPRC:i32:$rB, GPRC:i32:$rA)
+ // Emits: (SUBFE:i32 GPRC:i32:$rA, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_77(N, PPC::SUBFE, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sube:i64 0:i64, G8RC:i64:$rA)
+ // Emits: (SUBFZE8:i64 G8RC:i64:$rA)
+ // Pattern complexity = 8 cost = 1 size = 0
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_78(N, PPC::SUBFZE8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sube:i64 (imm:i64)<<P:Predicate_immAllOnes>>, G8RC:i64:$rA)
+ // Emits: (SUBFME8:i64 G8RC:i64:$rA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N0.getNode())) {
+ SDNode *Result = Emit_78(N, PPC::SUBFME8, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i64 G8RC:i64:$rB, G8RC:i64:$rA)
+ // Emits: (SUBFE8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_77(N, PPC::SUBFE8, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_79(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+SDNode *Select_ISD_TRAP(const SDValue &N) {
+ SDNode *Result = Emit_79(N, PPC::TRAP);
+ return Result;
+}
+
+SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_18(N, PPC::OR8To4, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_UDIV_i32(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::DIVWU, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_UDIV_i64(const SDValue &N) {
+ SDNode *Result = Emit_3(N, PPC::DIVDU, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = Transform_VSLDOI_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = Transform_VSPLTB_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, N0);
+}
+DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = Transform_VSPLTH_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, N0);
+}
+DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = Transform_VSPLTW_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, N0);
+}
+DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = Transform_VSLDOI_unary_get_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vspltb_shuffle>><<X:VSPLTB_get_imm>>:$UIMM
+ // Emits: (VSPLTB:v16i8 (VSPLTB_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vspltb_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_81(N, PPC::VSPLTB, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vsplth_shuffle>><<X:VSPLTH_get_imm>>:$UIMM
+ // Emits: (VSPLTH:v16i8 (VSPLTH_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vsplth_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_82(N, PPC::VSPLTH, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vspltw_shuffle>><<X:VSPLTW_get_imm>>:$UIMM
+ // Emits: (VSPLTW:v16i8 (VSPLTW_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vspltw_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_83(N, PPC::VSPLTW, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vsldoi_unary_shuffle>><<X:VSLDOI_unary_get_imm>>:$in
+ // Emits: (VSLDOI:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA, (VSLDOI_unary_get_imm:i32 VRRC:i32:$in))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vsldoi_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_84(N, PPC::VSLDOI, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vpkuwum_unary_shuffle>>
+ // Emits: (VPKUWUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vpkuwum_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VPKUWUM, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vpkuhum_unary_shuffle>>
+ // Emits: (VPKUHUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vpkuhum_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VPKUHUM, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglb_unary_shuffle>>
+ // Emits: (VMRGLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vmrglb_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VMRGLB, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglh_unary_shuffle>>
+ // Emits: (VMRGLH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vmrglh_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VMRGLH, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglw_unary_shuffle>>
+ // Emits: (VMRGLW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vmrglw_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VMRGLW, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghb_unary_shuffle>>
+ // Emits: (VMRGHB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vmrghb_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VMRGHB, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghh_unary_shuffle>>
+ // Emits: (VMRGHH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vmrghh_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VMRGHH, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghw_unary_shuffle>>
+ // Emits: (VMRGHW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_vmrghw_unary_shuffle(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_85(N, PPC::VMRGHW, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vsldoi_shuffle>><<X:VSLDOI_get_imm>>:$SH
+ // Emits: (VSLDOI:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, (VSLDOI_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB):$SH))
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vsldoi_shuffle(N.getNode())) {
+ SDNode *Result = Emit_80(N, PPC::VSLDOI, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghb_shuffle>>
+ // Emits: (VMRGHB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vmrghb_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VMRGHB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghh_shuffle>>
+ // Emits: (VMRGHH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vmrghh_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VMRGHH, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghw_shuffle>>
+ // Emits: (VMRGHW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vmrghw_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VMRGHW, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglb_shuffle>>
+ // Emits: (VMRGLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vmrglb_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VMRGLB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglh_shuffle>>
+ // Emits: (VMRGLH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vmrglh_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VMRGLH, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglw_shuffle>>
+ // Emits: (VMRGLW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vmrglw_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VMRGLW, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vpkuhum_shuffle>>
+ // Emits: (VPKUHUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vpkuhum_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VPKUHUM, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vpkuwum_shuffle>>
+ // Emits: (VPKUWUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_vpkuwum_shuffle(N.getNode())) {
+ SDNode *Result = Emit_3(N, PPC::VPKUWUM, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N01);
+}
+DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N1);
+}
+DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N0);
+}
+SDNode *Select_ISD_XOR_i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i32 (and:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (NAND:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::NAND, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 (or:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::NOR, MVT::i32);
+ return Result;
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (xor:i32 (xor:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::EQV, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 (xor:i32 GPRC:i32:$rS, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rB)
+ // Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_87(N, PPC::EQV, MVT::i32);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (xor:i32 GPRC:i32:$rB, (xor:i32 GPRC:i32:$rS, (imm:i32)<<P:Predicate_immAllOnes>>))
+ // Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_88(N, PPC::EQV, MVT::i32);
+ return Result;
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
+ // Emits: (XORI:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immZExt16(N1.getNode())) {
+ SDNode *Result = Emit_13(N, PPC::XORI, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
+ // Emits: (XORIS:i32 GPRC:i32:$src1, (HI16:i32 (imm:i32):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedZExt(N1.getNode())) {
+ SDNode *Result = Emit_1(N, PPC::XORIS, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GPRC:i32:$in, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOR:i32 GPRC:i32:$in, GPRC:i32:$in)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_85(N, PPC::NOR, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GPRC:i32:$in, (imm:i32):$imm)
+ // Emits: (XORIS:i32 (XORI:i32 GPRC:i32:$in, (LO16:i32 (imm:i32):$imm)), (HI16:i32 (imm:i32):$imm))
+ // Pattern complexity = 6 cost = 2 size = 0
+ SDNode *Result = Emit_60(N, PPC::XORI, PPC::XORIS, MVT::i32, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Emits: (XOR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::XOR, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_XOR_i64(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i64 (and:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
+ // Emits: (NAND8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::NAND8, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i64 (or:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::NOR8, MVT::i64);
+ return Result;
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (xor:i64 (xor:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
+ // Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::EQV8, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i64 (xor:i64 G8RC:i64:$rS, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rB)
+ // Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N01.getNode())) {
+ SDNode *Result = Emit_87(N, PPC::EQV8, MVT::i64);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (xor:i64 G8RC:i64:$rB, (xor:i64 G8RC:i64:$rS, (imm:i64)<<P:Predicate_immAllOnes>>))
+ // Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDNode *Result = Emit_88(N, PPC::EQV8, MVT::i64);
+ return Result;
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
+ // Emits: (XORI8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_immZExt16(N1.getNode())) {
+ SDNode *Result = Emit_15(N, PPC::XORI8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (xor:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
+ // Emits: (XORIS8:i64 G8RC:i64:$src1, (HI16:i32 (imm:i64):$src2))
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (Predicate_imm16ShiftedZExt(N1.getNode())) {
+ SDNode *Result = Emit_7(N, PPC::XORIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (xor:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Emits: (XOR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::XOR8, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N11);
+}
+DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N1);
+}
+SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (xor:v4i32 (or:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB), (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
+ // Emits: (VNOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (xor:v4i32 (or:v4i32 VRRC:v4i32:$A, VRRC:v4i32:$B), (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
+ // Emits: (VNOR:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N1.getNode())) {
+ SDNode *Result = Emit_86(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, (or:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB))
+ // Emits: (VNOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDNode *Result = Emit_89(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, (or:v4i32 VRRC:v4i32:$A, VRRC:v4i32:$B))
+ // Emits: (VNOR:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
+ // Pattern complexity = 10 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR) {
+ SDNode *Result = Emit_89(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (xor:v4i32 VRRC:v4i32:$vA, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
+ // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N1.getNode())) {
+ SDNode *Result = Emit_85(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (xor:v4i32 VRRC:v4i32:$vA, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
+ // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N1.getNode())) {
+ SDNode *Result = Emit_85(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vA)
+ // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N0.getNode())) {
+ SDNode *Result = Emit_90(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$vA)
+ // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N0.getNode())) {
+ SDNode *Result = Emit_90(N, PPC::VNOR, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Emits: (VXOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_3(N, PPC::VXOR, MVT::v4i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, N0), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x20ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3, Tmp4);
+}
+SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_91(N, PPC::OR4To8, PPC::RLDICL, MVT::i64, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_PPCISD_BCTRL_Darwin(const SDValue &N) {
+
+ // Pattern: (PPCbctrl_Darwin:isVoid)
+ // Emits: (BCTRL_Darwin:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!PPCSubTarget.isPPC64())) {
+ SDNode *Result = Emit_92(N, PPC::BCTRL_Darwin, 0);
+ return Result;
+ }
+
+ // Pattern: (PPCbctrl_Darwin:isVoid)
+ // Emits: (BCTRL8_Darwin:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((PPCSubTarget.isPPC64())) {
+ SDNode *Result = Emit_92(N, PPC::BCTRL8_Darwin, 0);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_BCTRL_SVR4(const SDValue &N) {
+
+ // Pattern: (PPCbctrl_SVR4:isVoid)
+ // Emits: (BCTRL_SVR4:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!PPCSubTarget.isPPC64())) {
+ SDNode *Result = Emit_92(N, PPC::BCTRL_SVR4, 0);
+ return Result;
+ }
+
+ // Pattern: (PPCbctrl_SVR4:isVoid)
+ // Emits: (BCTRL8_ELF:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((PPCSubTarget.isPPC64())) {
+ SDNode *Result = Emit_92(N, PPC::BCTRL8_ELF, 0);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(Tmp0);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(Tmp0);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (PPCcall_Darwin:isVoid (imm:i32):$func)
+ // Emits: (BLA_Darwin:isVoid (imm:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_93(N, PPC::BLA_Darwin, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_Darwin:isVoid (imm:i64):$func)
+ // Emits: (BLA8_Darwin:isVoid (imm:i64):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_94(N, PPC::BLA8_Darwin, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (PPCcall_Darwin:isVoid (tglobaladdr:i64):$dst)
+ // Emits: (BL8_Darwin:isVoid (tglobaladdr:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_95(N, PPC::BL8_Darwin, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_Darwin:isVoid (texternalsym:i64):$dst)
+ // Emits: (BL8_Darwin:isVoid (texternalsym:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_95(N, PPC::BL8_Darwin, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_Darwin:isVoid (tglobaladdr:i32):$dst)
+ // Emits: (BL_Darwin:isVoid (tglobaladdr:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_95(N, PPC::BL_Darwin, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_Darwin:isVoid (texternalsym:i32):$dst)
+ // Emits: (BL_Darwin:isVoid (texternalsym:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_95(N, PPC::BL_Darwin, 1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (PPCcall_SVR4:isVoid (imm:i32):$func)
+ // Emits: (BLA_SVR4:isVoid (imm:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_93(N, PPC::BLA_SVR4, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_SVR4:isVoid (imm:i64):$func)
+ // Emits: (BLA8_ELF:isVoid (imm:i64):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_94(N, PPC::BLA8_ELF, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (PPCcall_SVR4:isVoid (tglobaladdr:i64):$dst)
+ // Emits: (BL8_ELF:isVoid (tglobaladdr:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_95(N, PPC::BL8_ELF, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_SVR4:isVoid (texternalsym:i64):$dst)
+ // Emits: (BL8_ELF:isVoid (texternalsym:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_95(N, PPC::BL8_ELF, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_SVR4:isVoid (tglobaladdr:i32):$dst)
+ // Emits: (BL_SVR4:isVoid (tglobaladdr:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_95(N, PPC::BL_SVR4, 1);
+ return Result;
+ }
+
+ // Pattern: (PPCcall_SVR4:isVoid (texternalsym:i32):$dst)
+ // Emits: (BL_SVR4:isVoid (texternalsym:iPTR):$dst)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_95(N, PPC::BL_SVR4, 1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+}
+SDNode *Select_PPCISD_DYNALLOC_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_96(N, PPC::DYNALLOC, MVT::i32, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_DYNALLOC_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i64 &&
+ N2.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_96(N, PPC::DYNALLOC8, MVT::i64, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_EXTSW_32_i32(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::EXTSW_32, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_PPCISD_FADDRTZ_f64(const SDValue &N) {
+ SDNode *Result = Emit_11(N, PPC::FADDrtz, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_PPCISD_FCFID_f64(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FCFID, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_PPCISD_FCTIDZ_f64(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FCTIDZ, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_PPCISD_FCTIWZ_f64(const SDValue &N) {
+ SDNode *Result = Emit_29(N, PPC::FCTIWZ, MVT::f64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, N2);
+}
+SDNode *Select_PPCISD_FSEL_f32(const SDValue &N) {
+ SDNode *Result = Emit_97(N, PPC::FSELS, MVT::f32);
+ return Result;
+}
+
+SDNode *Select_PPCISD_FSEL_f64(const SDValue &N) {
+ SDNode *Result = Emit_97(N, PPC::FSELD, MVT::f64);
+ return Result;
+}
+
+SDNode *Select_PPCISD_Hi_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (PPChi:i32 (tglobaladdr:i32):$in, 0:i32)
+ // Emits: (LIS:i32 (tglobaladdr:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPChi:i32 (tconstpool:i32):$in, 0:i32)
+ // Emits: (LIS:i32 (tconstpool:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPChi:i32 (tjumptable:i32):$in, 0:i32)
+ // Emits: (LIS:i32 (tjumptable:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPChi:i32 (tblockaddress:i32):$in, 0:i32)
+ // Emits: (LIS:i32 (tblockaddress:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_Hi_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (PPChi:i64 (tglobaladdr:i64):$in, 0:i64)
+ // Emits: (LIS8:i64 (tglobaladdr:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPChi:i64 (tconstpool:i64):$in, 0:i64)
+ // Emits: (LIS8:i64 (tconstpool:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPChi:i64 (tjumptable:i64):$in, 0:i64)
+ // Emits: (LIS8:i64 (tjumptable:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPChi:i64 (tblockaddress:i64):$in, 0:i64)
+ // Emits: (LIS8:i64 (tblockaddress:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
+}
+SDNode *Select_PPCISD_LARX_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_98(N, PPC::LWARX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_LARX_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDNode *Result = Emit_98(N, PPC::LDARX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
+}
+SDNode *Select_PPCISD_LBRX_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (PPClbrx:i32 xoaddr:iPTR:$src, i16:Other)
+ // Emits: (LHBRX:i32 xoaddr:iPTR:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_99(N, PPC::LHBRX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+
+ // Pattern: (PPClbrx:i32 xoaddr:iPTR:$src, i32:Other)
+ // Emits: (LWBRX:i32 xoaddr:iPTR:$src)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_99(N, PPC::LWBRX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (PPClo:i32 (tglobaladdr:i32):$in, 0:i32)
+ // Emits: (LI:i32 (tglobaladdr:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPClo:i32 (tconstpool:i32):$in, 0:i32)
+ // Emits: (LI:i32 (tconstpool:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPClo:i32 (tjumptable:i32):$in, 0:i32)
+ // Emits: (LI:i32 (tjumptable:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPClo:i32 (tblockaddress:i32):$in, 0:i32)
+ // Emits: (LI:i32 (tblockaddress:i32):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (PPClo:i64 (tglobaladdr:i64):$in, 0:i64)
+ // Emits: (LI8:i64 (tglobaladdr:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPClo:i64 (tconstpool:i64):$in, 0:i64)
+ // Emits: (LI8:i64 (tconstpool:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPClo:i64 (tjumptable:i64):$in, 0:i64)
+ // Emits: (LI8:i64 (tjumptable:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPClo:i64 (tblockaddress:i64):$in, 0:i64)
+ // Emits: (LI8:i64 (tblockaddress:i64):$in)
+ // Pattern complexity = 11 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_PPCISD_MFFS_f64(const SDValue &N) {
+ SDNode *Result = Emit_100(N, PPC::MFFS, MVT::f64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { N1, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 3 : 2);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_PPCISD_MTCTR(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (PPCmtctr:isVoid GPRC:i32:$rS)
+ // Emits: (MTCTR:isVoid GPRC:i32:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_101(N, PPC::MTCTR);
+ return Result;
+ }
+
+ // Pattern: (PPCmtctr:isVoid G8RC:i64:$rS)
+ // Emits: (MTCTR8:isVoid G8RC:i64:$rS)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_101(N, PPC::MTCTR8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue InFlag = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Tmp0, InFlag);
+ InFlag = SDValue(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+SDNode *Select_PPCISD_MTFSB0(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_102(N, PPC::MTFSB0);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_MTFSB1(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_102(N, PPC::MTFSB1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
+ SDValue InFlag = N.getOperand(3);
+ SDValue Ops0[] = { Tmp0, N1, N2, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_PPCISD_MTFSF_f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_103(N, PPC::MTFSF, MVT::f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
+ SDValue InFlag = N.getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, InFlag);
+ InFlag = SDValue(ResNode, 0);
+ ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ return ResNode;
+}
+SDNode *Select_PPCISD_NOP(const SDValue &N) {
+ SDNode *Result = Emit_104(N, PPC::NOP);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue Tmp0 = CurDAG->getTargetConstant(0x14ULL, MVT::i32);
+ SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
+}
+SDNode *Select_PPCISD_RET_FLAG(const SDValue &N) {
+ SDNode *Result = Emit_105(N, PPC::BLR);
+ return Result;
+}
+
+SDNode *Select_PPCISD_SHL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SLW, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_SHL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SLD, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_SRA_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRAW, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_SRA_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRAD, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_SRL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRW, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_SRL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_3(N, PPC::SRD, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+}
+SDNode *Select_PPCISD_STBRX(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDValue N3 = N.getOperand(3);
+
+ // Pattern: (PPCstbrx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst, i16:Other)
+ // Emits: (STHBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (cast<VTSDNode>(N3)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_106(N, PPC::STHBRX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (PPCstbrx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst, i32:Other)
+ // Emits: (STWBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (cast<VTSDNode>(N3)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_106(N, PPC::STWBRX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+}
+SDNode *Select_PPCISD_STCX(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+
+ // Pattern: (PPCstcx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STWCX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_107(N, PPC::STWCX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (PPCstcx:isVoid G8RC:i64:$rS, xoaddr:iPTR:$dst)
+ // Emits: (STDCX:isVoid G8RC:i64:$rS, xoaddr:iPTR:$dst)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_107(N, PPC::STDCX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_STD_32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+
+ // Pattern: (PPCstd_32:isVoid GPRC:i32:$rT, ixaddr:iPTR:$dst)
+ // Emits: (STD_32:isVoid GPRC:i32:$rT, ixaddr:iPTR:$dst)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (SelectAddrImmShift(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_107(N, PPC::STD_32, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ // Pattern: (PPCstd_32:isVoid GPRC:i32:$rT, xaddr:iPTR:$dst)
+ // Emits: (STDX_32:isVoid GPRC:i32:$rT, xaddr:iPTR:$dst)
+ // Pattern complexity = 12 cost = 1 size = 0
+ if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_107(N, PPC::STDX_32, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_STFIWX(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
+ SDNode *Result = Emit_107(N, PPC::STFIWX, CPTmpN2_0, CPTmpN2_1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(Tmp0);
+ Ops0.push_back(Tmp1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(Tmp0);
+ Ops0.push_back(Tmp1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ Ops0.push_back(Tmp1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+
+ // Pattern: (PPCtc_return:isVoid (imm:i32):$func, (imm:i32):$offset)
+ // Emits: (TCRETURNai:isVoid (imm:i32):$func, (imm:i32):$offset)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_108(N, PPC::TCRETURNai, 2);
+ return Result;
+ }
+
+ // Pattern: (PPCtc_return:isVoid (imm:i64):$func, (imm:i32):$offset)
+ // Emits: (TCRETURNai8:isVoid (imm:i64):$func, (imm:i32):$offset)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_109(N, PPC::TCRETURNai8, 2);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (PPCtc_return:isVoid (tglobaladdr:i64):$dst, (imm:i32):$imm)
+ // Emits: (TCRETURNdi8:isVoid (tglobaladdr:iPTR):$dst, (imm:i32):$imm)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_110(N, PPC::TCRETURNdi8, 2);
+ return Result;
+ }
+ }
+
+ // Pattern: (PPCtc_return:isVoid (texternalsym:i64):$dst, (imm:i32):$imm)
+ // Emits: (TCRETURNdi8:isVoid (texternalsym:iPTR):$dst, (imm:i32):$imm)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_110(N, PPC::TCRETURNdi8, 2);
+ return Result;
+ }
+ }
+
+ // Pattern: (PPCtc_return:isVoid (tglobaladdr:i32):$dst, (imm:i32):$imm)
+ // Emits: (TCRETURNdi:isVoid (tglobaladdr:iPTR):$dst, (imm:i32):$imm)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_110(N, PPC::TCRETURNdi, 2);
+ return Result;
+ }
+ }
+
+ // Pattern: (PPCtc_return:isVoid (texternalsym:i32):$dst, (imm:i32):$imm)
+ // Emits: (TCRETURNdi:isVoid (texternalsym:iPTR):$dst, (imm:i32):$imm)
+ // Pattern complexity = 9 cost = 1 size = 0
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_110(N, PPC::TCRETURNdi, 2);
+ return Result;
+ }
+ }
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+
+ // Pattern: (PPCtc_return:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
+ // Emits: (TCRETURNri8:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_110(N, PPC::TCRETURNri8, 2);
+ return Result;
+ }
+
+ // Pattern: (PPCtc_return:isVoid CTRRC:i32:$dst, (imm:i32):$imm)
+ // Emits: (TCRETURNri:isVoid CTRRC:i32:$dst, (imm:i32):$imm)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_110(N, PPC::TCRETURNri, 2);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_TOC_ENTRY_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_3(N, PPC::LDtoc, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1);
+}
+SDNode *Select_PPCISD_VCMP_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 6:i32)
+ // Emits: (VCMPEQUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPEQUB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 774:i32)
+ // Emits: (VCMPGTSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(774)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTSB, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 518:i32)
+ // Emits: (VCMPGTUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(518)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTUB, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VCMP_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 70:i32)
+ // Emits: (VCMPEQUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(70)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPEQUH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 838:i32)
+ // Emits: (VCMPGTSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(838)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTSH, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 582:i32)
+ // Emits: (VCMPGTUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(582)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTUH, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VCMP_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 134:i32)
+ // Emits: (VCMPEQUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(134)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPEQUW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 902:i32)
+ // Emits: (VCMPGTSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(902)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTSW, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 646:i32)
+ // Emits: (VCMPGTUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(646)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTUW, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 966:i32)
+ // Emits: (VCMPBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(966)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPBFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 198:i32)
+ // Emits: (VCMPEQFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(198)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPEQFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 454:i32)
+ // Emits: (VCMPGEFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(454)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGEFP, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 710:i32)
+ // Emits: (VCMPGTFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(710)) {
+ SDNode *Result = Emit_111(N, PPC::VCMPGTFP, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_PPCISD_VCMPo_v16i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp_o:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 6:i32)
+ // Emits: (VCMPEQUBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPEQUBo, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 774:i32)
+ // Emits: (VCMPGTSBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(774)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTSBo, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 518:i32)
+ // Emits: (VCMPGTUBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(518)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTUBo, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VCMPo_v8i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp_o:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 70:i32)
+ // Emits: (VCMPEQUHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(70)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPEQUHo, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 838:i32)
+ // Emits: (VCMPGTSHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(838)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTSHo, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 582:i32)
+ // Emits: (VCMPGTUHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(582)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTUHo, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VCMPo_v4i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp_o:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 134:i32)
+ // Emits: (VCMPEQUWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(134)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPEQUWo, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 902:i32)
+ // Emits: (VCMPGTSWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(902)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTSWo, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 646:i32)
+ // Emits: (VCMPGTUWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(646)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTUWo, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 966:i32)
+ // Emits: (VCMPBFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(966)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPBFPo, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 198:i32)
+ // Emits: (VCMPEQFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(198)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPEQFPo, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 454:i32)
+ // Emits: (VCMPGEFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(454)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGEFPo, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 710:i32)
+ // Emits: (VCMPGTFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(710)) {
+ SDNode *Result = Emit_112(N, PPC::VCMPGTFPo, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_PPCISD_VMADDFP_v4f32(const SDValue &N) {
+ SDNode *Result = Emit_97(N, PPC::VMADDFP, MVT::v4f32);
+ return Result;
+}
+
+SDNode *Select_PPCISD_VNMSUBFP_v4f32(const SDValue &N) {
+ SDNode *Result = Emit_97(N, PPC::VNMSUBFP, MVT::v4f32);
+ return Result;
+}
+
+SDNode *Select_PPCISD_VPERM_v16i8(const SDValue &N) {
+ SDNode *Result = Emit_97(N, PPC::VPERM, MVT::v16i8);
+ return Result;
+}
+
+// The main instruction selector code.
+SDNode *SelectCode(SDValue N) {
+ MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
+ switch (N.getOpcode()) {
+ default:
+ assert(!N.isMachineOpcode() && "Node already selected!");
+ break;
+ case ISD::EntryToken: // These nodes remain the same.
+ case ISD::BasicBlock:
+ case ISD::Register:
+ case ISD::HANDLENODE:
+ case ISD::TargetConstant:
+ case ISD::TargetConstantFP:
+ case ISD::TargetConstantPool:
+ case ISD::TargetFrameIndex:
+ case ISD::TargetExternalSymbol:
+ case ISD::TargetBlockAddress:
+ case ISD::TargetJumpTable:
+ case ISD::TargetGlobalTLSAddress:
+ case ISD::TargetGlobalAddress:
+ case ISD::TokenFactor:
+ case ISD::CopyFromReg:
+ case ISD::CopyToReg: {
+ return NULL;
+ }
+ case ISD::AssertSext:
+ case ISD::AssertZext: {
+ ReplaceUses(N, N.getOperand(0));
+ return NULL;
+ }
+ case ISD::INLINEASM: return Select_INLINEASM(N);
+ case ISD::EH_LABEL: return Select_EH_LABEL(N);
+ case ISD::UNDEF: return Select_UNDEF(N);
+ case ISD::ADD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADD_i32(N);
+ case MVT::i64:
+ return Select_ISD_ADD_i64(N);
+ case MVT::v16i8:
+ return Select_ISD_ADD_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_ADD_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_ADD_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ADDC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADDC_i32(N);
+ case MVT::i64:
+ return Select_ISD_ADDC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ADDE: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADDE_i32(N);
+ case MVT::i64:
+ return Select_ISD_ADDE_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::AND: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_AND_i32(N);
+ case MVT::i64:
+ return Select_ISD_AND_i64(N);
+ case MVT::v4i32:
+ return Select_ISD_AND_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ANY_EXTEND: {
+ switch (NVT) {
+ case MVT::i64:
+ return Select_ISD_ANY_EXTEND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_CMP_SWAP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_CMP_SWAP_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_CMP_SWAP_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_ADD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_ADD_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_ADD_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_AND: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_AND_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_AND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_NAND: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_NAND_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_NAND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_OR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_OR_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_OR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_SUB: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_SUB_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_SUB_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_XOR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_XOR_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_XOR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_SWAP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ATOMIC_SWAP_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_SWAP_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BIT_CONVERT: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_ISD_BIT_CONVERT_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_BIT_CONVERT_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_BIT_CONVERT_v4i32(N);
+ case MVT::v4f32:
+ return Select_ISD_BIT_CONVERT_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BR: {
+ return Select_ISD_BR(N);
+ break;
+ }
+ case ISD::BUILD_VECTOR: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_ISD_BUILD_VECTOR_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_BUILD_VECTOR_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_BUILD_VECTOR_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::CALLSEQ_END: {
+ return Select_ISD_CALLSEQ_END(N);
+ break;
+ }
+ case ISD::CALLSEQ_START: {
+ return Select_ISD_CALLSEQ_START(N);
+ break;
+ }
+ case ISD::CTLZ: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_CTLZ_i32(N);
+ case MVT::i64:
+ return Select_ISD_CTLZ_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::Constant: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_Constant_i32(N);
+ case MVT::i64:
+ return Select_ISD_Constant_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FABS: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FABS_f32(N);
+ case MVT::f64:
+ return Select_ISD_FABS_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FADD: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FADD_f32(N);
+ case MVT::f64:
+ return Select_ISD_FADD_f64(N);
+ case MVT::v4f32:
+ return Select_ISD_FADD_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FDIV: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FDIV_f32(N);
+ case MVT::f64:
+ return Select_ISD_FDIV_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FMUL: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FMUL_f32(N);
+ case MVT::f64:
+ return Select_ISD_FMUL_f64(N);
+ case MVT::v4f32:
+ return Select_ISD_FMUL_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FNEG: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FNEG_f32(N);
+ case MVT::f64:
+ return Select_ISD_FNEG_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_EXTEND: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_ISD_FP_EXTEND_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_ROUND: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FP_ROUND_f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSQRT: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSQRT_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSQRT_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSUB: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSUB_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSUB_f64(N);
+ case MVT::v4f32:
+ return Select_ISD_FSUB_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INTRINSIC_VOID: {
+ return Select_ISD_INTRINSIC_VOID(N);
+ break;
+ }
+ case ISD::INTRINSIC_WO_CHAIN: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4i32(N);
+ case MVT::v4f32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INTRINSIC_W_CHAIN: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_ISD_INTRINSIC_W_CHAIN_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_INTRINSIC_W_CHAIN_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_INTRINSIC_W_CHAIN_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::LOAD: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_LOAD_i32(N);
+ case MVT::i64:
+ return Select_ISD_LOAD_i64(N);
+ case MVT::f32:
+ return Select_ISD_LOAD_f32(N);
+ case MVT::f64:
+ return Select_ISD_LOAD_f64(N);
+ case MVT::v4i32:
+ return Select_ISD_LOAD_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::MEMBARRIER: {
+ return Select_ISD_MEMBARRIER(N);
+ break;
+ }
+ case ISD::MUL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_MUL_i32(N);
+ case MVT::i64:
+ return Select_ISD_MUL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::MULHS: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_MULHS_i32(N);
+ case MVT::i64:
+ return Select_ISD_MULHS_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::MULHU: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_MULHU_i32(N);
+ case MVT::i64:
+ return Select_ISD_MULHU_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::OR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_OR_i32(N);
+ case MVT::i64:
+ return Select_ISD_OR_i64(N);
+ case MVT::v4i32:
+ return Select_ISD_OR_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ROTL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ROTL_i32(N);
+ case MVT::i64:
+ return Select_ISD_ROTL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SDIV: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SDIV_i32(N);
+ case MVT::i64:
+ return Select_ISD_SDIV_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SHL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SHL_i32(N);
+ case MVT::i64:
+ return Select_ISD_SHL_i64(N);
+ case MVT::v16i8:
+ return Select_ISD_SHL_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_SHL_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_SHL_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SIGN_EXTEND: {
+ switch (NVT) {
+ case MVT::i64:
+ return Select_ISD_SIGN_EXTEND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SIGN_EXTEND_INREG: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SIGN_EXTEND_INREG_i32(N);
+ case MVT::i64:
+ return Select_ISD_SIGN_EXTEND_INREG_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SRA: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SRA_i32(N);
+ case MVT::i64:
+ return Select_ISD_SRA_i64(N);
+ case MVT::v16i8:
+ return Select_ISD_SRA_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_SRA_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_SRA_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SRL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SRL_i32(N);
+ case MVT::i64:
+ return Select_ISD_SRL_i64(N);
+ case MVT::v16i8:
+ return Select_ISD_SRL_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_SRL_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_SRL_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::STORE: {
+ switch (NVT) {
+ default:
+ if (TLI.getPointerTy() == NVT)
+ return Select_ISD_STORE_iPTR(N);
+ return Select_ISD_STORE(N);
+ break;
+ }
+ break;
+ }
+ case ISD::SUB: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUB_i32(N);
+ case MVT::i64:
+ return Select_ISD_SUB_i64(N);
+ case MVT::v16i8:
+ return Select_ISD_SUB_v16i8(N);
+ case MVT::v8i16:
+ return Select_ISD_SUB_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_SUB_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SUBC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUBC_i32(N);
+ case MVT::i64:
+ return Select_ISD_SUBC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SUBE: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUBE_i32(N);
+ case MVT::i64:
+ return Select_ISD_SUBE_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::TRAP: {
+ return Select_ISD_TRAP(N);
+ break;
+ }
+ case ISD::TRUNCATE: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_TRUNCATE_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::UDIV: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_UDIV_i32(N);
+ case MVT::i64:
+ return Select_ISD_UDIV_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::VECTOR_SHUFFLE: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_ISD_VECTOR_SHUFFLE_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::XOR: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_XOR_i32(N);
+ case MVT::i64:
+ return Select_ISD_XOR_i64(N);
+ case MVT::v4i32:
+ return Select_ISD_XOR_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ZERO_EXTEND: {
+ switch (NVT) {
+ case MVT::i64:
+ return Select_ISD_ZERO_EXTEND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::BCTRL_Darwin: {
+ return Select_PPCISD_BCTRL_Darwin(N);
+ break;
+ }
+ case PPCISD::BCTRL_SVR4: {
+ return Select_PPCISD_BCTRL_SVR4(N);
+ break;
+ }
+ case PPCISD::CALL_Darwin: {
+ return Select_PPCISD_CALL_Darwin(N);
+ break;
+ }
+ case PPCISD::CALL_SVR4: {
+ return Select_PPCISD_CALL_SVR4(N);
+ break;
+ }
+ case PPCISD::DYNALLOC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_DYNALLOC_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_DYNALLOC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::EXTSW_32: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_EXTSW_32_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::FADDRTZ: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_PPCISD_FADDRTZ_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::FCFID: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_PPCISD_FCFID_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::FCTIDZ: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_PPCISD_FCTIDZ_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::FCTIWZ: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_PPCISD_FCTIWZ_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::FSEL: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_PPCISD_FSEL_f32(N);
+ case MVT::f64:
+ return Select_PPCISD_FSEL_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::Hi: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_Hi_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_Hi_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::LARX: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_LARX_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_LARX_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::LBRX: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_LBRX_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::Lo: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_Lo_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_Lo_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::MFFS: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_PPCISD_MFFS_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::MTCTR: {
+ return Select_PPCISD_MTCTR(N);
+ break;
+ }
+ case PPCISD::MTFSB0: {
+ return Select_PPCISD_MTFSB0(N);
+ break;
+ }
+ case PPCISD::MTFSB1: {
+ return Select_PPCISD_MTFSB1(N);
+ break;
+ }
+ case PPCISD::MTFSF: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_PPCISD_MTFSF_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::NOP: {
+ return Select_PPCISD_NOP(N);
+ break;
+ }
+ case PPCISD::RET_FLAG: {
+ return Select_PPCISD_RET_FLAG(N);
+ break;
+ }
+ case PPCISD::SHL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_SHL_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_SHL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::SRA: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_SRA_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_SRA_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::SRL: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_PPCISD_SRL_i32(N);
+ case MVT::i64:
+ return Select_PPCISD_SRL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::STBRX: {
+ return Select_PPCISD_STBRX(N);
+ break;
+ }
+ case PPCISD::STCX: {
+ return Select_PPCISD_STCX(N);
+ break;
+ }
+ case PPCISD::STD_32: {
+ return Select_PPCISD_STD_32(N);
+ break;
+ }
+ case PPCISD::STFIWX: {
+ return Select_PPCISD_STFIWX(N);
+ break;
+ }
+ case PPCISD::TC_RETURN: {
+ return Select_PPCISD_TC_RETURN(N);
+ break;
+ }
+ case PPCISD::TOC_ENTRY: {
+ switch (NVT) {
+ case MVT::i64:
+ return Select_PPCISD_TOC_ENTRY_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::VCMP: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_PPCISD_VCMP_v16i8(N);
+ case MVT::v8i16:
+ return Select_PPCISD_VCMP_v8i16(N);
+ case MVT::v4i32:
+ return Select_PPCISD_VCMP_v4i32(N);
+ case MVT::v4f32:
+ return Select_PPCISD_VCMP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::VCMPo: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_PPCISD_VCMPo_v16i8(N);
+ case MVT::v8i16:
+ return Select_PPCISD_VCMPo_v8i16(N);
+ case MVT::v4i32:
+ return Select_PPCISD_VCMPo_v4i32(N);
+ case MVT::v4f32:
+ return Select_PPCISD_VCMPo_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::VMADDFP: {
+ switch (NVT) {
+ case MVT::v4f32:
+ return Select_PPCISD_VMADDFP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::VNMSUBFP: {
+ switch (NVT) {
+ case MVT::v4f32:
+ return Select_PPCISD_VNMSUBFP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case PPCISD::VPERM: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_PPCISD_VPERM_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ } // end of big switch.
+
+ if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&
+ N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
+ N.getOpcode() != ISD::INTRINSIC_VOID) {
+ CannotYetSelect(N);
+ } else {
+ CannotYetSelectIntrinsic(N);
+ }
+ return NULL;
+}
+
diff --git a/libclamav/c++/PPCGenInstrInfo.inc b/libclamav/c++/PPCGenInstrInfo.inc
new file mode 100644
index 0000000..f608bff
--- /dev/null
+++ b/libclamav/c++/PPCGenInstrInfo.inc
@@ -0,0 +1,643 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Instruction Descriptors
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+static const TargetRegisterClass* Barriers1[] = { &PPC::CARRYRCRegClass, NULL };
+static const unsigned ImplicitList1[] = { PPC::CARRY, 0 };
+static const unsigned ImplicitList2[] = { PPC::R1, 0 };
+static const unsigned ImplicitList3[] = { PPC::CR0, 0 };
+static const unsigned ImplicitList4[] = { PPC::CTR, 0 };
+static const unsigned ImplicitList5[] = { PPC::CTR8, PPC::RM, 0 };
+static const TargetRegisterClass* Barriers2[] = { &PPC::CARRYRCRegClass, &PPC::CTRRC8RegClass, NULL };
+static const unsigned ImplicitList6[] = { PPC::X0, PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
+static const unsigned ImplicitList7[] = { PPC::CTR, PPC::RM, 0 };
+static const TargetRegisterClass* Barriers3[] = { &PPC::CARRYRCRegClass, &PPC::CTRRCRegClass, NULL };
+static const unsigned ImplicitList8[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CARRY, 0 };
+static const unsigned ImplicitList9[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CARRY, 0 };
+static const unsigned ImplicitList10[] = { PPC::RM, 0 };
+static const unsigned ImplicitList11[] = { PPC::LR, PPC::RM, 0 };
+static const unsigned ImplicitList12[] = { PPC::X1, 0 };
+static const unsigned ImplicitList13[] = { PPC::CTR8, 0 };
+static const unsigned ImplicitList14[] = { PPC::LR, 0 };
+static const unsigned ImplicitList15[] = { PPC::LR8, 0 };
+static const TargetRegisterClass* Barriers4[] = { &PPC::CTRRCRegClass, NULL };
+static const TargetRegisterClass* Barriers5[] = { &PPC::CTRRC8RegClass, NULL };
+static const unsigned ImplicitList16[] = { PPC::CR6, 0 };
+
+static const TargetOperandInfo OperandInfo2[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo3[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo4[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo5[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo6[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo7[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo8[] = { { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo9[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo10[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo11[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo12[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo13[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo14[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { PPC::CRRCRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo16[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo17[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo18[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo19[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo21[] = { { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, { PPC::CRBITRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo22[] = { { PPC::CRBITRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo23[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo25[] = { { 0, 0, 0 }, { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo26[] = { { 0, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo27[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo28[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo29[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo30[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo31[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo32[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo33[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo34[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo35[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo36[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo37[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo38[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo39[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo40[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo41[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo42[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo43[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo44[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo45[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo46[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo51[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo52[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo53[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo54[] = { { PPC::F4RCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { PPC::CRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { PPC::F8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { PPC::VRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { 0, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo65[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { PPC::F4RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { PPC::F8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { PPC::GPRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::CRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { PPC::G8RCRegClassID, 0, 0 }, { PPC::G8RCRegClassID, 0, 0 }, { PPC::GPRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::GPRCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo80[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::G8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo81[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F8RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo82[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { PPC::F4RCRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo83[] = { { PPC::CTRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { PPC::CTRRC8RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo88[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo89[] = { { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { PPC::VRRCRegClassID, 0, 0 }, { 0, 0, 0 }, };
+
+static const TargetInstrDesc PPCInsts[] = {
+ { 0, 0, 0, 52, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
+ { 1, 0, 0, 52, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM
+ { 2, 1, 0, 52, "DBG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #2 = DBG_LABEL
+ { 3, 1, 0, 52, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #3 = EH_LABEL
+ { 4, 1, 0, 52, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #4 = GC_LABEL
+ { 5, 0, 0, 52, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
+ { 6, 3, 1, 52, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #6 = EXTRACT_SUBREG
+ { 7, 4, 1, 52, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo41 }, // Inst #7 = INSERT_SUBREG
+ { 8, 1, 1, 52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #8 = IMPLICIT_DEF
+ { 9, 4, 1, 52, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #9 = SUBREG_TO_REG
+ { 10, 3, 1, 52, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #10 = COPY_TO_REGCLASS
+ { 11, 3, 1, 14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #11 = ADD4
+ { 12, 3, 1, 14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #12 = ADD8
+ { 13, 3, 1, 14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #13 = ADDC
+ { 14, 3, 1, 14, "ADDC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #14 = ADDC8
+ { 15, 3, 1, 14, "ADDE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #15 = ADDE
+ { 16, 3, 1, 14, "ADDE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #16 = ADDE8
+ { 17, 3, 1, 14, "ADDI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #17 = ADDI
+ { 18, 3, 1, 14, "ADDI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #18 = ADDI8
+ { 19, 3, 1, 14, "ADDIC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #19 = ADDIC
+ { 20, 3, 1, 14, "ADDIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #20 = ADDIC8
+ { 21, 3, 1, 14, "ADDICo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #21 = ADDICo
+ { 22, 3, 1, 14, "ADDIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #22 = ADDIS
+ { 23, 3, 1, 14, "ADDIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #23 = ADDIS8
+ { 24, 2, 1, 14, "ADDME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #24 = ADDME
+ { 25, 2, 1, 14, "ADDME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #25 = ADDME8
+ { 26, 2, 1, 14, "ADDZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADDZE
+ { 27, 2, 1, 14, "ADDZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #27 = ADDZE8
+ { 28, 1, 0, 52, "ADJCALLSTACKDOWN", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo8 }, // Inst #28 = ADJCALLSTACKDOWN
+ { 29, 2, 0, 52, "ADJCALLSTACKUP", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo9 }, // Inst #29 = ADJCALLSTACKUP
+ { 30, 3, 1, 14, "AND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #30 = AND
+ { 31, 3, 1, 14, "AND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #31 = AND8
+ { 32, 3, 1, 14, "ANDC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #32 = ANDC
+ { 33, 3, 1, 14, "ANDC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #33 = ANDC8
+ { 34, 3, 1, 14, "ANDISo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #34 = ANDISo
+ { 35, 3, 1, 14, "ANDISo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #35 = ANDISo8
+ { 36, 3, 1, 14, "ANDIo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #36 = ANDIo
+ { 37, 3, 1, 14, "ANDIo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #37 = ANDIo8
+ { 38, 5, 1, 52, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #38 = ATOMIC_CMP_SWAP_I16
+ { 39, 5, 1, 52, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #39 = ATOMIC_CMP_SWAP_I32
+ { 40, 5, 1, 52, "ATOMIC_CMP_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo11 }, // Inst #40 = ATOMIC_CMP_SWAP_I64
+ { 41, 5, 1, 52, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #41 = ATOMIC_CMP_SWAP_I8
+ { 42, 4, 1, 52, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #42 = ATOMIC_LOAD_ADD_I16
+ { 43, 4, 1, 52, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #43 = ATOMIC_LOAD_ADD_I32
+ { 44, 4, 1, 52, "ATOMIC_LOAD_ADD_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #44 = ATOMIC_LOAD_ADD_I64
+ { 45, 4, 1, 52, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #45 = ATOMIC_LOAD_ADD_I8
+ { 46, 4, 1, 52, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #46 = ATOMIC_LOAD_AND_I16
+ { 47, 4, 1, 52, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #47 = ATOMIC_LOAD_AND_I32
+ { 48, 4, 1, 52, "ATOMIC_LOAD_AND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #48 = ATOMIC_LOAD_AND_I64
+ { 49, 4, 1, 52, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #49 = ATOMIC_LOAD_AND_I8
+ { 50, 4, 1, 52, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #50 = ATOMIC_LOAD_NAND_I16
+ { 51, 4, 1, 52, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #51 = ATOMIC_LOAD_NAND_I32
+ { 52, 4, 1, 52, "ATOMIC_LOAD_NAND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #52 = ATOMIC_LOAD_NAND_I64
+ { 53, 4, 1, 52, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #53 = ATOMIC_LOAD_NAND_I8
+ { 54, 4, 1, 52, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #54 = ATOMIC_LOAD_OR_I16
+ { 55, 4, 1, 52, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #55 = ATOMIC_LOAD_OR_I32
+ { 56, 4, 1, 52, "ATOMIC_LOAD_OR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #56 = ATOMIC_LOAD_OR_I64
+ { 57, 4, 1, 52, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #57 = ATOMIC_LOAD_OR_I8
+ { 58, 4, 1, 52, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #58 = ATOMIC_LOAD_SUB_I16
+ { 59, 4, 1, 52, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #59 = ATOMIC_LOAD_SUB_I32
+ { 60, 4, 1, 52, "ATOMIC_LOAD_SUB_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #60 = ATOMIC_LOAD_SUB_I64
+ { 61, 4, 1, 52, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #61 = ATOMIC_LOAD_SUB_I8
+ { 62, 4, 1, 52, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #62 = ATOMIC_LOAD_XOR_I16
+ { 63, 4, 1, 52, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #63 = ATOMIC_LOAD_XOR_I32
+ { 64, 4, 1, 52, "ATOMIC_LOAD_XOR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #64 = ATOMIC_LOAD_XOR_I64
+ { 65, 4, 1, 52, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #65 = ATOMIC_LOAD_XOR_I8
+ { 66, 4, 1, 52, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #66 = ATOMIC_SWAP_I16
+ { 67, 4, 1, 52, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #67 = ATOMIC_SWAP_I32
+ { 68, 4, 1, 52, "ATOMIC_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #68 = ATOMIC_SWAP_I64
+ { 69, 4, 1, 52, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #69 = ATOMIC_SWAP_I8
+ { 70, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(7<<3), NULL, NULL, NULL, OperandInfo8 }, // Inst #70 = B
+ { 71, 3, 0, 0, "BCC", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, NULL, NULL, OperandInfo14 }, // Inst #71 = BCC
+ { 72, 0, 0, 0, "BCTR", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList4, NULL, NULL, 0 }, // Inst #72 = BCTR
+ { 73, 0, 0, 0, "BCTRL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #73 = BCTRL8_Darwin
+ { 74, 0, 0, 0, "BCTRL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #74 = BCTRL8_ELF
+ { 75, 0, 0, 0, "BCTRL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList8, Barriers3, 0 }, // Inst #75 = BCTRL_Darwin
+ { 76, 0, 0, 0, "BCTRL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList9, Barriers3, 0 }, // Inst #76 = BCTRL_SVR4
+ { 77, 1, 0, 0, "BL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #77 = BL8_Darwin
+ { 78, 1, 0, 0, "BL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #78 = BL8_ELF
+ { 79, 1, 0, 0, "BLA8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #79 = BLA8_Darwin
+ { 80, 1, 0, 0, "BLA8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #80 = BLA8_ELF
+ { 81, 1, 0, 0, "BLA_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #81 = BLA_Darwin
+ { 82, 1, 0, 0, "BLA_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #82 = BLA_SVR4
+ { 83, 2, 0, 0, "BLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(7<<3), ImplicitList11, NULL, NULL, OperandInfo15 }, // Inst #83 = BLR
+ { 84, 1, 0, 0, "BL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #84 = BL_Darwin
+ { 85, 1, 0, 0, "BL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #85 = BL_SVR4
+ { 86, 3, 1, 11, "CMPD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #86 = CMPD
+ { 87, 3, 1, 11, "CMPDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #87 = CMPDI
+ { 88, 3, 1, 11, "CMPLD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #88 = CMPLD
+ { 89, 3, 1, 11, "CMPLDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #89 = CMPLDI
+ { 90, 3, 1, 11, "CMPLW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #90 = CMPLW
+ { 91, 3, 1, 11, "CMPLWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #91 = CMPLWI
+ { 92, 3, 1, 11, "CMPW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #92 = CMPW
+ { 93, 3, 1, 11, "CMPWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #93 = CMPWI
+ { 94, 2, 1, 14, "CNTLZD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #94 = CNTLZD
+ { 95, 2, 1, 14, "CNTLZW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #95 = CNTLZW
+ { 96, 3, 1, 1, "CREQV", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #96 = CREQV
+ { 97, 3, 1, 1, "CROR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #97 = CROR
+ { 98, 1, 1, 1, "CRSET", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo22 }, // Inst #98 = CRSET
+ { 99, 2, 0, 30, "DCBA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #99 = DCBA
+ { 100, 2, 0, 30, "DCBF", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #100 = DCBF
+ { 101, 2, 0, 30, "DCBI", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #101 = DCBI
+ { 102, 2, 0, 30, "DCBST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #102 = DCBST
+ { 103, 2, 0, 30, "DCBT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #103 = DCBT
+ { 104, 2, 0, 30, "DCBTST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #104 = DCBTST
+ { 105, 2, 0, 30, "DCBZ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #105 = DCBZ
+ { 106, 2, 0, 30, "DCBZL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #106 = DCBZL
+ { 107, 3, 1, 12, "DIVD", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #107 = DIVD
+ { 108, 3, 1, 12, "DIVDU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #108 = DIVDU
+ { 109, 3, 1, 13, "DIVW", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #109 = DIVW
+ { 110, 3, 1, 13, "DIVWU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #110 = DIVWU
+ { 111, 4, 0, 33, "DSS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #111 = DSS
+ { 112, 4, 0, 33, "DSSALL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #112 = DSSALL
+ { 113, 4, 0, 33, "DST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #113 = DST
+ { 114, 4, 0, 33, "DST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #114 = DST64
+ { 115, 4, 0, 33, "DSTST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #115 = DSTST
+ { 116, 4, 0, 33, "DSTST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #116 = DSTST64
+ { 117, 4, 0, 33, "DSTSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #117 = DSTSTT
+ { 118, 4, 0, 33, "DSTSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #118 = DSTSTT64
+ { 119, 4, 0, 33, "DSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #119 = DSTT
+ { 120, 4, 0, 33, "DSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #120 = DSTT64
+ { 121, 4, 1, 52, "DYNALLOC", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo27 }, // Inst #121 = DYNALLOC
+ { 122, 4, 1, 52, "DYNALLOC8", 0, 0, ImplicitList12, ImplicitList12, NULL, OperandInfo28 }, // Inst #122 = DYNALLOC8
+ { 123, 3, 1, 14, "EQV", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #123 = EQV
+ { 124, 3, 1, 14, "EQV8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #124 = EQV8
+ { 125, 2, 1, 14, "EXTSB", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #125 = EXTSB
+ { 126, 2, 1, 14, "EXTSB8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #126 = EXTSB8
+ { 127, 2, 1, 14, "EXTSH", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #127 = EXTSH
+ { 128, 2, 1, 14, "EXTSH8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #128 = EXTSH8
+ { 129, 2, 1, 14, "EXTSW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #129 = EXTSW
+ { 130, 2, 1, 14, "EXTSW_32", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #130 = EXTSW_32
+ { 131, 2, 1, 14, "EXTSW_32_64", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo29 }, // Inst #131 = EXTSW_32_64
+ { 132, 2, 1, 8, "FABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #132 = FABSD
+ { 133, 2, 1, 8, "FABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #133 = FABSS
+ { 134, 3, 1, 8, "FADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #134 = FADD
+ { 135, 3, 1, 8, "FADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #135 = FADDS
+ { 136, 3, 1, 8, "FADDrtz", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #136 = FADDrtz
+ { 137, 2, 1, 8, "FCFID", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #137 = FCFID
+ { 138, 3, 1, 4, "FCMPUD", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo34 }, // Inst #138 = FCMPUD
+ { 139, 3, 1, 4, "FCMPUS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo35 }, // Inst #139 = FCMPUS
+ { 140, 2, 1, 8, "FCTIDZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #140 = FCTIDZ
+ { 141, 2, 1, 8, "FCTIWZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #141 = FCTIWZ
+ { 142, 3, 1, 5, "FDIV", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #142 = FDIV
+ { 143, 3, 1, 6, "FDIVS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #143 = FDIVS
+ { 144, 4, 1, 7, "FMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #144 = FMADD
+ { 145, 4, 1, 8, "FMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #145 = FMADDS
+ { 146, 2, 1, 8, "FMRD", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #146 = FMRD
+ { 147, 2, 1, 8, "FMRS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #147 = FMRS
+ { 148, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #148 = FMRSD
+ { 149, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #149 = FMSUB
+ { 150, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #150 = FMSUBS
+ { 151, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #151 = FMUL
+ { 152, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #152 = FMULS
+ { 153, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #153 = FNABSD
+ { 154, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #154 = FNABSS
+ { 155, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #155 = FNEGD
+ { 156, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #156 = FNEGS
+ { 157, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #157 = FNMADD
+ { 158, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #158 = FNMADDS
+ { 159, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #159 = FNMSUB
+ { 160, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #160 = FNMSUBS
+ { 161, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #161 = FRSP
+ { 162, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #162 = FSELD
+ { 163, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #163 = FSELS
+ { 164, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #164 = FSQRT
+ { 165, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #165 = FSQRTS
+ { 166, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #166 = FSUB
+ { 167, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #167 = FSUBS
+ { 168, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #168 = LA
+ { 169, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = LBZ
+ { 170, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = LBZ8
+ { 171, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #171 = LBZU
+ { 172, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #172 = LBZU8
+ { 173, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #173 = LBZX
+ { 174, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #174 = LBZX8
+ { 175, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #175 = LD
+ { 176, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #176 = LDARX
+ { 177, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #177 = LDU
+ { 178, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #178 = LDX
+ { 179, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDtoc
+ { 180, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LFD
+ { 181, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #181 = LFDU
+ { 182, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #182 = LFDX
+ { 183, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #183 = LFS
+ { 184, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #184 = LFSU
+ { 185, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #185 = LFSX
+ { 186, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #186 = LHA
+ { 187, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #187 = LHA8
+ { 188, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #188 = LHAU
+ { 189, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #189 = LHAU8
+ { 190, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #190 = LHAX
+ { 191, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #191 = LHAX8
+ { 192, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHBRX
+ { 193, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #193 = LHZ
+ { 194, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #194 = LHZ8
+ { 195, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #195 = LHZU
+ { 196, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #196 = LHZU8
+ { 197, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #197 = LHZX
+ { 198, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #198 = LHZX8
+ { 199, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #199 = LI
+ { 200, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #200 = LI8
+ { 201, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #201 = LIS
+ { 202, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #202 = LIS8
+ { 203, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #203 = LVEBX
+ { 204, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LVEHX
+ { 205, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #205 = LVEWX
+ { 206, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #206 = LVSL
+ { 207, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #207 = LVSR
+ { 208, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #208 = LVX
+ { 209, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #209 = LVXL
+ { 210, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #210 = LWA
+ { 211, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #211 = LWARX
+ { 212, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #212 = LWAX
+ { 213, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWBRX
+ { 214, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #214 = LWZ
+ { 215, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #215 = LWZ8
+ { 216, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #216 = LWZU
+ { 217, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #217 = LWZU8
+ { 218, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #218 = LWZX
+ { 219, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #219 = LWZX8
+ { 220, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #220 = MCRF
+ { 221, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #221 = MFCR
+ { 222, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo59 }, // Inst #222 = MFCTR
+ { 223, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCTR8
+ { 224, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #224 = MFFS
+ { 225, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo59 }, // Inst #225 = MFLR
+ { 226, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo60 }, // Inst #226 = MFLR8
+ { 227, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #227 = MFOCRF
+ { 228, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #228 = MFVRSAVE
+ { 229, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #229 = MFVSCR
+ { 230, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #230 = MTCRF
+ { 231, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo59 }, // Inst #231 = MTCTR
+ { 232, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo60 }, // Inst #232 = MTCTR8
+ { 233, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #233 = MTFSB0
+ { 234, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #234 = MTFSB1
+ { 235, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #235 = MTFSF
+ { 236, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo59 }, // Inst #236 = MTLR
+ { 237, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo60 }, // Inst #237 = MTLR8
+ { 238, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #238 = MTVRSAVE
+ { 239, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #239 = MTVSCR
+ { 240, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #240 = MULHD
+ { 241, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #241 = MULHDU
+ { 242, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #242 = MULHW
+ { 243, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #243 = MULHWU
+ { 244, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #244 = MULLD
+ { 245, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #245 = MULLI
+ { 246, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #246 = MULLW
+ { 247, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #247 = MovePCtoLR
+ { 248, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #248 = MovePCtoLR8
+ { 249, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #249 = NAND
+ { 250, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #250 = NAND8
+ { 251, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #251 = NEG
+ { 252, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #252 = NEG8
+ { 253, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #253 = NOP
+ { 254, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #254 = NOR
+ { 255, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #255 = NOR8
+ { 256, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = OR
+ { 257, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #257 = OR4To8
+ { 258, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #258 = OR8
+ { 259, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #259 = OR8To4
+ { 260, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #260 = ORC
+ { 261, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #261 = ORC8
+ { 262, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #262 = ORI
+ { 263, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #263 = ORI8
+ { 264, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORIS
+ { 265, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORIS8
+ { 266, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #266 = RLDCL
+ { 267, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #267 = RLDICL
+ { 268, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #268 = RLDICR
+ { 269, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #269 = RLDIMI
+ { 270, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #270 = RLWIMI
+ { 271, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #271 = RLWINM
+ { 272, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #272 = RLWINMo
+ { 273, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #273 = RLWNM
+ { 274, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #274 = SELECT_CC_F4
+ { 275, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #275 = SELECT_CC_F8
+ { 276, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #276 = SELECT_CC_I4
+ { 277, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #277 = SELECT_CC_I8
+ { 278, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #278 = SELECT_CC_VRRC
+ { 279, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #279 = SLD
+ { 280, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #280 = SLW
+ { 281, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #281 = SPILL_CR
+ { 282, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #282 = SRAD
+ { 283, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #283 = SRADI
+ { 284, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #284 = SRAW
+ { 285, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #285 = SRAWI
+ { 286, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #286 = SRD
+ { 287, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #287 = SRW
+ { 288, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #288 = STB
+ { 289, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #289 = STB8
+ { 290, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #290 = STBU
+ { 291, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #291 = STBU8
+ { 292, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #292 = STBX
+ { 293, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #293 = STBX8
+ { 294, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #294 = STD
+ { 295, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #295 = STDCX
+ { 296, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #296 = STDU
+ { 297, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #297 = STDUX
+ { 298, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #298 = STDX
+ { 299, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #299 = STDX_32
+ { 300, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #300 = STD_32
+ { 301, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #301 = STFD
+ { 302, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #302 = STFDU
+ { 303, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #303 = STFDX
+ { 304, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #304 = STFIWX
+ { 305, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFS
+ { 306, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #306 = STFSU
+ { 307, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #307 = STFSX
+ { 308, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #308 = STH
+ { 309, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #309 = STH8
+ { 310, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #310 = STHBRX
+ { 311, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #311 = STHU
+ { 312, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #312 = STHU8
+ { 313, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #313 = STHX
+ { 314, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #314 = STHX8
+ { 315, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #315 = STVEBX
+ { 316, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #316 = STVEHX
+ { 317, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #317 = STVEWX
+ { 318, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #318 = STVX
+ { 319, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #319 = STVXL
+ { 320, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #320 = STW
+ { 321, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #321 = STW8
+ { 322, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #322 = STWBRX
+ { 323, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #323 = STWCX
+ { 324, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #324 = STWU
+ { 325, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #325 = STWU8
+ { 326, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #326 = STWUX
+ { 327, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #327 = STWX
+ { 328, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #328 = STWX8
+ { 329, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #329 = SUBF
+ { 330, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #330 = SUBF8
+ { 331, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #331 = SUBFC
+ { 332, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #332 = SUBFC8
+ { 333, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #333 = SUBFE
+ { 334, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #334 = SUBFE8
+ { 335, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #335 = SUBFIC
+ { 336, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #336 = SUBFIC8
+ { 337, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #337 = SUBFME
+ { 338, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #338 = SUBFME8
+ { 339, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #339 = SUBFZE
+ { 340, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #340 = SUBFZE8
+ { 341, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #341 = SYNC
+ { 342, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #342 = TAILB
+ { 343, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #343 = TAILB8
+ { 344, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILBA
+ { 345, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILBA8
+ { 346, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #346 = TAILBCTR
+ { 347, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #347 = TAILBCTR8
+ { 348, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #348 = TCRETURNai
+ { 349, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #349 = TCRETURNai8
+ { 350, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNdi
+ { 351, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNdi8
+ { 352, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #352 = TCRETURNri
+ { 353, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #353 = TCRETURNri8
+ { 354, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #354 = TRAP
+ { 355, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #355 = UPDATE_VRSAVE
+ { 356, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #356 = VADDCUW
+ { 357, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #357 = VADDFP
+ { 358, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDSBS
+ { 359, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDSHS
+ { 360, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSWS
+ { 361, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDUBM
+ { 362, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDUBS
+ { 363, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUHM
+ { 364, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUHS
+ { 365, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUWM
+ { 366, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUWS
+ { 367, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VAND
+ { 368, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VANDC
+ { 369, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VAVGSB
+ { 370, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAVGSH
+ { 371, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSW
+ { 372, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGUB
+ { 373, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGUH
+ { 374, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUW
+ { 375, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #375 = VCFSX
+ { 376, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #376 = VCFUX
+ { 377, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #377 = VCMPBFP
+ { 378, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #378 = VCMPBFPo
+ { 379, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #379 = VCMPEQFP
+ { 380, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #380 = VCMPEQFPo
+ { 381, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #381 = VCMPEQUB
+ { 382, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #382 = VCMPEQUBo
+ { 383, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUH
+ { 384, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUHo
+ { 385, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUW
+ { 386, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUWo
+ { 387, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #387 = VCMPGEFP
+ { 388, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #388 = VCMPGEFPo
+ { 389, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #389 = VCMPGTFP
+ { 390, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #390 = VCMPGTFPo
+ { 391, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #391 = VCMPGTSB
+ { 392, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #392 = VCMPGTSBo
+ { 393, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSH
+ { 394, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSHo
+ { 395, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSW
+ { 396, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSWo
+ { 397, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #397 = VCMPGTUB
+ { 398, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #398 = VCMPGTUBo
+ { 399, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUH
+ { 400, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUHo
+ { 401, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUW
+ { 402, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUWo
+ { 403, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #403 = VCTSXS
+ { 404, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #404 = VCTUXS
+ { 405, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #405 = VEXPTEFP
+ { 406, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #406 = VLOGEFP
+ { 407, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #407 = VMADDFP
+ { 408, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #408 = VMAXFP
+ { 409, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #409 = VMAXSB
+ { 410, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXSH
+ { 411, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSW
+ { 412, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXUB
+ { 413, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXUH
+ { 414, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUW
+ { 415, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #415 = VMHADDSHS
+ { 416, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #416 = VMHRADDSHS
+ { 417, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #417 = VMINFP
+ { 418, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #418 = VMINSB
+ { 419, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINSH
+ { 420, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSW
+ { 421, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINUB
+ { 422, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINUH
+ { 423, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUW
+ { 424, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #424 = VMLADDUHM
+ { 425, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMRGHB
+ { 426, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMRGHH
+ { 427, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHW
+ { 428, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGLB
+ { 429, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGLH
+ { 430, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLW
+ { 431, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #431 = VMSUMMBM
+ { 432, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #432 = VMSUMSHM
+ { 433, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMSHS
+ { 434, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMUBM
+ { 435, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMUHM
+ { 436, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUHS
+ { 437, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #437 = VMULESB
+ { 438, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #438 = VMULESH
+ { 439, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULEUB
+ { 440, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULEUH
+ { 441, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULOSB
+ { 442, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULOSH
+ { 443, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOUB
+ { 444, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOUH
+ { 445, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #445 = VNMSUBFP
+ { 446, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VNOR
+ { 447, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VOR
+ { 448, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #448 = VPERM
+ { 449, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VPKPX
+ { 450, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VPKSHSS
+ { 451, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKSHUS
+ { 452, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSWSS
+ { 453, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSWUS
+ { 454, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKUHUM
+ { 455, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKUHUS
+ { 456, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUWUM
+ { 457, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUWUS
+ { 458, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #458 = VREFP
+ { 459, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #459 = VRFIM
+ { 460, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VRFIN
+ { 461, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIP
+ { 462, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIZ
+ { 463, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #463 = VRLB
+ { 464, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #464 = VRLH
+ { 465, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLW
+ { 466, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #466 = VRSQRTEFP
+ { 467, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #467 = VSEL
+ { 468, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #468 = VSL
+ { 469, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #469 = VSLB
+ { 470, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #470 = VSLDOI
+ { 471, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSLH
+ { 472, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLO
+ { 473, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLW
+ { 474, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #474 = VSPLTB
+ { 475, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #475 = VSPLTH
+ { 476, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #476 = VSPLTISB
+ { 477, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #477 = VSPLTISH
+ { 478, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISW
+ { 479, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #479 = VSPLTW
+ { 480, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #480 = VSR
+ { 481, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #481 = VSRAB
+ { 482, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSRAH
+ { 483, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAW
+ { 484, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRB
+ { 485, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRH
+ { 486, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRO
+ { 487, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRW
+ { 488, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSUBCUW
+ { 489, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSUBFP
+ { 490, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBSBS
+ { 491, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBSHS
+ { 492, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSWS
+ { 493, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBUBM
+ { 494, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBUBS
+ { 495, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUHM
+ { 496, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUHS
+ { 497, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUWM
+ { 498, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUWS
+ { 499, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUM2SWS
+ { 500, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUM4SBS
+ { 501, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM4SHS
+ { 502, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4UBS
+ { 503, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUMSWS
+ { 504, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #504 = VUPKHPX
+ { 505, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #505 = VUPKHSB
+ { 506, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHSH
+ { 507, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKLPX
+ { 508, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKLSB
+ { 509, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLSH
+ { 510, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #510 = VXOR
+ { 511, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #511 = V_SET0
+ { 512, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #512 = XOR
+ { 513, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #513 = XOR8
+ { 514, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #514 = XORI
+ { 515, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #515 = XORI8
+ { 516, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #516 = XORIS
+ { 517, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #517 = XORIS8
+};
+} // End llvm namespace
diff --git a/libclamav/c++/PPCGenInstrNames.inc b/libclamav/c++/PPCGenInstrNames.inc
new file mode 100644
index 0000000..7cc9414
--- /dev/null
+++ b/libclamav/c++/PPCGenInstrNames.inc
@@ -0,0 +1,534 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Instruction Enum Values
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace PPC {
+ enum {
+ PHI = 0,
+ INLINEASM = 1,
+ DBG_LABEL = 2,
+ EH_LABEL = 3,
+ GC_LABEL = 4,
+ KILL = 5,
+ EXTRACT_SUBREG = 6,
+ INSERT_SUBREG = 7,
+ IMPLICIT_DEF = 8,
+ SUBREG_TO_REG = 9,
+ COPY_TO_REGCLASS = 10,
+ ADD4 = 11,
+ ADD8 = 12,
+ ADDC = 13,
+ ADDC8 = 14,
+ ADDE = 15,
+ ADDE8 = 16,
+ ADDI = 17,
+ ADDI8 = 18,
+ ADDIC = 19,
+ ADDIC8 = 20,
+ ADDICo = 21,
+ ADDIS = 22,
+ ADDIS8 = 23,
+ ADDME = 24,
+ ADDME8 = 25,
+ ADDZE = 26,
+ ADDZE8 = 27,
+ ADJCALLSTACKDOWN = 28,
+ ADJCALLSTACKUP = 29,
+ AND = 30,
+ AND8 = 31,
+ ANDC = 32,
+ ANDC8 = 33,
+ ANDISo = 34,
+ ANDISo8 = 35,
+ ANDIo = 36,
+ ANDIo8 = 37,
+ ATOMIC_CMP_SWAP_I16 = 38,
+ ATOMIC_CMP_SWAP_I32 = 39,
+ ATOMIC_CMP_SWAP_I64 = 40,
+ ATOMIC_CMP_SWAP_I8 = 41,
+ ATOMIC_LOAD_ADD_I16 = 42,
+ ATOMIC_LOAD_ADD_I32 = 43,
+ ATOMIC_LOAD_ADD_I64 = 44,
+ ATOMIC_LOAD_ADD_I8 = 45,
+ ATOMIC_LOAD_AND_I16 = 46,
+ ATOMIC_LOAD_AND_I32 = 47,
+ ATOMIC_LOAD_AND_I64 = 48,
+ ATOMIC_LOAD_AND_I8 = 49,
+ ATOMIC_LOAD_NAND_I16 = 50,
+ ATOMIC_LOAD_NAND_I32 = 51,
+ ATOMIC_LOAD_NAND_I64 = 52,
+ ATOMIC_LOAD_NAND_I8 = 53,
+ ATOMIC_LOAD_OR_I16 = 54,
+ ATOMIC_LOAD_OR_I32 = 55,
+ ATOMIC_LOAD_OR_I64 = 56,
+ ATOMIC_LOAD_OR_I8 = 57,
+ ATOMIC_LOAD_SUB_I16 = 58,
+ ATOMIC_LOAD_SUB_I32 = 59,
+ ATOMIC_LOAD_SUB_I64 = 60,
+ ATOMIC_LOAD_SUB_I8 = 61,
+ ATOMIC_LOAD_XOR_I16 = 62,
+ ATOMIC_LOAD_XOR_I32 = 63,
+ ATOMIC_LOAD_XOR_I64 = 64,
+ ATOMIC_LOAD_XOR_I8 = 65,
+ ATOMIC_SWAP_I16 = 66,
+ ATOMIC_SWAP_I32 = 67,
+ ATOMIC_SWAP_I64 = 68,
+ ATOMIC_SWAP_I8 = 69,
+ B = 70,
+ BCC = 71,
+ BCTR = 72,
+ BCTRL8_Darwin = 73,
+ BCTRL8_ELF = 74,
+ BCTRL_Darwin = 75,
+ BCTRL_SVR4 = 76,
+ BL8_Darwin = 77,
+ BL8_ELF = 78,
+ BLA8_Darwin = 79,
+ BLA8_ELF = 80,
+ BLA_Darwin = 81,
+ BLA_SVR4 = 82,
+ BLR = 83,
+ BL_Darwin = 84,
+ BL_SVR4 = 85,
+ CMPD = 86,
+ CMPDI = 87,
+ CMPLD = 88,
+ CMPLDI = 89,
+ CMPLW = 90,
+ CMPLWI = 91,
+ CMPW = 92,
+ CMPWI = 93,
+ CNTLZD = 94,
+ CNTLZW = 95,
+ CREQV = 96,
+ CROR = 97,
+ CRSET = 98,
+ DCBA = 99,
+ DCBF = 100,
+ DCBI = 101,
+ DCBST = 102,
+ DCBT = 103,
+ DCBTST = 104,
+ DCBZ = 105,
+ DCBZL = 106,
+ DIVD = 107,
+ DIVDU = 108,
+ DIVW = 109,
+ DIVWU = 110,
+ DSS = 111,
+ DSSALL = 112,
+ DST = 113,
+ DST64 = 114,
+ DSTST = 115,
+ DSTST64 = 116,
+ DSTSTT = 117,
+ DSTSTT64 = 118,
+ DSTT = 119,
+ DSTT64 = 120,
+ DYNALLOC = 121,
+ DYNALLOC8 = 122,
+ EQV = 123,
+ EQV8 = 124,
+ EXTSB = 125,
+ EXTSB8 = 126,
+ EXTSH = 127,
+ EXTSH8 = 128,
+ EXTSW = 129,
+ EXTSW_32 = 130,
+ EXTSW_32_64 = 131,
+ FABSD = 132,
+ FABSS = 133,
+ FADD = 134,
+ FADDS = 135,
+ FADDrtz = 136,
+ FCFID = 137,
+ FCMPUD = 138,
+ FCMPUS = 139,
+ FCTIDZ = 140,
+ FCTIWZ = 141,
+ FDIV = 142,
+ FDIVS = 143,
+ FMADD = 144,
+ FMADDS = 145,
+ FMRD = 146,
+ FMRS = 147,
+ FMRSD = 148,
+ FMSUB = 149,
+ FMSUBS = 150,
+ FMUL = 151,
+ FMULS = 152,
+ FNABSD = 153,
+ FNABSS = 154,
+ FNEGD = 155,
+ FNEGS = 156,
+ FNMADD = 157,
+ FNMADDS = 158,
+ FNMSUB = 159,
+ FNMSUBS = 160,
+ FRSP = 161,
+ FSELD = 162,
+ FSELS = 163,
+ FSQRT = 164,
+ FSQRTS = 165,
+ FSUB = 166,
+ FSUBS = 167,
+ LA = 168,
+ LBZ = 169,
+ LBZ8 = 170,
+ LBZU = 171,
+ LBZU8 = 172,
+ LBZX = 173,
+ LBZX8 = 174,
+ LD = 175,
+ LDARX = 176,
+ LDU = 177,
+ LDX = 178,
+ LDtoc = 179,
+ LFD = 180,
+ LFDU = 181,
+ LFDX = 182,
+ LFS = 183,
+ LFSU = 184,
+ LFSX = 185,
+ LHA = 186,
+ LHA8 = 187,
+ LHAU = 188,
+ LHAU8 = 189,
+ LHAX = 190,
+ LHAX8 = 191,
+ LHBRX = 192,
+ LHZ = 193,
+ LHZ8 = 194,
+ LHZU = 195,
+ LHZU8 = 196,
+ LHZX = 197,
+ LHZX8 = 198,
+ LI = 199,
+ LI8 = 200,
+ LIS = 201,
+ LIS8 = 202,
+ LVEBX = 203,
+ LVEHX = 204,
+ LVEWX = 205,
+ LVSL = 206,
+ LVSR = 207,
+ LVX = 208,
+ LVXL = 209,
+ LWA = 210,
+ LWARX = 211,
+ LWAX = 212,
+ LWBRX = 213,
+ LWZ = 214,
+ LWZ8 = 215,
+ LWZU = 216,
+ LWZU8 = 217,
+ LWZX = 218,
+ LWZX8 = 219,
+ MCRF = 220,
+ MFCR = 221,
+ MFCTR = 222,
+ MFCTR8 = 223,
+ MFFS = 224,
+ MFLR = 225,
+ MFLR8 = 226,
+ MFOCRF = 227,
+ MFVRSAVE = 228,
+ MFVSCR = 229,
+ MTCRF = 230,
+ MTCTR = 231,
+ MTCTR8 = 232,
+ MTFSB0 = 233,
+ MTFSB1 = 234,
+ MTFSF = 235,
+ MTLR = 236,
+ MTLR8 = 237,
+ MTVRSAVE = 238,
+ MTVSCR = 239,
+ MULHD = 240,
+ MULHDU = 241,
+ MULHW = 242,
+ MULHWU = 243,
+ MULLD = 244,
+ MULLI = 245,
+ MULLW = 246,
+ MovePCtoLR = 247,
+ MovePCtoLR8 = 248,
+ NAND = 249,
+ NAND8 = 250,
+ NEG = 251,
+ NEG8 = 252,
+ NOP = 253,
+ NOR = 254,
+ NOR8 = 255,
+ OR = 256,
+ OR4To8 = 257,
+ OR8 = 258,
+ OR8To4 = 259,
+ ORC = 260,
+ ORC8 = 261,
+ ORI = 262,
+ ORI8 = 263,
+ ORIS = 264,
+ ORIS8 = 265,
+ RLDCL = 266,
+ RLDICL = 267,
+ RLDICR = 268,
+ RLDIMI = 269,
+ RLWIMI = 270,
+ RLWINM = 271,
+ RLWINMo = 272,
+ RLWNM = 273,
+ SELECT_CC_F4 = 274,
+ SELECT_CC_F8 = 275,
+ SELECT_CC_I4 = 276,
+ SELECT_CC_I8 = 277,
+ SELECT_CC_VRRC = 278,
+ SLD = 279,
+ SLW = 280,
+ SPILL_CR = 281,
+ SRAD = 282,
+ SRADI = 283,
+ SRAW = 284,
+ SRAWI = 285,
+ SRD = 286,
+ SRW = 287,
+ STB = 288,
+ STB8 = 289,
+ STBU = 290,
+ STBU8 = 291,
+ STBX = 292,
+ STBX8 = 293,
+ STD = 294,
+ STDCX = 295,
+ STDU = 296,
+ STDUX = 297,
+ STDX = 298,
+ STDX_32 = 299,
+ STD_32 = 300,
+ STFD = 301,
+ STFDU = 302,
+ STFDX = 303,
+ STFIWX = 304,
+ STFS = 305,
+ STFSU = 306,
+ STFSX = 307,
+ STH = 308,
+ STH8 = 309,
+ STHBRX = 310,
+ STHU = 311,
+ STHU8 = 312,
+ STHX = 313,
+ STHX8 = 314,
+ STVEBX = 315,
+ STVEHX = 316,
+ STVEWX = 317,
+ STVX = 318,
+ STVXL = 319,
+ STW = 320,
+ STW8 = 321,
+ STWBRX = 322,
+ STWCX = 323,
+ STWU = 324,
+ STWU8 = 325,
+ STWUX = 326,
+ STWX = 327,
+ STWX8 = 328,
+ SUBF = 329,
+ SUBF8 = 330,
+ SUBFC = 331,
+ SUBFC8 = 332,
+ SUBFE = 333,
+ SUBFE8 = 334,
+ SUBFIC = 335,
+ SUBFIC8 = 336,
+ SUBFME = 337,
+ SUBFME8 = 338,
+ SUBFZE = 339,
+ SUBFZE8 = 340,
+ SYNC = 341,
+ TAILB = 342,
+ TAILB8 = 343,
+ TAILBA = 344,
+ TAILBA8 = 345,
+ TAILBCTR = 346,
+ TAILBCTR8 = 347,
+ TCRETURNai = 348,
+ TCRETURNai8 = 349,
+ TCRETURNdi = 350,
+ TCRETURNdi8 = 351,
+ TCRETURNri = 352,
+ TCRETURNri8 = 353,
+ TRAP = 354,
+ UPDATE_VRSAVE = 355,
+ VADDCUW = 356,
+ VADDFP = 357,
+ VADDSBS = 358,
+ VADDSHS = 359,
+ VADDSWS = 360,
+ VADDUBM = 361,
+ VADDUBS = 362,
+ VADDUHM = 363,
+ VADDUHS = 364,
+ VADDUWM = 365,
+ VADDUWS = 366,
+ VAND = 367,
+ VANDC = 368,
+ VAVGSB = 369,
+ VAVGSH = 370,
+ VAVGSW = 371,
+ VAVGUB = 372,
+ VAVGUH = 373,
+ VAVGUW = 374,
+ VCFSX = 375,
+ VCFUX = 376,
+ VCMPBFP = 377,
+ VCMPBFPo = 378,
+ VCMPEQFP = 379,
+ VCMPEQFPo = 380,
+ VCMPEQUB = 381,
+ VCMPEQUBo = 382,
+ VCMPEQUH = 383,
+ VCMPEQUHo = 384,
+ VCMPEQUW = 385,
+ VCMPEQUWo = 386,
+ VCMPGEFP = 387,
+ VCMPGEFPo = 388,
+ VCMPGTFP = 389,
+ VCMPGTFPo = 390,
+ VCMPGTSB = 391,
+ VCMPGTSBo = 392,
+ VCMPGTSH = 393,
+ VCMPGTSHo = 394,
+ VCMPGTSW = 395,
+ VCMPGTSWo = 396,
+ VCMPGTUB = 397,
+ VCMPGTUBo = 398,
+ VCMPGTUH = 399,
+ VCMPGTUHo = 400,
+ VCMPGTUW = 401,
+ VCMPGTUWo = 402,
+ VCTSXS = 403,
+ VCTUXS = 404,
+ VEXPTEFP = 405,
+ VLOGEFP = 406,
+ VMADDFP = 407,
+ VMAXFP = 408,
+ VMAXSB = 409,
+ VMAXSH = 410,
+ VMAXSW = 411,
+ VMAXUB = 412,
+ VMAXUH = 413,
+ VMAXUW = 414,
+ VMHADDSHS = 415,
+ VMHRADDSHS = 416,
+ VMINFP = 417,
+ VMINSB = 418,
+ VMINSH = 419,
+ VMINSW = 420,
+ VMINUB = 421,
+ VMINUH = 422,
+ VMINUW = 423,
+ VMLADDUHM = 424,
+ VMRGHB = 425,
+ VMRGHH = 426,
+ VMRGHW = 427,
+ VMRGLB = 428,
+ VMRGLH = 429,
+ VMRGLW = 430,
+ VMSUMMBM = 431,
+ VMSUMSHM = 432,
+ VMSUMSHS = 433,
+ VMSUMUBM = 434,
+ VMSUMUHM = 435,
+ VMSUMUHS = 436,
+ VMULESB = 437,
+ VMULESH = 438,
+ VMULEUB = 439,
+ VMULEUH = 440,
+ VMULOSB = 441,
+ VMULOSH = 442,
+ VMULOUB = 443,
+ VMULOUH = 444,
+ VNMSUBFP = 445,
+ VNOR = 446,
+ VOR = 447,
+ VPERM = 448,
+ VPKPX = 449,
+ VPKSHSS = 450,
+ VPKSHUS = 451,
+ VPKSWSS = 452,
+ VPKSWUS = 453,
+ VPKUHUM = 454,
+ VPKUHUS = 455,
+ VPKUWUM = 456,
+ VPKUWUS = 457,
+ VREFP = 458,
+ VRFIM = 459,
+ VRFIN = 460,
+ VRFIP = 461,
+ VRFIZ = 462,
+ VRLB = 463,
+ VRLH = 464,
+ VRLW = 465,
+ VRSQRTEFP = 466,
+ VSEL = 467,
+ VSL = 468,
+ VSLB = 469,
+ VSLDOI = 470,
+ VSLH = 471,
+ VSLO = 472,
+ VSLW = 473,
+ VSPLTB = 474,
+ VSPLTH = 475,
+ VSPLTISB = 476,
+ VSPLTISH = 477,
+ VSPLTISW = 478,
+ VSPLTW = 479,
+ VSR = 480,
+ VSRAB = 481,
+ VSRAH = 482,
+ VSRAW = 483,
+ VSRB = 484,
+ VSRH = 485,
+ VSRO = 486,
+ VSRW = 487,
+ VSUBCUW = 488,
+ VSUBFP = 489,
+ VSUBSBS = 490,
+ VSUBSHS = 491,
+ VSUBSWS = 492,
+ VSUBUBM = 493,
+ VSUBUBS = 494,
+ VSUBUHM = 495,
+ VSUBUHS = 496,
+ VSUBUWM = 497,
+ VSUBUWS = 498,
+ VSUM2SWS = 499,
+ VSUM4SBS = 500,
+ VSUM4SHS = 501,
+ VSUM4UBS = 502,
+ VSUMSWS = 503,
+ VUPKHPX = 504,
+ VUPKHSB = 505,
+ VUPKHSH = 506,
+ VUPKLPX = 507,
+ VUPKLSB = 508,
+ VUPKLSH = 509,
+ VXOR = 510,
+ V_SET0 = 511,
+ XOR = 512,
+ XOR8 = 513,
+ XORI = 514,
+ XORI8 = 515,
+ XORIS = 516,
+ XORIS8 = 517,
+ INSTRUCTION_LIST_END = 518
+ };
+}
+} // End llvm namespace
diff --git a/libclamav/c++/PPCGenRegisterInfo.h.inc b/libclamav/c++/PPCGenRegisterInfo.h.inc
new file mode 100644
index 0000000..9997c92
--- /dev/null
+++ b/libclamav/c++/PPCGenRegisterInfo.h.inc
@@ -0,0 +1,102 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Register Information Header Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <string>
+
+namespace llvm {
+
+struct PPCGenRegisterInfo : public TargetRegisterInfo {
+ explicit PPCGenRegisterInfo(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
+ virtual int getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) const;
+ virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
+ virtual bool needsStackRealignment(const MachineFunction &) const
+ { return false; }
+ unsigned getSubReg(unsigned RegNo, unsigned Index) const;
+ unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
+};
+
+namespace PPC { // Register classes
+ enum {
+ CARRYRCRegClassID = 1,
+ CRBITRCRegClassID = 2,
+ CRRCRegClassID = 3,
+ CTRRCRegClassID = 4,
+ CTRRC8RegClassID = 5,
+ F4RCRegClassID = 6,
+ F8RCRegClassID = 7,
+ G8RCRegClassID = 8,
+ GPRCRegClassID = 9,
+ VRRCRegClassID = 10,
+ VRSAVERCRegClassID = 11
+ };
+
+ struct CARRYRCClass : public TargetRegisterClass {
+ CARRYRCClass();
+ };
+ extern CARRYRCClass CARRYRCRegClass;
+ static TargetRegisterClass * const CARRYRCRegisterClass = &CARRYRCRegClass;
+ struct CRBITRCClass : public TargetRegisterClass {
+ CRBITRCClass();
+ };
+ extern CRBITRCClass CRBITRCRegClass;
+ static TargetRegisterClass * const CRBITRCRegisterClass = &CRBITRCRegClass;
+ struct CRRCClass : public TargetRegisterClass {
+ CRRCClass();
+ };
+ extern CRRCClass CRRCRegClass;
+ static TargetRegisterClass * const CRRCRegisterClass = &CRRCRegClass;
+ struct CTRRCClass : public TargetRegisterClass {
+ CTRRCClass();
+ };
+ extern CTRRCClass CTRRCRegClass;
+ static TargetRegisterClass * const CTRRCRegisterClass = &CTRRCRegClass;
+ struct CTRRC8Class : public TargetRegisterClass {
+ CTRRC8Class();
+ };
+ extern CTRRC8Class CTRRC8RegClass;
+ static TargetRegisterClass * const CTRRC8RegisterClass = &CTRRC8RegClass;
+ struct F4RCClass : public TargetRegisterClass {
+ F4RCClass();
+ };
+ extern F4RCClass F4RCRegClass;
+ static TargetRegisterClass * const F4RCRegisterClass = &F4RCRegClass;
+ struct F8RCClass : public TargetRegisterClass {
+ F8RCClass();
+ };
+ extern F8RCClass F8RCRegClass;
+ static TargetRegisterClass * const F8RCRegisterClass = &F8RCRegClass;
+ struct G8RCClass : public TargetRegisterClass {
+ G8RCClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern G8RCClass G8RCRegClass;
+ static TargetRegisterClass * const G8RCRegisterClass = &G8RCRegClass;
+ struct GPRCClass : public TargetRegisterClass {
+ GPRCClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GPRCClass GPRCRegClass;
+ static TargetRegisterClass * const GPRCRegisterClass = &GPRCRegClass;
+ struct VRRCClass : public TargetRegisterClass {
+ VRRCClass();
+ };
+ extern VRRCClass VRRCRegClass;
+ static TargetRegisterClass * const VRRCRegisterClass = &VRRCRegClass;
+ struct VRSAVERCClass : public TargetRegisterClass {
+ VRSAVERCClass();
+ };
+ extern VRSAVERCClass VRSAVERCRegClass;
+ static TargetRegisterClass * const VRSAVERCRegisterClass = &VRSAVERCRegClass;
+} // end of namespace PPC
+
+} // End llvm namespace
diff --git a/libclamav/c++/PPCGenRegisterInfo.inc b/libclamav/c++/PPCGenRegisterInfo.inc
new file mode 100644
index 0000000..ea90909
--- /dev/null
+++ b/libclamav/c++/PPCGenRegisterInfo.inc
@@ -0,0 +1,3725 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Register Information Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace { // Register classes...
+ // CARRYRC Register Class...
+ static const unsigned CARRYRC[] = {
+ PPC::CARRY,
+ };
+
+ // CRBITRC Register Class...
+ static const unsigned CRBITRC[] = {
+ PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN,
+ };
+
+ // CRRC Register Class...
+ static const unsigned CRRC[] = {
+ PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4,
+ };
+
+ // CTRRC Register Class...
+ static const unsigned CTRRC[] = {
+ PPC::CTR,
+ };
+
+ // CTRRC8 Register Class...
+ static const unsigned CTRRC8[] = {
+ PPC::CTR8,
+ };
+
+ // F4RC Register Class...
+ static const unsigned F4RC[] = {
+ PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
+ };
+
+ // F8RC Register Class...
+ static const unsigned F8RC[] = {
+ PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
+ };
+
+ // G8RC Register Class...
+ static const unsigned G8RC[] = {
+ PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::LR8,
+ };
+
+ // GPRC Register Class...
+ static const unsigned GPRC[] = {
+ PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::LR,
+ };
+
+ // VRRC Register Class...
+ static const unsigned VRRC[] = {
+ PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
+ };
+
+ // VRSAVERC Register Class...
+ static const unsigned VRSAVERC[] = {
+ PPC::VRSAVE,
+ };
+
+ // CARRYRCVTs Register Class Value Types...
+ static const EVT CARRYRCVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // CRBITRCVTs Register Class Value Types...
+ static const EVT CRBITRCVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // CRRCVTs Register Class Value Types...
+ static const EVT CRRCVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // CTRRCVTs Register Class Value Types...
+ static const EVT CTRRCVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // CTRRC8VTs Register Class Value Types...
+ static const EVT CTRRC8VTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // F4RCVTs Register Class Value Types...
+ static const EVT F4RCVTs[] = {
+ MVT::f32, MVT::Other
+ };
+
+ // F8RCVTs Register Class Value Types...
+ static const EVT F8RCVTs[] = {
+ MVT::f64, MVT::Other
+ };
+
+ // G8RCVTs Register Class Value Types...
+ static const EVT G8RCVTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // GPRCVTs Register Class Value Types...
+ static const EVT GPRCVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // VRRCVTs Register Class Value Types...
+ static const EVT VRRCVTs[] = {
+ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::Other
+ };
+
+ // VRSAVERCVTs Register Class Value Types...
+ static const EVT VRSAVERCVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+} // end anonymous namespace
+
+namespace PPC { // Register class instances
+ CARRYRCClass CARRYRCRegClass;
+ CRBITRCClass CRBITRCRegClass;
+ CRRCClass CRRCRegClass;
+ CTRRCClass CTRRCRegClass;
+ CTRRC8Class CTRRC8RegClass;
+ F4RCClass F4RCRegClass;
+ F8RCClass F8RCRegClass;
+ G8RCClass G8RCRegClass;
+ GPRCClass GPRCRegClass;
+ VRRCClass VRRCRegClass;
+ VRSAVERCClass VRSAVERCRegClass;
+
+ // CARRYRC Sub-register Classes...
+ static const TargetRegisterClass* const CARRYRCSubRegClasses[] = {
+ NULL
+ };
+
+ // CRBITRC Sub-register Classes...
+ static const TargetRegisterClass* const CRBITRCSubRegClasses[] = {
+ NULL
+ };
+
+ // CRRC Sub-register Classes...
+ static const TargetRegisterClass* const CRRCSubRegClasses[] = {
+ &PPC::CRBITRCRegClass, &PPC::CRBITRCRegClass, &PPC::CRBITRCRegClass, &PPC::CRBITRCRegClass, NULL
+ };
+
+ // CTRRC Sub-register Classes...
+ static const TargetRegisterClass* const CTRRCSubRegClasses[] = {
+ NULL
+ };
+
+ // CTRRC8 Sub-register Classes...
+ static const TargetRegisterClass* const CTRRC8SubRegClasses[] = {
+ NULL
+ };
+
+ // F4RC Sub-register Classes...
+ static const TargetRegisterClass* const F4RCSubRegClasses[] = {
+ NULL
+ };
+
+ // F8RC Sub-register Classes...
+ static const TargetRegisterClass* const F8RCSubRegClasses[] = {
+ NULL
+ };
+
+ // G8RC Sub-register Classes...
+ static const TargetRegisterClass* const G8RCSubRegClasses[] = {
+ NULL
+ };
+
+ // GPRC Sub-register Classes...
+ static const TargetRegisterClass* const GPRCSubRegClasses[] = {
+ NULL
+ };
+
+ // VRRC Sub-register Classes...
+ static const TargetRegisterClass* const VRRCSubRegClasses[] = {
+ NULL
+ };
+
+ // VRSAVERC Sub-register Classes...
+ static const TargetRegisterClass* const VRSAVERCSubRegClasses[] = {
+ NULL
+ };
+
+ // CARRYRC Super-register Classes...
+ static const TargetRegisterClass* const CARRYRCSuperRegClasses[] = {
+ NULL
+ };
+
+ // CRBITRC Super-register Classes...
+ static const TargetRegisterClass* const CRBITRCSuperRegClasses[] = {
+ &PPC::CRRCRegClass, NULL
+ };
+
+ // CRRC Super-register Classes...
+ static const TargetRegisterClass* const CRRCSuperRegClasses[] = {
+ NULL
+ };
+
+ // CTRRC Super-register Classes...
+ static const TargetRegisterClass* const CTRRCSuperRegClasses[] = {
+ NULL
+ };
+
+ // CTRRC8 Super-register Classes...
+ static const TargetRegisterClass* const CTRRC8SuperRegClasses[] = {
+ NULL
+ };
+
+ // F4RC Super-register Classes...
+ static const TargetRegisterClass* const F4RCSuperRegClasses[] = {
+ NULL
+ };
+
+ // F8RC Super-register Classes...
+ static const TargetRegisterClass* const F8RCSuperRegClasses[] = {
+ NULL
+ };
+
+ // G8RC Super-register Classes...
+ static const TargetRegisterClass* const G8RCSuperRegClasses[] = {
+ NULL
+ };
+
+ // GPRC Super-register Classes...
+ static const TargetRegisterClass* const GPRCSuperRegClasses[] = {
+ NULL
+ };
+
+ // VRRC Super-register Classes...
+ static const TargetRegisterClass* const VRRCSuperRegClasses[] = {
+ NULL
+ };
+
+ // VRSAVERC Super-register Classes...
+ static const TargetRegisterClass* const VRSAVERCSuperRegClasses[] = {
+ NULL
+ };
+
+ // CARRYRC Register Class sub-classes...
+ static const TargetRegisterClass* const CARRYRCSubclasses[] = {
+ NULL
+ };
+
+ // CRBITRC Register Class sub-classes...
+ static const TargetRegisterClass* const CRBITRCSubclasses[] = {
+ NULL
+ };
+
+ // CRRC Register Class sub-classes...
+ static const TargetRegisterClass* const CRRCSubclasses[] = {
+ NULL
+ };
+
+ // CTRRC Register Class sub-classes...
+ static const TargetRegisterClass* const CTRRCSubclasses[] = {
+ NULL
+ };
+
+ // CTRRC8 Register Class sub-classes...
+ static const TargetRegisterClass* const CTRRC8Subclasses[] = {
+ NULL
+ };
+
+ // F4RC Register Class sub-classes...
+ static const TargetRegisterClass* const F4RCSubclasses[] = {
+ &PPC::F8RCRegClass, NULL
+ };
+
+ // F8RC Register Class sub-classes...
+ static const TargetRegisterClass* const F8RCSubclasses[] = {
+ NULL
+ };
+
+ // G8RC Register Class sub-classes...
+ static const TargetRegisterClass* const G8RCSubclasses[] = {
+ NULL
+ };
+
+ // GPRC Register Class sub-classes...
+ static const TargetRegisterClass* const GPRCSubclasses[] = {
+ NULL
+ };
+
+ // VRRC Register Class sub-classes...
+ static const TargetRegisterClass* const VRRCSubclasses[] = {
+ NULL
+ };
+
+ // VRSAVERC Register Class sub-classes...
+ static const TargetRegisterClass* const VRSAVERCSubclasses[] = {
+ NULL
+ };
+
+ // CARRYRC Register Class super-classes...
+ static const TargetRegisterClass* const CARRYRCSuperclasses[] = {
+ NULL
+ };
+
+ // CRBITRC Register Class super-classes...
+ static const TargetRegisterClass* const CRBITRCSuperclasses[] = {
+ NULL
+ };
+
+ // CRRC Register Class super-classes...
+ static const TargetRegisterClass* const CRRCSuperclasses[] = {
+ NULL
+ };
+
+ // CTRRC Register Class super-classes...
+ static const TargetRegisterClass* const CTRRCSuperclasses[] = {
+ NULL
+ };
+
+ // CTRRC8 Register Class super-classes...
+ static const TargetRegisterClass* const CTRRC8Superclasses[] = {
+ NULL
+ };
+
+ // F4RC Register Class super-classes...
+ static const TargetRegisterClass* const F4RCSuperclasses[] = {
+ NULL
+ };
+
+ // F8RC Register Class super-classes...
+ static const TargetRegisterClass* const F8RCSuperclasses[] = {
+ &PPC::F4RCRegClass, NULL
+ };
+
+ // G8RC Register Class super-classes...
+ static const TargetRegisterClass* const G8RCSuperclasses[] = {
+ NULL
+ };
+
+ // GPRC Register Class super-classes...
+ static const TargetRegisterClass* const GPRCSuperclasses[] = {
+ NULL
+ };
+
+ // VRRC Register Class super-classes...
+ static const TargetRegisterClass* const VRRCSuperclasses[] = {
+ NULL
+ };
+
+ // VRSAVERC Register Class super-classes...
+ static const TargetRegisterClass* const VRSAVERCSuperclasses[] = {
+ NULL
+ };
+
+
+CARRYRCClass::CARRYRCClass() : TargetRegisterClass(CARRYRCRegClassID, "CARRYRC", CARRYRCVTs, CARRYRCSubclasses, CARRYRCSuperclasses, CARRYRCSubRegClasses, CARRYRCSuperRegClasses, 4, 4, -1, CARRYRC, CARRYRC + 1) {}
+
+CRBITRCClass::CRBITRCClass() : TargetRegisterClass(CRBITRCRegClassID, "CRBITRC", CRBITRCVTs, CRBITRCSubclasses, CRBITRCSuperclasses, CRBITRCSubRegClasses, CRBITRCSuperRegClasses, 4, 4, -1, CRBITRC, CRBITRC + 32) {}
+
+CRRCClass::CRRCClass() : TargetRegisterClass(CRRCRegClassID, "CRRC", CRRCVTs, CRRCSubclasses, CRRCSuperclasses, CRRCSubRegClasses, CRRCSuperRegClasses, 4, 4, 1, CRRC, CRRC + 8) {}
+
+CTRRCClass::CTRRCClass() : TargetRegisterClass(CTRRCRegClassID, "CTRRC", CTRRCVTs, CTRRCSubclasses, CTRRCSuperclasses, CTRRCSubRegClasses, CTRRCSuperRegClasses, 4, 4, 1, CTRRC, CTRRC + 1) {}
+
+CTRRC8Class::CTRRC8Class() : TargetRegisterClass(CTRRC8RegClassID, "CTRRC8", CTRRC8VTs, CTRRC8Subclasses, CTRRC8Superclasses, CTRRC8SubRegClasses, CTRRC8SuperRegClasses, 8, 8, 1, CTRRC8, CTRRC8 + 1) {}
+
+F4RCClass::F4RCClass() : TargetRegisterClass(F4RCRegClassID, "F4RC", F4RCVTs, F4RCSubclasses, F4RCSuperclasses, F4RCSubRegClasses, F4RCSuperRegClasses, 4, 4, 1, F4RC, F4RC + 32) {}
+
+F8RCClass::F8RCClass() : TargetRegisterClass(F8RCRegClassID, "F8RC", F8RCVTs, F8RCSubclasses, F8RCSuperclasses, F8RCSubRegClasses, F8RCSuperRegClasses, 8, 8, 1, F8RC, F8RC + 32) {}
+
+ G8RCClass::iterator
+ G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
+ // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
+ if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
+ return begin()+1;
+
+ return begin();
+ }
+ G8RCClass::iterator
+ G8RCClass::allocation_order_end(const MachineFunction &MF) const {
+ if (needsFP(MF))
+ return end()-5;
+ else
+ return end()-4;
+ }
+
+G8RCClass::G8RCClass() : TargetRegisterClass(G8RCRegClassID, "G8RC", G8RCVTs, G8RCSubclasses, G8RCSuperclasses, G8RCSubRegClasses, G8RCSuperRegClasses, 8, 8, 1, G8RC, G8RC + 33) {}
+
+ GPRCClass::iterator
+ GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
+ // 32-bit SVR4 ABI: r2 is reserved for the OS.
+ // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
+ if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
+ return begin()+1;
+
+ return begin();
+ }
+ GPRCClass::iterator
+ GPRCClass::allocation_order_end(const MachineFunction &MF) const {
+ // On PPC64, r13 is the thread pointer. Never allocate this register.
+ // Note that this is overconservative, as it also prevents allocation of
+ // R31 when the FP is not needed.
+ // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area
+ // pointer.
+ const PPCSubtarget &Subtarget
+ = MF.getTarget().getSubtarget<PPCSubtarget>();
+
+ if (Subtarget.isPPC64() || Subtarget.isSVR4ABI())
+ return end()-5; // don't allocate R13, R31, R0, R1, LR
+
+ if (needsFP(MF))
+ return end()-4; // don't allocate R31, R0, R1, LR
+ else
+ return end()-3; // don't allocate R0, R1, LR
+ }
+
+GPRCClass::GPRCClass() : TargetRegisterClass(GPRCRegClassID, "GPRC", GPRCVTs, GPRCSubclasses, GPRCSuperclasses, GPRCSubRegClasses, GPRCSuperRegClasses, 4, 4, 1, GPRC, GPRC + 33) {}
+
+VRRCClass::VRRCClass() : TargetRegisterClass(VRRCRegClassID, "VRRC", VRRCVTs, VRRCSubclasses, VRRCSuperclasses, VRRCSubRegClasses, VRRCSuperRegClasses, 16, 16, 1, VRRC, VRRC + 32) {}
+
+VRSAVERCClass::VRSAVERCClass() : TargetRegisterClass(VRSAVERCRegClassID, "VRSAVERC", VRSAVERCVTs, VRSAVERCSubclasses, VRSAVERCSuperclasses, VRSAVERCSubRegClasses, VRSAVERCSuperRegClasses, 4, 4, 1, VRSAVERC, VRSAVERC + 1) {}
+}
+
+namespace {
+ const TargetRegisterClass* const RegisterClasses[] = {
+ &PPC::CARRYRCRegClass,
+ &PPC::CRBITRCRegClass,
+ &PPC::CRRCRegClass,
+ &PPC::CTRRCRegClass,
+ &PPC::CTRRC8RegClass,
+ &PPC::F4RCRegClass,
+ &PPC::F8RCRegClass,
+ &PPC::G8RCRegClass,
+ &PPC::GPRCRegClass,
+ &PPC::VRRCRegClass,
+ &PPC::VRSAVERCRegClass,
+ };
+
+
+ // Number of hash collisions: 11
+ const unsigned SubregHashTable[] = { PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X22, PPC::R22,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2, PPC::CR2GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X10, PPC::R10,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X7, PPC::R7,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X23, PPC::R23,
+ PPC::CR2, PPC::CR2LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X11, PPC::R11,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X8, PPC::R8,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2, PPC::CR2UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X24, PPC::R24,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X12, PPC::R12,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X9, PPC::R9,
+ PPC::CR0, PPC::CR0EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X25, PPC::R25,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X13, PPC::R13,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR0, PPC::CR0GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X26, PPC::R26,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3, PPC::CR3EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X14, PPC::R14,
+ PPC::CR0, PPC::CR0LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X27, PPC::R27,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3, PPC::CR3GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR0, PPC::CR0UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X15, PPC::R15,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X28, PPC::R28,
+ PPC::CR3, PPC::CR3LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X16, PPC::R16,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3, PPC::CR3UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X29, PPC::R29,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X17, PPC::R17,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1, PPC::CR1EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X3, PPC::R3,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X18, PPC::R18,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1, PPC::CR1GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X30, PPC::R30,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4, PPC::CR4EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X19, PPC::R19,
+ PPC::CR1, PPC::CR1LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X31, PPC::R31,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4, PPC::CR4GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1, PPC::CR1UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X2, PPC::R2,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X4, PPC::R4,
+ PPC::CR4, PPC::CR4LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X20, PPC::R20,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X0, PPC::R0,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4, PPC::CR4UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X5, PPC::R5,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X21, PPC::R21,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2, PPC::CR2EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X1, PPC::R1,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X6, PPC::R6,
+PPC::NoRegister, PPC::NoRegister };
+ const unsigned SubregHashTableSize = 512;
+
+
+ // Number of hash collisions: 10
+ const unsigned SuperregHashTable[] = { PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R14, PPC::X14,
+ PPC::CR5EQ, PPC::CR5,
+ PPC::CR5GT, PPC::CR5,
+ PPC::CR5LT, PPC::CR5,
+ PPC::CR5UN, PPC::CR5,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R27, PPC::X27,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R15, PPC::X15,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R28, PPC::X28,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR0EQ, PPC::CR0,
+ PPC::CR0GT, PPC::CR0,
+ PPC::CR0LT, PPC::CR0,
+ PPC::CR0UN, PPC::CR0,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R16, PPC::X16,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R29, PPC::X29,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R17, PPC::X17,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3EQ, PPC::CR3,
+ PPC::CR3GT, PPC::CR3,
+ PPC::CR3LT, PPC::CR3,
+ PPC::CR3UN, PPC::CR3,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R3, PPC::X3,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R18, PPC::X18,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R30, PPC::X30,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R19, PPC::X19,
+ PPC::CR6EQ, PPC::CR6,
+ PPC::CR6GT, PPC::CR6,
+ PPC::CR6LT, PPC::CR6,
+ PPC::CR6UN, PPC::CR6,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R31, PPC::X31,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R2, PPC::X2,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R4, PPC::X4,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1EQ, PPC::CR1,
+ PPC::CR1GT, PPC::CR1,
+ PPC::CR1LT, PPC::CR1,
+ PPC::CR1UN, PPC::CR1,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R20, PPC::X20,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R0, PPC::X0,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R5, PPC::X5,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R21, PPC::X21,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R1, PPC::X1,
+ PPC::CR4EQ, PPC::CR4,
+ PPC::CR4GT, PPC::CR4,
+ PPC::CR4LT, PPC::CR4,
+ PPC::CR4UN, PPC::CR4,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R6, PPC::X6,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R22, PPC::X22,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R10, PPC::X10,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R7, PPC::X7,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R23, PPC::X23,
+ PPC::CR7EQ, PPC::CR7,
+ PPC::CR7GT, PPC::CR7,
+ PPC::CR7LT, PPC::CR7,
+ PPC::CR7UN, PPC::CR7,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R11, PPC::X11,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R8, PPC::X8,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R24, PPC::X24,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R12, PPC::X12,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R9, PPC::X9,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2EQ, PPC::CR2,
+ PPC::CR2GT, PPC::CR2,
+ PPC::CR2LT, PPC::CR2,
+ PPC::CR2UN, PPC::CR2,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R25, PPC::X25,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R13, PPC::X13,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R26, PPC::X26,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+PPC::NoRegister, PPC::NoRegister };
+ const unsigned SuperregHashTableSize = 512;
+
+
+ // Number of hash collisions: 11
+ const unsigned AliasesHashTable[] = { PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5EQ, PPC::CR5,
+ PPC::CR5GT, PPC::CR5,
+ PPC::CR5LT, PPC::CR5,
+ PPC::CR5UN, PPC::CR5,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R27, PPC::X27,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X10, PPC::R10,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X7, PPC::R7,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R28, PPC::X28,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X11, PPC::R11,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X8, PPC::R8,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5GT,
+ PPC::CR0EQ, PPC::CR0,
+ PPC::CR0GT, PPC::CR0,
+ PPC::CR0LT, PPC::CR0,
+ PPC::CR0UN, PPC::CR0,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R29, PPC::X29,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X12, PPC::R12,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X9, PPC::R9,
+ PPC::CR0, PPC::CR0EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R3, PPC::X3,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X13, PPC::R13,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR0, PPC::CR0GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR5, PPC::CR5UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R30, PPC::X30,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X14, PPC::R14,
+ PPC::CR0, PPC::CR0LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6EQ, PPC::CR6,
+ PPC::CR6GT, PPC::CR6,
+ PPC::CR6LT, PPC::CR6,
+ PPC::CR6UN, PPC::CR6,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R31, PPC::X31,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR0, PPC::CR0UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X15, PPC::R15,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R4, PPC::X4,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X16, PPC::R16,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6GT,
+ PPC::CR1EQ, PPC::CR1,
+ PPC::CR1GT, PPC::CR1,
+ PPC::CR1LT, PPC::CR1,
+ PPC::CR1UN, PPC::CR1,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R0, PPC::X0,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R5, PPC::X5,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X17, PPC::R17,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1, PPC::CR1EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R1, PPC::X1,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R6, PPC::X6,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X18, PPC::R18,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1, PPC::CR1GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR6, PPC::CR6UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R10, PPC::X10,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R7, PPC::X7,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X19, PPC::R19,
+ PPC::CR1, PPC::CR1LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7EQ, PPC::CR7,
+ PPC::CR7GT, PPC::CR7,
+ PPC::CR7LT, PPC::CR7,
+ PPC::CR7UN, PPC::CR7,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R11, PPC::X11,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R8, PPC::X8,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR1, PPC::CR1UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X2, PPC::R2,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R12, PPC::X12,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R9, PPC::X9,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X20, PPC::R20,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7GT,
+ PPC::CR2EQ, PPC::CR2,
+ PPC::CR2GT, PPC::CR2,
+ PPC::CR2LT, PPC::CR2,
+ PPC::CR2UN, PPC::CR2,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R13, PPC::X13,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X21, PPC::R21,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2, PPC::CR2EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R14, PPC::X14,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X22, PPC::R22,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2, PPC::CR2GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR7, PPC::CR7UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R15, PPC::X15,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X23, PPC::R23,
+ PPC::CR2, PPC::CR2LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R16, PPC::X16,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR2, PPC::CR2UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X24, PPC::R24,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R17, PPC::X17,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X25, PPC::R25,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3EQ, PPC::CR3,
+ PPC::CR3GT, PPC::CR3,
+ PPC::CR3LT, PPC::CR3,
+ PPC::CR3UN, PPC::CR3,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R18, PPC::X18,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X26, PPC::R26,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3, PPC::CR3EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R19, PPC::X19,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X27, PPC::R27,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3, PPC::CR3GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R2, PPC::X2,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X28, PPC::R28,
+ PPC::CR3, PPC::CR3LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R20, PPC::X20,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR3, PPC::CR3UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X29, PPC::R29,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R21, PPC::X21,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X3, PPC::R3,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4EQ, PPC::CR4,
+ PPC::CR4GT, PPC::CR4,
+ PPC::CR4LT, PPC::CR4,
+ PPC::CR4UN, PPC::CR4,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R22, PPC::X22,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X30, PPC::R30,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4, PPC::CR4EQ,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R23, PPC::X23,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X31, PPC::R31,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4, PPC::CR4GT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R24, PPC::X24,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X4, PPC::R4,
+ PPC::CR4, PPC::CR4LT,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R25, PPC::X25,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X0, PPC::R0,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::CR4, PPC::CR4UN,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X5, PPC::R5,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::R26, PPC::X26,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X1, PPC::R1,
+ PPC::NoRegister, PPC::NoRegister,
+ PPC::X6, PPC::R6,
+PPC::NoRegister, PPC::NoRegister };
+ const unsigned AliasesHashTableSize = 1024;
+
+
+ // Register Alias Sets...
+ const unsigned Empty_AliasSet[] = { 0 };
+ const unsigned CARRY_AliasSet[] = { 0 };
+ const unsigned CR0_AliasSet[] = { PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 0 };
+ const unsigned CR0EQ_AliasSet[] = { PPC::CR0, 0 };
+ const unsigned CR0GT_AliasSet[] = { PPC::CR0, 0 };
+ const unsigned CR0LT_AliasSet[] = { PPC::CR0, 0 };
+ const unsigned CR0UN_AliasSet[] = { PPC::CR0, 0 };
+ const unsigned CR1_AliasSet[] = { PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 0 };
+ const unsigned CR1EQ_AliasSet[] = { PPC::CR1, 0 };
+ const unsigned CR1GT_AliasSet[] = { PPC::CR1, 0 };
+ const unsigned CR1LT_AliasSet[] = { PPC::CR1, 0 };
+ const unsigned CR1UN_AliasSet[] = { PPC::CR1, 0 };
+ const unsigned CR2_AliasSet[] = { PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 0 };
+ const unsigned CR2EQ_AliasSet[] = { PPC::CR2, 0 };
+ const unsigned CR2GT_AliasSet[] = { PPC::CR2, 0 };
+ const unsigned CR2LT_AliasSet[] = { PPC::CR2, 0 };
+ const unsigned CR2UN_AliasSet[] = { PPC::CR2, 0 };
+ const unsigned CR3_AliasSet[] = { PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 0 };
+ const unsigned CR3EQ_AliasSet[] = { PPC::CR3, 0 };
+ const unsigned CR3GT_AliasSet[] = { PPC::CR3, 0 };
+ const unsigned CR3LT_AliasSet[] = { PPC::CR3, 0 };
+ const unsigned CR3UN_AliasSet[] = { PPC::CR3, 0 };
+ const unsigned CR4_AliasSet[] = { PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 0 };
+ const unsigned CR4EQ_AliasSet[] = { PPC::CR4, 0 };
+ const unsigned CR4GT_AliasSet[] = { PPC::CR4, 0 };
+ const unsigned CR4LT_AliasSet[] = { PPC::CR4, 0 };
+ const unsigned CR4UN_AliasSet[] = { PPC::CR4, 0 };
+ const unsigned CR5_AliasSet[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 0 };
+ const unsigned CR5EQ_AliasSet[] = { PPC::CR5, 0 };
+ const unsigned CR5GT_AliasSet[] = { PPC::CR5, 0 };
+ const unsigned CR5LT_AliasSet[] = { PPC::CR5, 0 };
+ const unsigned CR5UN_AliasSet[] = { PPC::CR5, 0 };
+ const unsigned CR6_AliasSet[] = { PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 0 };
+ const unsigned CR6EQ_AliasSet[] = { PPC::CR6, 0 };
+ const unsigned CR6GT_AliasSet[] = { PPC::CR6, 0 };
+ const unsigned CR6LT_AliasSet[] = { PPC::CR6, 0 };
+ const unsigned CR6UN_AliasSet[] = { PPC::CR6, 0 };
+ const unsigned CR7_AliasSet[] = { PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, 0 };
+ const unsigned CR7EQ_AliasSet[] = { PPC::CR7, 0 };
+ const unsigned CR7GT_AliasSet[] = { PPC::CR7, 0 };
+ const unsigned CR7LT_AliasSet[] = { PPC::CR7, 0 };
+ const unsigned CR7UN_AliasSet[] = { PPC::CR7, 0 };
+ const unsigned CTR_AliasSet[] = { 0 };
+ const unsigned CTR8_AliasSet[] = { 0 };
+ const unsigned F0_AliasSet[] = { 0 };
+ const unsigned F1_AliasSet[] = { 0 };
+ const unsigned F10_AliasSet[] = { 0 };
+ const unsigned F11_AliasSet[] = { 0 };
+ const unsigned F12_AliasSet[] = { 0 };
+ const unsigned F13_AliasSet[] = { 0 };
+ const unsigned F14_AliasSet[] = { 0 };
+ const unsigned F15_AliasSet[] = { 0 };
+ const unsigned F16_AliasSet[] = { 0 };
+ const unsigned F17_AliasSet[] = { 0 };
+ const unsigned F18_AliasSet[] = { 0 };
+ const unsigned F19_AliasSet[] = { 0 };
+ const unsigned F2_AliasSet[] = { 0 };
+ const unsigned F20_AliasSet[] = { 0 };
+ const unsigned F21_AliasSet[] = { 0 };
+ const unsigned F22_AliasSet[] = { 0 };
+ const unsigned F23_AliasSet[] = { 0 };
+ const unsigned F24_AliasSet[] = { 0 };
+ const unsigned F25_AliasSet[] = { 0 };
+ const unsigned F26_AliasSet[] = { 0 };
+ const unsigned F27_AliasSet[] = { 0 };
+ const unsigned F28_AliasSet[] = { 0 };
+ const unsigned F29_AliasSet[] = { 0 };
+ const unsigned F3_AliasSet[] = { 0 };
+ const unsigned F30_AliasSet[] = { 0 };
+ const unsigned F31_AliasSet[] = { 0 };
+ const unsigned F4_AliasSet[] = { 0 };
+ const unsigned F5_AliasSet[] = { 0 };
+ const unsigned F6_AliasSet[] = { 0 };
+ const unsigned F7_AliasSet[] = { 0 };
+ const unsigned F8_AliasSet[] = { 0 };
+ const unsigned F9_AliasSet[] = { 0 };
+ const unsigned LR_AliasSet[] = { 0 };
+ const unsigned LR8_AliasSet[] = { 0 };
+ const unsigned R0_AliasSet[] = { PPC::X0, 0 };
+ const unsigned R1_AliasSet[] = { PPC::X1, 0 };
+ const unsigned R10_AliasSet[] = { PPC::X10, 0 };
+ const unsigned R11_AliasSet[] = { PPC::X11, 0 };
+ const unsigned R12_AliasSet[] = { PPC::X12, 0 };
+ const unsigned R13_AliasSet[] = { PPC::X13, 0 };
+ const unsigned R14_AliasSet[] = { PPC::X14, 0 };
+ const unsigned R15_AliasSet[] = { PPC::X15, 0 };
+ const unsigned R16_AliasSet[] = { PPC::X16, 0 };
+ const unsigned R17_AliasSet[] = { PPC::X17, 0 };
+ const unsigned R18_AliasSet[] = { PPC::X18, 0 };
+ const unsigned R19_AliasSet[] = { PPC::X19, 0 };
+ const unsigned R2_AliasSet[] = { PPC::X2, 0 };
+ const unsigned R20_AliasSet[] = { PPC::X20, 0 };
+ const unsigned R21_AliasSet[] = { PPC::X21, 0 };
+ const unsigned R22_AliasSet[] = { PPC::X22, 0 };
+ const unsigned R23_AliasSet[] = { PPC::X23, 0 };
+ const unsigned R24_AliasSet[] = { PPC::X24, 0 };
+ const unsigned R25_AliasSet[] = { PPC::X25, 0 };
+ const unsigned R26_AliasSet[] = { PPC::X26, 0 };
+ const unsigned R27_AliasSet[] = { PPC::X27, 0 };
+ const unsigned R28_AliasSet[] = { PPC::X28, 0 };
+ const unsigned R29_AliasSet[] = { PPC::X29, 0 };
+ const unsigned R3_AliasSet[] = { PPC::X3, 0 };
+ const unsigned R30_AliasSet[] = { PPC::X30, 0 };
+ const unsigned R31_AliasSet[] = { PPC::X31, 0 };
+ const unsigned R4_AliasSet[] = { PPC::X4, 0 };
+ const unsigned R5_AliasSet[] = { PPC::X5, 0 };
+ const unsigned R6_AliasSet[] = { PPC::X6, 0 };
+ const unsigned R7_AliasSet[] = { PPC::X7, 0 };
+ const unsigned R8_AliasSet[] = { PPC::X8, 0 };
+ const unsigned R9_AliasSet[] = { PPC::X9, 0 };
+ const unsigned RM_AliasSet[] = { 0 };
+ const unsigned V0_AliasSet[] = { 0 };
+ const unsigned V1_AliasSet[] = { 0 };
+ const unsigned V10_AliasSet[] = { 0 };
+ const unsigned V11_AliasSet[] = { 0 };
+ const unsigned V12_AliasSet[] = { 0 };
+ const unsigned V13_AliasSet[] = { 0 };
+ const unsigned V14_AliasSet[] = { 0 };
+ const unsigned V15_AliasSet[] = { 0 };
+ const unsigned V16_AliasSet[] = { 0 };
+ const unsigned V17_AliasSet[] = { 0 };
+ const unsigned V18_AliasSet[] = { 0 };
+ const unsigned V19_AliasSet[] = { 0 };
+ const unsigned V2_AliasSet[] = { 0 };
+ const unsigned V20_AliasSet[] = { 0 };
+ const unsigned V21_AliasSet[] = { 0 };
+ const unsigned V22_AliasSet[] = { 0 };
+ const unsigned V23_AliasSet[] = { 0 };
+ const unsigned V24_AliasSet[] = { 0 };
+ const unsigned V25_AliasSet[] = { 0 };
+ const unsigned V26_AliasSet[] = { 0 };
+ const unsigned V27_AliasSet[] = { 0 };
+ const unsigned V28_AliasSet[] = { 0 };
+ const unsigned V29_AliasSet[] = { 0 };
+ const unsigned V3_AliasSet[] = { 0 };
+ const unsigned V30_AliasSet[] = { 0 };
+ const unsigned V31_AliasSet[] = { 0 };
+ const unsigned V4_AliasSet[] = { 0 };
+ const unsigned V5_AliasSet[] = { 0 };
+ const unsigned V6_AliasSet[] = { 0 };
+ const unsigned V7_AliasSet[] = { 0 };
+ const unsigned V8_AliasSet[] = { 0 };
+ const unsigned V9_AliasSet[] = { 0 };
+ const unsigned VRSAVE_AliasSet[] = { 0 };
+ const unsigned X0_AliasSet[] = { PPC::R0, 0 };
+ const unsigned X1_AliasSet[] = { PPC::R1, 0 };
+ const unsigned X10_AliasSet[] = { PPC::R10, 0 };
+ const unsigned X11_AliasSet[] = { PPC::R11, 0 };
+ const unsigned X12_AliasSet[] = { PPC::R12, 0 };
+ const unsigned X13_AliasSet[] = { PPC::R13, 0 };
+ const unsigned X14_AliasSet[] = { PPC::R14, 0 };
+ const unsigned X15_AliasSet[] = { PPC::R15, 0 };
+ const unsigned X16_AliasSet[] = { PPC::R16, 0 };
+ const unsigned X17_AliasSet[] = { PPC::R17, 0 };
+ const unsigned X18_AliasSet[] = { PPC::R18, 0 };
+ const unsigned X19_AliasSet[] = { PPC::R19, 0 };
+ const unsigned X2_AliasSet[] = { PPC::R2, 0 };
+ const unsigned X20_AliasSet[] = { PPC::R20, 0 };
+ const unsigned X21_AliasSet[] = { PPC::R21, 0 };
+ const unsigned X22_AliasSet[] = { PPC::R22, 0 };
+ const unsigned X23_AliasSet[] = { PPC::R23, 0 };
+ const unsigned X24_AliasSet[] = { PPC::R24, 0 };
+ const unsigned X25_AliasSet[] = { PPC::R25, 0 };
+ const unsigned X26_AliasSet[] = { PPC::R26, 0 };
+ const unsigned X27_AliasSet[] = { PPC::R27, 0 };
+ const unsigned X28_AliasSet[] = { PPC::R28, 0 };
+ const unsigned X29_AliasSet[] = { PPC::R29, 0 };
+ const unsigned X3_AliasSet[] = { PPC::R3, 0 };
+ const unsigned X30_AliasSet[] = { PPC::R30, 0 };
+ const unsigned X31_AliasSet[] = { PPC::R31, 0 };
+ const unsigned X4_AliasSet[] = { PPC::R4, 0 };
+ const unsigned X5_AliasSet[] = { PPC::R5, 0 };
+ const unsigned X6_AliasSet[] = { PPC::R6, 0 };
+ const unsigned X7_AliasSet[] = { PPC::R7, 0 };
+ const unsigned X8_AliasSet[] = { PPC::R8, 0 };
+ const unsigned X9_AliasSet[] = { PPC::R9, 0 };
+
+
+ // Register Sub-registers Sets...
+ const unsigned Empty_SubRegsSet[] = { 0 };
+ const unsigned CARRY_SubRegsSet[] = { 0 };
+ const unsigned CR0_SubRegsSet[] = { PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 0 };
+ const unsigned CR0EQ_SubRegsSet[] = { 0 };
+ const unsigned CR0GT_SubRegsSet[] = { 0 };
+ const unsigned CR0LT_SubRegsSet[] = { 0 };
+ const unsigned CR0UN_SubRegsSet[] = { 0 };
+ const unsigned CR1_SubRegsSet[] = { PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 0 };
+ const unsigned CR1EQ_SubRegsSet[] = { 0 };
+ const unsigned CR1GT_SubRegsSet[] = { 0 };
+ const unsigned CR1LT_SubRegsSet[] = { 0 };
+ const unsigned CR1UN_SubRegsSet[] = { 0 };
+ const unsigned CR2_SubRegsSet[] = { PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 0 };
+ const unsigned CR2EQ_SubRegsSet[] = { 0 };
+ const unsigned CR2GT_SubRegsSet[] = { 0 };
+ const unsigned CR2LT_SubRegsSet[] = { 0 };
+ const unsigned CR2UN_SubRegsSet[] = { 0 };
+ const unsigned CR3_SubRegsSet[] = { PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 0 };
+ const unsigned CR3EQ_SubRegsSet[] = { 0 };
+ const unsigned CR3GT_SubRegsSet[] = { 0 };
+ const unsigned CR3LT_SubRegsSet[] = { 0 };
+ const unsigned CR3UN_SubRegsSet[] = { 0 };
+ const unsigned CR4_SubRegsSet[] = { PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 0 };
+ const unsigned CR4EQ_SubRegsSet[] = { 0 };
+ const unsigned CR4GT_SubRegsSet[] = { 0 };
+ const unsigned CR4LT_SubRegsSet[] = { 0 };
+ const unsigned CR4UN_SubRegsSet[] = { 0 };
+ const unsigned CR5_SubRegsSet[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 0 };
+ const unsigned CR5EQ_SubRegsSet[] = { 0 };
+ const unsigned CR5GT_SubRegsSet[] = { 0 };
+ const unsigned CR5LT_SubRegsSet[] = { 0 };
+ const unsigned CR5UN_SubRegsSet[] = { 0 };
+ const unsigned CR6_SubRegsSet[] = { PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 0 };
+ const unsigned CR6EQ_SubRegsSet[] = { 0 };
+ const unsigned CR6GT_SubRegsSet[] = { 0 };
+ const unsigned CR6LT_SubRegsSet[] = { 0 };
+ const unsigned CR6UN_SubRegsSet[] = { 0 };
+ const unsigned CR7_SubRegsSet[] = { PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, 0 };
+ const unsigned CR7EQ_SubRegsSet[] = { 0 };
+ const unsigned CR7GT_SubRegsSet[] = { 0 };
+ const unsigned CR7LT_SubRegsSet[] = { 0 };
+ const unsigned CR7UN_SubRegsSet[] = { 0 };
+ const unsigned CTR_SubRegsSet[] = { 0 };
+ const unsigned CTR8_SubRegsSet[] = { 0 };
+ const unsigned F0_SubRegsSet[] = { 0 };
+ const unsigned F1_SubRegsSet[] = { 0 };
+ const unsigned F10_SubRegsSet[] = { 0 };
+ const unsigned F11_SubRegsSet[] = { 0 };
+ const unsigned F12_SubRegsSet[] = { 0 };
+ const unsigned F13_SubRegsSet[] = { 0 };
+ const unsigned F14_SubRegsSet[] = { 0 };
+ const unsigned F15_SubRegsSet[] = { 0 };
+ const unsigned F16_SubRegsSet[] = { 0 };
+ const unsigned F17_SubRegsSet[] = { 0 };
+ const unsigned F18_SubRegsSet[] = { 0 };
+ const unsigned F19_SubRegsSet[] = { 0 };
+ const unsigned F2_SubRegsSet[] = { 0 };
+ const unsigned F20_SubRegsSet[] = { 0 };
+ const unsigned F21_SubRegsSet[] = { 0 };
+ const unsigned F22_SubRegsSet[] = { 0 };
+ const unsigned F23_SubRegsSet[] = { 0 };
+ const unsigned F24_SubRegsSet[] = { 0 };
+ const unsigned F25_SubRegsSet[] = { 0 };
+ const unsigned F26_SubRegsSet[] = { 0 };
+ const unsigned F27_SubRegsSet[] = { 0 };
+ const unsigned F28_SubRegsSet[] = { 0 };
+ const unsigned F29_SubRegsSet[] = { 0 };
+ const unsigned F3_SubRegsSet[] = { 0 };
+ const unsigned F30_SubRegsSet[] = { 0 };
+ const unsigned F31_SubRegsSet[] = { 0 };
+ const unsigned F4_SubRegsSet[] = { 0 };
+ const unsigned F5_SubRegsSet[] = { 0 };
+ const unsigned F6_SubRegsSet[] = { 0 };
+ const unsigned F7_SubRegsSet[] = { 0 };
+ const unsigned F8_SubRegsSet[] = { 0 };
+ const unsigned F9_SubRegsSet[] = { 0 };
+ const unsigned LR_SubRegsSet[] = { 0 };
+ const unsigned LR8_SubRegsSet[] = { 0 };
+ const unsigned R0_SubRegsSet[] = { 0 };
+ const unsigned R1_SubRegsSet[] = { 0 };
+ const unsigned R10_SubRegsSet[] = { 0 };
+ const unsigned R11_SubRegsSet[] = { 0 };
+ const unsigned R12_SubRegsSet[] = { 0 };
+ const unsigned R13_SubRegsSet[] = { 0 };
+ const unsigned R14_SubRegsSet[] = { 0 };
+ const unsigned R15_SubRegsSet[] = { 0 };
+ const unsigned R16_SubRegsSet[] = { 0 };
+ const unsigned R17_SubRegsSet[] = { 0 };
+ const unsigned R18_SubRegsSet[] = { 0 };
+ const unsigned R19_SubRegsSet[] = { 0 };
+ const unsigned R2_SubRegsSet[] = { 0 };
+ const unsigned R20_SubRegsSet[] = { 0 };
+ const unsigned R21_SubRegsSet[] = { 0 };
+ const unsigned R22_SubRegsSet[] = { 0 };
+ const unsigned R23_SubRegsSet[] = { 0 };
+ const unsigned R24_SubRegsSet[] = { 0 };
+ const unsigned R25_SubRegsSet[] = { 0 };
+ const unsigned R26_SubRegsSet[] = { 0 };
+ const unsigned R27_SubRegsSet[] = { 0 };
+ const unsigned R28_SubRegsSet[] = { 0 };
+ const unsigned R29_SubRegsSet[] = { 0 };
+ const unsigned R3_SubRegsSet[] = { 0 };
+ const unsigned R30_SubRegsSet[] = { 0 };
+ const unsigned R31_SubRegsSet[] = { 0 };
+ const unsigned R4_SubRegsSet[] = { 0 };
+ const unsigned R5_SubRegsSet[] = { 0 };
+ const unsigned R6_SubRegsSet[] = { 0 };
+ const unsigned R7_SubRegsSet[] = { 0 };
+ const unsigned R8_SubRegsSet[] = { 0 };
+ const unsigned R9_SubRegsSet[] = { 0 };
+ const unsigned RM_SubRegsSet[] = { 0 };
+ const unsigned V0_SubRegsSet[] = { 0 };
+ const unsigned V1_SubRegsSet[] = { 0 };
+ const unsigned V10_SubRegsSet[] = { 0 };
+ const unsigned V11_SubRegsSet[] = { 0 };
+ const unsigned V12_SubRegsSet[] = { 0 };
+ const unsigned V13_SubRegsSet[] = { 0 };
+ const unsigned V14_SubRegsSet[] = { 0 };
+ const unsigned V15_SubRegsSet[] = { 0 };
+ const unsigned V16_SubRegsSet[] = { 0 };
+ const unsigned V17_SubRegsSet[] = { 0 };
+ const unsigned V18_SubRegsSet[] = { 0 };
+ const unsigned V19_SubRegsSet[] = { 0 };
+ const unsigned V2_SubRegsSet[] = { 0 };
+ const unsigned V20_SubRegsSet[] = { 0 };
+ const unsigned V21_SubRegsSet[] = { 0 };
+ const unsigned V22_SubRegsSet[] = { 0 };
+ const unsigned V23_SubRegsSet[] = { 0 };
+ const unsigned V24_SubRegsSet[] = { 0 };
+ const unsigned V25_SubRegsSet[] = { 0 };
+ const unsigned V26_SubRegsSet[] = { 0 };
+ const unsigned V27_SubRegsSet[] = { 0 };
+ const unsigned V28_SubRegsSet[] = { 0 };
+ const unsigned V29_SubRegsSet[] = { 0 };
+ const unsigned V3_SubRegsSet[] = { 0 };
+ const unsigned V30_SubRegsSet[] = { 0 };
+ const unsigned V31_SubRegsSet[] = { 0 };
+ const unsigned V4_SubRegsSet[] = { 0 };
+ const unsigned V5_SubRegsSet[] = { 0 };
+ const unsigned V6_SubRegsSet[] = { 0 };
+ const unsigned V7_SubRegsSet[] = { 0 };
+ const unsigned V8_SubRegsSet[] = { 0 };
+ const unsigned V9_SubRegsSet[] = { 0 };
+ const unsigned VRSAVE_SubRegsSet[] = { 0 };
+ const unsigned X0_SubRegsSet[] = { PPC::R0, 0 };
+ const unsigned X1_SubRegsSet[] = { PPC::R1, 0 };
+ const unsigned X10_SubRegsSet[] = { PPC::R10, 0 };
+ const unsigned X11_SubRegsSet[] = { PPC::R11, 0 };
+ const unsigned X12_SubRegsSet[] = { PPC::R12, 0 };
+ const unsigned X13_SubRegsSet[] = { PPC::R13, 0 };
+ const unsigned X14_SubRegsSet[] = { PPC::R14, 0 };
+ const unsigned X15_SubRegsSet[] = { PPC::R15, 0 };
+ const unsigned X16_SubRegsSet[] = { PPC::R16, 0 };
+ const unsigned X17_SubRegsSet[] = { PPC::R17, 0 };
+ const unsigned X18_SubRegsSet[] = { PPC::R18, 0 };
+ const unsigned X19_SubRegsSet[] = { PPC::R19, 0 };
+ const unsigned X2_SubRegsSet[] = { PPC::R2, 0 };
+ const unsigned X20_SubRegsSet[] = { PPC::R20, 0 };
+ const unsigned X21_SubRegsSet[] = { PPC::R21, 0 };
+ const unsigned X22_SubRegsSet[] = { PPC::R22, 0 };
+ const unsigned X23_SubRegsSet[] = { PPC::R23, 0 };
+ const unsigned X24_SubRegsSet[] = { PPC::R24, 0 };
+ const unsigned X25_SubRegsSet[] = { PPC::R25, 0 };
+ const unsigned X26_SubRegsSet[] = { PPC::R26, 0 };
+ const unsigned X27_SubRegsSet[] = { PPC::R27, 0 };
+ const unsigned X28_SubRegsSet[] = { PPC::R28, 0 };
+ const unsigned X29_SubRegsSet[] = { PPC::R29, 0 };
+ const unsigned X3_SubRegsSet[] = { PPC::R3, 0 };
+ const unsigned X30_SubRegsSet[] = { PPC::R30, 0 };
+ const unsigned X31_SubRegsSet[] = { PPC::R31, 0 };
+ const unsigned X4_SubRegsSet[] = { PPC::R4, 0 };
+ const unsigned X5_SubRegsSet[] = { PPC::R5, 0 };
+ const unsigned X6_SubRegsSet[] = { PPC::R6, 0 };
+ const unsigned X7_SubRegsSet[] = { PPC::R7, 0 };
+ const unsigned X8_SubRegsSet[] = { PPC::R8, 0 };
+ const unsigned X9_SubRegsSet[] = { PPC::R9, 0 };
+
+
+ // Register Super-registers Sets...
+ const unsigned Empty_SuperRegsSet[] = { 0 };
+ const unsigned CARRY_SuperRegsSet[] = { 0 };
+ const unsigned CR0_SuperRegsSet[] = { 0 };
+ const unsigned CR0EQ_SuperRegsSet[] = { PPC::CR0, 0 };
+ const unsigned CR0GT_SuperRegsSet[] = { PPC::CR0, 0 };
+ const unsigned CR0LT_SuperRegsSet[] = { PPC::CR0, 0 };
+ const unsigned CR0UN_SuperRegsSet[] = { PPC::CR0, 0 };
+ const unsigned CR1_SuperRegsSet[] = { 0 };
+ const unsigned CR1EQ_SuperRegsSet[] = { PPC::CR1, 0 };
+ const unsigned CR1GT_SuperRegsSet[] = { PPC::CR1, 0 };
+ const unsigned CR1LT_SuperRegsSet[] = { PPC::CR1, 0 };
+ const unsigned CR1UN_SuperRegsSet[] = { PPC::CR1, 0 };
+ const unsigned CR2_SuperRegsSet[] = { 0 };
+ const unsigned CR2EQ_SuperRegsSet[] = { PPC::CR2, 0 };
+ const unsigned CR2GT_SuperRegsSet[] = { PPC::CR2, 0 };
+ const unsigned CR2LT_SuperRegsSet[] = { PPC::CR2, 0 };
+ const unsigned CR2UN_SuperRegsSet[] = { PPC::CR2, 0 };
+ const unsigned CR3_SuperRegsSet[] = { 0 };
+ const unsigned CR3EQ_SuperRegsSet[] = { PPC::CR3, 0 };
+ const unsigned CR3GT_SuperRegsSet[] = { PPC::CR3, 0 };
+ const unsigned CR3LT_SuperRegsSet[] = { PPC::CR3, 0 };
+ const unsigned CR3UN_SuperRegsSet[] = { PPC::CR3, 0 };
+ const unsigned CR4_SuperRegsSet[] = { 0 };
+ const unsigned CR4EQ_SuperRegsSet[] = { PPC::CR4, 0 };
+ const unsigned CR4GT_SuperRegsSet[] = { PPC::CR4, 0 };
+ const unsigned CR4LT_SuperRegsSet[] = { PPC::CR4, 0 };
+ const unsigned CR4UN_SuperRegsSet[] = { PPC::CR4, 0 };
+ const unsigned CR5_SuperRegsSet[] = { 0 };
+ const unsigned CR5EQ_SuperRegsSet[] = { PPC::CR5, 0 };
+ const unsigned CR5GT_SuperRegsSet[] = { PPC::CR5, 0 };
+ const unsigned CR5LT_SuperRegsSet[] = { PPC::CR5, 0 };
+ const unsigned CR5UN_SuperRegsSet[] = { PPC::CR5, 0 };
+ const unsigned CR6_SuperRegsSet[] = { 0 };
+ const unsigned CR6EQ_SuperRegsSet[] = { PPC::CR6, 0 };
+ const unsigned CR6GT_SuperRegsSet[] = { PPC::CR6, 0 };
+ const unsigned CR6LT_SuperRegsSet[] = { PPC::CR6, 0 };
+ const unsigned CR6UN_SuperRegsSet[] = { PPC::CR6, 0 };
+ const unsigned CR7_SuperRegsSet[] = { 0 };
+ const unsigned CR7EQ_SuperRegsSet[] = { PPC::CR7, 0 };
+ const unsigned CR7GT_SuperRegsSet[] = { PPC::CR7, 0 };
+ const unsigned CR7LT_SuperRegsSet[] = { PPC::CR7, 0 };
+ const unsigned CR7UN_SuperRegsSet[] = { PPC::CR7, 0 };
+ const unsigned CTR_SuperRegsSet[] = { 0 };
+ const unsigned CTR8_SuperRegsSet[] = { 0 };
+ const unsigned F0_SuperRegsSet[] = { 0 };
+ const unsigned F1_SuperRegsSet[] = { 0 };
+ const unsigned F10_SuperRegsSet[] = { 0 };
+ const unsigned F11_SuperRegsSet[] = { 0 };
+ const unsigned F12_SuperRegsSet[] = { 0 };
+ const unsigned F13_SuperRegsSet[] = { 0 };
+ const unsigned F14_SuperRegsSet[] = { 0 };
+ const unsigned F15_SuperRegsSet[] = { 0 };
+ const unsigned F16_SuperRegsSet[] = { 0 };
+ const unsigned F17_SuperRegsSet[] = { 0 };
+ const unsigned F18_SuperRegsSet[] = { 0 };
+ const unsigned F19_SuperRegsSet[] = { 0 };
+ const unsigned F2_SuperRegsSet[] = { 0 };
+ const unsigned F20_SuperRegsSet[] = { 0 };
+ const unsigned F21_SuperRegsSet[] = { 0 };
+ const unsigned F22_SuperRegsSet[] = { 0 };
+ const unsigned F23_SuperRegsSet[] = { 0 };
+ const unsigned F24_SuperRegsSet[] = { 0 };
+ const unsigned F25_SuperRegsSet[] = { 0 };
+ const unsigned F26_SuperRegsSet[] = { 0 };
+ const unsigned F27_SuperRegsSet[] = { 0 };
+ const unsigned F28_SuperRegsSet[] = { 0 };
+ const unsigned F29_SuperRegsSet[] = { 0 };
+ const unsigned F3_SuperRegsSet[] = { 0 };
+ const unsigned F30_SuperRegsSet[] = { 0 };
+ const unsigned F31_SuperRegsSet[] = { 0 };
+ const unsigned F4_SuperRegsSet[] = { 0 };
+ const unsigned F5_SuperRegsSet[] = { 0 };
+ const unsigned F6_SuperRegsSet[] = { 0 };
+ const unsigned F7_SuperRegsSet[] = { 0 };
+ const unsigned F8_SuperRegsSet[] = { 0 };
+ const unsigned F9_SuperRegsSet[] = { 0 };
+ const unsigned LR_SuperRegsSet[] = { 0 };
+ const unsigned LR8_SuperRegsSet[] = { 0 };
+ const unsigned R0_SuperRegsSet[] = { PPC::X0, 0 };
+ const unsigned R1_SuperRegsSet[] = { PPC::X1, 0 };
+ const unsigned R10_SuperRegsSet[] = { PPC::X10, 0 };
+ const unsigned R11_SuperRegsSet[] = { PPC::X11, 0 };
+ const unsigned R12_SuperRegsSet[] = { PPC::X12, 0 };
+ const unsigned R13_SuperRegsSet[] = { PPC::X13, 0 };
+ const unsigned R14_SuperRegsSet[] = { PPC::X14, 0 };
+ const unsigned R15_SuperRegsSet[] = { PPC::X15, 0 };
+ const unsigned R16_SuperRegsSet[] = { PPC::X16, 0 };
+ const unsigned R17_SuperRegsSet[] = { PPC::X17, 0 };
+ const unsigned R18_SuperRegsSet[] = { PPC::X18, 0 };
+ const unsigned R19_SuperRegsSet[] = { PPC::X19, 0 };
+ const unsigned R2_SuperRegsSet[] = { PPC::X2, 0 };
+ const unsigned R20_SuperRegsSet[] = { PPC::X20, 0 };
+ const unsigned R21_SuperRegsSet[] = { PPC::X21, 0 };
+ const unsigned R22_SuperRegsSet[] = { PPC::X22, 0 };
+ const unsigned R23_SuperRegsSet[] = { PPC::X23, 0 };
+ const unsigned R24_SuperRegsSet[] = { PPC::X24, 0 };
+ const unsigned R25_SuperRegsSet[] = { PPC::X25, 0 };
+ const unsigned R26_SuperRegsSet[] = { PPC::X26, 0 };
+ const unsigned R27_SuperRegsSet[] = { PPC::X27, 0 };
+ const unsigned R28_SuperRegsSet[] = { PPC::X28, 0 };
+ const unsigned R29_SuperRegsSet[] = { PPC::X29, 0 };
+ const unsigned R3_SuperRegsSet[] = { PPC::X3, 0 };
+ const unsigned R30_SuperRegsSet[] = { PPC::X30, 0 };
+ const unsigned R31_SuperRegsSet[] = { PPC::X31, 0 };
+ const unsigned R4_SuperRegsSet[] = { PPC::X4, 0 };
+ const unsigned R5_SuperRegsSet[] = { PPC::X5, 0 };
+ const unsigned R6_SuperRegsSet[] = { PPC::X6, 0 };
+ const unsigned R7_SuperRegsSet[] = { PPC::X7, 0 };
+ const unsigned R8_SuperRegsSet[] = { PPC::X8, 0 };
+ const unsigned R9_SuperRegsSet[] = { PPC::X9, 0 };
+ const unsigned RM_SuperRegsSet[] = { 0 };
+ const unsigned V0_SuperRegsSet[] = { 0 };
+ const unsigned V1_SuperRegsSet[] = { 0 };
+ const unsigned V10_SuperRegsSet[] = { 0 };
+ const unsigned V11_SuperRegsSet[] = { 0 };
+ const unsigned V12_SuperRegsSet[] = { 0 };
+ const unsigned V13_SuperRegsSet[] = { 0 };
+ const unsigned V14_SuperRegsSet[] = { 0 };
+ const unsigned V15_SuperRegsSet[] = { 0 };
+ const unsigned V16_SuperRegsSet[] = { 0 };
+ const unsigned V17_SuperRegsSet[] = { 0 };
+ const unsigned V18_SuperRegsSet[] = { 0 };
+ const unsigned V19_SuperRegsSet[] = { 0 };
+ const unsigned V2_SuperRegsSet[] = { 0 };
+ const unsigned V20_SuperRegsSet[] = { 0 };
+ const unsigned V21_SuperRegsSet[] = { 0 };
+ const unsigned V22_SuperRegsSet[] = { 0 };
+ const unsigned V23_SuperRegsSet[] = { 0 };
+ const unsigned V24_SuperRegsSet[] = { 0 };
+ const unsigned V25_SuperRegsSet[] = { 0 };
+ const unsigned V26_SuperRegsSet[] = { 0 };
+ const unsigned V27_SuperRegsSet[] = { 0 };
+ const unsigned V28_SuperRegsSet[] = { 0 };
+ const unsigned V29_SuperRegsSet[] = { 0 };
+ const unsigned V3_SuperRegsSet[] = { 0 };
+ const unsigned V30_SuperRegsSet[] = { 0 };
+ const unsigned V31_SuperRegsSet[] = { 0 };
+ const unsigned V4_SuperRegsSet[] = { 0 };
+ const unsigned V5_SuperRegsSet[] = { 0 };
+ const unsigned V6_SuperRegsSet[] = { 0 };
+ const unsigned V7_SuperRegsSet[] = { 0 };
+ const unsigned V8_SuperRegsSet[] = { 0 };
+ const unsigned V9_SuperRegsSet[] = { 0 };
+ const unsigned VRSAVE_SuperRegsSet[] = { 0 };
+ const unsigned X0_SuperRegsSet[] = { 0 };
+ const unsigned X1_SuperRegsSet[] = { 0 };
+ const unsigned X10_SuperRegsSet[] = { 0 };
+ const unsigned X11_SuperRegsSet[] = { 0 };
+ const unsigned X12_SuperRegsSet[] = { 0 };
+ const unsigned X13_SuperRegsSet[] = { 0 };
+ const unsigned X14_SuperRegsSet[] = { 0 };
+ const unsigned X15_SuperRegsSet[] = { 0 };
+ const unsigned X16_SuperRegsSet[] = { 0 };
+ const unsigned X17_SuperRegsSet[] = { 0 };
+ const unsigned X18_SuperRegsSet[] = { 0 };
+ const unsigned X19_SuperRegsSet[] = { 0 };
+ const unsigned X2_SuperRegsSet[] = { 0 };
+ const unsigned X20_SuperRegsSet[] = { 0 };
+ const unsigned X21_SuperRegsSet[] = { 0 };
+ const unsigned X22_SuperRegsSet[] = { 0 };
+ const unsigned X23_SuperRegsSet[] = { 0 };
+ const unsigned X24_SuperRegsSet[] = { 0 };
+ const unsigned X25_SuperRegsSet[] = { 0 };
+ const unsigned X26_SuperRegsSet[] = { 0 };
+ const unsigned X27_SuperRegsSet[] = { 0 };
+ const unsigned X28_SuperRegsSet[] = { 0 };
+ const unsigned X29_SuperRegsSet[] = { 0 };
+ const unsigned X3_SuperRegsSet[] = { 0 };
+ const unsigned X30_SuperRegsSet[] = { 0 };
+ const unsigned X31_SuperRegsSet[] = { 0 };
+ const unsigned X4_SuperRegsSet[] = { 0 };
+ const unsigned X5_SuperRegsSet[] = { 0 };
+ const unsigned X6_SuperRegsSet[] = { 0 };
+ const unsigned X7_SuperRegsSet[] = { 0 };
+ const unsigned X8_SuperRegsSet[] = { 0 };
+ const unsigned X9_SuperRegsSet[] = { 0 };
+
+ const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors
+ { "NOREG", 0, 0, 0 },
+ { "CARRY", CARRY_AliasSet, CARRY_SubRegsSet, CARRY_SuperRegsSet },
+ { "CR0", CR0_AliasSet, CR0_SubRegsSet, CR0_SuperRegsSet },
+ { "CR0EQ", CR0EQ_AliasSet, CR0EQ_SubRegsSet, CR0EQ_SuperRegsSet },
+ { "CR0GT", CR0GT_AliasSet, CR0GT_SubRegsSet, CR0GT_SuperRegsSet },
+ { "CR0LT", CR0LT_AliasSet, CR0LT_SubRegsSet, CR0LT_SuperRegsSet },
+ { "CR0UN", CR0UN_AliasSet, CR0UN_SubRegsSet, CR0UN_SuperRegsSet },
+ { "CR1", CR1_AliasSet, CR1_SubRegsSet, CR1_SuperRegsSet },
+ { "CR1EQ", CR1EQ_AliasSet, CR1EQ_SubRegsSet, CR1EQ_SuperRegsSet },
+ { "CR1GT", CR1GT_AliasSet, CR1GT_SubRegsSet, CR1GT_SuperRegsSet },
+ { "CR1LT", CR1LT_AliasSet, CR1LT_SubRegsSet, CR1LT_SuperRegsSet },
+ { "CR1UN", CR1UN_AliasSet, CR1UN_SubRegsSet, CR1UN_SuperRegsSet },
+ { "CR2", CR2_AliasSet, CR2_SubRegsSet, CR2_SuperRegsSet },
+ { "CR2EQ", CR2EQ_AliasSet, CR2EQ_SubRegsSet, CR2EQ_SuperRegsSet },
+ { "CR2GT", CR2GT_AliasSet, CR2GT_SubRegsSet, CR2GT_SuperRegsSet },
+ { "CR2LT", CR2LT_AliasSet, CR2LT_SubRegsSet, CR2LT_SuperRegsSet },
+ { "CR2UN", CR2UN_AliasSet, CR2UN_SubRegsSet, CR2UN_SuperRegsSet },
+ { "CR3", CR3_AliasSet, CR3_SubRegsSet, CR3_SuperRegsSet },
+ { "CR3EQ", CR3EQ_AliasSet, CR3EQ_SubRegsSet, CR3EQ_SuperRegsSet },
+ { "CR3GT", CR3GT_AliasSet, CR3GT_SubRegsSet, CR3GT_SuperRegsSet },
+ { "CR3LT", CR3LT_AliasSet, CR3LT_SubRegsSet, CR3LT_SuperRegsSet },
+ { "CR3UN", CR3UN_AliasSet, CR3UN_SubRegsSet, CR3UN_SuperRegsSet },
+ { "CR4", CR4_AliasSet, CR4_SubRegsSet, CR4_SuperRegsSet },
+ { "CR4EQ", CR4EQ_AliasSet, CR4EQ_SubRegsSet, CR4EQ_SuperRegsSet },
+ { "CR4GT", CR4GT_AliasSet, CR4GT_SubRegsSet, CR4GT_SuperRegsSet },
+ { "CR4LT", CR4LT_AliasSet, CR4LT_SubRegsSet, CR4LT_SuperRegsSet },
+ { "CR4UN", CR4UN_AliasSet, CR4UN_SubRegsSet, CR4UN_SuperRegsSet },
+ { "CR5", CR5_AliasSet, CR5_SubRegsSet, CR5_SuperRegsSet },
+ { "CR5EQ", CR5EQ_AliasSet, CR5EQ_SubRegsSet, CR5EQ_SuperRegsSet },
+ { "CR5GT", CR5GT_AliasSet, CR5GT_SubRegsSet, CR5GT_SuperRegsSet },
+ { "CR5LT", CR5LT_AliasSet, CR5LT_SubRegsSet, CR5LT_SuperRegsSet },
+ { "CR5UN", CR5UN_AliasSet, CR5UN_SubRegsSet, CR5UN_SuperRegsSet },
+ { "CR6", CR6_AliasSet, CR6_SubRegsSet, CR6_SuperRegsSet },
+ { "CR6EQ", CR6EQ_AliasSet, CR6EQ_SubRegsSet, CR6EQ_SuperRegsSet },
+ { "CR6GT", CR6GT_AliasSet, CR6GT_SubRegsSet, CR6GT_SuperRegsSet },
+ { "CR6LT", CR6LT_AliasSet, CR6LT_SubRegsSet, CR6LT_SuperRegsSet },
+ { "CR6UN", CR6UN_AliasSet, CR6UN_SubRegsSet, CR6UN_SuperRegsSet },
+ { "CR7", CR7_AliasSet, CR7_SubRegsSet, CR7_SuperRegsSet },
+ { "CR7EQ", CR7EQ_AliasSet, CR7EQ_SubRegsSet, CR7EQ_SuperRegsSet },
+ { "CR7GT", CR7GT_AliasSet, CR7GT_SubRegsSet, CR7GT_SuperRegsSet },
+ { "CR7LT", CR7LT_AliasSet, CR7LT_SubRegsSet, CR7LT_SuperRegsSet },
+ { "CR7UN", CR7UN_AliasSet, CR7UN_SubRegsSet, CR7UN_SuperRegsSet },
+ { "CTR", CTR_AliasSet, CTR_SubRegsSet, CTR_SuperRegsSet },
+ { "CTR8", CTR8_AliasSet, CTR8_SubRegsSet, CTR8_SuperRegsSet },
+ { "F0", F0_AliasSet, F0_SubRegsSet, F0_SuperRegsSet },
+ { "F1", F1_AliasSet, F1_SubRegsSet, F1_SuperRegsSet },
+ { "F10", F10_AliasSet, F10_SubRegsSet, F10_SuperRegsSet },
+ { "F11", F11_AliasSet, F11_SubRegsSet, F11_SuperRegsSet },
+ { "F12", F12_AliasSet, F12_SubRegsSet, F12_SuperRegsSet },
+ { "F13", F13_AliasSet, F13_SubRegsSet, F13_SuperRegsSet },
+ { "F14", F14_AliasSet, F14_SubRegsSet, F14_SuperRegsSet },
+ { "F15", F15_AliasSet, F15_SubRegsSet, F15_SuperRegsSet },
+ { "F16", F16_AliasSet, F16_SubRegsSet, F16_SuperRegsSet },
+ { "F17", F17_AliasSet, F17_SubRegsSet, F17_SuperRegsSet },
+ { "F18", F18_AliasSet, F18_SubRegsSet, F18_SuperRegsSet },
+ { "F19", F19_AliasSet, F19_SubRegsSet, F19_SuperRegsSet },
+ { "F2", F2_AliasSet, F2_SubRegsSet, F2_SuperRegsSet },
+ { "F20", F20_AliasSet, F20_SubRegsSet, F20_SuperRegsSet },
+ { "F21", F21_AliasSet, F21_SubRegsSet, F21_SuperRegsSet },
+ { "F22", F22_AliasSet, F22_SubRegsSet, F22_SuperRegsSet },
+ { "F23", F23_AliasSet, F23_SubRegsSet, F23_SuperRegsSet },
+ { "F24", F24_AliasSet, F24_SubRegsSet, F24_SuperRegsSet },
+ { "F25", F25_AliasSet, F25_SubRegsSet, F25_SuperRegsSet },
+ { "F26", F26_AliasSet, F26_SubRegsSet, F26_SuperRegsSet },
+ { "F27", F27_AliasSet, F27_SubRegsSet, F27_SuperRegsSet },
+ { "F28", F28_AliasSet, F28_SubRegsSet, F28_SuperRegsSet },
+ { "F29", F29_AliasSet, F29_SubRegsSet, F29_SuperRegsSet },
+ { "F3", F3_AliasSet, F3_SubRegsSet, F3_SuperRegsSet },
+ { "F30", F30_AliasSet, F30_SubRegsSet, F30_SuperRegsSet },
+ { "F31", F31_AliasSet, F31_SubRegsSet, F31_SuperRegsSet },
+ { "F4", F4_AliasSet, F4_SubRegsSet, F4_SuperRegsSet },
+ { "F5", F5_AliasSet, F5_SubRegsSet, F5_SuperRegsSet },
+ { "F6", F6_AliasSet, F6_SubRegsSet, F6_SuperRegsSet },
+ { "F7", F7_AliasSet, F7_SubRegsSet, F7_SuperRegsSet },
+ { "F8", F8_AliasSet, F8_SubRegsSet, F8_SuperRegsSet },
+ { "F9", F9_AliasSet, F9_SubRegsSet, F9_SuperRegsSet },
+ { "LR", LR_AliasSet, LR_SubRegsSet, LR_SuperRegsSet },
+ { "LR8", LR8_AliasSet, LR8_SubRegsSet, LR8_SuperRegsSet },
+ { "R0", R0_AliasSet, R0_SubRegsSet, R0_SuperRegsSet },
+ { "R1", R1_AliasSet, R1_SubRegsSet, R1_SuperRegsSet },
+ { "R10", R10_AliasSet, R10_SubRegsSet, R10_SuperRegsSet },
+ { "R11", R11_AliasSet, R11_SubRegsSet, R11_SuperRegsSet },
+ { "R12", R12_AliasSet, R12_SubRegsSet, R12_SuperRegsSet },
+ { "R13", R13_AliasSet, R13_SubRegsSet, R13_SuperRegsSet },
+ { "R14", R14_AliasSet, R14_SubRegsSet, R14_SuperRegsSet },
+ { "R15", R15_AliasSet, R15_SubRegsSet, R15_SuperRegsSet },
+ { "R16", R16_AliasSet, R16_SubRegsSet, R16_SuperRegsSet },
+ { "R17", R17_AliasSet, R17_SubRegsSet, R17_SuperRegsSet },
+ { "R18", R18_AliasSet, R18_SubRegsSet, R18_SuperRegsSet },
+ { "R19", R19_AliasSet, R19_SubRegsSet, R19_SuperRegsSet },
+ { "R2", R2_AliasSet, R2_SubRegsSet, R2_SuperRegsSet },
+ { "R20", R20_AliasSet, R20_SubRegsSet, R20_SuperRegsSet },
+ { "R21", R21_AliasSet, R21_SubRegsSet, R21_SuperRegsSet },
+ { "R22", R22_AliasSet, R22_SubRegsSet, R22_SuperRegsSet },
+ { "R23", R23_AliasSet, R23_SubRegsSet, R23_SuperRegsSet },
+ { "R24", R24_AliasSet, R24_SubRegsSet, R24_SuperRegsSet },
+ { "R25", R25_AliasSet, R25_SubRegsSet, R25_SuperRegsSet },
+ { "R26", R26_AliasSet, R26_SubRegsSet, R26_SuperRegsSet },
+ { "R27", R27_AliasSet, R27_SubRegsSet, R27_SuperRegsSet },
+ { "R28", R28_AliasSet, R28_SubRegsSet, R28_SuperRegsSet },
+ { "R29", R29_AliasSet, R29_SubRegsSet, R29_SuperRegsSet },
+ { "R3", R3_AliasSet, R3_SubRegsSet, R3_SuperRegsSet },
+ { "R30", R30_AliasSet, R30_SubRegsSet, R30_SuperRegsSet },
+ { "R31", R31_AliasSet, R31_SubRegsSet, R31_SuperRegsSet },
+ { "R4", R4_AliasSet, R4_SubRegsSet, R4_SuperRegsSet },
+ { "R5", R5_AliasSet, R5_SubRegsSet, R5_SuperRegsSet },
+ { "R6", R6_AliasSet, R6_SubRegsSet, R6_SuperRegsSet },
+ { "R7", R7_AliasSet, R7_SubRegsSet, R7_SuperRegsSet },
+ { "R8", R8_AliasSet, R8_SubRegsSet, R8_SuperRegsSet },
+ { "R9", R9_AliasSet, R9_SubRegsSet, R9_SuperRegsSet },
+ { "RM", RM_AliasSet, RM_SubRegsSet, RM_SuperRegsSet },
+ { "V0", V0_AliasSet, V0_SubRegsSet, V0_SuperRegsSet },
+ { "V1", V1_AliasSet, V1_SubRegsSet, V1_SuperRegsSet },
+ { "V10", V10_AliasSet, V10_SubRegsSet, V10_SuperRegsSet },
+ { "V11", V11_AliasSet, V11_SubRegsSet, V11_SuperRegsSet },
+ { "V12", V12_AliasSet, V12_SubRegsSet, V12_SuperRegsSet },
+ { "V13", V13_AliasSet, V13_SubRegsSet, V13_SuperRegsSet },
+ { "V14", V14_AliasSet, V14_SubRegsSet, V14_SuperRegsSet },
+ { "V15", V15_AliasSet, V15_SubRegsSet, V15_SuperRegsSet },
+ { "V16", V16_AliasSet, V16_SubRegsSet, V16_SuperRegsSet },
+ { "V17", V17_AliasSet, V17_SubRegsSet, V17_SuperRegsSet },
+ { "V18", V18_AliasSet, V18_SubRegsSet, V18_SuperRegsSet },
+ { "V19", V19_AliasSet, V19_SubRegsSet, V19_SuperRegsSet },
+ { "V2", V2_AliasSet, V2_SubRegsSet, V2_SuperRegsSet },
+ { "V20", V20_AliasSet, V20_SubRegsSet, V20_SuperRegsSet },
+ { "V21", V21_AliasSet, V21_SubRegsSet, V21_SuperRegsSet },
+ { "V22", V22_AliasSet, V22_SubRegsSet, V22_SuperRegsSet },
+ { "V23", V23_AliasSet, V23_SubRegsSet, V23_SuperRegsSet },
+ { "V24", V24_AliasSet, V24_SubRegsSet, V24_SuperRegsSet },
+ { "V25", V25_AliasSet, V25_SubRegsSet, V25_SuperRegsSet },
+ { "V26", V26_AliasSet, V26_SubRegsSet, V26_SuperRegsSet },
+ { "V27", V27_AliasSet, V27_SubRegsSet, V27_SuperRegsSet },
+ { "V28", V28_AliasSet, V28_SubRegsSet, V28_SuperRegsSet },
+ { "V29", V29_AliasSet, V29_SubRegsSet, V29_SuperRegsSet },
+ { "V3", V3_AliasSet, V3_SubRegsSet, V3_SuperRegsSet },
+ { "V30", V30_AliasSet, V30_SubRegsSet, V30_SuperRegsSet },
+ { "V31", V31_AliasSet, V31_SubRegsSet, V31_SuperRegsSet },
+ { "V4", V4_AliasSet, V4_SubRegsSet, V4_SuperRegsSet },
+ { "V5", V5_AliasSet, V5_SubRegsSet, V5_SuperRegsSet },
+ { "V6", V6_AliasSet, V6_SubRegsSet, V6_SuperRegsSet },
+ { "V7", V7_AliasSet, V7_SubRegsSet, V7_SuperRegsSet },
+ { "V8", V8_AliasSet, V8_SubRegsSet, V8_SuperRegsSet },
+ { "V9", V9_AliasSet, V9_SubRegsSet, V9_SuperRegsSet },
+ { "VRSAVE", VRSAVE_AliasSet, VRSAVE_SubRegsSet, VRSAVE_SuperRegsSet },
+ { "X0", X0_AliasSet, X0_SubRegsSet, X0_SuperRegsSet },
+ { "X1", X1_AliasSet, X1_SubRegsSet, X1_SuperRegsSet },
+ { "X10", X10_AliasSet, X10_SubRegsSet, X10_SuperRegsSet },
+ { "X11", X11_AliasSet, X11_SubRegsSet, X11_SuperRegsSet },
+ { "X12", X12_AliasSet, X12_SubRegsSet, X12_SuperRegsSet },
+ { "X13", X13_AliasSet, X13_SubRegsSet, X13_SuperRegsSet },
+ { "X14", X14_AliasSet, X14_SubRegsSet, X14_SuperRegsSet },
+ { "X15", X15_AliasSet, X15_SubRegsSet, X15_SuperRegsSet },
+ { "X16", X16_AliasSet, X16_SubRegsSet, X16_SuperRegsSet },
+ { "X17", X17_AliasSet, X17_SubRegsSet, X17_SuperRegsSet },
+ { "X18", X18_AliasSet, X18_SubRegsSet, X18_SuperRegsSet },
+ { "X19", X19_AliasSet, X19_SubRegsSet, X19_SuperRegsSet },
+ { "X2", X2_AliasSet, X2_SubRegsSet, X2_SuperRegsSet },
+ { "X20", X20_AliasSet, X20_SubRegsSet, X20_SuperRegsSet },
+ { "X21", X21_AliasSet, X21_SubRegsSet, X21_SuperRegsSet },
+ { "X22", X22_AliasSet, X22_SubRegsSet, X22_SuperRegsSet },
+ { "X23", X23_AliasSet, X23_SubRegsSet, X23_SuperRegsSet },
+ { "X24", X24_AliasSet, X24_SubRegsSet, X24_SuperRegsSet },
+ { "X25", X25_AliasSet, X25_SubRegsSet, X25_SuperRegsSet },
+ { "X26", X26_AliasSet, X26_SubRegsSet, X26_SuperRegsSet },
+ { "X27", X27_AliasSet, X27_SubRegsSet, X27_SuperRegsSet },
+ { "X28", X28_AliasSet, X28_SubRegsSet, X28_SuperRegsSet },
+ { "X29", X29_AliasSet, X29_SubRegsSet, X29_SuperRegsSet },
+ { "X3", X3_AliasSet, X3_SubRegsSet, X3_SuperRegsSet },
+ { "X30", X30_AliasSet, X30_SubRegsSet, X30_SuperRegsSet },
+ { "X31", X31_AliasSet, X31_SubRegsSet, X31_SuperRegsSet },
+ { "X4", X4_AliasSet, X4_SubRegsSet, X4_SuperRegsSet },
+ { "X5", X5_AliasSet, X5_SubRegsSet, X5_SuperRegsSet },
+ { "X6", X6_AliasSet, X6_SubRegsSet, X6_SuperRegsSet },
+ { "X7", X7_AliasSet, X7_SubRegsSet, X7_SuperRegsSet },
+ { "X8", X8_AliasSet, X8_SubRegsSet, X8_SuperRegsSet },
+ { "X9", X9_AliasSet, X9_SubRegsSet, X9_SuperRegsSet },
+ };
+}
+
+unsigned PPCGenRegisterInfo::getSubReg(unsigned RegNo, unsigned Index) const {
+ switch (RegNo) {
+ default:
+ return 0;
+ case PPC::CR0:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR0LT;
+ case 2: return PPC::CR0GT;
+ case 3: return PPC::CR0EQ;
+ case 4: return PPC::CR0UN;
+ };
+ break;
+ case PPC::CR1:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR1LT;
+ case 2: return PPC::CR1GT;
+ case 3: return PPC::CR1EQ;
+ case 4: return PPC::CR1UN;
+ };
+ break;
+ case PPC::CR2:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR2LT;
+ case 2: return PPC::CR2GT;
+ case 3: return PPC::CR2EQ;
+ case 4: return PPC::CR2UN;
+ };
+ break;
+ case PPC::CR3:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR3LT;
+ case 2: return PPC::CR3GT;
+ case 3: return PPC::CR3EQ;
+ case 4: return PPC::CR3UN;
+ };
+ break;
+ case PPC::CR4:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR4LT;
+ case 2: return PPC::CR4GT;
+ case 3: return PPC::CR4EQ;
+ case 4: return PPC::CR4UN;
+ };
+ break;
+ case PPC::CR5:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR5LT;
+ case 2: return PPC::CR5GT;
+ case 3: return PPC::CR5EQ;
+ case 4: return PPC::CR5UN;
+ };
+ break;
+ case PPC::CR6:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR6LT;
+ case 2: return PPC::CR6GT;
+ case 3: return PPC::CR6EQ;
+ case 4: return PPC::CR6UN;
+ };
+ break;
+ case PPC::CR7:
+ switch (Index) {
+ default: return 0;
+ case 1: return PPC::CR7LT;
+ case 2: return PPC::CR7GT;
+ case 3: return PPC::CR7EQ;
+ case 4: return PPC::CR7UN;
+ };
+ break;
+ };
+ return 0;
+}
+
+unsigned PPCGenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
+ switch (RegNo) {
+ default:
+ return 0;
+ case PPC::CR0:
+ if (SubRegNo == PPC::CR0LT) return 1;
+ if (SubRegNo == PPC::CR0GT) return 2;
+ if (SubRegNo == PPC::CR0EQ) return 3;
+ if (SubRegNo == PPC::CR0UN) return 4;
+ return 0;
+ case PPC::CR1:
+ if (SubRegNo == PPC::CR1LT) return 1;
+ if (SubRegNo == PPC::CR1GT) return 2;
+ if (SubRegNo == PPC::CR1EQ) return 3;
+ if (SubRegNo == PPC::CR1UN) return 4;
+ return 0;
+ case PPC::CR2:
+ if (SubRegNo == PPC::CR2LT) return 1;
+ if (SubRegNo == PPC::CR2GT) return 2;
+ if (SubRegNo == PPC::CR2EQ) return 3;
+ if (SubRegNo == PPC::CR2UN) return 4;
+ return 0;
+ case PPC::CR3:
+ if (SubRegNo == PPC::CR3LT) return 1;
+ if (SubRegNo == PPC::CR3GT) return 2;
+ if (SubRegNo == PPC::CR3EQ) return 3;
+ if (SubRegNo == PPC::CR3UN) return 4;
+ return 0;
+ case PPC::CR4:
+ if (SubRegNo == PPC::CR4LT) return 1;
+ if (SubRegNo == PPC::CR4GT) return 2;
+ if (SubRegNo == PPC::CR4EQ) return 3;
+ if (SubRegNo == PPC::CR4UN) return 4;
+ return 0;
+ case PPC::CR5:
+ if (SubRegNo == PPC::CR5LT) return 1;
+ if (SubRegNo == PPC::CR5GT) return 2;
+ if (SubRegNo == PPC::CR5EQ) return 3;
+ if (SubRegNo == PPC::CR5UN) return 4;
+ return 0;
+ case PPC::CR6:
+ if (SubRegNo == PPC::CR6LT) return 1;
+ if (SubRegNo == PPC::CR6GT) return 2;
+ if (SubRegNo == PPC::CR6EQ) return 3;
+ if (SubRegNo == PPC::CR6UN) return 4;
+ return 0;
+ case PPC::CR7:
+ if (SubRegNo == PPC::CR7LT) return 1;
+ if (SubRegNo == PPC::CR7GT) return 2;
+ if (SubRegNo == PPC::CR7EQ) return 3;
+ if (SubRegNo == PPC::CR7UN) return 4;
+ return 0;
+ };
+ return 0;
+}
+
+PPCGenRegisterInfo::PPCGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
+ : TargetRegisterInfo(RegisterDescriptors, 176, RegisterClasses, RegisterClasses+11,
+ CallFrameSetupOpcode, CallFrameDestroyOpcode,
+ SubregHashTable, SubregHashTableSize,
+ SuperregHashTable, SuperregHashTableSize,
+ AliasesHashTable, AliasesHashTableSize) {
+}
+
+int PPCGenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) const {
+ switch (Flavour) {
+ default:
+ assert(0 && "Unknown DWARF flavour");
+ return -1;
+ case 0:
+ switch (RegNum) {
+ default:
+ assert(0 && "Invalid RegNum");
+ return -1;
+ case PPC::CARRY:
+ return 0;
+ case PPC::CR0:
+ return 68;
+ case PPC::CR0EQ:
+ return 0;
+ case PPC::CR0GT:
+ return 0;
+ case PPC::CR0LT:
+ return 0;
+ case PPC::CR0UN:
+ return 0;
+ case PPC::CR1:
+ return 69;
+ case PPC::CR1EQ:
+ return 0;
+ case PPC::CR1GT:
+ return 0;
+ case PPC::CR1LT:
+ return 0;
+ case PPC::CR1UN:
+ return 0;
+ case PPC::CR2:
+ return 70;
+ case PPC::CR2EQ:
+ return 0;
+ case PPC::CR2GT:
+ return 0;
+ case PPC::CR2LT:
+ return 0;
+ case PPC::CR2UN:
+ return 0;
+ case PPC::CR3:
+ return 71;
+ case PPC::CR3EQ:
+ return 0;
+ case PPC::CR3GT:
+ return 0;
+ case PPC::CR3LT:
+ return 0;
+ case PPC::CR3UN:
+ return 0;
+ case PPC::CR4:
+ return 72;
+ case PPC::CR4EQ:
+ return 0;
+ case PPC::CR4GT:
+ return 0;
+ case PPC::CR4LT:
+ return 0;
+ case PPC::CR4UN:
+ return 0;
+ case PPC::CR5:
+ return 73;
+ case PPC::CR5EQ:
+ return 0;
+ case PPC::CR5GT:
+ return 0;
+ case PPC::CR5LT:
+ return 0;
+ case PPC::CR5UN:
+ return 0;
+ case PPC::CR6:
+ return 74;
+ case PPC::CR6EQ:
+ return 0;
+ case PPC::CR6GT:
+ return 0;
+ case PPC::CR6LT:
+ return 0;
+ case PPC::CR6UN:
+ return 0;
+ case PPC::CR7:
+ return 75;
+ case PPC::CR7EQ:
+ return 0;
+ case PPC::CR7GT:
+ return 0;
+ case PPC::CR7LT:
+ return 0;
+ case PPC::CR7UN:
+ return 0;
+ case PPC::CTR:
+ return 66;
+ case PPC::CTR8:
+ return 66;
+ case PPC::F0:
+ return 32;
+ case PPC::F1:
+ return 33;
+ case PPC::F10:
+ return 42;
+ case PPC::F11:
+ return 43;
+ case PPC::F12:
+ return 44;
+ case PPC::F13:
+ return 45;
+ case PPC::F14:
+ return 46;
+ case PPC::F15:
+ return 47;
+ case PPC::F16:
+ return 48;
+ case PPC::F17:
+ return 49;
+ case PPC::F18:
+ return 50;
+ case PPC::F19:
+ return 51;
+ case PPC::F2:
+ return 34;
+ case PPC::F20:
+ return 52;
+ case PPC::F21:
+ return 53;
+ case PPC::F22:
+ return 54;
+ case PPC::F23:
+ return 55;
+ case PPC::F24:
+ return 56;
+ case PPC::F25:
+ return 57;
+ case PPC::F26:
+ return 58;
+ case PPC::F27:
+ return 59;
+ case PPC::F28:
+ return 60;
+ case PPC::F29:
+ return 61;
+ case PPC::F3:
+ return 35;
+ case PPC::F30:
+ return 62;
+ case PPC::F31:
+ return 63;
+ case PPC::F4:
+ return 36;
+ case PPC::F5:
+ return 37;
+ case PPC::F6:
+ return 38;
+ case PPC::F7:
+ return 39;
+ case PPC::F8:
+ return 40;
+ case PPC::F9:
+ return 41;
+ case PPC::LR:
+ return 65;
+ case PPC::LR8:
+ return 65;
+ case PPC::R0:
+ return 0;
+ case PPC::R1:
+ return 1;
+ case PPC::R10:
+ return 10;
+ case PPC::R11:
+ return 11;
+ case PPC::R12:
+ return 12;
+ case PPC::R13:
+ return 13;
+ case PPC::R14:
+ return 14;
+ case PPC::R15:
+ return 15;
+ case PPC::R16:
+ return 16;
+ case PPC::R17:
+ return 17;
+ case PPC::R18:
+ return 18;
+ case PPC::R19:
+ return 19;
+ case PPC::R2:
+ return 2;
+ case PPC::R20:
+ return 20;
+ case PPC::R21:
+ return 21;
+ case PPC::R22:
+ return 22;
+ case PPC::R23:
+ return 23;
+ case PPC::R24:
+ return 24;
+ case PPC::R25:
+ return 25;
+ case PPC::R26:
+ return 26;
+ case PPC::R27:
+ return 27;
+ case PPC::R28:
+ return 28;
+ case PPC::R29:
+ return 29;
+ case PPC::R3:
+ return 3;
+ case PPC::R30:
+ return 30;
+ case PPC::R31:
+ return 31;
+ case PPC::R4:
+ return 4;
+ case PPC::R5:
+ return 5;
+ case PPC::R6:
+ return 6;
+ case PPC::R7:
+ return 7;
+ case PPC::R8:
+ return 8;
+ case PPC::R9:
+ return 9;
+ case PPC::RM:
+ return 0;
+ case PPC::V0:
+ return 77;
+ case PPC::V1:
+ return 78;
+ case PPC::V10:
+ return 87;
+ case PPC::V11:
+ return 88;
+ case PPC::V12:
+ return 89;
+ case PPC::V13:
+ return 90;
+ case PPC::V14:
+ return 91;
+ case PPC::V15:
+ return 92;
+ case PPC::V16:
+ return 93;
+ case PPC::V17:
+ return 94;
+ case PPC::V18:
+ return 95;
+ case PPC::V19:
+ return 96;
+ case PPC::V2:
+ return 79;
+ case PPC::V20:
+ return 97;
+ case PPC::V21:
+ return 98;
+ case PPC::V22:
+ return 99;
+ case PPC::V23:
+ return 100;
+ case PPC::V24:
+ return 101;
+ case PPC::V25:
+ return 102;
+ case PPC::V26:
+ return 103;
+ case PPC::V27:
+ return 104;
+ case PPC::V28:
+ return 105;
+ case PPC::V29:
+ return 106;
+ case PPC::V3:
+ return 80;
+ case PPC::V30:
+ return 107;
+ case PPC::V31:
+ return 108;
+ case PPC::V4:
+ return 81;
+ case PPC::V5:
+ return 82;
+ case PPC::V6:
+ return 83;
+ case PPC::V7:
+ return 84;
+ case PPC::V8:
+ return 85;
+ case PPC::V9:
+ return 86;
+ case PPC::VRSAVE:
+ return 107;
+ case PPC::X0:
+ return 0;
+ case PPC::X1:
+ return 1;
+ case PPC::X10:
+ return 10;
+ case PPC::X11:
+ return 11;
+ case PPC::X12:
+ return 12;
+ case PPC::X13:
+ return 13;
+ case PPC::X14:
+ return 14;
+ case PPC::X15:
+ return 15;
+ case PPC::X16:
+ return 16;
+ case PPC::X17:
+ return 17;
+ case PPC::X18:
+ return 18;
+ case PPC::X19:
+ return 19;
+ case PPC::X2:
+ return 2;
+ case PPC::X20:
+ return 20;
+ case PPC::X21:
+ return 21;
+ case PPC::X22:
+ return 22;
+ case PPC::X23:
+ return 23;
+ case PPC::X24:
+ return 24;
+ case PPC::X25:
+ return 25;
+ case PPC::X26:
+ return 26;
+ case PPC::X27:
+ return 27;
+ case PPC::X28:
+ return 28;
+ case PPC::X29:
+ return 29;
+ case PPC::X3:
+ return 3;
+ case PPC::X30:
+ return 30;
+ case PPC::X31:
+ return 31;
+ case PPC::X4:
+ return 4;
+ case PPC::X5:
+ return 5;
+ case PPC::X6:
+ return 6;
+ case PPC::X7:
+ return 7;
+ case PPC::X8:
+ return 8;
+ case PPC::X9:
+ return 9;
+ };
+ };
+}
+
+} // End llvm namespace
diff --git a/libclamav/c++/PPCGenRegisterNames.inc b/libclamav/c++/PPCGenRegisterNames.inc
new file mode 100644
index 0000000..26d9cb3
--- /dev/null
+++ b/libclamav/c++/PPCGenRegisterNames.inc
@@ -0,0 +1,192 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Register Enum Values
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace PPC {
+ enum {
+ NoRegister,
+ CARRY, // 1
+ CR0, // 2
+ CR0EQ, // 3
+ CR0GT, // 4
+ CR0LT, // 5
+ CR0UN, // 6
+ CR1, // 7
+ CR1EQ, // 8
+ CR1GT, // 9
+ CR1LT, // 10
+ CR1UN, // 11
+ CR2, // 12
+ CR2EQ, // 13
+ CR2GT, // 14
+ CR2LT, // 15
+ CR2UN, // 16
+ CR3, // 17
+ CR3EQ, // 18
+ CR3GT, // 19
+ CR3LT, // 20
+ CR3UN, // 21
+ CR4, // 22
+ CR4EQ, // 23
+ CR4GT, // 24
+ CR4LT, // 25
+ CR4UN, // 26
+ CR5, // 27
+ CR5EQ, // 28
+ CR5GT, // 29
+ CR5LT, // 30
+ CR5UN, // 31
+ CR6, // 32
+ CR6EQ, // 33
+ CR6GT, // 34
+ CR6LT, // 35
+ CR6UN, // 36
+ CR7, // 37
+ CR7EQ, // 38
+ CR7GT, // 39
+ CR7LT, // 40
+ CR7UN, // 41
+ CTR, // 42
+ CTR8, // 43
+ F0, // 44
+ F1, // 45
+ F10, // 46
+ F11, // 47
+ F12, // 48
+ F13, // 49
+ F14, // 50
+ F15, // 51
+ F16, // 52
+ F17, // 53
+ F18, // 54
+ F19, // 55
+ F2, // 56
+ F20, // 57
+ F21, // 58
+ F22, // 59
+ F23, // 60
+ F24, // 61
+ F25, // 62
+ F26, // 63
+ F27, // 64
+ F28, // 65
+ F29, // 66
+ F3, // 67
+ F30, // 68
+ F31, // 69
+ F4, // 70
+ F5, // 71
+ F6, // 72
+ F7, // 73
+ F8, // 74
+ F9, // 75
+ LR, // 76
+ LR8, // 77
+ R0, // 78
+ R1, // 79
+ R10, // 80
+ R11, // 81
+ R12, // 82
+ R13, // 83
+ R14, // 84
+ R15, // 85
+ R16, // 86
+ R17, // 87
+ R18, // 88
+ R19, // 89
+ R2, // 90
+ R20, // 91
+ R21, // 92
+ R22, // 93
+ R23, // 94
+ R24, // 95
+ R25, // 96
+ R26, // 97
+ R27, // 98
+ R28, // 99
+ R29, // 100
+ R3, // 101
+ R30, // 102
+ R31, // 103
+ R4, // 104
+ R5, // 105
+ R6, // 106
+ R7, // 107
+ R8, // 108
+ R9, // 109
+ RM, // 110
+ V0, // 111
+ V1, // 112
+ V10, // 113
+ V11, // 114
+ V12, // 115
+ V13, // 116
+ V14, // 117
+ V15, // 118
+ V16, // 119
+ V17, // 120
+ V18, // 121
+ V19, // 122
+ V2, // 123
+ V20, // 124
+ V21, // 125
+ V22, // 126
+ V23, // 127
+ V24, // 128
+ V25, // 129
+ V26, // 130
+ V27, // 131
+ V28, // 132
+ V29, // 133
+ V3, // 134
+ V30, // 135
+ V31, // 136
+ V4, // 137
+ V5, // 138
+ V6, // 139
+ V7, // 140
+ V8, // 141
+ V9, // 142
+ VRSAVE, // 143
+ X0, // 144
+ X1, // 145
+ X10, // 146
+ X11, // 147
+ X12, // 148
+ X13, // 149
+ X14, // 150
+ X15, // 151
+ X16, // 152
+ X17, // 153
+ X18, // 154
+ X19, // 155
+ X2, // 156
+ X20, // 157
+ X21, // 158
+ X22, // 159
+ X23, // 160
+ X24, // 161
+ X25, // 162
+ X26, // 163
+ X27, // 164
+ X28, // 165
+ X29, // 166
+ X3, // 167
+ X30, // 168
+ X31, // 169
+ X4, // 170
+ X5, // 171
+ X6, // 172
+ X7, // 173
+ X8, // 174
+ X9, // 175
+ NUM_TARGET_REGS // 176
+ };
+}
+} // End llvm namespace
diff --git a/libclamav/c++/PPCGenSubtarget.inc b/libclamav/c++/PPCGenSubtarget.inc
new file mode 100644
index 0000000..74f8ea3
--- /dev/null
+++ b/libclamav/c++/PPCGenSubtarget.inc
@@ -0,0 +1,548 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Subtarget Enumeration Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/SubtargetFeature.h"
+#include "llvm/Target/TargetInstrItineraries.h"
+
+enum {
+ BPU = 1 << 0,
+ FPU1 = 1 << 1,
+ FPU2 = 1 << 2,
+ IU1 = 1 << 3,
+ IU2 = 1 << 4,
+ IU3 = 1 << 5,
+ IU4 = 1 << 6,
+ SLU = 1 << 7,
+ SRU = 1 << 8,
+ VFPU = 1 << 9,
+ VIU1 = 1 << 10,
+ VIU2 = 1 << 11,
+ VPU = 1 << 12
+};
+
+enum {
+ Directive32 = 1 << 0,
+ Directive601 = 1 << 1,
+ Directive602 = 1 << 2,
+ Directive603 = 1 << 3,
+ Directive604 = 1 << 4,
+ Directive620 = 1 << 5,
+ Directive64 = 1 << 6,
+ Directive7400 = 1 << 7,
+ Directive750 = 1 << 8,
+ Directive970 = 1 << 9,
+ Feature64Bit = 1 << 10,
+ Feature64BitRegs = 1 << 11,
+ FeatureAltivec = 1 << 12,
+ FeatureFSqrt = 1 << 13,
+ FeatureGPUL = 1 << 14,
+ FeatureSTFIWX = 1 << 15
+};
+
+// Sorted (by key) array of values for CPU features.
+static const llvm::SubtargetFeatureKV FeatureKV[] = {
+ { "64bit", "Enable 64-bit instructions", Feature64Bit, 0 },
+ { "64bitregs", "Enable 64-bit registers usage for ppc32 [beta]", Feature64BitRegs, 0 },
+ { "altivec", "Enable Altivec instructions", FeatureAltivec, 0 },
+ { "fsqrt", "Enable the fsqrt instruction", FeatureFSqrt, 0 },
+ { "gpul", "Enable GPUL instructions", FeatureGPUL, 0 },
+ { "stfiwx", "Enable the stfiwx instruction", FeatureSTFIWX, 0 }
+};
+
+enum {
+ FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)
+};
+
+// Sorted (by key) array of values for CPU subtype.
+static const llvm::SubtargetFeatureKV SubTypeKV[] = {
+ { "601", "Select the 601 processor", Directive601, 0 },
+ { "602", "Select the 602 processor", Directive602, 0 },
+ { "603", "Select the 603 processor", Directive603, 0 },
+ { "603e", "Select the 603e processor", Directive603, 0 },
+ { "603ev", "Select the 603ev processor", Directive603, 0 },
+ { "604", "Select the 604 processor", Directive604, 0 },
+ { "604e", "Select the 604e processor", Directive604, 0 },
+ { "620", "Select the 620 processor", Directive620, 0 },
+ { "7400", "Select the 7400 processor", Directive7400 | FeatureAltivec, 0 },
+ { "7450", "Select the 7450 processor", Directive7400 | FeatureAltivec, 0 },
+ { "750", "Select the 750 processor", Directive750 | FeatureAltivec, 0 },
+ { "970", "Select the 970 processor", Directive970 | FeatureAltivec | FeatureGPUL | FeatureFSqrt | FeatureSTFIWX | Feature64Bit, 0 },
+ { "g3", "Select the g3 processor", Directive7400, 0 },
+ { "g4", "Select the g4 processor", Directive7400 | FeatureAltivec, 0 },
+ { "g4+", "Select the g4+ processor", Directive750 | FeatureAltivec, 0 },
+ { "g5", "Select the g5 processor", Directive970 | FeatureAltivec | FeatureGPUL | FeatureFSqrt | FeatureSTFIWX | Feature64Bit, 0 },
+ { "generic", "Select the generic processor", Directive32, 0 },
+ { "ppc", "Select the ppc processor", Directive32, 0 },
+ { "ppc64", "Select the ppc64 processor", Directive64 | FeatureAltivec | FeatureGPUL | FeatureFSqrt | FeatureSTFIWX | Feature64Bit, 0 }
+};
+
+enum {
+ SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)
+};
+
+
+enum {
+ ItinClassesSize = 74
+};
+static const llvm::InstrStage Stages[] = {
+ { 0, 0, 0 }, // No itinerary
+ { 1, IU1 | IU2, -1 }, // 1
+ { 19, IU1, -1 }, // 2
+ { 1, FPU1, -1 }, // 3
+ { 3, FPU1, -1 }, // 4
+ { 5, IU1, -1 }, // 5
+ { 6, IU1, -1 }, // 6
+ { 3, IU1, -1 }, // 7
+ { 2, IU1 | IU2, -1 }, // 8
+ { 1, BPU, -1 }, // 9
+ { 1, SRU, -1 }, // 10
+ { 2, SLU, -1 }, // 11
+ { 3, SLU, -1 }, // 12
+ { 34, SLU, -1 }, // 13
+ { 8, SLU, -1 }, // 14
+ { 2, SRU, -1 }, // 15
+ { 3, SRU, -1 }, // 16
+ { 31, FPU1, -1 }, // 17
+ { 17, FPU1, -1 }, // 18
+ { 2, FPU1, -1 }, // 19
+ { 10, FPU1, -1 }, // 20
+ { 1, VIU1, -1 }, // 21
+ { 5, SLU, -1 }, // 22
+ { 8, SRU, -1 }, // 23
+ { 4, VFPU, -1 }, // 24
+ { 3, VIU2, -1 }, // 25
+ { 1, VPU, -1 }, // 26
+ { 1, IU1 | IU2 | IU3 | IU4, -1 }, // 27
+ { 23, IU2, -1 }, // 28
+ { 5, FPU1, -1 }, // 29
+ { 2, VFPU, -1 }, // 30
+ { 4, IU2, -1 }, // 31
+ { 3, IU2, -1 }, // 32
+ { 2, IU1 | IU2 | IU3 | IU4, -1 }, // 33
+ { 2, IU2, -1 }, // 34
+ { 4, SLU, -1 }, // 35
+ { 37, SLU, -1 }, // 36
+ { 35, SLU, -1 }, // 37
+ { 0, IU1 | IU2 | IU3 | IU4, -1 }, // 38
+ { 5, IU2, -1 }, // 39
+ { 35, FPU1, -1 }, // 40
+ { 21, FPU1, -1 }, // 41
+ { 14, FPU1, -1 }, // 42
+ { 4, VIU2, -1 }, // 43
+ { 2, VPU, -1 }, // 44
+ { 4, VIU1, -1 }, // 45
+ { 3, IU1 | IU2, -1 }, // 46
+ { 68, IU1, -1 }, // 47
+ { 36, IU1, -1 }, // 48
+ { 6, IU2, -1 }, // 49
+ { 1, VFPU, -1 }, // 50
+ { 6, FPU1 | FPU2, -1 }, // 51
+ { 7, IU1 | IU2, -1 }, // 52
+ { 5, IU1 | IU2, -1 }, // 53
+ { 4, IU1 | IU2, -1 }, // 54
+ { 1, IU2, -1 }, // 55
+ { 4, BPU, -1 }, // 56
+ { 2, BPU, -1 }, // 57
+ { 3, BPU, -1 }, // 58
+ { 10, SLU, -1 }, // 59
+ { 40, SLU, -1 }, // 60
+ { 11, SLU, -1 }, // 61
+ { 64, SLU, -1 }, // 62
+ { 10, IU2, -1 }, // 63
+ { 8, IU2, -1 }, // 64
+ { 8, FPU1 | FPU2, -1 }, // 65
+ { 33, FPU1 | FPU2, -1 }, // 66
+ { 40, FPU1 | FPU2, -1 }, // 67
+ { 2, VIU1, -1 }, // 68
+ { 8, VFPU, -1 }, // 69
+ { 5, VIU2, -1 }, // 70
+ { 3, VPU, -1 }, // 71
+ { 0, 0, 0 } // End itinerary
+};
+static const unsigned OperandCycles[] = {
+ 0, // No itinerary
+ 0 // End itinerary
+};
+
+enum {
+ StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),
+ OperandCyclesSize = sizeof(OperandCycles)/sizeof(unsigned)
+};
+
+static const llvm::InstrItinerary G3Itineraries[] = {
+ { 9, 10, 0, 0 }, // 0
+ { 10, 11, 0, 0 }, // 1
+ { 10, 11, 0, 0 }, // 2
+ { 10, 11, 0, 0 }, // 3
+ { 3, 4, 0, 0 }, // 4
+ { 17, 18, 0, 0 }, // 5
+ { 18, 19, 0, 0 }, // 6
+ { 19, 20, 0, 0 }, // 7
+ { 3, 4, 0, 0 }, // 8
+ { 20, 21, 0, 0 }, // 9
+ { 0, 0, 0, 0 }, // 10
+ { 1, 2, 0, 0 }, // 11
+ { 0, 0, 0, 0 }, // 12
+ { 2, 3, 0, 0 }, // 13
+ { 1, 2, 0, 0 }, // 14
+ { 3, 4, 0, 0 }, // 15
+ { 0, 0, 0, 0 }, // 16
+ { 4, 5, 0, 0 }, // 17
+ { 0, 0, 0, 0 }, // 18
+ { 0, 0, 0, 0 }, // 19
+ { 5, 6, 0, 0 }, // 20
+ { 6, 7, 0, 0 }, // 21
+ { 7, 8, 0, 0 }, // 22
+ { 0, 0, 0, 0 }, // 23
+ { 1, 2, 0, 0 }, // 24
+ { 0, 0, 0, 0 }, // 25
+ { 1, 2, 0, 0 }, // 26
+ { 0, 0, 0, 0 }, // 27
+ { 8, 9, 0, 0 }, // 28
+ { 11, 12, 0, 0 }, // 29
+ { 12, 13, 0, 0 }, // 30
+ { 12, 13, 0, 0 }, // 31
+ { 0, 0, 0, 0 }, // 32
+ { 11, 12, 0, 0 }, // 33
+ { 12, 13, 0, 0 }, // 34
+ { 0, 0, 0, 0 }, // 35
+ { 0, 0, 0, 0 }, // 36
+ { 11, 12, 0, 0 }, // 37
+ { 11, 12, 0, 0 }, // 38
+ { 11, 12, 0, 0 }, // 39
+ { 13, 14, 0, 0 }, // 40
+ { 0, 0, 0, 0 }, // 41
+ { 0, 0, 0, 0 }, // 42
+ { 12, 13, 0, 0 }, // 43
+ { 0, 0, 0, 0 }, // 44
+ { 0, 0, 0, 0 }, // 45
+ { 0, 0, 0, 0 }, // 46
+ { 0, 0, 0, 0 }, // 47
+ { 0, 0, 0, 0 }, // 48
+ { 14, 15, 0, 0 }, // 49
+ { 12, 13, 0, 0 }, // 50
+ { 11, 12, 0, 0 }, // 51
+ { 0, 0, 0, 0 }, // 52
+ { 15, 16, 0, 0 }, // 53
+ { 10, 11, 0, 0 }, // 54
+ { 10, 11, 0, 0 }, // 55
+ { 16, 17, 0, 0 }, // 56
+ { 16, 17, 0, 0 }, // 57
+ { 16, 17, 0, 0 }, // 58
+ { 10, 11, 0, 0 }, // 59
+ { 15, 16, 0, 0 }, // 60
+ { 15, 16, 0, 0 }, // 61
+ { 15, 16, 0, 0 }, // 62
+ { 15, 16, 0, 0 }, // 63
+ { 15, 16, 0, 0 }, // 64
+ { 16, 17, 0, 0 }, // 65
+ { 0, 0, 0, 0 }, // 66
+ { 0, 0, 0, 0 }, // 67
+ { 0, 0, 0, 0 }, // 68
+ { 0, 0, 0, 0 }, // 69
+ { 0, 0, 0, 0 }, // 70
+ { 0, 0, 0, 0 }, // 71
+ { 0, 0, 0, 0 }, // 72
+ { 0, 0, 0, 0 }, // 73
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+static const llvm::InstrItinerary G4Itineraries[] = {
+ { 9, 10, 0, 0 }, // 0
+ { 10, 11, 0, 0 }, // 1
+ { 10, 11, 0, 0 }, // 2
+ { 10, 11, 0, 0 }, // 3
+ { 3, 4, 0, 0 }, // 4
+ { 17, 18, 0, 0 }, // 5
+ { 18, 19, 0, 0 }, // 6
+ { 3, 4, 0, 0 }, // 7
+ { 3, 4, 0, 0 }, // 8
+ { 20, 21, 0, 0 }, // 9
+ { 0, 0, 0, 0 }, // 10
+ { 1, 2, 0, 0 }, // 11
+ { 0, 0, 0, 0 }, // 12
+ { 2, 3, 0, 0 }, // 13
+ { 1, 2, 0, 0 }, // 14
+ { 4, 5, 0, 0 }, // 15
+ { 21, 22, 0, 0 }, // 16
+ { 4, 5, 0, 0 }, // 17
+ { 0, 0, 0, 0 }, // 18
+ { 0, 0, 0, 0 }, // 19
+ { 5, 6, 0, 0 }, // 20
+ { 6, 7, 0, 0 }, // 21
+ { 7, 8, 0, 0 }, // 22
+ { 0, 0, 0, 0 }, // 23
+ { 1, 2, 0, 0 }, // 24
+ { 0, 0, 0, 0 }, // 25
+ { 1, 2, 0, 0 }, // 26
+ { 0, 0, 0, 0 }, // 27
+ { 8, 9, 0, 0 }, // 28
+ { 0, 0, 0, 0 }, // 29
+ { 11, 12, 0, 0 }, // 30
+ { 11, 12, 0, 0 }, // 31
+ { 11, 12, 0, 0 }, // 32
+ { 11, 12, 0, 0 }, // 33
+ { 11, 12, 0, 0 }, // 34
+ { 0, 0, 0, 0 }, // 35
+ { 0, 0, 0, 0 }, // 36
+ { 11, 12, 0, 0 }, // 37
+ { 11, 12, 0, 0 }, // 38
+ { 11, 12, 0, 0 }, // 39
+ { 13, 14, 0, 0 }, // 40
+ { 11, 12, 0, 0 }, // 41
+ { 0, 0, 0, 0 }, // 42
+ { 12, 13, 0, 0 }, // 43
+ { 0, 0, 0, 0 }, // 44
+ { 0, 0, 0, 0 }, // 45
+ { 0, 0, 0, 0 }, // 46
+ { 0, 0, 0, 0 }, // 47
+ { 11, 12, 0, 0 }, // 48
+ { 22, 23, 0, 0 }, // 49
+ { 14, 15, 0, 0 }, // 50
+ { 11, 12, 0, 0 }, // 51
+ { 0, 0, 0, 0 }, // 52
+ { 15, 16, 0, 0 }, // 53
+ { 10, 11, 0, 0 }, // 54
+ { 10, 11, 0, 0 }, // 55
+ { 16, 17, 0, 0 }, // 56
+ { 16, 17, 0, 0 }, // 57
+ { 10, 11, 0, 0 }, // 58
+ { 10, 11, 0, 0 }, // 59
+ { 15, 16, 0, 0 }, // 60
+ { 15, 16, 0, 0 }, // 61
+ { 15, 16, 0, 0 }, // 62
+ { 15, 16, 0, 0 }, // 63
+ { 15, 16, 0, 0 }, // 64
+ { 23, 24, 0, 0 }, // 65
+ { 25, 26, 0, 0 }, // 66
+ { 24, 25, 0, 0 }, // 67
+ { 21, 22, 0, 0 }, // 68
+ { 24, 25, 0, 0 }, // 69
+ { 21, 22, 0, 0 }, // 70
+ { 26, 27, 0, 0 }, // 71
+ { 21, 22, 0, 0 }, // 72
+ { 21, 22, 0, 0 }, // 73
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+static const llvm::InstrItinerary G4PlusItineraries[] = {
+ { 9, 10, 0, 0 }, // 0
+ { 34, 35, 0, 0 }, // 1
+ { 34, 35, 0, 0 }, // 2
+ { 34, 35, 0, 0 }, // 3
+ { 29, 30, 0, 0 }, // 4
+ { 40, 41, 0, 0 }, // 5
+ { 41, 42, 0, 0 }, // 6
+ { 29, 30, 0, 0 }, // 7
+ { 29, 30, 0, 0 }, // 8
+ { 42, 43, 0, 0 }, // 9
+ { 0, 0, 0, 0 }, // 10
+ { 27, 28, 0, 0 }, // 11
+ { 0, 0, 0, 0 }, // 12
+ { 28, 29, 0, 0 }, // 13
+ { 27, 28, 0, 0 }, // 14
+ { 29, 30, 0, 0 }, // 15
+ { 30, 31, 0, 0 }, // 16
+ { 29, 30, 0, 0 }, // 17
+ { 0, 0, 0, 0 }, // 18
+ { 0, 0, 0, 0 }, // 19
+ { 31, 32, 0, 0 }, // 20
+ { 31, 32, 0, 0 }, // 21
+ { 32, 33, 0, 0 }, // 22
+ { 0, 0, 0, 0 }, // 23
+ { 27, 28, 0, 0 }, // 24
+ { 0, 0, 0, 0 }, // 25
+ { 33, 34, 0, 0 }, // 26
+ { 0, 0, 0, 0 }, // 27
+ { 33, 34, 0, 0 }, // 28
+ { 0, 0, 0, 0 }, // 29
+ { 12, 13, 0, 0 }, // 30
+ { 12, 13, 0, 0 }, // 31
+ { 12, 13, 0, 0 }, // 32
+ { 12, 13, 0, 0 }, // 33
+ { 32, 33, 0, 0 }, // 34
+ { 0, 0, 0, 0 }, // 35
+ { 0, 0, 0, 0 }, // 36
+ { 35, 36, 0, 0 }, // 37
+ { 35, 36, 0, 0 }, // 38
+ { 12, 13, 0, 0 }, // 39
+ { 36, 37, 0, 0 }, // 40
+ { 12, 13, 0, 0 }, // 41
+ { 12, 13, 0, 0 }, // 42
+ { 12, 13, 0, 0 }, // 43
+ { 0, 0, 0, 0 }, // 44
+ { 0, 0, 0, 0 }, // 45
+ { 12, 13, 0, 0 }, // 46
+ { 12, 13, 0, 0 }, // 47
+ { 12, 13, 0, 0 }, // 48
+ { 12, 13, 0, 0 }, // 49
+ { 37, 38, 0, 0 }, // 50
+ { 12, 13, 0, 0 }, // 51
+ { 0, 0, 0, 0 }, // 52
+ { 38, 39, 0, 0 }, // 53
+ { 34, 35, 0, 0 }, // 54
+ { 32, 33, 0, 0 }, // 55
+ { 31, 32, 0, 0 }, // 56
+ { 31, 32, 0, 0 }, // 57
+ { 39, 40, 0, 0 }, // 58
+ { 34, 35, 0, 0 }, // 59
+ { 34, 35, 0, 0 }, // 60
+ { 34, 35, 0, 0 }, // 61
+ { 34, 35, 0, 0 }, // 62
+ { 27, 28, 0, 0 }, // 63
+ { 38, 39, 0, 0 }, // 64
+ { 12, 13, 0, 0 }, // 65
+ { 43, 44, 0, 0 }, // 66
+ { 24, 25, 0, 0 }, // 67
+ { 30, 31, 0, 0 }, // 68
+ { 45, 46, 0, 0 }, // 69
+ { 21, 22, 0, 0 }, // 70
+ { 44, 45, 0, 0 }, // 71
+ { 44, 45, 0, 0 }, // 72
+ { 44, 45, 0, 0 }, // 73
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+static const llvm::InstrItinerary G5Itineraries[] = {
+ { 9, 10, 0, 0 }, // 0
+ { 56, 57, 0, 0 }, // 1
+ { 57, 58, 0, 0 }, // 2
+ { 58, 59, 0, 0 }, // 3
+ { 65, 66, 0, 0 }, // 4
+ { 66, 67, 0, 0 }, // 5
+ { 66, 67, 0, 0 }, // 6
+ { 51, 52, 0, 0 }, // 7
+ { 51, 52, 0, 0 }, // 8
+ { 51, 52, 0, 0 }, // 9
+ { 67, 68, 0, 0 }, // 10
+ { 46, 47, 0, 0 }, // 11
+ { 47, 48, 0, 0 }, // 12
+ { 48, 49, 0, 0 }, // 13
+ { 8, 9, 0, 0 }, // 14
+ { 49, 50, 0, 0 }, // 15
+ { 50, 51, 0, 0 }, // 16
+ { 51, 52, 0, 0 }, // 17
+ { 0, 0, 0, 0 }, // 18
+ { 52, 53, 0, 0 }, // 19
+ { 53, 54, 0, 0 }, // 20
+ { 53, 54, 0, 0 }, // 21
+ { 54, 55, 0, 0 }, // 22
+ { 55, 56, 0, 0 }, // 23
+ { 54, 55, 0, 0 }, // 24
+ { 8, 9, 0, 0 }, // 25
+ { 8, 9, 0, 0 }, // 26
+ { 1, 2, 0, 0 }, // 27
+ { 1, 2, 0, 0 }, // 28
+ { 0, 0, 0, 0 }, // 29
+ { 12, 13, 0, 0 }, // 30
+ { 0, 0, 0, 0 }, // 31
+ { 59, 60, 0, 0 }, // 32
+ { 12, 13, 0, 0 }, // 33
+ { 60, 61, 0, 0 }, // 34
+ { 12, 13, 0, 0 }, // 35
+ { 61, 62, 0, 0 }, // 36
+ { 12, 13, 0, 0 }, // 37
+ { 22, 23, 0, 0 }, // 38
+ { 22, 23, 0, 0 }, // 39
+ { 62, 63, 0, 0 }, // 40
+ { 12, 13, 0, 0 }, // 41
+ { 22, 23, 0, 0 }, // 42
+ { 61, 62, 0, 0 }, // 43
+ { 60, 61, 0, 0 }, // 44
+ { 11, 12, 0, 0 }, // 45
+ { 12, 13, 0, 0 }, // 46
+ { 61, 62, 0, 0 }, // 47
+ { 22, 23, 0, 0 }, // 48
+ { 61, 62, 0, 0 }, // 49
+ { 37, 38, 0, 0 }, // 50
+ { 35, 36, 0, 0 }, // 51
+ { 0, 0, 0, 0 }, // 52
+ { 60, 61, 0, 0 }, // 53
+ { 34, 35, 0, 0 }, // 54
+ { 32, 33, 0, 0 }, // 55
+ { 32, 33, 0, 0 }, // 56
+ { 12, 13, 0, 0 }, // 57
+ { 63, 64, 0, 0 }, // 58
+ { 12, 13, 0, 0 }, // 59
+ { 64, 65, 0, 0 }, // 60
+ { 12, 13, 0, 0 }, // 61
+ { 0, 0, 0, 0 }, // 62
+ { 0, 0, 0, 0 }, // 63
+ { 55, 56, 0, 0 }, // 64
+ { 12, 13, 0, 0 }, // 65
+ { 70, 71, 0, 0 }, // 66
+ { 69, 70, 0, 0 }, // 67
+ { 30, 31, 0, 0 }, // 68
+ { 69, 70, 0, 0 }, // 69
+ { 68, 69, 0, 0 }, // 70
+ { 71, 72, 0, 0 }, // 71
+ { 68, 69, 0, 0 }, // 72
+ { 71, 72, 0, 0 }, // 73
+ { ~0U, ~0U, ~0U, ~0U } // end marker
+};
+
+// Sorted (by key) array of itineraries for CPU subtype.
+static const llvm::SubtargetInfoKV ProcItinKV[] = {
+ { "601", (void *)&G3Itineraries },
+ { "602", (void *)&G3Itineraries },
+ { "603", (void *)&G3Itineraries },
+ { "603e", (void *)&G3Itineraries },
+ { "603ev", (void *)&G3Itineraries },
+ { "604", (void *)&G3Itineraries },
+ { "604e", (void *)&G3Itineraries },
+ { "620", (void *)&G3Itineraries },
+ { "7400", (void *)&G4Itineraries },
+ { "7450", (void *)&G4PlusItineraries },
+ { "750", (void *)&G4Itineraries },
+ { "970", (void *)&G5Itineraries },
+ { "g3", (void *)&G3Itineraries },
+ { "g4", (void *)&G4Itineraries },
+ { "g4+", (void *)&G4PlusItineraries },
+ { "g5", (void *)&G5Itineraries },
+ { "generic", (void *)&G3Itineraries },
+ { "ppc", (void *)&G3Itineraries },
+ { "ppc64", (void *)&G5Itineraries }
+};
+
+enum {
+ ProcItinKVSize = sizeof(ProcItinKV)/sizeof(llvm::SubtargetInfoKV)
+};
+
+// ParseSubtargetFeatures - Parses features string setting specified
+// subtarget options.
+std::string llvm::PPCSubtarget::ParseSubtargetFeatures(const std::string &FS,
+ const std::string &CPU) {
+ DEBUG(errs() << "\nFeatures:" << FS);
+ DEBUG(errs() << "\nCPU:" << CPU);
+ SubtargetFeatures Features(FS);
+ Features.setCPUIfNone(CPU);
+ uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,
+ FeatureKV, FeatureKVSize);
+ if ((Bits & Directive32) != 0 && DarwinDirective < PPC::DIR_32) DarwinDirective = PPC::DIR_32;
+ if ((Bits & Directive601) != 0 && DarwinDirective < PPC::DIR_601) DarwinDirective = PPC::DIR_601;
+ if ((Bits & Directive602) != 0 && DarwinDirective < PPC::DIR_602) DarwinDirective = PPC::DIR_602;
+ if ((Bits & Directive603) != 0 && DarwinDirective < PPC::DIR_603) DarwinDirective = PPC::DIR_603;
+ if ((Bits & Directive604) != 0 && DarwinDirective < PPC::DIR_603) DarwinDirective = PPC::DIR_603;
+ if ((Bits & Directive620) != 0 && DarwinDirective < PPC::DIR_603) DarwinDirective = PPC::DIR_603;
+ if ((Bits & Directive64) != 0 && DarwinDirective < PPC::DIR_64) DarwinDirective = PPC::DIR_64;
+ if ((Bits & Directive7400) != 0 && DarwinDirective < PPC::DIR_7400) DarwinDirective = PPC::DIR_7400;
+ if ((Bits & Directive750) != 0 && DarwinDirective < PPC::DIR_750) DarwinDirective = PPC::DIR_750;
+ if ((Bits & Directive970) != 0 && DarwinDirective < PPC::DIR_970) DarwinDirective = PPC::DIR_970;
+ if ((Bits & Feature64Bit) != 0) Has64BitSupport = true;
+ if ((Bits & Feature64BitRegs) != 0) Use64BitRegs = true;
+ if ((Bits & FeatureAltivec) != 0) HasAltivec = true;
+ if ((Bits & FeatureFSqrt) != 0) HasFSQRT = true;
+ if ((Bits & FeatureGPUL) != 0) IsGigaProcessor = true;
+ if ((Bits & FeatureSTFIWX) != 0) HasSTFIWX = true;
+
+ InstrItinerary *Itinerary = (InstrItinerary *)Features.getInfo(ProcItinKV, ProcItinKVSize);
+ InstrItins = InstrItineraryData(Stages, OperandCycles, Itinerary);
+ return Features.getCPU();
+}
diff --git a/libclamav/c++/X86GenAsmMatcher.inc b/libclamav/c++/X86GenAsmMatcher.inc
new file mode 100644
index 0000000..f63d239
--- /dev/null
+++ b/libclamav/c++/X86GenAsmMatcher.inc
@@ -0,0 +1,6869 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Assembly Matcher Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
+ switch (Name.size()) {
+ default: break;
+ case 2: // 25 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 3 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ return 1; // "ah"
+ case 'l': // 1 strings to match.
+ return 2; // "al"
+ case 'x': // 1 strings to match.
+ return 3; // "ax"
+ }
+ break;
+ case 'b': // 4 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ return 4; // "bh"
+ case 'l': // 1 strings to match.
+ return 5; // "bl"
+ case 'p': // 1 strings to match.
+ return 6; // "bp"
+ case 'x': // 1 strings to match.
+ return 8; // "bx"
+ }
+ break;
+ case 'c': // 4 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ return 9; // "ch"
+ case 'l': // 1 strings to match.
+ return 10; // "cl"
+ case 's': // 1 strings to match.
+ return 11; // "cs"
+ case 'x': // 1 strings to match.
+ return 12; // "cx"
+ }
+ break;
+ case 'd': // 5 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ return 13; // "dh"
+ case 'i': // 1 strings to match.
+ return 14; // "di"
+ case 'l': // 1 strings to match.
+ return 16; // "dl"
+ case 's': // 1 strings to match.
+ return 17; // "ds"
+ case 'x': // 1 strings to match.
+ return 18; // "dx"
+ }
+ break;
+ case 'e': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return 27; // "es"
+ case 'f': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return 37; // "fs"
+ case 'g': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return 38; // "gs"
+ case 'i': // 1 strings to match.
+ if (Name[1] != 'p')
+ break;
+ return 39; // "ip"
+ case 'r': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '8': // 1 strings to match.
+ return 72; // "r8"
+ case '9': // 1 strings to match.
+ return 76; // "r9"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return 89; // "si"
+ case 'p': // 1 strings to match.
+ return 91; // "sp"
+ case 's': // 1 strings to match.
+ return 93; // "ss"
+ }
+ break;
+ }
+ break;
+ case 3: // 49 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ if (Name.substr(1,2) != "pl")
+ break;
+ return 7; // "bpl"
+ case 'd': // 1 strings to match.
+ if (Name.substr(1,2) != "il")
+ break;
+ return 15; // "dil"
+ case 'e': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name[2] != 'x')
+ break;
+ return 19; // "eax"
+ case 'b': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ return 20; // "ebp"
+ case 'x': // 1 strings to match.
+ return 21; // "ebx"
+ }
+ break;
+ case 'c': // 1 strings to match.
+ if (Name[2] != 'x')
+ break;
+ return 22; // "ecx"
+ case 'd': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return 23; // "edi"
+ case 'x': // 1 strings to match.
+ return 24; // "edx"
+ }
+ break;
+ case 'i': // 1 strings to match.
+ if (Name[2] != 'p')
+ break;
+ return 26; // "eip"
+ case 's': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return 28; // "esi"
+ case 'p': // 1 strings to match.
+ return 29; // "esp"
+ }
+ break;
+ }
+ break;
+ case 'f': // 7 strings to match.
+ if (Name[1] != 'p')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 30; // "fp0"
+ case '1': // 1 strings to match.
+ return 31; // "fp1"
+ case '2': // 1 strings to match.
+ return 32; // "fp2"
+ case '3': // 1 strings to match.
+ return 33; // "fp3"
+ case '4': // 1 strings to match.
+ return 34; // "fp4"
+ case '5': // 1 strings to match.
+ return 35; // "fp5"
+ case '6': // 1 strings to match.
+ return 36; // "fp6"
+ }
+ break;
+ case 'm': // 8 strings to match.
+ if (Name[1] != 'm')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 40; // "mm0"
+ case '1': // 1 strings to match.
+ return 41; // "mm1"
+ case '2': // 1 strings to match.
+ return 42; // "mm2"
+ case '3': // 1 strings to match.
+ return 43; // "mm3"
+ case '4': // 1 strings to match.
+ return 44; // "mm4"
+ case '5': // 1 strings to match.
+ return 45; // "mm5"
+ case '6': // 1 strings to match.
+ return 46; // "mm6"
+ case '7': // 1 strings to match.
+ return 47; // "mm7"
+ }
+ break;
+ case 'r': // 21 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '1': // 6 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 48; // "r10"
+ case '1': // 1 strings to match.
+ return 52; // "r11"
+ case '2': // 1 strings to match.
+ return 56; // "r12"
+ case '3': // 1 strings to match.
+ return 60; // "r13"
+ case '4': // 1 strings to match.
+ return 64; // "r14"
+ case '5': // 1 strings to match.
+ return 68; // "r15"
+ }
+ break;
+ case '8': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 73; // "r8b"
+ case 'd': // 1 strings to match.
+ return 74; // "r8d"
+ case 'w': // 1 strings to match.
+ return 75; // "r8w"
+ }
+ break;
+ case '9': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 77; // "r9b"
+ case 'd': // 1 strings to match.
+ return 78; // "r9d"
+ case 'w': // 1 strings to match.
+ return 79; // "r9w"
+ }
+ break;
+ case 'a': // 1 strings to match.
+ if (Name[2] != 'x')
+ break;
+ return 80; // "rax"
+ case 'b': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ return 81; // "rbp"
+ case 'x': // 1 strings to match.
+ return 82; // "rbx"
+ }
+ break;
+ case 'c': // 1 strings to match.
+ if (Name[2] != 'x')
+ break;
+ return 83; // "rcx"
+ case 'd': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return 84; // "rdi"
+ case 'x': // 1 strings to match.
+ return 85; // "rdx"
+ }
+ break;
+ case 'i': // 1 strings to match.
+ if (Name[2] != 'p')
+ break;
+ return 86; // "rip"
+ case 's': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return 87; // "rsi"
+ case 'p': // 1 strings to match.
+ return 88; // "rsp"
+ }
+ break;
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ if (Name[2] != 'l')
+ break;
+ return 90; // "sil"
+ case 'p': // 1 strings to match.
+ if (Name[2] != 'l')
+ break;
+ return 92; // "spl"
+ }
+ break;
+ }
+ break;
+ case 4: // 38 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'r': // 18 strings to match.
+ if (Name[1] != '1')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case '0': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 49; // "r10b"
+ case 'd': // 1 strings to match.
+ return 50; // "r10d"
+ case 'w': // 1 strings to match.
+ return 51; // "r10w"
+ }
+ break;
+ case '1': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 53; // "r11b"
+ case 'd': // 1 strings to match.
+ return 54; // "r11d"
+ case 'w': // 1 strings to match.
+ return 55; // "r11w"
+ }
+ break;
+ case '2': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 57; // "r12b"
+ case 'd': // 1 strings to match.
+ return 58; // "r12d"
+ case 'w': // 1 strings to match.
+ return 59; // "r12w"
+ }
+ break;
+ case '3': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 61; // "r13b"
+ case 'd': // 1 strings to match.
+ return 62; // "r13d"
+ case 'w': // 1 strings to match.
+ return 63; // "r13w"
+ }
+ break;
+ case '4': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 65; // "r14b"
+ case 'd': // 1 strings to match.
+ return 66; // "r14d"
+ case 'w': // 1 strings to match.
+ return 67; // "r14w"
+ }
+ break;
+ case '5': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return 69; // "r15b"
+ case 'd': // 1 strings to match.
+ return 70; // "r15d"
+ case 'w': // 1 strings to match.
+ return 71; // "r15w"
+ }
+ break;
+ }
+ break;
+ case 'x': // 10 strings to match.
+ if (Name.substr(1,2) != "mm")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 102; // "xmm0"
+ case '1': // 1 strings to match.
+ return 103; // "xmm1"
+ case '2': // 1 strings to match.
+ return 110; // "xmm2"
+ case '3': // 1 strings to match.
+ return 111; // "xmm3"
+ case '4': // 1 strings to match.
+ return 112; // "xmm4"
+ case '5': // 1 strings to match.
+ return 113; // "xmm5"
+ case '6': // 1 strings to match.
+ return 114; // "xmm6"
+ case '7': // 1 strings to match.
+ return 115; // "xmm7"
+ case '8': // 1 strings to match.
+ return 116; // "xmm8"
+ case '9': // 1 strings to match.
+ return 117; // "xmm9"
+ }
+ break;
+ case 'y': // 10 strings to match.
+ if (Name.substr(1,2) != "mm")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 118; // "ymm0"
+ case '1': // 1 strings to match.
+ return 119; // "ymm1"
+ case '2': // 1 strings to match.
+ return 126; // "ymm2"
+ case '3': // 1 strings to match.
+ return 127; // "ymm3"
+ case '4': // 1 strings to match.
+ return 128; // "ymm4"
+ case '5': // 1 strings to match.
+ return 129; // "ymm5"
+ case '6': // 1 strings to match.
+ return 130; // "ymm6"
+ case '7': // 1 strings to match.
+ return 131; // "ymm7"
+ case '8': // 1 strings to match.
+ return 132; // "ymm8"
+ case '9': // 1 strings to match.
+ return 133; // "ymm9"
+ }
+ break;
+ }
+ break;
+ case 5: // 21 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 1 strings to match.
+ if (Name.substr(1,4) != "lags")
+ break;
+ return 25; // "flags"
+ case 's': // 8 strings to match.
+ if (Name.substr(1,2) != "t(")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 94; // "st(0)"
+ case '1': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 95; // "st(1)"
+ case '2': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 96; // "st(2)"
+ case '3': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 97; // "st(3)"
+ case '4': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 98; // "st(4)"
+ case '5': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 99; // "st(5)"
+ case '6': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 100; // "st(6)"
+ case '7': // 1 strings to match.
+ if (Name[4] != ')')
+ break;
+ return 101; // "st(7)"
+ }
+ break;
+ case 'x': // 6 strings to match.
+ if (Name.substr(1,3) != "mm1")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 104; // "xmm10"
+ case '1': // 1 strings to match.
+ return 105; // "xmm11"
+ case '2': // 1 strings to match.
+ return 106; // "xmm12"
+ case '3': // 1 strings to match.
+ return 107; // "xmm13"
+ case '4': // 1 strings to match.
+ return 108; // "xmm14"
+ case '5': // 1 strings to match.
+ return 109; // "xmm15"
+ }
+ break;
+ case 'y': // 6 strings to match.
+ if (Name.substr(1,3) != "mm1")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return 120; // "ymm10"
+ case '1': // 1 strings to match.
+ return 121; // "ymm11"
+ case '2': // 1 strings to match.
+ return 122; // "ymm12"
+ case '3': // 1 strings to match.
+ return 123; // "ymm13"
+ case '4': // 1 strings to match.
+ return 124; // "ymm14"
+ case '5': // 1 strings to match.
+ return 125; // "ymm15"
+ }
+ break;
+ }
+ break;
+ }
+ return 0;
+}
+
+// Unified function for converting operants to MCInst instances.
+
+enum ConversionKind {
+ Convert,
+ ConvertImp,
+ Convert_Reg1_1Imp,
+ Convert_Imm1_1,
+ Convert_Mem5_1,
+ Convert_Reg1_1,
+ Convert_Reg1_2_ImpReg1_1,
+ Convert_Mem5_2_Reg1_1,
+ Convert_Reg1_2_ImpImm1_1,
+ Convert_Mem5_2_Imm1_1,
+ Convert_Reg1_2_ImpMem5_1,
+ Convert_Reg1_2_ImpImmSExt81_1,
+ Convert_Mem5_2_ImmSExt81_1,
+ Convert_Reg1_2_Reg1_1,
+ Convert_Reg1_2_Mem5_1,
+ Convert_Reg1_2_ImmSExt81_1,
+ Convert_Reg1_2,
+ Convert_Mem5_2,
+ Convert_Reg1_2_Imm1_1,
+ Convert_ImpReg1_2_Reg1_1,
+ Convert_ImpReg1_2_Mem5_1,
+ Convert_Imm1_1_Imm1_2,
+ Convert_ImmSExt81_1,
+ Convert_Reg1_2_Mem4_1,
+ Convert_Imm1_2,
+ Convert_ImmSExt81_2,
+ Convert_Reg1_2Imp,
+ Convert_Mem5_2ImpImpImpImpImp,
+ Convert_Mem5_2_ImpImpImpImpImpImm1_1,
+ Convert_ImpMem5_2_Reg1_1,
+ Convert_Reg1_3_ImpReg1_2_ImmSExt81_1,
+ Convert_Reg1_3_ImpMem5_2_ImmSExt81_1,
+ Convert_Reg1_3_ImpReg1_2,
+ Convert_Reg1_3_ImpMem5_2,
+ Convert_Reg1_3_Reg1_2_ImmSExt81_1,
+ Convert_Mem5_3_Reg1_2_ImmSExt81_1,
+ Convert_Reg1_3_Mem5_2_ImmSExt81_1,
+ Convert_Reg1_3_Reg1_2_Imm1_1,
+ Convert_Reg1_3_Mem5_2_Imm1_1,
+ Convert_Reg1_3_ImpReg1_2_Imm1_1,
+ Convert_Reg1_3_ImpMem5_2_Imm1_1,
+ Convert_Mem5_3_Reg1_2,
+ Convert_Mem5_3_Reg1_2_Imm1_1,
+ Convert_Reg1_4_ImpReg1_3_Imm1_1,
+ Convert_Reg1_4_ImpMem5_3_Imm1_1,
+ NumConversionVariants
+};
+
+static bool ConvertToMCInst(ConversionKind Kind, MCInst &Inst, unsigned Opcode,
+ SmallVectorImpl<X86Operand> &Operands) {
+ Inst.setOpcode(Opcode);
+ switch (Kind) {
+ default:
+ case Convert:
+ break;
+ case ConvertImp:
+ Inst.addOperand(MCOperand::CreateReg(0));
+ break;
+ case Convert_Reg1_1Imp:
+ Operands[1].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ break;
+ case Convert_Imm1_1:
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Mem5_1:
+ Operands[1].addMemOperands(Inst, 5);
+ break;
+ case Convert_Reg1_1:
+ Operands[1].addRegOperands(Inst, 1);
+ break;
+ case Convert_Reg1_2_ImpReg1_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[1].addRegOperands(Inst, 1);
+ break;
+ case Convert_Mem5_2_Reg1_1:
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addRegOperands(Inst, 1);
+ break;
+ case Convert_Reg1_2_ImpImm1_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Mem5_2_Imm1_1:
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Reg1_2_ImpMem5_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[1].addMemOperands(Inst, 5);
+ break;
+ case Convert_Reg1_2_ImpImmSExt81_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Mem5_2_ImmSExt81_1:
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_2_Reg1_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addRegOperands(Inst, 1);
+ break;
+ case Convert_Reg1_2_Mem5_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addMemOperands(Inst, 5);
+ break;
+ case Convert_Reg1_2_ImmSExt81_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_2:
+ Operands[2].addRegOperands(Inst, 1);
+ break;
+ case Convert_Mem5_2:
+ Operands[2].addMemOperands(Inst, 5);
+ break;
+ case Convert_Reg1_2_Imm1_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_ImpReg1_2_Reg1_1:
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addRegOperands(Inst, 1);
+ break;
+ case Convert_ImpReg1_2_Mem5_1:
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addMemOperands(Inst, 5);
+ break;
+ case Convert_Imm1_1_Imm1_2:
+ Operands[1].addImmOperands(Inst, 1);
+ Operands[2].addImmOperands(Inst, 1);
+ break;
+ case Convert_ImmSExt81_1:
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_2_Mem4_1:
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addMemOperands(Inst, 4);
+ break;
+ case Convert_Imm1_2:
+ Operands[2].addImmOperands(Inst, 1);
+ break;
+ case Convert_ImmSExt81_2:
+ Operands[2].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_2Imp:
+ Operands[2].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ break;
+ case Convert_Mem5_2ImpImpImpImpImp:
+ Operands[2].addMemOperands(Inst, 5);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ break;
+ case Convert_Mem5_2_ImpImpImpImpImpImm1_1:
+ Operands[2].addMemOperands(Inst, 5);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_ImpMem5_2_Reg1_1:
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addRegOperands(Inst, 1);
+ break;
+ case Convert_Reg1_3_ImpReg1_2_ImmSExt81_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_3_ImpMem5_2_ImmSExt81_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_3_ImpReg1_2:
+ Operands[3].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addRegOperands(Inst, 1);
+ break;
+ case Convert_Reg1_3_ImpMem5_2:
+ Operands[3].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addMemOperands(Inst, 5);
+ break;
+ case Convert_Reg1_3_Reg1_2_ImmSExt81_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Mem5_3_Reg1_2_ImmSExt81_1:
+ Operands[3].addMemOperands(Inst, 5);
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_3_Mem5_2_ImmSExt81_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addImmSExt8Operands(Inst, 1);
+ break;
+ case Convert_Reg1_3_Reg1_2_Imm1_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Reg1_3_Mem5_2_Imm1_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Reg1_3_ImpReg1_2_Imm1_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Reg1_3_ImpMem5_2_Imm1_1:
+ Operands[3].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[2].addMemOperands(Inst, 5);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Mem5_3_Reg1_2:
+ Operands[3].addMemOperands(Inst, 5);
+ Operands[2].addRegOperands(Inst, 1);
+ break;
+ case Convert_Mem5_3_Reg1_2_Imm1_1:
+ Operands[3].addMemOperands(Inst, 5);
+ Operands[2].addRegOperands(Inst, 1);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Reg1_4_ImpReg1_3_Imm1_1:
+ Operands[4].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[3].addRegOperands(Inst, 1);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ case Convert_Reg1_4_ImpMem5_3_Imm1_1:
+ Operands[4].addRegOperands(Inst, 1);
+ Inst.addOperand(MCOperand::CreateReg(0));
+ Operands[3].addMemOperands(Inst, 5);
+ Operands[1].addImmOperands(Inst, 1);
+ break;
+ }
+ return false;
+}
+
+namespace {
+
+/// MatchClassKind - The kinds of classes which participate in
+/// instruction matching.
+enum MatchClassKind {
+ InvalidMatchClass = 0,
+ MCK__STAR_, // '*'
+ MCK_1, // '1'
+ MCK_3, // '3'
+ MCK_adcb, // 'adcb'
+ MCK_adcl, // 'adcl'
+ MCK_adcq, // 'adcq'
+ MCK_adcw, // 'adcw'
+ MCK_addb, // 'addb'
+ MCK_addl, // 'addl'
+ MCK_addpd, // 'addpd'
+ MCK_addps, // 'addps'
+ MCK_addq, // 'addq'
+ MCK_addsd, // 'addsd'
+ MCK_addss, // 'addss'
+ MCK_addsubpd, // 'addsubpd'
+ MCK_addsubps, // 'addsubps'
+ MCK_addw, // 'addw'
+ MCK_andb, // 'andb'
+ MCK_andl, // 'andl'
+ MCK_andnpd, // 'andnpd'
+ MCK_andnps, // 'andnps'
+ MCK_andpd, // 'andpd'
+ MCK_andps, // 'andps'
+ MCK_andq, // 'andq'
+ MCK_andw, // 'andw'
+ MCK_blendpd, // 'blendpd'
+ MCK_blendps, // 'blendps'
+ MCK_blendvpd, // 'blendvpd'
+ MCK_blendvps, // 'blendvps'
+ MCK_bsfl, // 'bsfl'
+ MCK_bsfq, // 'bsfq'
+ MCK_bsfw, // 'bsfw'
+ MCK_bsrl, // 'bsrl'
+ MCK_bsrq, // 'bsrq'
+ MCK_bsrw, // 'bsrw'
+ MCK_bswapl, // 'bswapl'
+ MCK_bswapq, // 'bswapq'
+ MCK_btl, // 'btl'
+ MCK_btq, // 'btq'
+ MCK_btw, // 'btw'
+ MCK_call, // 'call'
+ MCK_cbtw, // 'cbtw'
+ MCK_clflush, // 'clflush'
+ MCK_cltd, // 'cltd'
+ MCK_cltq, // 'cltq'
+ MCK_cmova, // 'cmova'
+ MCK_cmovae, // 'cmovae'
+ MCK_cmovb, // 'cmovb'
+ MCK_cmovbe, // 'cmovbe'
+ MCK_cmove, // 'cmove'
+ MCK_cmovg, // 'cmovg'
+ MCK_cmovge, // 'cmovge'
+ MCK_cmovl, // 'cmovl'
+ MCK_cmovle, // 'cmovle'
+ MCK_cmovne, // 'cmovne'
+ MCK_cmovno, // 'cmovno'
+ MCK_cmovnp, // 'cmovnp'
+ MCK_cmovns, // 'cmovns'
+ MCK_cmovo, // 'cmovo'
+ MCK_cmovp, // 'cmovp'
+ MCK_cmovs, // 'cmovs'
+ MCK_cmp, // 'cmp'
+ MCK_cmpb, // 'cmpb'
+ MCK_cmpl, // 'cmpl'
+ MCK_cmpq, // 'cmpq'
+ MCK_cmpsb, // 'cmpsb'
+ MCK_cmpsl, // 'cmpsl'
+ MCK_cmpsq, // 'cmpsq'
+ MCK_cmpsw, // 'cmpsw'
+ MCK_cmpw, // 'cmpw'
+ MCK_comisd, // 'comisd'
+ MCK_cqto, // 'cqto'
+ MCK_crc32, // 'crc32'
+ MCK_cvtdq2pd, // 'cvtdq2pd'
+ MCK_cvtdq2ps, // 'cvtdq2ps'
+ MCK_cvtpd2dq, // 'cvtpd2dq'
+ MCK_cvtpd2pi, // 'cvtpd2pi'
+ MCK_cvtpi2pd, // 'cvtpi2pd'
+ MCK_cvtpi2ps, // 'cvtpi2ps'
+ MCK_cvtps2dq, // 'cvtps2dq'
+ MCK_cvtps2pi, // 'cvtps2pi'
+ MCK_cvtsd2ss, // 'cvtsd2ss'
+ MCK_cvtsi2sd, // 'cvtsi2sd'
+ MCK_cvtsi2sdq, // 'cvtsi2sdq'
+ MCK_cvtsi2ss, // 'cvtsi2ss'
+ MCK_cvtsi2ssq, // 'cvtsi2ssq'
+ MCK_cvtss2sd, // 'cvtss2sd'
+ MCK_cvttpd2pi, // 'cvttpd2pi'
+ MCK_cvttps2pi, // 'cvttps2pi'
+ MCK_cvttsd2si, // 'cvttsd2si'
+ MCK_cvttsd2siq, // 'cvttsd2siq'
+ MCK_cvttss2si, // 'cvttss2si'
+ MCK_cvttss2siq, // 'cvttss2siq'
+ MCK_cwtd, // 'cwtd'
+ MCK_cwtl, // 'cwtl'
+ MCK_decb, // 'decb'
+ MCK_decl, // 'decl'
+ MCK_decq, // 'decq'
+ MCK_decw, // 'decw'
+ MCK_divb, // 'divb'
+ MCK_divl, // 'divl'
+ MCK_divpd, // 'divpd'
+ MCK_divps, // 'divps'
+ MCK_divq, // 'divq'
+ MCK_divsd, // 'divsd'
+ MCK_divss, // 'divss'
+ MCK_divw, // 'divw'
+ MCK_dppd, // 'dppd'
+ MCK_dpps, // 'dpps'
+ MCK_emms, // 'emms'
+ MCK_enter, // 'enter'
+ MCK_extractps, // 'extractps'
+ MCK_fabs, // 'fabs'
+ MCK_fadd, // 'fadd'
+ MCK_faddl, // 'faddl'
+ MCK_faddp, // 'faddp'
+ MCK_fadds, // 'fadds'
+ MCK_fbld, // 'fbld'
+ MCK_fbstp, // 'fbstp'
+ MCK_fchs, // 'fchs'
+ MCK_fcmovb, // 'fcmovb'
+ MCK_fcmovbe, // 'fcmovbe'
+ MCK_fcmove, // 'fcmove'
+ MCK_fcmovnb, // 'fcmovnb'
+ MCK_fcmovnbe, // 'fcmovnbe'
+ MCK_fcmovne, // 'fcmovne'
+ MCK_fcmovnu, // 'fcmovnu'
+ MCK_fcmovu, // 'fcmovu'
+ MCK_fcom, // 'fcom'
+ MCK_fcomp, // 'fcomp'
+ MCK_fcos, // 'fcos'
+ MCK_fdiv, // 'fdiv'
+ MCK_fdivl, // 'fdivl'
+ MCK_fdivp, // 'fdivp'
+ MCK_fdivr, // 'fdivr'
+ MCK_fdivrl, // 'fdivrl'
+ MCK_fdivrp, // 'fdivrp'
+ MCK_fdivrs, // 'fdivrs'
+ MCK_fdivs, // 'fdivs'
+ MCK_femms, // 'femms'
+ MCK_fiaddl, // 'fiaddl'
+ MCK_fiadds, // 'fiadds'
+ MCK_ficoml, // 'ficoml'
+ MCK_ficompl, // 'ficompl'
+ MCK_ficompw, // 'ficompw'
+ MCK_ficomw, // 'ficomw'
+ MCK_fidivl, // 'fidivl'
+ MCK_fidivrl, // 'fidivrl'
+ MCK_fidivrs, // 'fidivrs'
+ MCK_fidivs, // 'fidivs'
+ MCK_fildl, // 'fildl'
+ MCK_fildll, // 'fildll'
+ MCK_filds, // 'filds'
+ MCK_fimull, // 'fimull'
+ MCK_fimuls, // 'fimuls'
+ MCK_fistl, // 'fistl'
+ MCK_fistpl, // 'fistpl'
+ MCK_fistpll, // 'fistpll'
+ MCK_fistps, // 'fistps'
+ MCK_fists, // 'fists'
+ MCK_fisttpl, // 'fisttpl'
+ MCK_fisttpll, // 'fisttpll'
+ MCK_fisttps, // 'fisttps'
+ MCK_fisubl, // 'fisubl'
+ MCK_fisubrl, // 'fisubrl'
+ MCK_fisubrs, // 'fisubrs'
+ MCK_fisubs, // 'fisubs'
+ MCK_fld, // 'fld'
+ MCK_fld1, // 'fld1'
+ MCK_fldcw, // 'fldcw'
+ MCK_fldenv, // 'fldenv'
+ MCK_fldl, // 'fldl'
+ MCK_flds, // 'flds'
+ MCK_fldt, // 'fldt'
+ MCK_fldz, // 'fldz'
+ MCK_fmul, // 'fmul'
+ MCK_fmull, // 'fmull'
+ MCK_fmulp, // 'fmulp'
+ MCK_fmuls, // 'fmuls'
+ MCK_fnstcw, // 'fnstcw'
+ MCK_fnstsw, // 'fnstsw'
+ MCK_frstor, // 'frstor'
+ MCK_fsave, // 'fsave'
+ MCK_fsin, // 'fsin'
+ MCK_fsqrt, // 'fsqrt'
+ MCK_fst, // 'fst'
+ MCK_fstenv, // 'fstenv'
+ MCK_fstl, // 'fstl'
+ MCK_fstp, // 'fstp'
+ MCK_fstpl, // 'fstpl'
+ MCK_fstps, // 'fstps'
+ MCK_fstpt, // 'fstpt'
+ MCK_fsts, // 'fsts'
+ MCK_fstsw, // 'fstsw'
+ MCK_fsub, // 'fsub'
+ MCK_fsubl, // 'fsubl'
+ MCK_fsubp, // 'fsubp'
+ MCK_fsubr, // 'fsubr'
+ MCK_fsubrl, // 'fsubrl'
+ MCK_fsubrp, // 'fsubrp'
+ MCK_fsubrs, // 'fsubrs'
+ MCK_fsubs, // 'fsubs'
+ MCK_ftst, // 'ftst'
+ MCK_fucom, // 'fucom'
+ MCK_fucomi, // 'fucomi'
+ MCK_fucomip, // 'fucomip'
+ MCK_fucomp, // 'fucomp'
+ MCK_fucompp, // 'fucompp'
+ MCK_fxch, // 'fxch'
+ MCK_haddpd, // 'haddpd'
+ MCK_haddps, // 'haddps'
+ MCK_hsubpd, // 'hsubpd'
+ MCK_hsubps, // 'hsubps'
+ MCK_idivb, // 'idivb'
+ MCK_idivl, // 'idivl'
+ MCK_idivq, // 'idivq'
+ MCK_idivw, // 'idivw'
+ MCK_imulb, // 'imulb'
+ MCK_imull, // 'imull'
+ MCK_imulq, // 'imulq'
+ MCK_imulw, // 'imulw'
+ MCK_inb, // 'inb'
+ MCK_incb, // 'incb'
+ MCK_incl, // 'incl'
+ MCK_incq, // 'incq'
+ MCK_incw, // 'incw'
+ MCK_inl, // 'inl'
+ MCK_insertps, // 'insertps'
+ MCK_int, // 'int'
+ MCK_inw, // 'inw'
+ MCK_ja, // 'ja'
+ MCK_jae, // 'jae'
+ MCK_jb, // 'jb'
+ MCK_jbe, // 'jbe'
+ MCK_jcxz, // 'jcxz'
+ MCK_je, // 'je'
+ MCK_jg, // 'jg'
+ MCK_jge, // 'jge'
+ MCK_jl, // 'jl'
+ MCK_jle, // 'jle'
+ MCK_jmp, // 'jmp'
+ MCK_jmpl, // 'jmpl'
+ MCK_jmpq, // 'jmpq'
+ MCK_jne, // 'jne'
+ MCK_jno, // 'jno'
+ MCK_jnp, // 'jnp'
+ MCK_jns, // 'jns'
+ MCK_jo, // 'jo'
+ MCK_jp, // 'jp'
+ MCK_js, // 'js'
+ MCK_lahf, // 'lahf'
+ MCK_larl, // 'larl'
+ MCK_larq, // 'larq'
+ MCK_larw, // 'larw'
+ MCK_lcalll, // 'lcalll'
+ MCK_lcallq, // 'lcallq'
+ MCK_lcallw, // 'lcallw'
+ MCK_lddqu, // 'lddqu'
+ MCK_ldmxcsr, // 'ldmxcsr'
+ MCK_leal, // 'leal'
+ MCK_leaq, // 'leaq'
+ MCK_leave, // 'leave'
+ MCK_leaw, // 'leaw'
+ MCK_lfence, // 'lfence'
+ MCK_ljmpl, // 'ljmpl'
+ MCK_ljmpq, // 'ljmpq'
+ MCK_ljmpw, // 'ljmpw'
+ MCK_lodsb, // 'lodsb'
+ MCK_lodsd, // 'lodsd'
+ MCK_lodsq, // 'lodsq'
+ MCK_lodsw, // 'lodsw'
+ MCK_loop, // 'loop'
+ MCK_loope, // 'loope'
+ MCK_loopne, // 'loopne'
+ MCK_lret, // 'lret'
+ MCK_maskmovdqu, // 'maskmovdqu'
+ MCK_maskmovq, // 'maskmovq'
+ MCK_maxpd, // 'maxpd'
+ MCK_maxps, // 'maxps'
+ MCK_maxsd, // 'maxsd'
+ MCK_maxss, // 'maxss'
+ MCK_mfence, // 'mfence'
+ MCK_minpd, // 'minpd'
+ MCK_minps, // 'minps'
+ MCK_minsd, // 'minsd'
+ MCK_minss, // 'minss'
+ MCK_monitor, // 'monitor'
+ MCK_movabsq, // 'movabsq'
+ MCK_movapd, // 'movapd'
+ MCK_movaps, // 'movaps'
+ MCK_movb, // 'movb'
+ MCK_movd, // 'movd'
+ MCK_movddup, // 'movddup'
+ MCK_movdq2q, // 'movdq2q'
+ MCK_movdqa, // 'movdqa'
+ MCK_movdqu, // 'movdqu'
+ MCK_movhlps, // 'movhlps'
+ MCK_movhpd, // 'movhpd'
+ MCK_movhps, // 'movhps'
+ MCK_movl, // 'movl'
+ MCK_movlhps, // 'movlhps'
+ MCK_movlpd, // 'movlpd'
+ MCK_movlps, // 'movlps'
+ MCK_movmskpd, // 'movmskpd'
+ MCK_movmskps, // 'movmskps'
+ MCK_movntdq, // 'movntdq'
+ MCK_movntdqa, // 'movntdqa'
+ MCK_movnti, // 'movnti'
+ MCK_movntpd, // 'movntpd'
+ MCK_movntps, // 'movntps'
+ MCK_movntq, // 'movntq'
+ MCK_movq, // 'movq'
+ MCK_movq2dq, // 'movq2dq'
+ MCK_movsbl, // 'movsbl'
+ MCK_movsbq, // 'movsbq'
+ MCK_movsd, // 'movsd'
+ MCK_movshdup, // 'movshdup'
+ MCK_movsldup, // 'movsldup'
+ MCK_movslq, // 'movslq'
+ MCK_movss, // 'movss'
+ MCK_movswl, // 'movswl'
+ MCK_movswq, // 'movswq'
+ MCK_movupd, // 'movupd'
+ MCK_movups, // 'movups'
+ MCK_movw, // 'movw'
+ MCK_movzbl, // 'movzbl'
+ MCK_movzwl, // 'movzwl'
+ MCK_mpsadbw, // 'mpsadbw'
+ MCK_mulb, // 'mulb'
+ MCK_mull, // 'mull'
+ MCK_mulpd, // 'mulpd'
+ MCK_mulps, // 'mulps'
+ MCK_mulq, // 'mulq'
+ MCK_mulsd, // 'mulsd'
+ MCK_mulss, // 'mulss'
+ MCK_mulw, // 'mulw'
+ MCK_mwait, // 'mwait'
+ MCK_negb, // 'negb'
+ MCK_negl, // 'negl'
+ MCK_negq, // 'negq'
+ MCK_negw, // 'negw'
+ MCK_nop, // 'nop'
+ MCK_nopl, // 'nopl'
+ MCK_notb, // 'notb'
+ MCK_notl, // 'notl'
+ MCK_notq, // 'notq'
+ MCK_notw, // 'notw'
+ MCK_orb, // 'orb'
+ MCK_orl, // 'orl'
+ MCK_orpd, // 'orpd'
+ MCK_orps, // 'orps'
+ MCK_orq, // 'orq'
+ MCK_orw, // 'orw'
+ MCK_outb, // 'outb'
+ MCK_outl, // 'outl'
+ MCK_outw, // 'outw'
+ MCK_pabsb, // 'pabsb'
+ MCK_pabsd, // 'pabsd'
+ MCK_pabsw, // 'pabsw'
+ MCK_packssdw, // 'packssdw'
+ MCK_packsswb, // 'packsswb'
+ MCK_packusdw, // 'packusdw'
+ MCK_packuswb, // 'packuswb'
+ MCK_paddb, // 'paddb'
+ MCK_paddd, // 'paddd'
+ MCK_paddq, // 'paddq'
+ MCK_paddsb, // 'paddsb'
+ MCK_paddsw, // 'paddsw'
+ MCK_paddusb, // 'paddusb'
+ MCK_paddusw, // 'paddusw'
+ MCK_paddw, // 'paddw'
+ MCK_palignr, // 'palignr'
+ MCK_pand, // 'pand'
+ MCK_pandn, // 'pandn'
+ MCK_pavgb, // 'pavgb'
+ MCK_pavgw, // 'pavgw'
+ MCK_pblendvb, // 'pblendvb'
+ MCK_pblendw, // 'pblendw'
+ MCK_pcmpeqb, // 'pcmpeqb'
+ MCK_pcmpeqd, // 'pcmpeqd'
+ MCK_pcmpeqq, // 'pcmpeqq'
+ MCK_pcmpeqw, // 'pcmpeqw'
+ MCK_pcmpestri, // 'pcmpestri'
+ MCK_pcmpestrm, // 'pcmpestrm'
+ MCK_pcmpgtb, // 'pcmpgtb'
+ MCK_pcmpgtd, // 'pcmpgtd'
+ MCK_pcmpgtq, // 'pcmpgtq'
+ MCK_pcmpgtw, // 'pcmpgtw'
+ MCK_pcmpistri, // 'pcmpistri'
+ MCK_pcmpistrm, // 'pcmpistrm'
+ MCK_pd, // 'pd'
+ MCK_pextrb, // 'pextrb'
+ MCK_pextrd, // 'pextrd'
+ MCK_pextrq, // 'pextrq'
+ MCK_pextrw, // 'pextrw'
+ MCK_phaddd, // 'phaddd'
+ MCK_phaddsw, // 'phaddsw'
+ MCK_phaddw, // 'phaddw'
+ MCK_phminposuw, // 'phminposuw'
+ MCK_phsubd, // 'phsubd'
+ MCK_phsubsw, // 'phsubsw'
+ MCK_phsubw, // 'phsubw'
+ MCK_pinsrb, // 'pinsrb'
+ MCK_pinsrd, // 'pinsrd'
+ MCK_pinsrq, // 'pinsrq'
+ MCK_pinsrw, // 'pinsrw'
+ MCK_pmaddubsw, // 'pmaddubsw'
+ MCK_pmaddwd, // 'pmaddwd'
+ MCK_pmaxsb, // 'pmaxsb'
+ MCK_pmaxsd, // 'pmaxsd'
+ MCK_pmaxsw, // 'pmaxsw'
+ MCK_pmaxub, // 'pmaxub'
+ MCK_pmaxud, // 'pmaxud'
+ MCK_pmaxuw, // 'pmaxuw'
+ MCK_pminsb, // 'pminsb'
+ MCK_pminsd, // 'pminsd'
+ MCK_pminsw, // 'pminsw'
+ MCK_pminub, // 'pminub'
+ MCK_pminud, // 'pminud'
+ MCK_pminuw, // 'pminuw'
+ MCK_pmovmskb, // 'pmovmskb'
+ MCK_pmovsxbd, // 'pmovsxbd'
+ MCK_pmovsxbq, // 'pmovsxbq'
+ MCK_pmovsxbw, // 'pmovsxbw'
+ MCK_pmovsxdq, // 'pmovsxdq'
+ MCK_pmovsxwd, // 'pmovsxwd'
+ MCK_pmovsxwq, // 'pmovsxwq'
+ MCK_pmovzxbd, // 'pmovzxbd'
+ MCK_pmovzxbq, // 'pmovzxbq'
+ MCK_pmovzxbw, // 'pmovzxbw'
+ MCK_pmovzxdq, // 'pmovzxdq'
+ MCK_pmovzxwd, // 'pmovzxwd'
+ MCK_pmovzxwq, // 'pmovzxwq'
+ MCK_pmuldq, // 'pmuldq'
+ MCK_pmulhrsw, // 'pmulhrsw'
+ MCK_pmulhuw, // 'pmulhuw'
+ MCK_pmulhw, // 'pmulhw'
+ MCK_pmulld, // 'pmulld'
+ MCK_pmullw, // 'pmullw'
+ MCK_pmuludq, // 'pmuludq'
+ MCK_popf, // 'popf'
+ MCK_popl, // 'popl'
+ MCK_popq, // 'popq'
+ MCK_popw, // 'popw'
+ MCK_por, // 'por'
+ MCK_prefetchnta, // 'prefetchnta'
+ MCK_prefetcht0, // 'prefetcht0'
+ MCK_prefetcht1, // 'prefetcht1'
+ MCK_prefetcht2, // 'prefetcht2'
+ MCK_ps, // 'ps'
+ MCK_psadbw, // 'psadbw'
+ MCK_pshufb, // 'pshufb'
+ MCK_pshufd, // 'pshufd'
+ MCK_pshufhw, // 'pshufhw'
+ MCK_pshuflw, // 'pshuflw'
+ MCK_pshufw, // 'pshufw'
+ MCK_psignb, // 'psignb'
+ MCK_psignd, // 'psignd'
+ MCK_psignw, // 'psignw'
+ MCK_pslld, // 'pslld'
+ MCK_pslldq, // 'pslldq'
+ MCK_psllq, // 'psllq'
+ MCK_psllw, // 'psllw'
+ MCK_psrad, // 'psrad'
+ MCK_psraw, // 'psraw'
+ MCK_psrld, // 'psrld'
+ MCK_psrldq, // 'psrldq'
+ MCK_psrlq, // 'psrlq'
+ MCK_psrlw, // 'psrlw'
+ MCK_psubb, // 'psubb'
+ MCK_psubd, // 'psubd'
+ MCK_psubq, // 'psubq'
+ MCK_psubsb, // 'psubsb'
+ MCK_psubsw, // 'psubsw'
+ MCK_psubusb, // 'psubusb'
+ MCK_psubusw, // 'psubusw'
+ MCK_psubw, // 'psubw'
+ MCK_ptest, // 'ptest'
+ MCK_punpckhbw, // 'punpckhbw'
+ MCK_punpckhdq, // 'punpckhdq'
+ MCK_punpckhqdq, // 'punpckhqdq'
+ MCK_punpckhwd, // 'punpckhwd'
+ MCK_punpcklbw, // 'punpcklbw'
+ MCK_punpckldq, // 'punpckldq'
+ MCK_punpcklqdq, // 'punpcklqdq'
+ MCK_punpcklwd, // 'punpcklwd'
+ MCK_pushf, // 'pushf'
+ MCK_pushl, // 'pushl'
+ MCK_pushq, // 'pushq'
+ MCK_pushw, // 'pushw'
+ MCK_pxor, // 'pxor'
+ MCK_rclb, // 'rclb'
+ MCK_rcll, // 'rcll'
+ MCK_rclq, // 'rclq'
+ MCK_rclw, // 'rclw'
+ MCK_rcpps, // 'rcpps'
+ MCK_rcpss, // 'rcpss'
+ MCK_rcrb, // 'rcrb'
+ MCK_rcrl, // 'rcrl'
+ MCK_rcrq, // 'rcrq'
+ MCK_rcrw, // 'rcrw'
+ MCK_rdtsc, // 'rdtsc'
+ MCK_rep_59_movsb, // 'rep;movsb'
+ MCK_rep_59_movsl, // 'rep;movsl'
+ MCK_rep_59_movsq, // 'rep;movsq'
+ MCK_rep_59_movsw, // 'rep;movsw'
+ MCK_rep_59_stosb, // 'rep;stosb'
+ MCK_rep_59_stosl, // 'rep;stosl'
+ MCK_rep_59_stosq, // 'rep;stosq'
+ MCK_rep_59_stosw, // 'rep;stosw'
+ MCK_ret, // 'ret'
+ MCK_rolb, // 'rolb'
+ MCK_roll, // 'roll'
+ MCK_rolq, // 'rolq'
+ MCK_rolw, // 'rolw'
+ MCK_rorb, // 'rorb'
+ MCK_rorl, // 'rorl'
+ MCK_rorq, // 'rorq'
+ MCK_rorw, // 'rorw'
+ MCK_rsqrtps, // 'rsqrtps'
+ MCK_rsqrtss, // 'rsqrtss'
+ MCK_sahf, // 'sahf'
+ MCK_sarb, // 'sarb'
+ MCK_sarl, // 'sarl'
+ MCK_sarq, // 'sarq'
+ MCK_sarw, // 'sarw'
+ MCK_sbbb, // 'sbbb'
+ MCK_sbbl, // 'sbbl'
+ MCK_sbbq, // 'sbbq'
+ MCK_sbbw, // 'sbbw'
+ MCK_scasb, // 'scasb'
+ MCK_scasl, // 'scasl'
+ MCK_scasq, // 'scasq'
+ MCK_scasw, // 'scasw'
+ MCK_sd, // 'sd'
+ MCK_seta, // 'seta'
+ MCK_setae, // 'setae'
+ MCK_setb, // 'setb'
+ MCK_setbe, // 'setbe'
+ MCK_sete, // 'sete'
+ MCK_setg, // 'setg'
+ MCK_setge, // 'setge'
+ MCK_setl, // 'setl'
+ MCK_setle, // 'setle'
+ MCK_setne, // 'setne'
+ MCK_setno, // 'setno'
+ MCK_setnp, // 'setnp'
+ MCK_setns, // 'setns'
+ MCK_seto, // 'seto'
+ MCK_setp, // 'setp'
+ MCK_sets, // 'sets'
+ MCK_sfence, // 'sfence'
+ MCK_shlb, // 'shlb'
+ MCK_shldl, // 'shldl'
+ MCK_shldq, // 'shldq'
+ MCK_shldw, // 'shldw'
+ MCK_shll, // 'shll'
+ MCK_shlq, // 'shlq'
+ MCK_shlw, // 'shlw'
+ MCK_shrb, // 'shrb'
+ MCK_shrdl, // 'shrdl'
+ MCK_shrdq, // 'shrdq'
+ MCK_shrdw, // 'shrdw'
+ MCK_shrl, // 'shrl'
+ MCK_shrq, // 'shrq'
+ MCK_shrw, // 'shrw'
+ MCK_shufpd, // 'shufpd'
+ MCK_shufps, // 'shufps'
+ MCK_sqrtpd, // 'sqrtpd'
+ MCK_sqrtps, // 'sqrtps'
+ MCK_sqrtsd, // 'sqrtsd'
+ MCK_sqrtss, // 'sqrtss'
+ MCK_ss, // 'ss'
+ MCK_stmxcsr, // 'stmxcsr'
+ MCK_subb, // 'subb'
+ MCK_subl, // 'subl'
+ MCK_subpd, // 'subpd'
+ MCK_subps, // 'subps'
+ MCK_subq, // 'subq'
+ MCK_subsd, // 'subsd'
+ MCK_subss, // 'subss'
+ MCK_subw, // 'subw'
+ MCK_syscall, // 'syscall'
+ MCK_sysenter, // 'sysenter'
+ MCK_sysexit, // 'sysexit'
+ MCK_sysret, // 'sysret'
+ MCK_testb, // 'testb'
+ MCK_testl, // 'testl'
+ MCK_testq, // 'testq'
+ MCK_testw, // 'testw'
+ MCK_ucomisd, // 'ucomisd'
+ MCK_ucomiss, // 'ucomiss'
+ MCK_ud2, // 'ud2'
+ MCK_unpckhpd, // 'unpckhpd'
+ MCK_unpckhps, // 'unpckhps'
+ MCK_unpcklpd, // 'unpcklpd'
+ MCK_unpcklps, // 'unpcklps'
+ MCK_wait, // 'wait'
+ MCK_xchg, // 'xchg'
+ MCK_xchgb, // 'xchgb'
+ MCK_xchgl, // 'xchgl'
+ MCK_xchgw, // 'xchgw'
+ MCK_xorb, // 'xorb'
+ MCK_xorl, // 'xorl'
+ MCK_xorpd, // 'xorpd'
+ MCK_xorps, // 'xorps'
+ MCK_xorq, // 'xorq'
+ MCK_xorw, // 'xorw'
+ MCK_AL, // register class 'AL'
+ MCK_CL, // register class 'CL'
+ MCK_GR8_ABCD_L, // register class 'GR8_ABCD_L'
+ MCK_GR8_ABCD_H, // register class 'GR8_ABCD_H'
+ MCK_GR8_NOREX, // register class 'GR8_NOREX'
+ MCK_GR8, // register class 'GR8'
+ MCK_AX, // register class 'AX'
+ MCK_DX, // register class 'DX'
+ MCK_GR16_ABCD, // register class 'GR16_ABCD'
+ MCK_GR16_NOREX, // register class 'GR16_NOREX'
+ MCK_GR16, // register class 'GR16'
+ MCK_EAX, // register class 'EAX'
+ MCK_GR32_AD, // register class 'GR32_AD'
+ MCK_GR32_ABCD, // register class 'GR32_ABCD'
+ MCK_Reg14, // derived register class
+ MCK_GR32_NOSP, // register class 'GR32_NOSP'
+ MCK_GR32_NOREX, // register class 'GR32_NOREX'
+ MCK_GR32, // register class 'GR32'
+ MCK_RAX, // register class 'RAX'
+ MCK_GR64_ABCD, // register class 'GR64_ABCD'
+ MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP'
+ MCK_GR64_NOREX, // register class 'GR64_NOREX'
+ MCK_GR64_NOSP, // register class 'GR64_NOSP'
+ MCK_GR64, // register class 'GR64'
+ MCK_VR64, // register class 'VR64'
+ MCK_RFP32, // register class 'RFP32,RFP64,RFP80'
+ MCK_XMM0, // register class 'XMM0'
+ MCK_FR32, // register class 'FR32,FR64,VR128'
+ MCK_VR256, // register class 'VR256'
+ MCK_ST0, // register class 'ST0'
+ MCK_RST, // register class 'RST'
+ MCK_CCR, // register class 'CCR'
+ MCK_SEGMENT_REG, // register class 'SEGMENT_REG'
+ MCK_ImmSExt8, // user defined class 'ImmSExt8AsmOperand'
+ MCK_Imm, // user defined class 'ImmAsmOperand'
+ MCK_Mem, // user defined class 'X86MemAsmOperand'
+ NumMatchClassKinds
+};
+
+}
+
+static MatchClassKind MatchTokenString(const StringRef &Name) {
+ switch (Name.size()) {
+ default: break;
+ case 1: // 3 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case '*': // 1 strings to match.
+ return MCK__STAR_; // "*"
+ case '1': // 1 strings to match.
+ return MCK_1; // "1"
+ case '3': // 1 strings to match.
+ return MCK_3; // "3"
+ }
+ break;
+ case 2: // 12 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'j': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ return MCK_ja; // "ja"
+ case 'b': // 1 strings to match.
+ return MCK_jb; // "jb"
+ case 'e': // 1 strings to match.
+ return MCK_je; // "je"
+ case 'g': // 1 strings to match.
+ return MCK_jg; // "jg"
+ case 'l': // 1 strings to match.
+ return MCK_jl; // "jl"
+ case 'o': // 1 strings to match.
+ return MCK_jo; // "jo"
+ case 'p': // 1 strings to match.
+ return MCK_jp; // "jp"
+ case 's': // 1 strings to match.
+ return MCK_js; // "js"
+ }
+ break;
+ case 'p': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pd; // "pd"
+ case 's': // 1 strings to match.
+ return MCK_ps; // "ps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_sd; // "sd"
+ case 's': // 1 strings to match.
+ return MCK_ss; // "ss"
+ }
+ break;
+ }
+ break;
+ case 3: // 27 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'b': // 3 strings to match.
+ if (Name[1] != 't')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_btl; // "btl"
+ case 'q': // 1 strings to match.
+ return MCK_btq; // "btq"
+ case 'w': // 1 strings to match.
+ return MCK_btw; // "btw"
+ }
+ break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(1,2) != "mp")
+ break;
+ return MCK_cmp; // "cmp"
+ case 'f': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ if (Name[2] != 'd')
+ break;
+ return MCK_fld; // "fld"
+ case 's': // 1 strings to match.
+ if (Name[2] != 't')
+ break;
+ return MCK_fst; // "fst"
+ }
+ break;
+ case 'i': // 4 strings to match.
+ if (Name[1] != 'n')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_inb; // "inb"
+ case 'l': // 1 strings to match.
+ return MCK_inl; // "inl"
+ case 't': // 1 strings to match.
+ return MCK_int; // "int"
+ case 'w': // 1 strings to match.
+ return MCK_inw; // "inw"
+ }
+ break;
+ case 'j': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name[2] != 'e')
+ break;
+ return MCK_jae; // "jae"
+ case 'b': // 1 strings to match.
+ if (Name[2] != 'e')
+ break;
+ return MCK_jbe; // "jbe"
+ case 'g': // 1 strings to match.
+ if (Name[2] != 'e')
+ break;
+ return MCK_jge; // "jge"
+ case 'l': // 1 strings to match.
+ if (Name[2] != 'e')
+ break;
+ return MCK_jle; // "jle"
+ case 'm': // 1 strings to match.
+ if (Name[2] != 'p')
+ break;
+ return MCK_jmp; // "jmp"
+ case 'n': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ return MCK_jne; // "jne"
+ case 'o': // 1 strings to match.
+ return MCK_jno; // "jno"
+ case 'p': // 1 strings to match.
+ return MCK_jnp; // "jnp"
+ case 's': // 1 strings to match.
+ return MCK_jns; // "jns"
+ }
+ break;
+ }
+ break;
+ case 'n': // 1 strings to match.
+ if (Name.substr(1,2) != "op")
+ break;
+ return MCK_nop; // "nop"
+ case 'o': // 4 strings to match.
+ if (Name[1] != 'r')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_orb; // "orb"
+ case 'l': // 1 strings to match.
+ return MCK_orl; // "orl"
+ case 'q': // 1 strings to match.
+ return MCK_orq; // "orq"
+ case 'w': // 1 strings to match.
+ return MCK_orw; // "orw"
+ }
+ break;
+ case 'p': // 1 strings to match.
+ if (Name.substr(1,2) != "or")
+ break;
+ return MCK_por; // "por"
+ case 'r': // 1 strings to match.
+ if (Name.substr(1,2) != "et")
+ break;
+ return MCK_ret; // "ret"
+ case 'u': // 1 strings to match.
+ if (Name.substr(1,2) != "d2")
+ break;
+ return MCK_ud2; // "ud2"
+ }
+ break;
+ case 4: // 156 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 12 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'd': // 8 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_adcb; // "adcb"
+ case 'l': // 1 strings to match.
+ return MCK_adcl; // "adcl"
+ case 'q': // 1 strings to match.
+ return MCK_adcq; // "adcq"
+ case 'w': // 1 strings to match.
+ return MCK_adcw; // "adcw"
+ }
+ break;
+ case 'd': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_addb; // "addb"
+ case 'l': // 1 strings to match.
+ return MCK_addl; // "addl"
+ case 'q': // 1 strings to match.
+ return MCK_addq; // "addq"
+ case 'w': // 1 strings to match.
+ return MCK_addw; // "addw"
+ }
+ break;
+ }
+ break;
+ case 'n': // 4 strings to match.
+ if (Name[2] != 'd')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_andb; // "andb"
+ case 'l': // 1 strings to match.
+ return MCK_andl; // "andl"
+ case 'q': // 1 strings to match.
+ return MCK_andq; // "andq"
+ case 'w': // 1 strings to match.
+ return MCK_andw; // "andw"
+ }
+ break;
+ }
+ break;
+ case 'b': // 6 strings to match.
+ if (Name[1] != 's')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case 'f': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_bsfl; // "bsfl"
+ case 'q': // 1 strings to match.
+ return MCK_bsfq; // "bsfq"
+ case 'w': // 1 strings to match.
+ return MCK_bsfw; // "bsfw"
+ }
+ break;
+ case 'r': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_bsrl; // "bsrl"
+ case 'q': // 1 strings to match.
+ return MCK_bsrq; // "bsrq"
+ case 'w': // 1 strings to match.
+ return MCK_bsrw; // "bsrw"
+ }
+ break;
+ }
+ break;
+ case 'c': // 11 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(2,2) != "ll")
+ break;
+ return MCK_call; // "call"
+ case 'b': // 1 strings to match.
+ if (Name.substr(2,2) != "tw")
+ break;
+ return MCK_cbtw; // "cbtw"
+ case 'l': // 2 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cltd; // "cltd"
+ case 'q': // 1 strings to match.
+ return MCK_cltq; // "cltq"
+ }
+ break;
+ case 'm': // 4 strings to match.
+ if (Name[2] != 'p')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_cmpb; // "cmpb"
+ case 'l': // 1 strings to match.
+ return MCK_cmpl; // "cmpl"
+ case 'q': // 1 strings to match.
+ return MCK_cmpq; // "cmpq"
+ case 'w': // 1 strings to match.
+ return MCK_cmpw; // "cmpw"
+ }
+ break;
+ case 'q': // 1 strings to match.
+ if (Name.substr(2,2) != "to")
+ break;
+ return MCK_cqto; // "cqto"
+ case 'w': // 2 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cwtd; // "cwtd"
+ case 'l': // 1 strings to match.
+ return MCK_cwtl; // "cwtl"
+ }
+ break;
+ }
+ break;
+ case 'd': // 10 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'e': // 4 strings to match.
+ if (Name[2] != 'c')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_decb; // "decb"
+ case 'l': // 1 strings to match.
+ return MCK_decl; // "decl"
+ case 'q': // 1 strings to match.
+ return MCK_decq; // "decq"
+ case 'w': // 1 strings to match.
+ return MCK_decw; // "decw"
+ }
+ break;
+ case 'i': // 4 strings to match.
+ if (Name[2] != 'v')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_divb; // "divb"
+ case 'l': // 1 strings to match.
+ return MCK_divl; // "divl"
+ case 'q': // 1 strings to match.
+ return MCK_divq; // "divq"
+ case 'w': // 1 strings to match.
+ return MCK_divw; // "divw"
+ }
+ break;
+ case 'p': // 2 strings to match.
+ if (Name[2] != 'p')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_dppd; // "dppd"
+ case 's': // 1 strings to match.
+ return MCK_dpps; // "dpps"
+ }
+ break;
+ }
+ break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(1,3) != "mms")
+ break;
+ return MCK_emms; // "emms"
+ case 'f': // 20 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ if (Name[3] != 's')
+ break;
+ return MCK_fabs; // "fabs"
+ case 'd': // 1 strings to match.
+ if (Name[3] != 'd')
+ break;
+ return MCK_fadd; // "fadd"
+ }
+ break;
+ case 'b': // 1 strings to match.
+ if (Name.substr(2,2) != "ld")
+ break;
+ return MCK_fbld; // "fbld"
+ case 'c': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name[3] != 's')
+ break;
+ return MCK_fchs; // "fchs"
+ case 'o': // 2 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'm': // 1 strings to match.
+ return MCK_fcom; // "fcom"
+ case 's': // 1 strings to match.
+ return MCK_fcos; // "fcos"
+ }
+ break;
+ }
+ break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(2,2) != "iv")
+ break;
+ return MCK_fdiv; // "fdiv"
+ case 'l': // 5 strings to match.
+ if (Name[2] != 'd')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '1': // 1 strings to match.
+ return MCK_fld1; // "fld1"
+ case 'l': // 1 strings to match.
+ return MCK_fldl; // "fldl"
+ case 's': // 1 strings to match.
+ return MCK_flds; // "flds"
+ case 't': // 1 strings to match.
+ return MCK_fldt; // "fldt"
+ case 'z': // 1 strings to match.
+ return MCK_fldz; // "fldz"
+ }
+ break;
+ case 'm': // 1 strings to match.
+ if (Name.substr(2,2) != "ul")
+ break;
+ return MCK_fmul; // "fmul"
+ case 's': // 5 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ if (Name[3] != 'n')
+ break;
+ return MCK_fsin; // "fsin"
+ case 't': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fstl; // "fstl"
+ case 'p': // 1 strings to match.
+ return MCK_fstp; // "fstp"
+ case 's': // 1 strings to match.
+ return MCK_fsts; // "fsts"
+ }
+ break;
+ case 'u': // 1 strings to match.
+ if (Name[3] != 'b')
+ break;
+ return MCK_fsub; // "fsub"
+ }
+ break;
+ case 't': // 1 strings to match.
+ if (Name.substr(2,2) != "st")
+ break;
+ return MCK_ftst; // "ftst"
+ case 'x': // 1 strings to match.
+ if (Name.substr(2,2) != "ch")
+ break;
+ return MCK_fxch; // "fxch"
+ }
+ break;
+ case 'i': // 4 strings to match.
+ if (Name.substr(1,2) != "nc")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_incb; // "incb"
+ case 'l': // 1 strings to match.
+ return MCK_incl; // "incl"
+ case 'q': // 1 strings to match.
+ return MCK_incq; // "incq"
+ case 'w': // 1 strings to match.
+ return MCK_incw; // "incw"
+ }
+ break;
+ case 'j': // 3 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(2,2) != "xz")
+ break;
+ return MCK_jcxz; // "jcxz"
+ case 'm': // 2 strings to match.
+ if (Name[2] != 'p')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_jmpl; // "jmpl"
+ case 'q': // 1 strings to match.
+ return MCK_jmpq; // "jmpq"
+ }
+ break;
+ }
+ break;
+ case 'l': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name[3] != 'f')
+ break;
+ return MCK_lahf; // "lahf"
+ case 'r': // 3 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_larl; // "larl"
+ case 'q': // 1 strings to match.
+ return MCK_larq; // "larq"
+ case 'w': // 1 strings to match.
+ return MCK_larw; // "larw"
+ }
+ break;
+ }
+ break;
+ case 'e': // 3 strings to match.
+ if (Name[2] != 'a')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_leal; // "leal"
+ case 'q': // 1 strings to match.
+ return MCK_leaq; // "leaq"
+ case 'w': // 1 strings to match.
+ return MCK_leaw; // "leaw"
+ }
+ break;
+ case 'o': // 1 strings to match.
+ if (Name.substr(2,2) != "op")
+ break;
+ return MCK_loop; // "loop"
+ case 'r': // 1 strings to match.
+ if (Name.substr(2,2) != "et")
+ break;
+ return MCK_lret; // "lret"
+ }
+ break;
+ case 'm': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'o': // 5 strings to match.
+ if (Name[2] != 'v')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_movb; // "movb"
+ case 'd': // 1 strings to match.
+ return MCK_movd; // "movd"
+ case 'l': // 1 strings to match.
+ return MCK_movl; // "movl"
+ case 'q': // 1 strings to match.
+ return MCK_movq; // "movq"
+ case 'w': // 1 strings to match.
+ return MCK_movw; // "movw"
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[2] != 'l')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_mulb; // "mulb"
+ case 'l': // 1 strings to match.
+ return MCK_mull; // "mull"
+ case 'q': // 1 strings to match.
+ return MCK_mulq; // "mulq"
+ case 'w': // 1 strings to match.
+ return MCK_mulw; // "mulw"
+ }
+ break;
+ }
+ break;
+ case 'n': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'e': // 4 strings to match.
+ if (Name[2] != 'g')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_negb; // "negb"
+ case 'l': // 1 strings to match.
+ return MCK_negl; // "negl"
+ case 'q': // 1 strings to match.
+ return MCK_negq; // "negq"
+ case 'w': // 1 strings to match.
+ return MCK_negw; // "negw"
+ }
+ break;
+ case 'o': // 5 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ if (Name[3] != 'l')
+ break;
+ return MCK_nopl; // "nopl"
+ case 't': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_notb; // "notb"
+ case 'l': // 1 strings to match.
+ return MCK_notl; // "notl"
+ case 'q': // 1 strings to match.
+ return MCK_notq; // "notq"
+ case 'w': // 1 strings to match.
+ return MCK_notw; // "notw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'o': // 5 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'r': // 2 strings to match.
+ if (Name[2] != 'p')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_orpd; // "orpd"
+ case 's': // 1 strings to match.
+ return MCK_orps; // "orps"
+ }
+ break;
+ case 'u': // 3 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_outb; // "outb"
+ case 'l': // 1 strings to match.
+ return MCK_outl; // "outl"
+ case 'w': // 1 strings to match.
+ return MCK_outw; // "outw"
+ }
+ break;
+ }
+ break;
+ case 'p': // 6 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(2,2) != "nd")
+ break;
+ return MCK_pand; // "pand"
+ case 'o': // 4 strings to match.
+ if (Name[2] != 'p')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'f': // 1 strings to match.
+ return MCK_popf; // "popf"
+ case 'l': // 1 strings to match.
+ return MCK_popl; // "popl"
+ case 'q': // 1 strings to match.
+ return MCK_popq; // "popq"
+ case 'w': // 1 strings to match.
+ return MCK_popw; // "popw"
+ }
+ break;
+ case 'x': // 1 strings to match.
+ if (Name.substr(2,2) != "or")
+ break;
+ return MCK_pxor; // "pxor"
+ }
+ break;
+ case 'r': // 16 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 8 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_rclb; // "rclb"
+ case 'l': // 1 strings to match.
+ return MCK_rcll; // "rcll"
+ case 'q': // 1 strings to match.
+ return MCK_rclq; // "rclq"
+ case 'w': // 1 strings to match.
+ return MCK_rclw; // "rclw"
+ }
+ break;
+ case 'r': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_rcrb; // "rcrb"
+ case 'l': // 1 strings to match.
+ return MCK_rcrl; // "rcrl"
+ case 'q': // 1 strings to match.
+ return MCK_rcrq; // "rcrq"
+ case 'w': // 1 strings to match.
+ return MCK_rcrw; // "rcrw"
+ }
+ break;
+ }
+ break;
+ case 'o': // 8 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_rolb; // "rolb"
+ case 'l': // 1 strings to match.
+ return MCK_roll; // "roll"
+ case 'q': // 1 strings to match.
+ return MCK_rolq; // "rolq"
+ case 'w': // 1 strings to match.
+ return MCK_rolw; // "rolw"
+ }
+ break;
+ case 'r': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_rorb; // "rorb"
+ case 'l': // 1 strings to match.
+ return MCK_rorl; // "rorl"
+ case 'q': // 1 strings to match.
+ return MCK_rorq; // "rorq"
+ case 'w': // 1 strings to match.
+ return MCK_rorw; // "rorw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's': // 29 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 5 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name[3] != 'f')
+ break;
+ return MCK_sahf; // "sahf"
+ case 'r': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_sarb; // "sarb"
+ case 'l': // 1 strings to match.
+ return MCK_sarl; // "sarl"
+ case 'q': // 1 strings to match.
+ return MCK_sarq; // "sarq"
+ case 'w': // 1 strings to match.
+ return MCK_sarw; // "sarw"
+ }
+ break;
+ }
+ break;
+ case 'b': // 4 strings to match.
+ if (Name[2] != 'b')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_sbbb; // "sbbb"
+ case 'l': // 1 strings to match.
+ return MCK_sbbl; // "sbbl"
+ case 'q': // 1 strings to match.
+ return MCK_sbbq; // "sbbq"
+ case 'w': // 1 strings to match.
+ return MCK_sbbw; // "sbbw"
+ }
+ break;
+ case 'e': // 8 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ return MCK_seta; // "seta"
+ case 'b': // 1 strings to match.
+ return MCK_setb; // "setb"
+ case 'e': // 1 strings to match.
+ return MCK_sete; // "sete"
+ case 'g': // 1 strings to match.
+ return MCK_setg; // "setg"
+ case 'l': // 1 strings to match.
+ return MCK_setl; // "setl"
+ case 'o': // 1 strings to match.
+ return MCK_seto; // "seto"
+ case 'p': // 1 strings to match.
+ return MCK_setp; // "setp"
+ case 's': // 1 strings to match.
+ return MCK_sets; // "sets"
+ }
+ break;
+ case 'h': // 8 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_shlb; // "shlb"
+ case 'l': // 1 strings to match.
+ return MCK_shll; // "shll"
+ case 'q': // 1 strings to match.
+ return MCK_shlq; // "shlq"
+ case 'w': // 1 strings to match.
+ return MCK_shlw; // "shlw"
+ }
+ break;
+ case 'r': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_shrb; // "shrb"
+ case 'l': // 1 strings to match.
+ return MCK_shrl; // "shrl"
+ case 'q': // 1 strings to match.
+ return MCK_shrq; // "shrq"
+ case 'w': // 1 strings to match.
+ return MCK_shrw; // "shrw"
+ }
+ break;
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[2] != 'b')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_subb; // "subb"
+ case 'l': // 1 strings to match.
+ return MCK_subl; // "subl"
+ case 'q': // 1 strings to match.
+ return MCK_subq; // "subq"
+ case 'w': // 1 strings to match.
+ return MCK_subw; // "subw"
+ }
+ break;
+ }
+ break;
+ case 'w': // 1 strings to match.
+ if (Name.substr(1,3) != "ait")
+ break;
+ return MCK_wait; // "wait"
+ case 'x': // 5 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(2,2) != "hg")
+ break;
+ return MCK_xchg; // "xchg"
+ case 'o': // 4 strings to match.
+ if (Name[2] != 'r')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_xorb; // "xorb"
+ case 'l': // 1 strings to match.
+ return MCK_xorl; // "xorl"
+ case 'q': // 1 strings to match.
+ return MCK_xorq; // "xorq"
+ case 'w': // 1 strings to match.
+ return MCK_xorw; // "xorw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 5: // 147 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 6 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'd': // 4 strings to match.
+ if (Name[2] != 'd')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_addpd; // "addpd"
+ case 's': // 1 strings to match.
+ return MCK_addps; // "addps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_addsd; // "addsd"
+ case 's': // 1 strings to match.
+ return MCK_addss; // "addss"
+ }
+ break;
+ }
+ break;
+ case 'n': // 2 strings to match.
+ if (Name.substr(2,2) != "dp")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_andpd; // "andpd"
+ case 's': // 1 strings to match.
+ return MCK_andps; // "andps"
+ }
+ break;
+ }
+ break;
+ case 'c': // 13 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'm': // 12 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'o': // 8 strings to match.
+ if (Name[3] != 'v')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ return MCK_cmova; // "cmova"
+ case 'b': // 1 strings to match.
+ return MCK_cmovb; // "cmovb"
+ case 'e': // 1 strings to match.
+ return MCK_cmove; // "cmove"
+ case 'g': // 1 strings to match.
+ return MCK_cmovg; // "cmovg"
+ case 'l': // 1 strings to match.
+ return MCK_cmovl; // "cmovl"
+ case 'o': // 1 strings to match.
+ return MCK_cmovo; // "cmovo"
+ case 'p': // 1 strings to match.
+ return MCK_cmovp; // "cmovp"
+ case 's': // 1 strings to match.
+ return MCK_cmovs; // "cmovs"
+ }
+ break;
+ case 'p': // 4 strings to match.
+ if (Name[3] != 's')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_cmpsb; // "cmpsb"
+ case 'l': // 1 strings to match.
+ return MCK_cmpsl; // "cmpsl"
+ case 'q': // 1 strings to match.
+ return MCK_cmpsq; // "cmpsq"
+ case 'w': // 1 strings to match.
+ return MCK_cmpsw; // "cmpsw"
+ }
+ break;
+ }
+ break;
+ case 'r': // 1 strings to match.
+ if (Name.substr(2,3) != "c32")
+ break;
+ return MCK_crc32; // "crc32"
+ }
+ break;
+ case 'd': // 4 strings to match.
+ if (Name.substr(1,2) != "iv")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_divpd; // "divpd"
+ case 's': // 1 strings to match.
+ return MCK_divps; // "divps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_divsd; // "divsd"
+ case 's': // 1 strings to match.
+ return MCK_divss; // "divss"
+ }
+ break;
+ }
+ break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(1,4) != "nter")
+ break;
+ return MCK_enter; // "enter"
+ case 'f': // 29 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 3 strings to match.
+ if (Name.substr(2,2) != "dd")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_faddl; // "faddl"
+ case 'p': // 1 strings to match.
+ return MCK_faddp; // "faddp"
+ case 's': // 1 strings to match.
+ return MCK_fadds; // "fadds"
+ }
+ break;
+ case 'b': // 1 strings to match.
+ if (Name.substr(2,3) != "stp")
+ break;
+ return MCK_fbstp; // "fbstp"
+ case 'c': // 1 strings to match.
+ if (Name.substr(2,3) != "omp")
+ break;
+ return MCK_fcomp; // "fcomp"
+ case 'd': // 4 strings to match.
+ if (Name.substr(2,2) != "iv")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fdivl; // "fdivl"
+ case 'p': // 1 strings to match.
+ return MCK_fdivp; // "fdivp"
+ case 'r': // 1 strings to match.
+ return MCK_fdivr; // "fdivr"
+ case 's': // 1 strings to match.
+ return MCK_fdivs; // "fdivs"
+ }
+ break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(2,3) != "mms")
+ break;
+ return MCK_femms; // "femms"
+ case 'i': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 2 strings to match.
+ if (Name[3] != 'd')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fildl; // "fildl"
+ case 's': // 1 strings to match.
+ return MCK_filds; // "filds"
+ }
+ break;
+ case 's': // 2 strings to match.
+ if (Name[3] != 't')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fistl; // "fistl"
+ case 's': // 1 strings to match.
+ return MCK_fists; // "fists"
+ }
+ break;
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(2,3) != "dcw")
+ break;
+ return MCK_fldcw; // "fldcw"
+ case 'm': // 3 strings to match.
+ if (Name.substr(2,2) != "ul")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fmull; // "fmull"
+ case 'p': // 1 strings to match.
+ return MCK_fmulp; // "fmulp"
+ case 's': // 1 strings to match.
+ return MCK_fmuls; // "fmuls"
+ }
+ break;
+ case 's': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(3,2) != "ve")
+ break;
+ return MCK_fsave; // "fsave"
+ case 'q': // 1 strings to match.
+ if (Name.substr(3,2) != "rt")
+ break;
+ return MCK_fsqrt; // "fsqrt"
+ case 't': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 3 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fstpl; // "fstpl"
+ case 's': // 1 strings to match.
+ return MCK_fstps; // "fstps"
+ case 't': // 1 strings to match.
+ return MCK_fstpt; // "fstpt"
+ }
+ break;
+ case 's': // 1 strings to match.
+ if (Name[4] != 'w')
+ break;
+ return MCK_fstsw; // "fstsw"
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[3] != 'b')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fsubl; // "fsubl"
+ case 'p': // 1 strings to match.
+ return MCK_fsubp; // "fsubp"
+ case 'r': // 1 strings to match.
+ return MCK_fsubr; // "fsubr"
+ case 's': // 1 strings to match.
+ return MCK_fsubs; // "fsubs"
+ }
+ break;
+ }
+ break;
+ case 'u': // 1 strings to match.
+ if (Name.substr(2,3) != "com")
+ break;
+ return MCK_fucom; // "fucom"
+ }
+ break;
+ case 'i': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'd': // 4 strings to match.
+ if (Name.substr(2,2) != "iv")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_idivb; // "idivb"
+ case 'l': // 1 strings to match.
+ return MCK_idivl; // "idivl"
+ case 'q': // 1 strings to match.
+ return MCK_idivq; // "idivq"
+ case 'w': // 1 strings to match.
+ return MCK_idivw; // "idivw"
+ }
+ break;
+ case 'm': // 4 strings to match.
+ if (Name.substr(2,2) != "ul")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_imulb; // "imulb"
+ case 'l': // 1 strings to match.
+ return MCK_imull; // "imull"
+ case 'q': // 1 strings to match.
+ return MCK_imulq; // "imulq"
+ case 'w': // 1 strings to match.
+ return MCK_imulw; // "imulw"
+ }
+ break;
+ }
+ break;
+ case 'l': // 10 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(2,3) != "dqu")
+ break;
+ return MCK_lddqu; // "lddqu"
+ case 'e': // 1 strings to match.
+ if (Name.substr(2,3) != "ave")
+ break;
+ return MCK_leave; // "leave"
+ case 'j': // 3 strings to match.
+ if (Name.substr(2,2) != "mp")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_ljmpl; // "ljmpl"
+ case 'q': // 1 strings to match.
+ return MCK_ljmpq; // "ljmpq"
+ case 'w': // 1 strings to match.
+ return MCK_ljmpw; // "ljmpw"
+ }
+ break;
+ case 'o': // 5 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'd': // 4 strings to match.
+ if (Name[3] != 's')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_lodsb; // "lodsb"
+ case 'd': // 1 strings to match.
+ return MCK_lodsd; // "lodsd"
+ case 'q': // 1 strings to match.
+ return MCK_lodsq; // "lodsq"
+ case 'w': // 1 strings to match.
+ return MCK_lodsw; // "lodsw"
+ }
+ break;
+ case 'o': // 1 strings to match.
+ if (Name.substr(3,2) != "pe")
+ break;
+ return MCK_loope; // "loope"
+ }
+ break;
+ }
+ break;
+ case 'm': // 15 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 4 strings to match.
+ if (Name[2] != 'x')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_maxpd; // "maxpd"
+ case 's': // 1 strings to match.
+ return MCK_maxps; // "maxps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_maxsd; // "maxsd"
+ case 's': // 1 strings to match.
+ return MCK_maxss; // "maxss"
+ }
+ break;
+ }
+ break;
+ case 'i': // 4 strings to match.
+ if (Name[2] != 'n')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_minpd; // "minpd"
+ case 's': // 1 strings to match.
+ return MCK_minps; // "minps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_minsd; // "minsd"
+ case 's': // 1 strings to match.
+ return MCK_minss; // "minss"
+ }
+ break;
+ }
+ break;
+ case 'o': // 2 strings to match.
+ if (Name.substr(2,2) != "vs")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movsd; // "movsd"
+ case 's': // 1 strings to match.
+ return MCK_movss; // "movss"
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[2] != 'l')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_mulpd; // "mulpd"
+ case 's': // 1 strings to match.
+ return MCK_mulps; // "mulps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_mulsd; // "mulsd"
+ case 's': // 1 strings to match.
+ return MCK_mulss; // "mulss"
+ }
+ break;
+ }
+ break;
+ case 'w': // 1 strings to match.
+ if (Name.substr(2,3) != "ait")
+ break;
+ return MCK_mwait; // "mwait"
+ }
+ break;
+ case 'p': // 27 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'b': // 3 strings to match.
+ if (Name[3] != 's')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pabsb; // "pabsb"
+ case 'd': // 1 strings to match.
+ return MCK_pabsd; // "pabsd"
+ case 'w': // 1 strings to match.
+ return MCK_pabsw; // "pabsw"
+ }
+ break;
+ case 'd': // 4 strings to match.
+ if (Name[3] != 'd')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_paddb; // "paddb"
+ case 'd': // 1 strings to match.
+ return MCK_paddd; // "paddd"
+ case 'q': // 1 strings to match.
+ return MCK_paddq; // "paddq"
+ case 'w': // 1 strings to match.
+ return MCK_paddw; // "paddw"
+ }
+ break;
+ case 'n': // 1 strings to match.
+ if (Name.substr(3,2) != "dn")
+ break;
+ return MCK_pandn; // "pandn"
+ case 'v': // 2 strings to match.
+ if (Name[3] != 'g')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pavgb; // "pavgb"
+ case 'w': // 1 strings to match.
+ return MCK_pavgw; // "pavgw"
+ }
+ break;
+ }
+ break;
+ case 's': // 12 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 3 strings to match.
+ if (Name[3] != 'l')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pslld; // "pslld"
+ case 'q': // 1 strings to match.
+ return MCK_psllq; // "psllq"
+ case 'w': // 1 strings to match.
+ return MCK_psllw; // "psllw"
+ }
+ break;
+ case 'r': // 5 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_psrad; // "psrad"
+ case 'w': // 1 strings to match.
+ return MCK_psraw; // "psraw"
+ }
+ break;
+ case 'l': // 3 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_psrld; // "psrld"
+ case 'q': // 1 strings to match.
+ return MCK_psrlq; // "psrlq"
+ case 'w': // 1 strings to match.
+ return MCK_psrlw; // "psrlw"
+ }
+ break;
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[3] != 'b')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_psubb; // "psubb"
+ case 'd': // 1 strings to match.
+ return MCK_psubd; // "psubd"
+ case 'q': // 1 strings to match.
+ return MCK_psubq; // "psubq"
+ case 'w': // 1 strings to match.
+ return MCK_psubw; // "psubw"
+ }
+ break;
+ }
+ break;
+ case 't': // 1 strings to match.
+ if (Name.substr(2,3) != "est")
+ break;
+ return MCK_ptest; // "ptest"
+ case 'u': // 4 strings to match.
+ if (Name.substr(2,2) != "sh")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'f': // 1 strings to match.
+ return MCK_pushf; // "pushf"
+ case 'l': // 1 strings to match.
+ return MCK_pushl; // "pushl"
+ case 'q': // 1 strings to match.
+ return MCK_pushq; // "pushq"
+ case 'w': // 1 strings to match.
+ return MCK_pushw; // "pushw"
+ }
+ break;
+ }
+ break;
+ case 'r': // 3 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 2 strings to match.
+ if (Name[2] != 'p')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ if (Name[4] != 's')
+ break;
+ return MCK_rcpps; // "rcpps"
+ case 's': // 1 strings to match.
+ if (Name[4] != 's')
+ break;
+ return MCK_rcpss; // "rcpss"
+ }
+ break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(2,3) != "tsc")
+ break;
+ return MCK_rdtsc; // "rdtsc"
+ }
+ break;
+ case 's': // 22 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 4 strings to match.
+ if (Name.substr(2,2) != "as")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_scasb; // "scasb"
+ case 'l': // 1 strings to match.
+ return MCK_scasl; // "scasl"
+ case 'q': // 1 strings to match.
+ return MCK_scasq; // "scasq"
+ case 'w': // 1 strings to match.
+ return MCK_scasw; // "scasw"
+ }
+ break;
+ case 'e': // 8 strings to match.
+ if (Name[2] != 't')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name[4] != 'e')
+ break;
+ return MCK_setae; // "setae"
+ case 'b': // 1 strings to match.
+ if (Name[4] != 'e')
+ break;
+ return MCK_setbe; // "setbe"
+ case 'g': // 1 strings to match.
+ if (Name[4] != 'e')
+ break;
+ return MCK_setge; // "setge"
+ case 'l': // 1 strings to match.
+ if (Name[4] != 'e')
+ break;
+ return MCK_setle; // "setle"
+ case 'n': // 4 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ return MCK_setne; // "setne"
+ case 'o': // 1 strings to match.
+ return MCK_setno; // "setno"
+ case 'p': // 1 strings to match.
+ return MCK_setnp; // "setnp"
+ case 's': // 1 strings to match.
+ return MCK_setns; // "setns"
+ }
+ break;
+ }
+ break;
+ case 'h': // 6 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'l': // 3 strings to match.
+ if (Name[3] != 'd')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_shldl; // "shldl"
+ case 'q': // 1 strings to match.
+ return MCK_shldq; // "shldq"
+ case 'w': // 1 strings to match.
+ return MCK_shldw; // "shldw"
+ }
+ break;
+ case 'r': // 3 strings to match.
+ if (Name[3] != 'd')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_shrdl; // "shrdl"
+ case 'q': // 1 strings to match.
+ return MCK_shrdq; // "shrdq"
+ case 'w': // 1 strings to match.
+ return MCK_shrdw; // "shrdw"
+ }
+ break;
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[2] != 'b')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_subpd; // "subpd"
+ case 's': // 1 strings to match.
+ return MCK_subps; // "subps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_subsd; // "subsd"
+ case 's': // 1 strings to match.
+ return MCK_subss; // "subss"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 't': // 4 strings to match.
+ if (Name.substr(1,3) != "est")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_testb; // "testb"
+ case 'l': // 1 strings to match.
+ return MCK_testl; // "testl"
+ case 'q': // 1 strings to match.
+ return MCK_testq; // "testq"
+ case 'w': // 1 strings to match.
+ return MCK_testw; // "testw"
+ }
+ break;
+ case 'x': // 5 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 3 strings to match.
+ if (Name.substr(2,2) != "hg")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_xchgb; // "xchgb"
+ case 'l': // 1 strings to match.
+ return MCK_xchgl; // "xchgl"
+ case 'w': // 1 strings to match.
+ return MCK_xchgw; // "xchgw"
+ }
+ break;
+ case 'o': // 2 strings to match.
+ if (Name.substr(2,2) != "rp")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_xorpd; // "xorpd"
+ case 's': // 1 strings to match.
+ return MCK_xorps; // "xorps"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 6: // 120 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name.substr(1,4) != "ndnp")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_andnpd; // "andnpd"
+ case 's': // 1 strings to match.
+ return MCK_andnps; // "andnps"
+ }
+ break;
+ case 'b': // 2 strings to match.
+ if (Name.substr(1,4) != "swap")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_bswapl; // "bswapl"
+ case 'q': // 1 strings to match.
+ return MCK_bswapq; // "bswapq"
+ }
+ break;
+ case 'c': // 9 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'm': // 8 strings to match.
+ if (Name.substr(2,2) != "ov")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name[5] != 'e')
+ break;
+ return MCK_cmovae; // "cmovae"
+ case 'b': // 1 strings to match.
+ if (Name[5] != 'e')
+ break;
+ return MCK_cmovbe; // "cmovbe"
+ case 'g': // 1 strings to match.
+ if (Name[5] != 'e')
+ break;
+ return MCK_cmovge; // "cmovge"
+ case 'l': // 1 strings to match.
+ if (Name[5] != 'e')
+ break;
+ return MCK_cmovle; // "cmovle"
+ case 'n': // 4 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'e': // 1 strings to match.
+ return MCK_cmovne; // "cmovne"
+ case 'o': // 1 strings to match.
+ return MCK_cmovno; // "cmovno"
+ case 'p': // 1 strings to match.
+ return MCK_cmovnp; // "cmovnp"
+ case 's': // 1 strings to match.
+ return MCK_cmovns; // "cmovns"
+ }
+ break;
+ }
+ break;
+ case 'o': // 1 strings to match.
+ if (Name.substr(2,4) != "misd")
+ break;
+ return MCK_comisd; // "comisd"
+ }
+ break;
+ case 'f': // 29 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 3 strings to match.
+ if (Name.substr(2,3) != "mov")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_fcmovb; // "fcmovb"
+ case 'e': // 1 strings to match.
+ return MCK_fcmove; // "fcmove"
+ case 'u': // 1 strings to match.
+ return MCK_fcmovu; // "fcmovu"
+ }
+ break;
+ case 'd': // 3 strings to match.
+ if (Name.substr(2,3) != "ivr")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fdivrl; // "fdivrl"
+ case 'p': // 1 strings to match.
+ return MCK_fdivrp; // "fdivrp"
+ case 's': // 1 strings to match.
+ return MCK_fdivrs; // "fdivrs"
+ }
+ break;
+ case 'i': // 13 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name.substr(3,2) != "dd")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fiaddl; // "fiaddl"
+ case 's': // 1 strings to match.
+ return MCK_fiadds; // "fiadds"
+ }
+ break;
+ case 'c': // 2 strings to match.
+ if (Name.substr(3,2) != "om")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_ficoml; // "ficoml"
+ case 'w': // 1 strings to match.
+ return MCK_ficomw; // "ficomw"
+ }
+ break;
+ case 'd': // 2 strings to match.
+ if (Name.substr(3,2) != "iv")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fidivl; // "fidivl"
+ case 's': // 1 strings to match.
+ return MCK_fidivs; // "fidivs"
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(3,3) != "dll")
+ break;
+ return MCK_fildll; // "fildll"
+ case 'm': // 2 strings to match.
+ if (Name.substr(3,2) != "ul")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fimull; // "fimull"
+ case 's': // 1 strings to match.
+ return MCK_fimuls; // "fimuls"
+ }
+ break;
+ case 's': // 4 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 't': // 2 strings to match.
+ if (Name[4] != 'p')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fistpl; // "fistpl"
+ case 's': // 1 strings to match.
+ return MCK_fistps; // "fistps"
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name[4] != 'b')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fisubl; // "fisubl"
+ case 's': // 1 strings to match.
+ return MCK_fisubs; // "fisubs"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(2,4) != "denv")
+ break;
+ return MCK_fldenv; // "fldenv"
+ case 'n': // 2 strings to match.
+ if (Name.substr(2,2) != "st")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name[5] != 'w')
+ break;
+ return MCK_fnstcw; // "fnstcw"
+ case 's': // 1 strings to match.
+ if (Name[5] != 'w')
+ break;
+ return MCK_fnstsw; // "fnstsw"
+ }
+ break;
+ case 'r': // 1 strings to match.
+ if (Name.substr(2,4) != "stor")
+ break;
+ return MCK_frstor; // "frstor"
+ case 's': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 't': // 1 strings to match.
+ if (Name.substr(3,3) != "env")
+ break;
+ return MCK_fstenv; // "fstenv"
+ case 'u': // 3 strings to match.
+ if (Name.substr(3,2) != "br")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fsubrl; // "fsubrl"
+ case 'p': // 1 strings to match.
+ return MCK_fsubrp; // "fsubrp"
+ case 's': // 1 strings to match.
+ return MCK_fsubrs; // "fsubrs"
+ }
+ break;
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name.substr(2,3) != "com")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return MCK_fucomi; // "fucomi"
+ case 'p': // 1 strings to match.
+ return MCK_fucomp; // "fucomp"
+ }
+ break;
+ }
+ break;
+ case 'h': // 4 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name.substr(2,3) != "ddp")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_haddpd; // "haddpd"
+ case 's': // 1 strings to match.
+ return MCK_haddps; // "haddps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ if (Name.substr(2,3) != "ubp")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_hsubpd; // "hsubpd"
+ case 's': // 1 strings to match.
+ return MCK_hsubps; // "hsubps"
+ }
+ break;
+ }
+ break;
+ case 'l': // 5 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 3 strings to match.
+ if (Name.substr(2,3) != "all")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_lcalll; // "lcalll"
+ case 'q': // 1 strings to match.
+ return MCK_lcallq; // "lcallq"
+ case 'w': // 1 strings to match.
+ return MCK_lcallw; // "lcallw"
+ }
+ break;
+ case 'f': // 1 strings to match.
+ if (Name.substr(2,4) != "ence")
+ break;
+ return MCK_lfence; // "lfence"
+ case 'o': // 1 strings to match.
+ if (Name.substr(2,4) != "opne")
+ break;
+ return MCK_loopne; // "loopne"
+ }
+ break;
+ case 'm': // 20 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'f': // 1 strings to match.
+ if (Name.substr(2,4) != "ence")
+ break;
+ return MCK_mfence; // "mfence"
+ case 'o': // 19 strings to match.
+ if (Name[2] != 'v')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name[4] != 'p')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movapd; // "movapd"
+ case 's': // 1 strings to match.
+ return MCK_movaps; // "movaps"
+ }
+ break;
+ case 'd': // 2 strings to match.
+ if (Name[4] != 'q')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ return MCK_movdqa; // "movdqa"
+ case 'u': // 1 strings to match.
+ return MCK_movdqu; // "movdqu"
+ }
+ break;
+ case 'h': // 2 strings to match.
+ if (Name[4] != 'p')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movhpd; // "movhpd"
+ case 's': // 1 strings to match.
+ return MCK_movhps; // "movhps"
+ }
+ break;
+ case 'l': // 2 strings to match.
+ if (Name[4] != 'p')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movlpd; // "movlpd"
+ case 's': // 1 strings to match.
+ return MCK_movlps; // "movlps"
+ }
+ break;
+ case 'n': // 2 strings to match.
+ if (Name[4] != 't')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return MCK_movnti; // "movnti"
+ case 'q': // 1 strings to match.
+ return MCK_movntq; // "movntq"
+ }
+ break;
+ case 's': // 5 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_movsbl; // "movsbl"
+ case 'q': // 1 strings to match.
+ return MCK_movsbq; // "movsbq"
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name[5] != 'q')
+ break;
+ return MCK_movslq; // "movslq"
+ case 'w': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_movswl; // "movswl"
+ case 'q': // 1 strings to match.
+ return MCK_movswq; // "movswq"
+ }
+ break;
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name[4] != 'p')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movupd; // "movupd"
+ case 's': // 1 strings to match.
+ return MCK_movups; // "movups"
+ }
+ break;
+ case 'z': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ if (Name[5] != 'l')
+ break;
+ return MCK_movzbl; // "movzbl"
+ case 'w': // 1 strings to match.
+ if (Name[5] != 'l')
+ break;
+ return MCK_movzwl; // "movzwl"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'p': // 41 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name.substr(2,3) != "dds")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_paddsb; // "paddsb"
+ case 'w': // 1 strings to match.
+ return MCK_paddsw; // "paddsw"
+ }
+ break;
+ case 'e': // 4 strings to match.
+ if (Name.substr(2,3) != "xtr")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pextrb; // "pextrb"
+ case 'd': // 1 strings to match.
+ return MCK_pextrd; // "pextrd"
+ case 'q': // 1 strings to match.
+ return MCK_pextrq; // "pextrq"
+ case 'w': // 1 strings to match.
+ return MCK_pextrw; // "pextrw"
+ }
+ break;
+ case 'h': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name.substr(3,2) != "dd")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_phaddd; // "phaddd"
+ case 'w': // 1 strings to match.
+ return MCK_phaddw; // "phaddw"
+ }
+ break;
+ case 's': // 2 strings to match.
+ if (Name.substr(3,2) != "ub")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_phsubd; // "phsubd"
+ case 'w': // 1 strings to match.
+ return MCK_phsubw; // "phsubw"
+ }
+ break;
+ }
+ break;
+ case 'i': // 4 strings to match.
+ if (Name.substr(2,3) != "nsr")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pinsrb; // "pinsrb"
+ case 'd': // 1 strings to match.
+ return MCK_pinsrd; // "pinsrd"
+ case 'q': // 1 strings to match.
+ return MCK_pinsrq; // "pinsrq"
+ case 'w': // 1 strings to match.
+ return MCK_pinsrw; // "pinsrw"
+ }
+ break;
+ case 'm': // 16 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 6 strings to match.
+ if (Name[3] != 'x')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 's': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pmaxsb; // "pmaxsb"
+ case 'd': // 1 strings to match.
+ return MCK_pmaxsd; // "pmaxsd"
+ case 'w': // 1 strings to match.
+ return MCK_pmaxsw; // "pmaxsw"
+ }
+ break;
+ case 'u': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pmaxub; // "pmaxub"
+ case 'd': // 1 strings to match.
+ return MCK_pmaxud; // "pmaxud"
+ case 'w': // 1 strings to match.
+ return MCK_pmaxuw; // "pmaxuw"
+ }
+ break;
+ }
+ break;
+ case 'i': // 6 strings to match.
+ if (Name[3] != 'n')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 's': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pminsb; // "pminsb"
+ case 'd': // 1 strings to match.
+ return MCK_pminsd; // "pminsd"
+ case 'w': // 1 strings to match.
+ return MCK_pminsw; // "pminsw"
+ }
+ break;
+ case 'u': // 3 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pminub; // "pminub"
+ case 'd': // 1 strings to match.
+ return MCK_pminud; // "pminud"
+ case 'w': // 1 strings to match.
+ return MCK_pminuw; // "pminuw"
+ }
+ break;
+ }
+ break;
+ case 'u': // 4 strings to match.
+ if (Name[3] != 'l')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[5] != 'q')
+ break;
+ return MCK_pmuldq; // "pmuldq"
+ case 'h': // 1 strings to match.
+ if (Name[5] != 'w')
+ break;
+ return MCK_pmulhw; // "pmulhw"
+ case 'l': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pmulld; // "pmulld"
+ case 'w': // 1 strings to match.
+ return MCK_pmullw; // "pmullw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's': // 11 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(3,3) != "dbw")
+ break;
+ return MCK_psadbw; // "psadbw"
+ case 'h': // 3 strings to match.
+ if (Name.substr(3,2) != "uf")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pshufb; // "pshufb"
+ case 'd': // 1 strings to match.
+ return MCK_pshufd; // "pshufd"
+ case 'w': // 1 strings to match.
+ return MCK_pshufw; // "pshufw"
+ }
+ break;
+ case 'i': // 3 strings to match.
+ if (Name.substr(3,2) != "gn")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_psignb; // "psignb"
+ case 'd': // 1 strings to match.
+ return MCK_psignd; // "psignd"
+ case 'w': // 1 strings to match.
+ return MCK_psignw; // "psignw"
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(3,3) != "ldq")
+ break;
+ return MCK_pslldq; // "pslldq"
+ case 'r': // 1 strings to match.
+ if (Name.substr(3,3) != "ldq")
+ break;
+ return MCK_psrldq; // "psrldq"
+ case 'u': // 2 strings to match.
+ if (Name.substr(3,2) != "bs")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_psubsb; // "psubsb"
+ case 'w': // 1 strings to match.
+ return MCK_psubsw; // "psubsw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'f': // 1 strings to match.
+ if (Name.substr(2,4) != "ence")
+ break;
+ return MCK_sfence; // "sfence"
+ case 'h': // 2 strings to match.
+ if (Name.substr(2,3) != "ufp")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_shufpd; // "shufpd"
+ case 's': // 1 strings to match.
+ return MCK_shufps; // "shufps"
+ }
+ break;
+ case 'q': // 4 strings to match.
+ if (Name.substr(2,2) != "rt")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_sqrtpd; // "sqrtpd"
+ case 's': // 1 strings to match.
+ return MCK_sqrtps; // "sqrtps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_sqrtsd; // "sqrtsd"
+ case 's': // 1 strings to match.
+ return MCK_sqrtss; // "sqrtss"
+ }
+ break;
+ }
+ break;
+ case 'y': // 1 strings to match.
+ if (Name.substr(2,4) != "sret")
+ break;
+ return MCK_sysret; // "sysret"
+ }
+ break;
+ }
+ break;
+ case 7: // 58 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'b': // 2 strings to match.
+ if (Name.substr(1,5) != "lendp")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_blendpd; // "blendpd"
+ case 's': // 1 strings to match.
+ return MCK_blendps; // "blendps"
+ }
+ break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(1,6) != "lflush")
+ break;
+ return MCK_clflush; // "clflush"
+ case 'f': // 15 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 4 strings to match.
+ if (Name.substr(2,3) != "mov")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ if (Name[6] != 'e')
+ break;
+ return MCK_fcmovbe; // "fcmovbe"
+ case 'n': // 3 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_fcmovnb; // "fcmovnb"
+ case 'e': // 1 strings to match.
+ return MCK_fcmovne; // "fcmovne"
+ case 'u': // 1 strings to match.
+ return MCK_fcmovnu; // "fcmovnu"
+ }
+ break;
+ }
+ break;
+ case 'i': // 9 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 2 strings to match.
+ if (Name.substr(3,3) != "omp")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_ficompl; // "ficompl"
+ case 'w': // 1 strings to match.
+ return MCK_ficompw; // "ficompw"
+ }
+ break;
+ case 'd': // 2 strings to match.
+ if (Name.substr(3,3) != "ivr")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fidivrl; // "fidivrl"
+ case 's': // 1 strings to match.
+ return MCK_fidivrs; // "fidivrs"
+ }
+ break;
+ case 's': // 5 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 't': // 3 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ if (Name.substr(5,2) != "ll")
+ break;
+ return MCK_fistpll; // "fistpll"
+ case 't': // 2 strings to match.
+ if (Name[5] != 'p')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fisttpl; // "fisttpl"
+ case 's': // 1 strings to match.
+ return MCK_fisttps; // "fisttps"
+ }
+ break;
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name.substr(4,2) != "br")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'l': // 1 strings to match.
+ return MCK_fisubrl; // "fisubrl"
+ case 's': // 1 strings to match.
+ return MCK_fisubrs; // "fisubrs"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name.substr(2,3) != "com")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ if (Name[6] != 'p')
+ break;
+ return MCK_fucomip; // "fucomip"
+ case 'p': // 1 strings to match.
+ if (Name[6] != 'p')
+ break;
+ return MCK_fucompp; // "fucompp"
+ }
+ break;
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(1,6) != "dmxcsr")
+ break;
+ return MCK_ldmxcsr; // "ldmxcsr"
+ case 'm': // 11 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'o': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'n': // 1 strings to match.
+ if (Name.substr(3,4) != "itor")
+ break;
+ return MCK_monitor; // "monitor"
+ case 'v': // 9 strings to match.
+ switch (Name[3]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(4,3) != "bsq")
+ break;
+ return MCK_movabsq; // "movabsq"
+ case 'd': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(5,2) != "up")
+ break;
+ return MCK_movddup; // "movddup"
+ case 'q': // 1 strings to match.
+ if (Name.substr(5,2) != "2q")
+ break;
+ return MCK_movdq2q; // "movdq2q"
+ }
+ break;
+ case 'h': // 1 strings to match.
+ if (Name.substr(4,3) != "lps")
+ break;
+ return MCK_movhlps; // "movhlps"
+ case 'l': // 1 strings to match.
+ if (Name.substr(4,3) != "hps")
+ break;
+ return MCK_movlhps; // "movlhps"
+ case 'n': // 3 strings to match.
+ if (Name[4] != 't')
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[6] != 'q')
+ break;
+ return MCK_movntdq; // "movntdq"
+ case 'p': // 2 strings to match.
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movntpd; // "movntpd"
+ case 's': // 1 strings to match.
+ return MCK_movntps; // "movntps"
+ }
+ break;
+ }
+ break;
+ case 'q': // 1 strings to match.
+ if (Name.substr(4,3) != "2dq")
+ break;
+ return MCK_movq2dq; // "movq2dq"
+ }
+ break;
+ }
+ break;
+ case 'p': // 1 strings to match.
+ if (Name.substr(2,5) != "sadbw")
+ break;
+ return MCK_mpsadbw; // "mpsadbw"
+ }
+ break;
+ case 'p': // 21 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'd': // 2 strings to match.
+ if (Name.substr(3,3) != "dus")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_paddusb; // "paddusb"
+ case 'w': // 1 strings to match.
+ return MCK_paddusw; // "paddusw"
+ }
+ break;
+ case 'l': // 1 strings to match.
+ if (Name.substr(3,4) != "ignr")
+ break;
+ return MCK_palignr; // "palignr"
+ }
+ break;
+ case 'b': // 1 strings to match.
+ if (Name.substr(2,5) != "lendw")
+ break;
+ return MCK_pblendw; // "pblendw"
+ case 'c': // 8 strings to match.
+ if (Name.substr(2,2) != "mp")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'e': // 4 strings to match.
+ if (Name[5] != 'q')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pcmpeqb; // "pcmpeqb"
+ case 'd': // 1 strings to match.
+ return MCK_pcmpeqd; // "pcmpeqd"
+ case 'q': // 1 strings to match.
+ return MCK_pcmpeqq; // "pcmpeqq"
+ case 'w': // 1 strings to match.
+ return MCK_pcmpeqw; // "pcmpeqw"
+ }
+ break;
+ case 'g': // 4 strings to match.
+ if (Name[5] != 't')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_pcmpgtb; // "pcmpgtb"
+ case 'd': // 1 strings to match.
+ return MCK_pcmpgtd; // "pcmpgtd"
+ case 'q': // 1 strings to match.
+ return MCK_pcmpgtq; // "pcmpgtq"
+ case 'w': // 1 strings to match.
+ return MCK_pcmpgtw; // "pcmpgtw"
+ }
+ break;
+ }
+ break;
+ case 'h': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(3,4) != "ddsw")
+ break;
+ return MCK_phaddsw; // "phaddsw"
+ case 's': // 1 strings to match.
+ if (Name.substr(3,4) != "ubsw")
+ break;
+ return MCK_phsubsw; // "phsubsw"
+ }
+ break;
+ case 'm': // 3 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(3,4) != "ddwd")
+ break;
+ return MCK_pmaddwd; // "pmaddwd"
+ case 'u': // 2 strings to match.
+ if (Name[3] != 'l')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name.substr(5,2) != "uw")
+ break;
+ return MCK_pmulhuw; // "pmulhuw"
+ case 'u': // 1 strings to match.
+ if (Name.substr(5,2) != "dq")
+ break;
+ return MCK_pmuludq; // "pmuludq"
+ }
+ break;
+ }
+ break;
+ case 's': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'h': // 2 strings to match.
+ if (Name.substr(3,2) != "uf")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name[6] != 'w')
+ break;
+ return MCK_pshufhw; // "pshufhw"
+ case 'l': // 1 strings to match.
+ if (Name[6] != 'w')
+ break;
+ return MCK_pshuflw; // "pshuflw"
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name.substr(3,3) != "bus")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_psubusb; // "psubusb"
+ case 'w': // 1 strings to match.
+ return MCK_psubusw; // "psubusw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'r': // 2 strings to match.
+ if (Name.substr(1,4) != "sqrt")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ if (Name[6] != 's')
+ break;
+ return MCK_rsqrtps; // "rsqrtps"
+ case 's': // 1 strings to match.
+ if (Name[6] != 's')
+ break;
+ return MCK_rsqrtss; // "rsqrtss"
+ }
+ break;
+ case 's': // 3 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 't': // 1 strings to match.
+ if (Name.substr(2,5) != "mxcsr")
+ break;
+ return MCK_stmxcsr; // "stmxcsr"
+ case 'y': // 2 strings to match.
+ if (Name[2] != 's')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(4,3) != "all")
+ break;
+ return MCK_syscall; // "syscall"
+ case 'e': // 1 strings to match.
+ if (Name.substr(4,3) != "xit")
+ break;
+ return MCK_sysexit; // "sysexit"
+ }
+ break;
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name.substr(1,5) != "comis")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_ucomisd; // "ucomisd"
+ case 's': // 1 strings to match.
+ return MCK_ucomiss; // "ucomiss"
+ }
+ break;
+ }
+ break;
+ case 8: // 49 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 2 strings to match.
+ if (Name.substr(1,6) != "ddsubp")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_addsubpd; // "addsubpd"
+ case 's': // 1 strings to match.
+ return MCK_addsubps; // "addsubps"
+ }
+ break;
+ case 'b': // 2 strings to match.
+ if (Name.substr(1,6) != "lendvp")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_blendvpd; // "blendvpd"
+ case 's': // 1 strings to match.
+ return MCK_blendvps; // "blendvps"
+ }
+ break;
+ case 'c': // 12 strings to match.
+ if (Name.substr(1,2) != "vt")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'd': // 2 strings to match.
+ if (Name.substr(4,3) != "q2p")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cvtdq2pd; // "cvtdq2pd"
+ case 's': // 1 strings to match.
+ return MCK_cvtdq2ps; // "cvtdq2ps"
+ }
+ break;
+ case 'p': // 6 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 2 strings to match.
+ if (Name[5] != '2')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'q')
+ break;
+ return MCK_cvtpd2dq; // "cvtpd2dq"
+ case 'p': // 1 strings to match.
+ if (Name[7] != 'i')
+ break;
+ return MCK_cvtpd2pi; // "cvtpd2pi"
+ }
+ break;
+ case 'i': // 2 strings to match.
+ if (Name.substr(5,2) != "2p")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cvtpi2pd; // "cvtpi2pd"
+ case 's': // 1 strings to match.
+ return MCK_cvtpi2ps; // "cvtpi2ps"
+ }
+ break;
+ case 's': // 2 strings to match.
+ if (Name[5] != '2')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'q')
+ break;
+ return MCK_cvtps2dq; // "cvtps2dq"
+ case 'p': // 1 strings to match.
+ if (Name[7] != 'i')
+ break;
+ return MCK_cvtps2pi; // "cvtps2pi"
+ }
+ break;
+ }
+ break;
+ case 's': // 4 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(5,3) != "2ss")
+ break;
+ return MCK_cvtsd2ss; // "cvtsd2ss"
+ case 'i': // 2 strings to match.
+ if (Name.substr(5,2) != "2s")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_cvtsi2sd; // "cvtsi2sd"
+ case 's': // 1 strings to match.
+ return MCK_cvtsi2ss; // "cvtsi2ss"
+ }
+ break;
+ case 's': // 1 strings to match.
+ if (Name.substr(5,3) != "2sd")
+ break;
+ return MCK_cvtss2sd; // "cvtss2sd"
+ }
+ break;
+ }
+ break;
+ case 'f': // 2 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name.substr(2,6) != "movnbe")
+ break;
+ return MCK_fcmovnbe; // "fcmovnbe"
+ case 'i': // 1 strings to match.
+ if (Name.substr(2,6) != "sttpll")
+ break;
+ return MCK_fisttpll; // "fisttpll"
+ }
+ break;
+ case 'i': // 1 strings to match.
+ if (Name.substr(1,7) != "nsertps")
+ break;
+ return MCK_insertps; // "insertps"
+ case 'm': // 6 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 1 strings to match.
+ if (Name.substr(2,6) != "skmovq")
+ break;
+ return MCK_maskmovq; // "maskmovq"
+ case 'o': // 5 strings to match.
+ if (Name[2] != 'v')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 'm': // 2 strings to match.
+ if (Name.substr(4,3) != "skp")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_movmskpd; // "movmskpd"
+ case 's': // 1 strings to match.
+ return MCK_movmskps; // "movmskps"
+ }
+ break;
+ case 'n': // 1 strings to match.
+ if (Name.substr(4,4) != "tdqa")
+ break;
+ return MCK_movntdqa; // "movntdqa"
+ case 's': // 2 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name.substr(5,3) != "dup")
+ break;
+ return MCK_movshdup; // "movshdup"
+ case 'l': // 1 strings to match.
+ if (Name.substr(5,3) != "dup")
+ break;
+ return MCK_movsldup; // "movsldup"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'p': // 19 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 4 strings to match.
+ if (Name.substr(2,2) != "ck")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 's': // 2 strings to match.
+ if (Name[5] != 's')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'w')
+ break;
+ return MCK_packssdw; // "packssdw"
+ case 'w': // 1 strings to match.
+ if (Name[7] != 'b')
+ break;
+ return MCK_packsswb; // "packsswb"
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name[5] != 's')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'w')
+ break;
+ return MCK_packusdw; // "packusdw"
+ case 'w': // 1 strings to match.
+ if (Name[7] != 'b')
+ break;
+ return MCK_packuswb; // "packuswb"
+ }
+ break;
+ }
+ break;
+ case 'b': // 1 strings to match.
+ if (Name.substr(2,6) != "lendvb")
+ break;
+ return MCK_pblendvb; // "pblendvb"
+ case 'm': // 14 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'o': // 13 strings to match.
+ if (Name[3] != 'v')
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'm': // 1 strings to match.
+ if (Name.substr(5,3) != "skb")
+ break;
+ return MCK_pmovmskb; // "pmovmskb"
+ case 's': // 6 strings to match.
+ if (Name[5] != 'x')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 3 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pmovsxbd; // "pmovsxbd"
+ case 'q': // 1 strings to match.
+ return MCK_pmovsxbq; // "pmovsxbq"
+ case 'w': // 1 strings to match.
+ return MCK_pmovsxbw; // "pmovsxbw"
+ }
+ break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'q')
+ break;
+ return MCK_pmovsxdq; // "pmovsxdq"
+ case 'w': // 2 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pmovsxwd; // "pmovsxwd"
+ case 'q': // 1 strings to match.
+ return MCK_pmovsxwq; // "pmovsxwq"
+ }
+ break;
+ }
+ break;
+ case 'z': // 6 strings to match.
+ if (Name[5] != 'x')
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'b': // 3 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pmovzxbd; // "pmovzxbd"
+ case 'q': // 1 strings to match.
+ return MCK_pmovzxbq; // "pmovzxbq"
+ case 'w': // 1 strings to match.
+ return MCK_pmovzxbw; // "pmovzxbw"
+ }
+ break;
+ case 'd': // 1 strings to match.
+ if (Name[7] != 'q')
+ break;
+ return MCK_pmovzxdq; // "pmovzxdq"
+ case 'w': // 2 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_pmovzxwd; // "pmovzxwd"
+ case 'q': // 1 strings to match.
+ return MCK_pmovzxwq; // "pmovzxwq"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'u': // 1 strings to match.
+ if (Name.substr(3,5) != "lhrsw")
+ break;
+ return MCK_pmulhrsw; // "pmulhrsw"
+ }
+ break;
+ }
+ break;
+ case 's': // 1 strings to match.
+ if (Name.substr(1,7) != "ysenter")
+ break;
+ return MCK_sysenter; // "sysenter"
+ case 'u': // 4 strings to match.
+ if (Name.substr(1,4) != "npck")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'h': // 2 strings to match.
+ if (Name[6] != 'p')
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_unpckhpd; // "unpckhpd"
+ case 's': // 1 strings to match.
+ return MCK_unpckhps; // "unpckhps"
+ }
+ break;
+ case 'l': // 2 strings to match.
+ if (Name[6] != 'p')
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ return MCK_unpcklpd; // "unpcklpd"
+ case 's': // 1 strings to match.
+ return MCK_unpcklps; // "unpcklps"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 9: // 26 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'c': // 6 strings to match.
+ if (Name.substr(1,2) != "vt")
+ break;
+ switch (Name[3]) {
+ default: break;
+ case 's': // 2 strings to match.
+ if (Name.substr(4,3) != "i2s")
+ break;
+ switch (Name[7]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_cvtsi2sdq; // "cvtsi2sdq"
+ case 's': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_cvtsi2ssq; // "cvtsi2ssq"
+ }
+ break;
+ case 't': // 4 strings to match.
+ switch (Name[4]) {
+ default: break;
+ case 'p': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(6,3) != "2pi")
+ break;
+ return MCK_cvttpd2pi; // "cvttpd2pi"
+ case 's': // 1 strings to match.
+ if (Name.substr(6,3) != "2pi")
+ break;
+ return MCK_cvttps2pi; // "cvttps2pi"
+ }
+ break;
+ case 's': // 2 strings to match.
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(6,3) != "2si")
+ break;
+ return MCK_cvttsd2si; // "cvttsd2si"
+ case 's': // 1 strings to match.
+ if (Name.substr(6,3) != "2si")
+ break;
+ return MCK_cvttss2si; // "cvttss2si"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(1,8) != "xtractps")
+ break;
+ return MCK_extractps; // "extractps"
+ case 'p': // 11 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'c': // 4 strings to match.
+ if (Name.substr(2,2) != "mp")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'e': // 2 strings to match.
+ if (Name.substr(5,3) != "str")
+ break;
+ switch (Name[8]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return MCK_pcmpestri; // "pcmpestri"
+ case 'm': // 1 strings to match.
+ return MCK_pcmpestrm; // "pcmpestrm"
+ }
+ break;
+ case 'i': // 2 strings to match.
+ if (Name.substr(5,3) != "str")
+ break;
+ switch (Name[8]) {
+ default: break;
+ case 'i': // 1 strings to match.
+ return MCK_pcmpistri; // "pcmpistri"
+ case 'm': // 1 strings to match.
+ return MCK_pcmpistrm; // "pcmpistrm"
+ }
+ break;
+ }
+ break;
+ case 'm': // 1 strings to match.
+ if (Name.substr(2,7) != "addubsw")
+ break;
+ return MCK_pmaddubsw; // "pmaddubsw"
+ case 'u': // 6 strings to match.
+ if (Name.substr(2,4) != "npck")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'h': // 3 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ if (Name[8] != 'w')
+ break;
+ return MCK_punpckhbw; // "punpckhbw"
+ case 'd': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_punpckhdq; // "punpckhdq"
+ case 'w': // 1 strings to match.
+ if (Name[8] != 'd')
+ break;
+ return MCK_punpckhwd; // "punpckhwd"
+ }
+ break;
+ case 'l': // 3 strings to match.
+ switch (Name[7]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ if (Name[8] != 'w')
+ break;
+ return MCK_punpcklbw; // "punpcklbw"
+ case 'd': // 1 strings to match.
+ if (Name[8] != 'q')
+ break;
+ return MCK_punpckldq; // "punpckldq"
+ case 'w': // 1 strings to match.
+ if (Name[8] != 'd')
+ break;
+ return MCK_punpcklwd; // "punpcklwd"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'r': // 8 strings to match.
+ if (Name.substr(1,3) != "ep;")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'm': // 4 strings to match.
+ if (Name.substr(5,3) != "ovs")
+ break;
+ switch (Name[8]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_rep_59_movsb; // "rep;movsb"
+ case 'l': // 1 strings to match.
+ return MCK_rep_59_movsl; // "rep;movsl"
+ case 'q': // 1 strings to match.
+ return MCK_rep_59_movsq; // "rep;movsq"
+ case 'w': // 1 strings to match.
+ return MCK_rep_59_movsw; // "rep;movsw"
+ }
+ break;
+ case 's': // 4 strings to match.
+ if (Name.substr(5,3) != "tos")
+ break;
+ switch (Name[8]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_rep_59_stosb; // "rep;stosb"
+ case 'l': // 1 strings to match.
+ return MCK_rep_59_stosl; // "rep;stosl"
+ case 'q': // 1 strings to match.
+ return MCK_rep_59_stosq; // "rep;stosq"
+ case 'w': // 1 strings to match.
+ return MCK_rep_59_stosw; // "rep;stosw"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 10: // 9 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'c': // 2 strings to match.
+ if (Name.substr(1,4) != "vtts")
+ break;
+ switch (Name[5]) {
+ default: break;
+ case 'd': // 1 strings to match.
+ if (Name.substr(6,4) != "2siq")
+ break;
+ return MCK_cvttsd2siq; // "cvttsd2siq"
+ case 's': // 1 strings to match.
+ if (Name.substr(6,4) != "2siq")
+ break;
+ return MCK_cvttss2siq; // "cvttss2siq"
+ }
+ break;
+ case 'm': // 1 strings to match.
+ if (Name.substr(1,9) != "askmovdqu")
+ break;
+ return MCK_maskmovdqu; // "maskmovdqu"
+ case 'p': // 6 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name.substr(2,8) != "minposuw")
+ break;
+ return MCK_phminposuw; // "phminposuw"
+ case 'r': // 3 strings to match.
+ if (Name.substr(2,7) != "efetcht")
+ break;
+ switch (Name[9]) {
+ default: break;
+ case '0': // 1 strings to match.
+ return MCK_prefetcht0; // "prefetcht0"
+ case '1': // 1 strings to match.
+ return MCK_prefetcht1; // "prefetcht1"
+ case '2': // 1 strings to match.
+ return MCK_prefetcht2; // "prefetcht2"
+ }
+ break;
+ case 'u': // 2 strings to match.
+ if (Name.substr(2,4) != "npck")
+ break;
+ switch (Name[6]) {
+ default: break;
+ case 'h': // 1 strings to match.
+ if (Name.substr(7,3) != "qdq")
+ break;
+ return MCK_punpckhqdq; // "punpckhqdq"
+ case 'l': // 1 strings to match.
+ if (Name.substr(7,3) != "qdq")
+ break;
+ return MCK_punpcklqdq; // "punpcklqdq"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 11: // 1 strings to match.
+ if (Name.substr(0,11) != "prefetchnta")
+ break;
+ return MCK_prefetchnta; // "prefetchnta"
+ }
+ return InvalidMatchClass;
+}
+
+static MatchClassKind ClassifyOperand(X86Operand &Operand) {
+ if (Operand.isToken())
+ return MatchTokenString(Operand.getToken());
+
+ if (Operand.isReg()) {
+ switch (Operand.getReg()) {
+ default: return InvalidMatchClass;
+ case X86::AL: return MCK_AL;
+ case X86::DL: return MCK_GR8_ABCD_L;
+ case X86::CL: return MCK_CL;
+ case X86::BL: return MCK_GR8_ABCD_L;
+ case X86::SIL: return MCK_GR8_NOREX;
+ case X86::DIL: return MCK_GR8_NOREX;
+ case X86::BPL: return MCK_GR8_NOREX;
+ case X86::SPL: return MCK_GR8_NOREX;
+ case X86::R8B: return MCK_GR8;
+ case X86::R9B: return MCK_GR8;
+ case X86::R10B: return MCK_GR8;
+ case X86::R11B: return MCK_GR8;
+ case X86::R12B: return MCK_GR8;
+ case X86::R13B: return MCK_GR8;
+ case X86::R14B: return MCK_GR8;
+ case X86::R15B: return MCK_GR8;
+ case X86::AH: return MCK_GR8_ABCD_H;
+ case X86::DH: return MCK_GR8_ABCD_H;
+ case X86::CH: return MCK_GR8_ABCD_H;
+ case X86::BH: return MCK_GR8_ABCD_H;
+ case X86::AX: return MCK_AX;
+ case X86::DX: return MCK_DX;
+ case X86::CX: return MCK_GR16_ABCD;
+ case X86::BX: return MCK_GR16_ABCD;
+ case X86::SI: return MCK_GR16_NOREX;
+ case X86::DI: return MCK_GR16_NOREX;
+ case X86::BP: return MCK_GR16_NOREX;
+ case X86::SP: return MCK_GR16_NOREX;
+ case X86::R8W: return MCK_GR16;
+ case X86::R9W: return MCK_GR16;
+ case X86::R10W: return MCK_GR16;
+ case X86::R11W: return MCK_GR16;
+ case X86::R12W: return MCK_GR16;
+ case X86::R13W: return MCK_GR16;
+ case X86::R14W: return MCK_GR16;
+ case X86::R15W: return MCK_GR16;
+ case X86::EAX: return MCK_EAX;
+ case X86::EDX: return MCK_GR32_AD;
+ case X86::ECX: return MCK_GR32_ABCD;
+ case X86::EBX: return MCK_GR32_ABCD;
+ case X86::ESI: return MCK_Reg14;
+ case X86::EDI: return MCK_Reg14;
+ case X86::EBP: return MCK_Reg14;
+ case X86::ESP: return MCK_GR32_NOREX;
+ case X86::R8D: return MCK_GR32_NOSP;
+ case X86::R9D: return MCK_GR32_NOSP;
+ case X86::R10D: return MCK_GR32_NOSP;
+ case X86::R11D: return MCK_GR32_NOSP;
+ case X86::R12D: return MCK_GR32_NOSP;
+ case X86::R13D: return MCK_GR32_NOSP;
+ case X86::R14D: return MCK_GR32_NOSP;
+ case X86::R15D: return MCK_GR32_NOSP;
+ case X86::RAX: return MCK_RAX;
+ case X86::RDX: return MCK_GR64_ABCD;
+ case X86::RCX: return MCK_GR64_ABCD;
+ case X86::RBX: return MCK_GR64_ABCD;
+ case X86::RSI: return MCK_GR64_NOREX_NOSP;
+ case X86::RDI: return MCK_GR64_NOREX_NOSP;
+ case X86::RBP: return MCK_GR64_NOREX_NOSP;
+ case X86::RSP: return MCK_GR64_NOREX;
+ case X86::R8: return MCK_GR64_NOSP;
+ case X86::R9: return MCK_GR64_NOSP;
+ case X86::R10: return MCK_GR64_NOSP;
+ case X86::R11: return MCK_GR64_NOSP;
+ case X86::R12: return MCK_GR64_NOSP;
+ case X86::R13: return MCK_GR64_NOSP;
+ case X86::R14: return MCK_GR64_NOSP;
+ case X86::R15: return MCK_GR64_NOSP;
+ case X86::RIP: return MCK_GR64_NOREX;
+ case X86::MM0: return MCK_VR64;
+ case X86::MM1: return MCK_VR64;
+ case X86::MM2: return MCK_VR64;
+ case X86::MM3: return MCK_VR64;
+ case X86::MM4: return MCK_VR64;
+ case X86::MM5: return MCK_VR64;
+ case X86::MM6: return MCK_VR64;
+ case X86::MM7: return MCK_VR64;
+ case X86::FP0: return MCK_RFP32;
+ case X86::FP1: return MCK_RFP32;
+ case X86::FP2: return MCK_RFP32;
+ case X86::FP3: return MCK_RFP32;
+ case X86::FP4: return MCK_RFP32;
+ case X86::FP5: return MCK_RFP32;
+ case X86::FP6: return MCK_RFP32;
+ case X86::XMM0: return MCK_XMM0;
+ case X86::XMM1: return MCK_FR32;
+ case X86::XMM2: return MCK_FR32;
+ case X86::XMM3: return MCK_FR32;
+ case X86::XMM4: return MCK_FR32;
+ case X86::XMM5: return MCK_FR32;
+ case X86::XMM6: return MCK_FR32;
+ case X86::XMM7: return MCK_FR32;
+ case X86::XMM8: return MCK_FR32;
+ case X86::XMM9: return MCK_FR32;
+ case X86::XMM10: return MCK_FR32;
+ case X86::XMM11: return MCK_FR32;
+ case X86::XMM12: return MCK_FR32;
+ case X86::XMM13: return MCK_FR32;
+ case X86::XMM14: return MCK_FR32;
+ case X86::XMM15: return MCK_FR32;
+ case X86::YMM0: return MCK_VR256;
+ case X86::YMM1: return MCK_VR256;
+ case X86::YMM2: return MCK_VR256;
+ case X86::YMM3: return MCK_VR256;
+ case X86::YMM4: return MCK_VR256;
+ case X86::YMM5: return MCK_VR256;
+ case X86::YMM6: return MCK_VR256;
+ case X86::YMM7: return MCK_VR256;
+ case X86::YMM8: return MCK_VR256;
+ case X86::YMM9: return MCK_VR256;
+ case X86::YMM10: return MCK_VR256;
+ case X86::YMM11: return MCK_VR256;
+ case X86::YMM12: return MCK_VR256;
+ case X86::YMM13: return MCK_VR256;
+ case X86::YMM14: return MCK_VR256;
+ case X86::YMM15: return MCK_VR256;
+ case X86::ST0: return MCK_ST0;
+ case X86::ST1: return MCK_RST;
+ case X86::ST2: return MCK_RST;
+ case X86::ST3: return MCK_RST;
+ case X86::ST4: return MCK_RST;
+ case X86::ST5: return MCK_RST;
+ case X86::ST6: return MCK_RST;
+ case X86::ST7: return MCK_RST;
+ case X86::EFLAGS: return MCK_CCR;
+ case X86::CS: return MCK_SEGMENT_REG;
+ case X86::DS: return MCK_SEGMENT_REG;
+ case X86::SS: return MCK_SEGMENT_REG;
+ case X86::ES: return MCK_SEGMENT_REG;
+ case X86::FS: return MCK_SEGMENT_REG;
+ case X86::GS: return MCK_SEGMENT_REG;
+ }
+ }
+
+ // 'ImmSExt8' class, subclass of 'Imm'
+ if (Operand.isImmSExt8()) {
+ assert(Operand.isImm() && "Invalid class relationship!");
+ return MCK_ImmSExt8;
+ }
+
+ // 'Imm' class
+ if (Operand.isImm()) {
+ return MCK_Imm;
+ }
+
+ // 'Mem' class
+ if (Operand.isMem()) {
+ return MCK_Mem;
+ }
+
+ return InvalidMatchClass;
+}
+
+/// IsSubclass - Compute whether \arg A is a subclass of \arg B.
+static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
+ if (A == B)
+ return true;
+
+ switch (A) {
+ default:
+ return false;
+
+ case MCK_AL:
+ switch (B) {
+ default: return false;
+ case MCK_GR8_ABCD_L: return true;
+ case MCK_GR8_NOREX: return true;
+ case MCK_GR8: return true;
+ }
+
+ case MCK_CL:
+ switch (B) {
+ default: return false;
+ case MCK_GR8_ABCD_L: return true;
+ case MCK_GR8_NOREX: return true;
+ case MCK_GR8: return true;
+ }
+
+ case MCK_GR8_ABCD_L:
+ switch (B) {
+ default: return false;
+ case MCK_GR8_NOREX: return true;
+ case MCK_GR8: return true;
+ }
+
+ case MCK_GR8_ABCD_H:
+ switch (B) {
+ default: return false;
+ case MCK_GR8_NOREX: return true;
+ case MCK_GR8: return true;
+ }
+
+ case MCK_GR8_NOREX:
+ return B == MCK_GR8;
+
+ case MCK_AX:
+ switch (B) {
+ default: return false;
+ case MCK_GR16_ABCD: return true;
+ case MCK_GR16_NOREX: return true;
+ case MCK_GR16: return true;
+ }
+
+ case MCK_DX:
+ switch (B) {
+ default: return false;
+ case MCK_GR16_ABCD: return true;
+ case MCK_GR16_NOREX: return true;
+ case MCK_GR16: return true;
+ }
+
+ case MCK_GR16_ABCD:
+ switch (B) {
+ default: return false;
+ case MCK_GR16_NOREX: return true;
+ case MCK_GR16: return true;
+ }
+
+ case MCK_GR16_NOREX:
+ return B == MCK_GR16;
+
+ case MCK_EAX:
+ switch (B) {
+ default: return false;
+ case MCK_GR32_AD: return true;
+ case MCK_GR32_ABCD: return true;
+ case MCK_Reg14: return true;
+ case MCK_GR32_NOSP: return true;
+ case MCK_GR32_NOREX: return true;
+ case MCK_GR32: return true;
+ }
+
+ case MCK_GR32_AD:
+ switch (B) {
+ default: return false;
+ case MCK_GR32_ABCD: return true;
+ case MCK_Reg14: return true;
+ case MCK_GR32_NOSP: return true;
+ case MCK_GR32_NOREX: return true;
+ case MCK_GR32: return true;
+ }
+
+ case MCK_GR32_ABCD:
+ switch (B) {
+ default: return false;
+ case MCK_Reg14: return true;
+ case MCK_GR32_NOSP: return true;
+ case MCK_GR32_NOREX: return true;
+ case MCK_GR32: return true;
+ }
+
+ case MCK_Reg14:
+ switch (B) {
+ default: return false;
+ case MCK_GR32_NOSP: return true;
+ case MCK_GR32_NOREX: return true;
+ case MCK_GR32: return true;
+ }
+
+ case MCK_GR32_NOSP:
+ return B == MCK_GR32;
+
+ case MCK_GR32_NOREX:
+ return B == MCK_GR32;
+
+ case MCK_RAX:
+ switch (B) {
+ default: return false;
+ case MCK_GR64_ABCD: return true;
+ case MCK_GR64_NOREX_NOSP: return true;
+ case MCK_GR64_NOREX: return true;
+ case MCK_GR64_NOSP: return true;
+ case MCK_GR64: return true;
+ }
+
+ case MCK_GR64_ABCD:
+ switch (B) {
+ default: return false;
+ case MCK_GR64_NOREX_NOSP: return true;
+ case MCK_GR64_NOREX: return true;
+ case MCK_GR64_NOSP: return true;
+ case MCK_GR64: return true;
+ }
+
+ case MCK_GR64_NOREX_NOSP:
+ switch (B) {
+ default: return false;
+ case MCK_GR64_NOREX: return true;
+ case MCK_GR64_NOSP: return true;
+ case MCK_GR64: return true;
+ }
+
+ case MCK_GR64_NOREX:
+ return B == MCK_GR64;
+
+ case MCK_GR64_NOSP:
+ return B == MCK_GR64;
+
+ case MCK_XMM0:
+ return B == MCK_FR32;
+
+ case MCK_ST0:
+ return B == MCK_RST;
+
+ case MCK_ImmSExt8:
+ return B == MCK_Imm;
+ }
+}
+
+bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MCInst &Inst) {
+ static const struct MatchEntry {
+ unsigned Opcode;
+ ConversionKind ConvertFn;
+ MatchClassKind Classes[5];
+ } MatchTable[1775] = {
+ { X86::CBW, Convert, { MCK_cbtw } },
+ { X86::CDQ, Convert, { MCK_cltd } },
+ { X86::CDQE, Convert, { MCK_cltq } },
+ { X86::CMPS8, Convert, { MCK_cmpsb } },
+ { X86::CMPS32, Convert, { MCK_cmpsl } },
+ { X86::CMPS64, Convert, { MCK_cmpsq } },
+ { X86::CMPS16, Convert, { MCK_cmpsw } },
+ { X86::CQO, Convert, { MCK_cqto } },
+ { X86::CWD, Convert, { MCK_cwtd } },
+ { X86::CWDE, Convert, { MCK_cwtl } },
+ { X86::MMX_EMMS, Convert, { MCK_emms } },
+ { X86::ABS_F, Convert, { MCK_fabs } },
+ { X86::CHS_F, Convert, { MCK_fchs } },
+ { X86::COS_F, Convert, { MCK_fcos } },
+ { X86::MMX_FEMMS, Convert, { MCK_femms } },
+ { X86::LD_F1, Convert, { MCK_fld1 } },
+ { X86::LD_F0, Convert, { MCK_fldz } },
+ { X86::FNSTSW8r, Convert, { MCK_fnstsw } },
+ { X86::SIN_F, Convert, { MCK_fsin } },
+ { X86::SQRT_F, Convert, { MCK_fsqrt } },
+ { X86::TST_F, Convert, { MCK_ftst } },
+ { X86::UCOM_FPPr, Convert, { MCK_fucompp } },
+ { X86::LAHF, Convert, { MCK_lahf } },
+ { X86::LEAVE, Convert, { MCK_leave } },
+ { X86::LEAVE64, Convert, { MCK_leave } },
+ { X86::LFENCE, Convert, { MCK_lfence } },
+ { X86::LODSB, Convert, { MCK_lodsb } },
+ { X86::LODSD, Convert, { MCK_lodsd } },
+ { X86::LODSQ, Convert, { MCK_lodsq } },
+ { X86::LODSW, Convert, { MCK_lodsw } },
+ { X86::LRET, Convert, { MCK_lret } },
+ { X86::MFENCE, Convert, { MCK_mfence } },
+ { X86::MONITOR, Convert, { MCK_monitor } },
+ { X86::MWAIT, Convert, { MCK_mwait } },
+ { X86::NOOP, Convert, { MCK_nop } },
+ { X86::POPFD, Convert, { MCK_popf } },
+ { X86::POPFQ, Convert, { MCK_popf } },
+ { X86::PUSHFD, Convert, { MCK_pushf } },
+ { X86::PUSHFQ, Convert, { MCK_pushf } },
+ { X86::RDTSC, Convert, { MCK_rdtsc } },
+ { X86::REP_MOVSB, Convert, { MCK_rep_59_movsb } },
+ { X86::REP_MOVSD, Convert, { MCK_rep_59_movsl } },
+ { X86::REP_MOVSQ, Convert, { MCK_rep_59_movsq } },
+ { X86::REP_MOVSW, Convert, { MCK_rep_59_movsw } },
+ { X86::REP_STOSB, Convert, { MCK_rep_59_stosb } },
+ { X86::REP_STOSD, Convert, { MCK_rep_59_stosl } },
+ { X86::REP_STOSQ, Convert, { MCK_rep_59_stosq } },
+ { X86::REP_STOSW, Convert, { MCK_rep_59_stosw } },
+ { X86::EH_RETURN64, ConvertImp, { MCK_ret } },
+ { X86::RET, Convert, { MCK_ret } },
+ { X86::SAHF, Convert, { MCK_sahf } },
+ { X86::SCAS8, Convert, { MCK_scasb } },
+ { X86::SCAS32, Convert, { MCK_scasl } },
+ { X86::SCAS64, Convert, { MCK_scasq } },
+ { X86::SCAS16, Convert, { MCK_scasw } },
+ { X86::SFENCE, Convert, { MCK_sfence } },
+ { X86::SYSCALL, Convert, { MCK_syscall } },
+ { X86::SYSENTER, Convert, { MCK_sysenter } },
+ { X86::SYSEXIT, Convert, { MCK_sysexit } },
+ { X86::SYSEXIT64, Convert, { MCK_sysexit } },
+ { X86::SYSRET, Convert, { MCK_sysret } },
+ { X86::TRAP, Convert, { MCK_ud2 } },
+ { X86::WAIT, Convert, { MCK_wait } },
+ { X86::BSWAP32r, Convert_Reg1_1Imp, { MCK_bswapl, MCK_GR32 } },
+ { X86::BSWAP64r, Convert_Reg1_1Imp, { MCK_bswapq, MCK_GR64 } },
+ { X86::WINCALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::CALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::CALLpcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::CLFLUSH, Convert_Mem5_1, { MCK_clflush, MCK_Mem } },
+ { X86::DEC8r, Convert_Reg1_1Imp, { MCK_decb, MCK_GR8 } },
+ { X86::DEC8m, Convert_Mem5_1, { MCK_decb, MCK_Mem } },
+ { X86::DEC32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
+ { X86::DEC64_32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
+ { X86::DEC64_32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC64r, Convert_Reg1_1Imp, { MCK_decq, MCK_GR64 } },
+ { X86::DEC64m, Convert_Mem5_1, { MCK_decq, MCK_Mem } },
+ { X86::DEC64_16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
+ { X86::DEC16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
+ { X86::DEC64_16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
+ { X86::DEC16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
+ { X86::DIV8r, Convert_Reg1_1, { MCK_divb, MCK_GR8 } },
+ { X86::DIV8m, Convert_Mem5_1, { MCK_divb, MCK_Mem } },
+ { X86::DIV32r, Convert_Reg1_1, { MCK_divl, MCK_GR32 } },
+ { X86::DIV32m, Convert_Mem5_1, { MCK_divl, MCK_Mem } },
+ { X86::DIV64r, Convert_Reg1_1, { MCK_divq, MCK_GR64 } },
+ { X86::DIV64m, Convert_Mem5_1, { MCK_divq, MCK_Mem } },
+ { X86::DIV16r, Convert_Reg1_1, { MCK_divw, MCK_GR16 } },
+ { X86::DIV16m, Convert_Mem5_1, { MCK_divw, MCK_Mem } },
+ { X86::ADD_FST0r, Convert_Reg1_1, { MCK_fadd, MCK_RST } },
+ { X86::ADD_F64m, Convert_Mem5_1, { MCK_faddl, MCK_Mem } },
+ { X86::ADD_FPrST0, Convert_Reg1_1, { MCK_faddp, MCK_RST } },
+ { X86::ADD_F32m, Convert_Mem5_1, { MCK_fadds, MCK_Mem } },
+ { X86::FBLDm, Convert_Mem5_1, { MCK_fbld, MCK_Mem } },
+ { X86::FBSTPm, Convert_Mem5_1, { MCK_fbstp, MCK_Mem } },
+ { X86::FCOM32m, Convert_Mem5_1, { MCK_fcom, MCK_Mem } },
+ { X86::FCOM64m, Convert_Mem5_1, { MCK_fcom, MCK_Mem } },
+ { X86::FCOMP32m, Convert_Mem5_1, { MCK_fcomp, MCK_Mem } },
+ { X86::FCOMP64m, Convert_Mem5_1, { MCK_fcomp, MCK_Mem } },
+ { X86::DIV_FST0r, Convert_Reg1_1, { MCK_fdiv, MCK_RST } },
+ { X86::DIV_F64m, Convert_Mem5_1, { MCK_fdivl, MCK_Mem } },
+ { X86::DIVR_FPrST0, Convert_Reg1_1, { MCK_fdivp, MCK_RST } },
+ { X86::DIVR_FST0r, Convert_Reg1_1, { MCK_fdivr, MCK_RST } },
+ { X86::DIVR_F64m, Convert_Mem5_1, { MCK_fdivrl, MCK_Mem } },
+ { X86::DIV_FPrST0, Convert_Reg1_1, { MCK_fdivrp, MCK_RST } },
+ { X86::DIVR_F32m, Convert_Mem5_1, { MCK_fdivrs, MCK_Mem } },
+ { X86::DIV_F32m, Convert_Mem5_1, { MCK_fdivs, MCK_Mem } },
+ { X86::ADD_FI32m, Convert_Mem5_1, { MCK_fiaddl, MCK_Mem } },
+ { X86::ADD_FI16m, Convert_Mem5_1, { MCK_fiadds, MCK_Mem } },
+ { X86::FICOM32m, Convert_Mem5_1, { MCK_ficoml, MCK_Mem } },
+ { X86::FICOMP32m, Convert_Mem5_1, { MCK_ficompl, MCK_Mem } },
+ { X86::FICOMP16m, Convert_Mem5_1, { MCK_ficompw, MCK_Mem } },
+ { X86::FICOM16m, Convert_Mem5_1, { MCK_ficomw, MCK_Mem } },
+ { X86::DIV_FI32m, Convert_Mem5_1, { MCK_fidivl, MCK_Mem } },
+ { X86::DIVR_FI32m, Convert_Mem5_1, { MCK_fidivrl, MCK_Mem } },
+ { X86::DIVR_FI16m, Convert_Mem5_1, { MCK_fidivrs, MCK_Mem } },
+ { X86::DIV_FI16m, Convert_Mem5_1, { MCK_fidivs, MCK_Mem } },
+ { X86::ILD_F32m, Convert_Mem5_1, { MCK_fildl, MCK_Mem } },
+ { X86::ILD_F64m, Convert_Mem5_1, { MCK_fildll, MCK_Mem } },
+ { X86::ILD_F16m, Convert_Mem5_1, { MCK_filds, MCK_Mem } },
+ { X86::MUL_FI32m, Convert_Mem5_1, { MCK_fimull, MCK_Mem } },
+ { X86::MUL_FI16m, Convert_Mem5_1, { MCK_fimuls, MCK_Mem } },
+ { X86::IST_F32m, Convert_Mem5_1, { MCK_fistl, MCK_Mem } },
+ { X86::IST_FP32m, Convert_Mem5_1, { MCK_fistpl, MCK_Mem } },
+ { X86::IST_FP64m, Convert_Mem5_1, { MCK_fistpll, MCK_Mem } },
+ { X86::IST_FP16m, Convert_Mem5_1, { MCK_fistps, MCK_Mem } },
+ { X86::IST_F16m, Convert_Mem5_1, { MCK_fists, MCK_Mem } },
+ { X86::FISTTP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
+ { X86::ISTT_FP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
+ { X86::ISTT_FP64m, Convert_Mem5_1, { MCK_fisttpll, MCK_Mem } },
+ { X86::ISTT_FP16m, Convert_Mem5_1, { MCK_fisttps, MCK_Mem } },
+ { X86::SUB_FI32m, Convert_Mem5_1, { MCK_fisubl, MCK_Mem } },
+ { X86::SUBR_FI32m, Convert_Mem5_1, { MCK_fisubrl, MCK_Mem } },
+ { X86::SUBR_FI16m, Convert_Mem5_1, { MCK_fisubrs, MCK_Mem } },
+ { X86::SUB_FI16m, Convert_Mem5_1, { MCK_fisubs, MCK_Mem } },
+ { X86::LD_Frr, Convert_Reg1_1, { MCK_fld, MCK_RST } },
+ { X86::FLDCW16m, Convert_Mem5_1, { MCK_fldcw, MCK_Mem } },
+ { X86::FLDENVm, Convert_Mem5_1, { MCK_fldenv, MCK_Mem } },
+ { X86::LD_F64m, Convert_Mem5_1, { MCK_fldl, MCK_Mem } },
+ { X86::LD_F32m, Convert_Mem5_1, { MCK_flds, MCK_Mem } },
+ { X86::LD_F80m, Convert_Mem5_1, { MCK_fldt, MCK_Mem } },
+ { X86::MUL_FST0r, Convert_Reg1_1, { MCK_fmul, MCK_RST } },
+ { X86::MUL_F64m, Convert_Mem5_1, { MCK_fmull, MCK_Mem } },
+ { X86::MUL_FPrST0, Convert_Reg1_1, { MCK_fmulp, MCK_RST } },
+ { X86::MUL_F32m, Convert_Mem5_1, { MCK_fmuls, MCK_Mem } },
+ { X86::FNSTCW16m, Convert_Mem5_1, { MCK_fnstcw, MCK_Mem } },
+ { X86::FRSTORm, Convert_Mem5_1, { MCK_frstor, MCK_Mem } },
+ { X86::FSAVEm, Convert_Mem5_1, { MCK_fsave, MCK_Mem } },
+ { X86::ST_Frr, Convert_Reg1_1, { MCK_fst, MCK_RST } },
+ { X86::FSTENVm, Convert_Mem5_1, { MCK_fstenv, MCK_Mem } },
+ { X86::ST_F64m, Convert_Mem5_1, { MCK_fstl, MCK_Mem } },
+ { X86::ST_FPrr, Convert_Reg1_1, { MCK_fstp, MCK_RST } },
+ { X86::ST_FP64m, Convert_Mem5_1, { MCK_fstpl, MCK_Mem } },
+ { X86::ST_FP32m, Convert_Mem5_1, { MCK_fstps, MCK_Mem } },
+ { X86::ST_FP80m, Convert_Mem5_1, { MCK_fstpt, MCK_Mem } },
+ { X86::ST_F32m, Convert_Mem5_1, { MCK_fsts, MCK_Mem } },
+ { X86::FSTSWm, Convert_Mem5_1, { MCK_fstsw, MCK_Mem } },
+ { X86::SUB_FST0r, Convert_Reg1_1, { MCK_fsub, MCK_RST } },
+ { X86::SUB_F64m, Convert_Mem5_1, { MCK_fsubl, MCK_Mem } },
+ { X86::SUBR_FPrST0, Convert_Reg1_1, { MCK_fsubp, MCK_RST } },
+ { X86::SUBR_FST0r, Convert_Reg1_1, { MCK_fsubr, MCK_RST } },
+ { X86::SUBR_F64m, Convert_Mem5_1, { MCK_fsubrl, MCK_Mem } },
+ { X86::SUB_FPrST0, Convert_Reg1_1, { MCK_fsubrp, MCK_RST } },
+ { X86::SUBR_F32m, Convert_Mem5_1, { MCK_fsubrs, MCK_Mem } },
+ { X86::SUB_F32m, Convert_Mem5_1, { MCK_fsubs, MCK_Mem } },
+ { X86::UCOM_Fr, Convert_Reg1_1, { MCK_fucom, MCK_RST } },
+ { X86::UCOM_FPr, Convert_Reg1_1, { MCK_fucomp, MCK_RST } },
+ { X86::XCH_F, Convert_Reg1_1, { MCK_fxch, MCK_RST } },
+ { X86::IDIV8r, Convert_Reg1_1, { MCK_idivb, MCK_GR8 } },
+ { X86::IDIV8m, Convert_Mem5_1, { MCK_idivb, MCK_Mem } },
+ { X86::IDIV32r, Convert_Reg1_1, { MCK_idivl, MCK_GR32 } },
+ { X86::IDIV32m, Convert_Mem5_1, { MCK_idivl, MCK_Mem } },
+ { X86::IDIV64r, Convert_Reg1_1, { MCK_idivq, MCK_GR64 } },
+ { X86::IDIV64m, Convert_Mem5_1, { MCK_idivq, MCK_Mem } },
+ { X86::IDIV16r, Convert_Reg1_1, { MCK_idivw, MCK_GR16 } },
+ { X86::IDIV16m, Convert_Mem5_1, { MCK_idivw, MCK_Mem } },
+ { X86::IMUL8r, Convert_Reg1_1, { MCK_imulb, MCK_GR8 } },
+ { X86::IMUL8m, Convert_Mem5_1, { MCK_imulb, MCK_Mem } },
+ { X86::IMUL32r, Convert_Reg1_1, { MCK_imull, MCK_GR32 } },
+ { X86::IMUL32m, Convert_Mem5_1, { MCK_imull, MCK_Mem } },
+ { X86::IMUL64r, Convert_Reg1_1, { MCK_imulq, MCK_GR64 } },
+ { X86::IMUL64m, Convert_Mem5_1, { MCK_imulq, MCK_Mem } },
+ { X86::IMUL16r, Convert_Reg1_1, { MCK_imulw, MCK_GR16 } },
+ { X86::IMUL16m, Convert_Mem5_1, { MCK_imulw, MCK_Mem } },
+ { X86::INC8r, Convert_Reg1_1Imp, { MCK_incb, MCK_GR8 } },
+ { X86::INC8m, Convert_Mem5_1, { MCK_incb, MCK_Mem } },
+ { X86::INC64_32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
+ { X86::INC32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
+ { X86::INC32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC64_32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC64r, Convert_Reg1_1Imp, { MCK_incq, MCK_GR64 } },
+ { X86::INC64m, Convert_Mem5_1, { MCK_incq, MCK_Mem } },
+ { X86::INC16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
+ { X86::INC64_16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
+ { X86::INC16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INC64_16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INT3, Convert, { MCK_int, MCK_3 } },
+ { X86::INT, Convert_Imm1_1, { MCK_int, MCK_Imm } },
+ { X86::JA8, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
+ { X86::JA, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
+ { X86::JAE8, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
+ { X86::JAE, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
+ { X86::JB8, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
+ { X86::JB, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
+ { X86::JBE, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
+ { X86::JBE8, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
+ { X86::JCXZ8, Convert_Imm1_1, { MCK_jcxz, MCK_Imm } },
+ { X86::JE, Convert_Imm1_1, { MCK_je, MCK_Imm } },
+ { X86::JE8, Convert_Imm1_1, { MCK_je, MCK_Imm } },
+ { X86::JG, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
+ { X86::JG8, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
+ { X86::JGE, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
+ { X86::JGE8, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
+ { X86::JL, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
+ { X86::JL8, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
+ { X86::JLE, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
+ { X86::JLE8, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
+ { X86::TAILJMPd, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
+ { X86::JMP, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
+ { X86::JMP8, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
+ { X86::JNE, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
+ { X86::JNE8, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
+ { X86::JNO, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
+ { X86::JNO8, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
+ { X86::JNP, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
+ { X86::JNP8, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
+ { X86::JNS, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
+ { X86::JNS8, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
+ { X86::JO8, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
+ { X86::JO, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
+ { X86::JP8, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
+ { X86::JP, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
+ { X86::JS, Convert_Imm1_1, { MCK_js, MCK_Imm } },
+ { X86::JS8, Convert_Imm1_1, { MCK_js, MCK_Imm } },
+ { X86::LDMXCSR, Convert_Mem5_1, { MCK_ldmxcsr, MCK_Mem } },
+ { X86::LOOP, Convert_Imm1_1, { MCK_loop, MCK_Imm } },
+ { X86::LOOPE, Convert_Imm1_1, { MCK_loope, MCK_Imm } },
+ { X86::LOOPNE, Convert_Imm1_1, { MCK_loopne, MCK_Imm } },
+ { X86::LRETI, Convert_Imm1_1, { MCK_lret, MCK_Imm } },
+ { X86::MUL8r, Convert_Reg1_1, { MCK_mulb, MCK_GR8 } },
+ { X86::MUL8m, Convert_Mem5_1, { MCK_mulb, MCK_Mem } },
+ { X86::MUL32r, Convert_Reg1_1, { MCK_mull, MCK_GR32 } },
+ { X86::MUL32m, Convert_Mem5_1, { MCK_mull, MCK_Mem } },
+ { X86::MUL64r, Convert_Reg1_1, { MCK_mulq, MCK_GR64 } },
+ { X86::MUL64m, Convert_Mem5_1, { MCK_mulq, MCK_Mem } },
+ { X86::MUL16r, Convert_Reg1_1, { MCK_mulw, MCK_GR16 } },
+ { X86::MUL16m, Convert_Mem5_1, { MCK_mulw, MCK_Mem } },
+ { X86::NEG8r, Convert_Reg1_1Imp, { MCK_negb, MCK_GR8 } },
+ { X86::NEG8m, Convert_Mem5_1, { MCK_negb, MCK_Mem } },
+ { X86::NEG32r, Convert_Reg1_1Imp, { MCK_negl, MCK_GR32 } },
+ { X86::NEG32m, Convert_Mem5_1, { MCK_negl, MCK_Mem } },
+ { X86::NEG64r, Convert_Reg1_1Imp, { MCK_negq, MCK_GR64 } },
+ { X86::NEG64m, Convert_Mem5_1, { MCK_negq, MCK_Mem } },
+ { X86::NEG16r, Convert_Reg1_1Imp, { MCK_negw, MCK_GR16 } },
+ { X86::NEG16m, Convert_Mem5_1, { MCK_negw, MCK_Mem } },
+ { X86::NOOPL, Convert_Mem5_1, { MCK_nopl, MCK_Mem } },
+ { X86::NOT8r, Convert_Reg1_1Imp, { MCK_notb, MCK_GR8 } },
+ { X86::NOT8m, Convert_Mem5_1, { MCK_notb, MCK_Mem } },
+ { X86::NOT32r, Convert_Reg1_1Imp, { MCK_notl, MCK_GR32 } },
+ { X86::NOT32m, Convert_Mem5_1, { MCK_notl, MCK_Mem } },
+ { X86::NOT64r, Convert_Reg1_1Imp, { MCK_notq, MCK_GR64 } },
+ { X86::NOT64m, Convert_Mem5_1, { MCK_notq, MCK_Mem } },
+ { X86::NOT16r, Convert_Reg1_1Imp, { MCK_notw, MCK_GR16 } },
+ { X86::NOT16m, Convert_Mem5_1, { MCK_notw, MCK_Mem } },
+ { X86::POP32rmr, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::POP32r, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::POP32rmm, Convert_Mem5_1, { MCK_popl, MCK_Mem } },
+ { X86::POP64r, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
+ { X86::POP64rmr, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
+ { X86::POP64rmm, Convert_Mem5_1, { MCK_popq, MCK_Mem } },
+ { X86::POP16r, Convert_Reg1_1, { MCK_popw, MCK_GR16 } },
+ { X86::POP16rmr, Convert_Reg1_1, { MCK_popw, MCK_GR16 } },
+ { X86::POP16rmm, Convert_Mem5_1, { MCK_popw, MCK_Mem } },
+ { X86::PREFETCHNTA, Convert_Mem5_1, { MCK_prefetchnta, MCK_Mem } },
+ { X86::PREFETCHT0, Convert_Mem5_1, { MCK_prefetcht0, MCK_Mem } },
+ { X86::PREFETCHT1, Convert_Mem5_1, { MCK_prefetcht1, MCK_Mem } },
+ { X86::PREFETCHT2, Convert_Mem5_1, { MCK_prefetcht2, MCK_Mem } },
+ { X86::PUSH32r, Convert_Reg1_1, { MCK_pushl, MCK_GR32 } },
+ { X86::PUSH32rmr, Convert_Reg1_1, { MCK_pushl, MCK_GR32 } },
+ { X86::PUSH32i8, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32i32, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32i16, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32rmm, Convert_Mem5_1, { MCK_pushl, MCK_Mem } },
+ { X86::PUSH64r, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
+ { X86::PUSH64rmr, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
+ { X86::PUSH64i16, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64i32, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64i8, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64rmm, Convert_Mem5_1, { MCK_pushq, MCK_Mem } },
+ { X86::PUSH16rmr, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
+ { X86::PUSH16r, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
+ { X86::PUSH16rmm, Convert_Mem5_1, { MCK_pushw, MCK_Mem } },
+ { X86::RETI, Convert_Imm1_1, { MCK_ret, MCK_Imm } },
+ { X86::ROL8r1, Convert_Reg1_1Imp, { MCK_rolb, MCK_GR8 } },
+ { X86::ROL8m1, Convert_Mem5_1, { MCK_rolb, MCK_Mem } },
+ { X86::ROL32r1, Convert_Reg1_1Imp, { MCK_roll, MCK_GR32 } },
+ { X86::ROL32m1, Convert_Mem5_1, { MCK_roll, MCK_Mem } },
+ { X86::ROL64r1, Convert_Reg1_1Imp, { MCK_rolq, MCK_GR64 } },
+ { X86::ROL64m1, Convert_Mem5_1, { MCK_rolq, MCK_Mem } },
+ { X86::ROL16r1, Convert_Reg1_1Imp, { MCK_rolw, MCK_GR16 } },
+ { X86::ROL16m1, Convert_Mem5_1, { MCK_rolw, MCK_Mem } },
+ { X86::ROR8r1, Convert_Reg1_1Imp, { MCK_rorb, MCK_GR8 } },
+ { X86::ROR8m1, Convert_Mem5_1, { MCK_rorb, MCK_Mem } },
+ { X86::ROR32r1, Convert_Reg1_1Imp, { MCK_rorl, MCK_GR32 } },
+ { X86::ROR32m1, Convert_Mem5_1, { MCK_rorl, MCK_Mem } },
+ { X86::ROR64r1, Convert_Reg1_1Imp, { MCK_rorq, MCK_GR64 } },
+ { X86::ROR64m1, Convert_Mem5_1, { MCK_rorq, MCK_Mem } },
+ { X86::ROR16r1, Convert_Reg1_1Imp, { MCK_rorw, MCK_GR16 } },
+ { X86::ROR16m1, Convert_Mem5_1, { MCK_rorw, MCK_Mem } },
+ { X86::SAR8r1, Convert_Reg1_1Imp, { MCK_sarb, MCK_GR8 } },
+ { X86::SAR8m1, Convert_Mem5_1, { MCK_sarb, MCK_Mem } },
+ { X86::SAR32r1, Convert_Reg1_1Imp, { MCK_sarl, MCK_GR32 } },
+ { X86::SAR32m1, Convert_Mem5_1, { MCK_sarl, MCK_Mem } },
+ { X86::SAR64r1, Convert_Reg1_1Imp, { MCK_sarq, MCK_GR64 } },
+ { X86::SAR64m1, Convert_Mem5_1, { MCK_sarq, MCK_Mem } },
+ { X86::SAR16r1, Convert_Reg1_1Imp, { MCK_sarw, MCK_GR16 } },
+ { X86::SAR16m1, Convert_Mem5_1, { MCK_sarw, MCK_Mem } },
+ { X86::SETAr, Convert_Reg1_1, { MCK_seta, MCK_GR8 } },
+ { X86::SETAm, Convert_Mem5_1, { MCK_seta, MCK_Mem } },
+ { X86::SETAEr, Convert_Reg1_1, { MCK_setae, MCK_GR8 } },
+ { X86::SETAEm, Convert_Mem5_1, { MCK_setae, MCK_Mem } },
+ { X86::SETBr, Convert_Reg1_1, { MCK_setb, MCK_GR8 } },
+ { X86::SETBm, Convert_Mem5_1, { MCK_setb, MCK_Mem } },
+ { X86::SETBEr, Convert_Reg1_1, { MCK_setbe, MCK_GR8 } },
+ { X86::SETBEm, Convert_Mem5_1, { MCK_setbe, MCK_Mem } },
+ { X86::SETEr, Convert_Reg1_1, { MCK_sete, MCK_GR8 } },
+ { X86::SETEm, Convert_Mem5_1, { MCK_sete, MCK_Mem } },
+ { X86::SETGr, Convert_Reg1_1, { MCK_setg, MCK_GR8 } },
+ { X86::SETGm, Convert_Mem5_1, { MCK_setg, MCK_Mem } },
+ { X86::SETGEr, Convert_Reg1_1, { MCK_setge, MCK_GR8 } },
+ { X86::SETGEm, Convert_Mem5_1, { MCK_setge, MCK_Mem } },
+ { X86::SETLr, Convert_Reg1_1, { MCK_setl, MCK_GR8 } },
+ { X86::SETLm, Convert_Mem5_1, { MCK_setl, MCK_Mem } },
+ { X86::SETLEr, Convert_Reg1_1, { MCK_setle, MCK_GR8 } },
+ { X86::SETLEm, Convert_Mem5_1, { MCK_setle, MCK_Mem } },
+ { X86::SETNEr, Convert_Reg1_1, { MCK_setne, MCK_GR8 } },
+ { X86::SETNEm, Convert_Mem5_1, { MCK_setne, MCK_Mem } },
+ { X86::SETNOr, Convert_Reg1_1, { MCK_setno, MCK_GR8 } },
+ { X86::SETNOm, Convert_Mem5_1, { MCK_setno, MCK_Mem } },
+ { X86::SETNPr, Convert_Reg1_1, { MCK_setnp, MCK_GR8 } },
+ { X86::SETNPm, Convert_Mem5_1, { MCK_setnp, MCK_Mem } },
+ { X86::SETNSr, Convert_Reg1_1, { MCK_setns, MCK_GR8 } },
+ { X86::SETNSm, Convert_Mem5_1, { MCK_setns, MCK_Mem } },
+ { X86::SETOr, Convert_Reg1_1, { MCK_seto, MCK_GR8 } },
+ { X86::SETOm, Convert_Mem5_1, { MCK_seto, MCK_Mem } },
+ { X86::SETPr, Convert_Reg1_1, { MCK_setp, MCK_GR8 } },
+ { X86::SETPm, Convert_Mem5_1, { MCK_setp, MCK_Mem } },
+ { X86::SETSr, Convert_Reg1_1, { MCK_sets, MCK_GR8 } },
+ { X86::SETSm, Convert_Mem5_1, { MCK_sets, MCK_Mem } },
+ { X86::SHL8r1, Convert_Reg1_1Imp, { MCK_shlb, MCK_GR8 } },
+ { X86::SHL8m1, Convert_Mem5_1, { MCK_shlb, MCK_Mem } },
+ { X86::SHL32r1, Convert_Reg1_1Imp, { MCK_shll, MCK_GR32 } },
+ { X86::SHL32m1, Convert_Mem5_1, { MCK_shll, MCK_Mem } },
+ { X86::SHL64m1, Convert_Mem5_1, { MCK_shlq, MCK_Mem } },
+ { X86::SHL16r1, Convert_Reg1_1Imp, { MCK_shlw, MCK_GR16 } },
+ { X86::SHL16m1, Convert_Mem5_1, { MCK_shlw, MCK_Mem } },
+ { X86::SHR8r1, Convert_Reg1_1Imp, { MCK_shrb, MCK_GR8 } },
+ { X86::SHR8m1, Convert_Mem5_1, { MCK_shrb, MCK_Mem } },
+ { X86::SHR32r1, Convert_Reg1_1Imp, { MCK_shrl, MCK_GR32 } },
+ { X86::SHR32m1, Convert_Mem5_1, { MCK_shrl, MCK_Mem } },
+ { X86::SHR64r1, Convert_Reg1_1Imp, { MCK_shrq, MCK_GR64 } },
+ { X86::SHL64r1, Convert_Reg1_1Imp, { MCK_shrq, MCK_GR64 } },
+ { X86::SHR64m1, Convert_Mem5_1, { MCK_shrq, MCK_Mem } },
+ { X86::SHR16r1, Convert_Reg1_1Imp, { MCK_shrw, MCK_GR16 } },
+ { X86::SHR16m1, Convert_Mem5_1, { MCK_shrw, MCK_Mem } },
+ { X86::STMXCSR, Convert_Mem5_1, { MCK_stmxcsr, MCK_Mem } },
+ { X86::ADC8rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
+ { X86::ADC8mr, Convert_Mem5_2_Reg1_1, { MCK_adcb, MCK_GR8, MCK_Mem } },
+ { X86::ADC8i8, Convert_Imm1_1, { MCK_adcb, MCK_Imm, MCK_AL } },
+ { X86::ADC8ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcb, MCK_Imm, MCK_GR8 } },
+ { X86::ADC8mi, Convert_Mem5_2_Imm1_1, { MCK_adcb, MCK_Imm, MCK_Mem } },
+ { X86::ADC8rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcb, MCK_Mem, MCK_GR8 } },
+ { X86::ADC32rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
+ { X86::ADC32mr, Convert_Mem5_2_Reg1_1, { MCK_adcl, MCK_GR32, MCK_Mem } },
+ { X86::ADC32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::ADC32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADC32i32, Convert_Imm1_1, { MCK_adcl, MCK_Imm, MCK_EAX } },
+ { X86::ADC32ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcl, MCK_Imm, MCK_GR32 } },
+ { X86::ADC32mi, Convert_Mem5_2_Imm1_1, { MCK_adcl, MCK_Imm, MCK_Mem } },
+ { X86::ADC32rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcl, MCK_Mem, MCK_GR32 } },
+ { X86::ADC64rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcq, MCK_GR64, MCK_GR64 } },
+ { X86::ADC64mr, Convert_Mem5_2_Reg1_1, { MCK_adcq, MCK_GR64, MCK_Mem } },
+ { X86::ADC64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::ADC64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADC64i32, Convert_Imm1_1, { MCK_adcq, MCK_Imm, MCK_RAX } },
+ { X86::ADC64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_adcq, MCK_Imm, MCK_GR64 } },
+ { X86::ADC64mi32, Convert_Mem5_2_Imm1_1, { MCK_adcq, MCK_Imm, MCK_Mem } },
+ { X86::ADC64rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcq, MCK_Mem, MCK_GR64 } },
+ { X86::ADC16rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
+ { X86::ADC16mr, Convert_Mem5_2_Reg1_1, { MCK_adcw, MCK_GR16, MCK_Mem } },
+ { X86::ADC16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::ADC16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADC16i16, Convert_Imm1_1, { MCK_adcw, MCK_Imm, MCK_AX } },
+ { X86::ADC16ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcw, MCK_Imm, MCK_GR16 } },
+ { X86::ADC16mi, Convert_Mem5_2_Imm1_1, { MCK_adcw, MCK_Imm, MCK_Mem } },
+ { X86::ADC16rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcw, MCK_Mem, MCK_GR16 } },
+ { X86::ADD8mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addb, MCK_GR8, MCK_GR8 } },
+ { X86::ADD8rr, Convert_Reg1_2_ImpReg1_1, { MCK_addb, MCK_GR8, MCK_GR8 } },
+ { X86::ADD8mr, Convert_Mem5_2_Reg1_1, { MCK_addb, MCK_GR8, MCK_Mem } },
+ { X86::ADD8i8, Convert_Imm1_1, { MCK_addb, MCK_Imm, MCK_AL } },
+ { X86::ADD8ri, Convert_Reg1_2_ImpImm1_1, { MCK_addb, MCK_Imm, MCK_GR8 } },
+ { X86::ADD8mi, Convert_Mem5_2_Imm1_1, { MCK_addb, MCK_Imm, MCK_Mem } },
+ { X86::ADD8rm, Convert_Reg1_2_ImpMem5_1, { MCK_addb, MCK_Mem, MCK_GR8 } },
+ { X86::ADD32mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addl, MCK_GR16, MCK_GR16 } },
+ { X86::ADD32rr, Convert_Reg1_2_ImpReg1_1, { MCK_addl, MCK_GR32, MCK_GR32 } },
+ { X86::ADD32mr, Convert_Mem5_2_Reg1_1, { MCK_addl, MCK_GR32, MCK_Mem } },
+ { X86::ADD64mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addl, MCK_GR64, MCK_GR64 } },
+ { X86::ADD32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::ADD32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADD32i32, Convert_Imm1_1, { MCK_addl, MCK_Imm, MCK_EAX } },
+ { X86::ADD32ri, Convert_Reg1_2_ImpImm1_1, { MCK_addl, MCK_Imm, MCK_GR32 } },
+ { X86::ADD32mi, Convert_Mem5_2_Imm1_1, { MCK_addl, MCK_Imm, MCK_Mem } },
+ { X86::ADD32rm, Convert_Reg1_2_ImpMem5_1, { MCK_addl, MCK_Mem, MCK_GR32 } },
+ { X86::ADDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_addpd, MCK_FR32, MCK_FR32 } },
+ { X86::ADDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addpd, MCK_Mem, MCK_FR32 } },
+ { X86::ADDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addps, MCK_FR32, MCK_FR32 } },
+ { X86::ADDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addps, MCK_Mem, MCK_FR32 } },
+ { X86::ADD64rr, Convert_Reg1_2_ImpReg1_1, { MCK_addq, MCK_GR64, MCK_GR64 } },
+ { X86::ADD64mr, Convert_Mem5_2_Reg1_1, { MCK_addq, MCK_GR64, MCK_Mem } },
+ { X86::ADD64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::ADD64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADD64i32, Convert_Imm1_1, { MCK_addq, MCK_Imm, MCK_RAX } },
+ { X86::ADD64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_addq, MCK_Imm, MCK_GR64 } },
+ { X86::ADD64mi32, Convert_Mem5_2_Imm1_1, { MCK_addq, MCK_Imm, MCK_Mem } },
+ { X86::ADD64rm, Convert_Reg1_2_ImpMem5_1, { MCK_addq, MCK_Mem, MCK_GR64 } },
+ { X86::ADDSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsd, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsd, MCK_Mem, MCK_FR32 } },
+ { X86::ADDSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addss, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addss, MCK_Mem, MCK_FR32 } },
+ { X86::ADDSUBPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsubpd, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsubpd, MCK_Mem, MCK_FR32 } },
+ { X86::ADDSUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsubps, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsubps, MCK_Mem, MCK_FR32 } },
+ { X86::ADD16mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
+ { X86::ADD16rr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
+ { X86::ADD16mr, Convert_Mem5_2_Reg1_1, { MCK_addw, MCK_GR16, MCK_Mem } },
+ { X86::ADD16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::ADD16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADD16i16, Convert_Imm1_1, { MCK_addw, MCK_Imm, MCK_AX } },
+ { X86::ADD16ri, Convert_Reg1_2_ImpImm1_1, { MCK_addw, MCK_Imm, MCK_GR16 } },
+ { X86::ADD16mi, Convert_Mem5_2_Imm1_1, { MCK_addw, MCK_Imm, MCK_Mem } },
+ { X86::ADD16rm, Convert_Reg1_2_ImpMem5_1, { MCK_addw, MCK_Mem, MCK_GR16 } },
+ { X86::AND8rr, Convert_Reg1_2_ImpReg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
+ { X86::AND8mr, Convert_Mem5_2_Reg1_1, { MCK_andb, MCK_GR8, MCK_Mem } },
+ { X86::AND8i8, Convert_Imm1_1, { MCK_andb, MCK_Imm, MCK_AL } },
+ { X86::AND8ri, Convert_Reg1_2_ImpImm1_1, { MCK_andb, MCK_Imm, MCK_GR8 } },
+ { X86::AND8mi, Convert_Mem5_2_Imm1_1, { MCK_andb, MCK_Imm, MCK_Mem } },
+ { X86::AND8rm, Convert_Reg1_2_ImpMem5_1, { MCK_andb, MCK_Mem, MCK_GR8 } },
+ { X86::AND32rr, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
+ { X86::AND32mr, Convert_Mem5_2_Reg1_1, { MCK_andl, MCK_GR32, MCK_Mem } },
+ { X86::AND32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::AND32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::AND32i32, Convert_Imm1_1, { MCK_andl, MCK_Imm, MCK_EAX } },
+ { X86::AND32ri, Convert_Reg1_2_ImpImm1_1, { MCK_andl, MCK_Imm, MCK_GR32 } },
+ { X86::AND32mi, Convert_Mem5_2_Imm1_1, { MCK_andl, MCK_Imm, MCK_Mem } },
+ { X86::AND32rm, Convert_Reg1_2_ImpMem5_1, { MCK_andl, MCK_Mem, MCK_GR32 } },
+ { X86::ANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
+ { X86::ANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
+ { X86::ANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
+ { X86::ANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
+ { X86::ANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
+ { X86::ANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
+ { X86::ANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
+ { X86::ANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
+ { X86::AND64rr, Convert_Reg1_2_ImpReg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
+ { X86::AND64mr, Convert_Mem5_2_Reg1_1, { MCK_andq, MCK_GR64, MCK_Mem } },
+ { X86::AND64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::AND64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::AND64i32, Convert_Imm1_1, { MCK_andq, MCK_Imm, MCK_RAX } },
+ { X86::AND64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_andq, MCK_Imm, MCK_GR64 } },
+ { X86::AND64mi32, Convert_Mem5_2_Imm1_1, { MCK_andq, MCK_Imm, MCK_Mem } },
+ { X86::AND64rm, Convert_Reg1_2_ImpMem5_1, { MCK_andq, MCK_Mem, MCK_GR64 } },
+ { X86::AND16rr, Convert_Reg1_2_ImpReg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
+ { X86::AND16mr, Convert_Mem5_2_Reg1_1, { MCK_andw, MCK_GR16, MCK_Mem } },
+ { X86::AND16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::AND16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::AND16i16, Convert_Imm1_1, { MCK_andw, MCK_Imm, MCK_AX } },
+ { X86::AND16ri, Convert_Reg1_2_ImpImm1_1, { MCK_andw, MCK_Imm, MCK_GR16 } },
+ { X86::AND16mi, Convert_Mem5_2_Imm1_1, { MCK_andw, MCK_Imm, MCK_Mem } },
+ { X86::AND16rm, Convert_Reg1_2_ImpMem5_1, { MCK_andw, MCK_Mem, MCK_GR16 } },
+ { X86::BSF32rr, Convert_Reg1_2_Reg1_1, { MCK_bsfl, MCK_GR32, MCK_GR32 } },
+ { X86::BSF32rm, Convert_Reg1_2_Mem5_1, { MCK_bsfl, MCK_Mem, MCK_GR32 } },
+ { X86::BSF64rr, Convert_Reg1_2_Reg1_1, { MCK_bsfq, MCK_GR64, MCK_GR64 } },
+ { X86::BSF64rm, Convert_Reg1_2_Mem5_1, { MCK_bsfq, MCK_Mem, MCK_GR64 } },
+ { X86::BSF16rr, Convert_Reg1_2_Reg1_1, { MCK_bsfw, MCK_GR16, MCK_GR16 } },
+ { X86::BSF16rm, Convert_Reg1_2_Mem5_1, { MCK_bsfw, MCK_Mem, MCK_GR16 } },
+ { X86::BSR32rr, Convert_Reg1_2_Reg1_1, { MCK_bsrl, MCK_GR32, MCK_GR32 } },
+ { X86::BSR32rm, Convert_Reg1_2_Mem5_1, { MCK_bsrl, MCK_Mem, MCK_GR32 } },
+ { X86::BSR64rr, Convert_Reg1_2_Reg1_1, { MCK_bsrq, MCK_GR64, MCK_GR64 } },
+ { X86::BSR64rm, Convert_Reg1_2_Mem5_1, { MCK_bsrq, MCK_Mem, MCK_GR64 } },
+ { X86::BSR16rr, Convert_Reg1_2_Reg1_1, { MCK_bsrw, MCK_GR16, MCK_GR16 } },
+ { X86::BSR16rm, Convert_Reg1_2_Mem5_1, { MCK_bsrw, MCK_Mem, MCK_GR16 } },
+ { X86::BT32rr, Convert_Reg1_2_Reg1_1, { MCK_btl, MCK_GR32, MCK_GR32 } },
+ { X86::BT32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BT32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BT64rr, Convert_Reg1_2_Reg1_1, { MCK_btq, MCK_GR64, MCK_GR64 } },
+ { X86::BT64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BT64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BT16rr, Convert_Reg1_2_Reg1_1, { MCK_btw, MCK_GR16, MCK_GR16 } },
+ { X86::BT16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BT16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CALL32r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR32 } },
+ { X86::CALL64r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR64 } },
+ { X86::WINCALL64r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR64 } },
+ { X86::CALL64m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
+ { X86::WINCALL64m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
+ { X86::CALL32m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
+ { X86::CMOVA16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmova, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVA32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmova, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVA64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmova, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVA16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmova, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVA32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmova, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVA64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmova, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVAE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovae, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVAE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovae, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVAE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovae, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVAE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovae, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVAE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovae, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVAE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovae, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovb, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovb, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovb, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovb, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovb, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovb, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVBE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbe, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVBE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbe, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVBE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbe, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVBE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbe, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVBE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbe, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVBE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbe, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmove, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmove, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmove, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmove, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmove, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmove, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVG16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovg, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVG32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovg, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVG64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovg, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVG16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovg, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVG32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovg, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVG64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovg, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVGE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovge, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVGE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovge, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVGE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovge, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVGE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovge, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVGE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovge, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVGE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovge, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVL16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovl, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVL32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVL64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovl, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVL16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovl, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVL32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVL64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovl, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVLE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovle, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVLE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovle, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVLE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovle, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVLE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovle, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVLE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovle, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVLE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovle, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovne, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovne, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovne, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovne, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovne, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovne, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovno, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovno, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovno, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovno, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovno, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovno, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnp, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnp, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnp, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnp, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnp, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnp, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovns, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovns, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovns, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovns, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovns, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovns, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovo, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovo, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovo, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovo, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovo, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovo, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovp, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovp, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovp, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovp, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovp, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovp, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovs, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovs, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovs, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovs, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovs, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovs, MCK_Mem, MCK_GR64 } },
+ { X86::CMP8mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
+ { X86::CMP8rr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
+ { X86::CMP8mr, Convert_Mem5_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_Mem } },
+ { X86::CMP8i8, Convert_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_AL } },
+ { X86::CMP8ri, Convert_Reg1_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_GR8 } },
+ { X86::CMP8mi, Convert_Mem5_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_Mem } },
+ { X86::CMP8rm, Convert_Reg1_2_Mem5_1, { MCK_cmpb, MCK_Mem, MCK_GR8 } },
+ { X86::CMP32rr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMP32mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMP32mr, Convert_Mem5_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_Mem } },
+ { X86::CMP32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::CMP32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CMP32i32, Convert_Imm1_1, { MCK_cmpl, MCK_Imm, MCK_EAX } },
+ { X86::CMP32ri, Convert_Reg1_2_Imm1_1, { MCK_cmpl, MCK_Imm, MCK_GR32 } },
+ { X86::CMP32mi, Convert_Mem5_2_Imm1_1, { MCK_cmpl, MCK_Imm, MCK_Mem } },
+ { X86::CMP32rm, Convert_Reg1_2_Mem5_1, { MCK_cmpl, MCK_Mem, MCK_GR32 } },
+ { X86::CMP64rr, Convert_Reg1_2_Reg1_1, { MCK_cmpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMP64mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMP64mr, Convert_Mem5_2_Reg1_1, { MCK_cmpq, MCK_GR64, MCK_Mem } },
+ { X86::CMP64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::CMP64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CMP64i32, Convert_Imm1_1, { MCK_cmpq, MCK_Imm, MCK_RAX } },
+ { X86::CMP64ri32, Convert_Reg1_2_Imm1_1, { MCK_cmpq, MCK_Imm, MCK_GR64 } },
+ { X86::CMP64mi32, Convert_Mem5_2_Imm1_1, { MCK_cmpq, MCK_Imm, MCK_Mem } },
+ { X86::CMP64rm, Convert_Reg1_2_Mem5_1, { MCK_cmpq, MCK_Mem, MCK_GR64 } },
+ { X86::CMP16mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMP16rr, Convert_Reg1_2_Reg1_1, { MCK_cmpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMP16mr, Convert_Mem5_2_Reg1_1, { MCK_cmpw, MCK_GR16, MCK_Mem } },
+ { X86::CMP16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::CMP16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CMP16i16, Convert_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_AX } },
+ { X86::CMP16ri, Convert_Reg1_2_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_GR16 } },
+ { X86::CMP16mi, Convert_Mem5_2_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_Mem } },
+ { X86::CMP16rm, Convert_Reg1_2_Mem5_1, { MCK_cmpw, MCK_Mem, MCK_GR16 } },
+ { X86::COMISDrr, Convert_Reg1_2_Reg1_1, { MCK_comisd, MCK_FR32, MCK_FR32 } },
+ { X86::COMISDrm, Convert_Reg1_2_Mem5_1, { MCK_comisd, MCK_Mem, MCK_FR32 } },
+ { X86::CRC32r8, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR8, MCK_GR32 } },
+ { X86::CRC32r16, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR16, MCK_GR32 } },
+ { X86::CRC32r32, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR32, MCK_GR32 } },
+ { X86::CRC64r64, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR64, MCK_GR64 } },
+ { X86::CRC32m8, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m32, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m16, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC64m64, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR64 } },
+ { X86::CVTDQ2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtdq2pd, MCK_FR32, MCK_FR32 } },
+ { X86::CVTDQ2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtdq2pd, MCK_Mem, MCK_FR32 } },
+ { X86::CVTDQ2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtdq2ps, MCK_FR32, MCK_FR32 } },
+ { X86::CVTDQ2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtdq2ps, MCK_Mem, MCK_FR32 } },
+ { X86::CVTPD2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2dq, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPD2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2dq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPD2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTPD2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2pi, MCK_Mem, MCK_VR64 } },
+ { X86::MMX_CVTPI2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpi2pd, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_CVTPI2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpi2pd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPI2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpi2ps, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_CVTPI2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpi2ps, MCK_Mem, MCK_FR32 } },
+ { X86::CVTPS2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2dq, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPS2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2dq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPS2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTPS2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTSD2SSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsd2ss, MCK_FR32, MCK_FR32 } },
+ { X86::CVTSD2SSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsd2ss, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2sd, MCK_GR32, MCK_FR32 } },
+ { X86::CVTSI2SDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2sd, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SD64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2sdq, MCK_GR64, MCK_FR32 } },
+ { X86::CVTSI2SD64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2sdq, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2ss, MCK_GR32, MCK_FR32 } },
+ { X86::CVTSI2SSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2ss, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SS64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2ssq, MCK_GR64, MCK_FR32 } },
+ { X86::CVTSI2SS64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2ssq, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSS2SDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2sd, MCK_FR32, MCK_FR32 } },
+ { X86::CVTSS2SDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2sd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTTPD2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttpd2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTTPD2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttpd2pi, MCK_Mem, MCK_VR64 } },
+ { X86::MMX_CVTTPS2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttps2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTTPS2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttps2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTTSD2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttsd2si, MCK_FR32, MCK_GR32 } },
+ { X86::CVTTSD2SIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttsd2si, MCK_Mem, MCK_GR32 } },
+ { X86::CVTTSD2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvttsd2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTTSD2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvttsd2siq, MCK_Mem, MCK_GR64 } },
+ { X86::CVTTSS2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttss2si, MCK_FR32, MCK_GR32 } },
+ { X86::CVTTSS2SIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttss2si, MCK_Mem, MCK_GR32 } },
+ { X86::CVTTSS2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvttss2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTTSS2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvttss2siq, MCK_Mem, MCK_GR64 } },
+ { X86::DIVPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_divpd, MCK_FR32, MCK_FR32 } },
+ { X86::DIVPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_divpd, MCK_Mem, MCK_FR32 } },
+ { X86::DIVPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_divps, MCK_FR32, MCK_FR32 } },
+ { X86::DIVPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_divps, MCK_Mem, MCK_FR32 } },
+ { X86::DIVSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_divsd, MCK_FR32, MCK_FR32 } },
+ { X86::DIVSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_divsd, MCK_Mem, MCK_FR32 } },
+ { X86::DIVSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_divss, MCK_FR32, MCK_FR32 } },
+ { X86::DIVSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_divss, MCK_Mem, MCK_FR32 } },
+ { X86::ENTER, Convert_Imm1_1_Imm1_2, { MCK_enter, MCK_Imm, MCK_Imm } },
+ { X86::ADD_FrST0, Convert_Reg1_2, { MCK_fadd, MCK_ST0, MCK_RST } },
+ { X86::CMOVB_F, Convert_Reg1_1, { MCK_fcmovb, MCK_RST, MCK_ST0 } },
+ { X86::CMOVBE_F, Convert_Reg1_1, { MCK_fcmovbe, MCK_RST, MCK_ST0 } },
+ { X86::CMOVE_F, Convert_Reg1_1, { MCK_fcmove, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNB_F, Convert_Reg1_1, { MCK_fcmovnb, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNBE_F, Convert_Reg1_1, { MCK_fcmovnbe, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNE_F, Convert_Reg1_1, { MCK_fcmovne, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNP_F, Convert_Reg1_1, { MCK_fcmovnu, MCK_RST, MCK_ST0 } },
+ { X86::CMOVP_F, Convert_Reg1_1, { MCK_fcmovu, MCK_RST, MCK_ST0 } },
+ { X86::DIVR_FrST0, Convert_Reg1_2, { MCK_fdiv, MCK_ST0, MCK_RST } },
+ { X86::DIV_FrST0, Convert_Reg1_2, { MCK_fdivr, MCK_ST0, MCK_RST } },
+ { X86::MUL_FrST0, Convert_Reg1_2, { MCK_fmul, MCK_ST0, MCK_RST } },
+ { X86::SUBR_FrST0, Convert_Reg1_2, { MCK_fsub, MCK_ST0, MCK_RST } },
+ { X86::SUB_FrST0, Convert_Reg1_2, { MCK_fsubr, MCK_ST0, MCK_RST } },
+ { X86::UCOM_FIr, Convert_Reg1_1, { MCK_fucomi, MCK_RST, MCK_ST0 } },
+ { X86::UCOM_FIPr, Convert_Reg1_1, { MCK_fucomip, MCK_RST, MCK_ST0 } },
+ { X86::HADDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_haddpd, MCK_FR32, MCK_FR32 } },
+ { X86::HADDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_haddpd, MCK_Mem, MCK_FR32 } },
+ { X86::HADDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_haddps, MCK_FR32, MCK_FR32 } },
+ { X86::HADDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_haddps, MCK_Mem, MCK_FR32 } },
+ { X86::HSUBPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_hsubpd, MCK_FR32, MCK_FR32 } },
+ { X86::HSUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_hsubpd, MCK_Mem, MCK_FR32 } },
+ { X86::HSUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_hsubps, MCK_FR32, MCK_FR32 } },
+ { X86::HSUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_hsubps, MCK_Mem, MCK_FR32 } },
+ { X86::IMUL32rr, Convert_Reg1_2_ImpReg1_1, { MCK_imull, MCK_GR32, MCK_GR32 } },
+ { X86::IMUL32rm, Convert_Reg1_2_ImpMem5_1, { MCK_imull, MCK_Mem, MCK_GR32 } },
+ { X86::IMUL64rr, Convert_Reg1_2_ImpReg1_1, { MCK_imulq, MCK_GR64, MCK_GR64 } },
+ { X86::IMUL64rm, Convert_Reg1_2_ImpMem5_1, { MCK_imulq, MCK_Mem, MCK_GR64 } },
+ { X86::IMUL16rr, Convert_Reg1_2_ImpReg1_1, { MCK_imulw, MCK_GR16, MCK_GR16 } },
+ { X86::IMUL16rm, Convert_Reg1_2_ImpMem5_1, { MCK_imulw, MCK_Mem, MCK_GR16 } },
+ { X86::IN8rr, Convert, { MCK_inb, MCK_DX, MCK_AL } },
+ { X86::IN8ri, Convert_ImmSExt81_1, { MCK_inb, MCK_ImmSExt8, MCK_AL } },
+ { X86::IN32rr, Convert, { MCK_inl, MCK_DX, MCK_EAX } },
+ { X86::IN32ri, Convert_ImmSExt81_1, { MCK_inl, MCK_ImmSExt8, MCK_EAX } },
+ { X86::IN16rr, Convert, { MCK_inw, MCK_DX, MCK_AX } },
+ { X86::IN16ri, Convert_ImmSExt81_1, { MCK_inw, MCK_ImmSExt8, MCK_AX } },
+ { X86::TAILJMPm, Convert_Mem5_2, { MCK_jmp, MCK__STAR_, MCK_Mem } },
+ { X86::TAILJMPr, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
+ { X86::JMP32r, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
+ { X86::JMP32m, Convert_Mem5_2, { MCK_jmpl, MCK__STAR_, MCK_Mem } },
+ { X86::TAILJMPr64, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
+ { X86::JMP64r, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
+ { X86::JMP64m, Convert_Mem5_2, { MCK_jmpq, MCK__STAR_, MCK_Mem } },
+ { X86::LAR32rr, Convert_Reg1_2_Reg1_1, { MCK_larl, MCK_GR32, MCK_GR32 } },
+ { X86::LAR32rm, Convert_Reg1_2_Mem5_1, { MCK_larl, MCK_Mem, MCK_GR32 } },
+ { X86::LAR64rr, Convert_Reg1_2_Reg1_1, { MCK_larq, MCK_GR32, MCK_GR64 } },
+ { X86::LAR64rm, Convert_Reg1_2_Mem5_1, { MCK_larq, MCK_Mem, MCK_GR64 } },
+ { X86::LAR16rr, Convert_Reg1_2_Reg1_1, { MCK_larw, MCK_GR16, MCK_GR16 } },
+ { X86::LAR16rm, Convert_Reg1_2_Mem5_1, { MCK_larw, MCK_Mem, MCK_GR16 } },
+ { X86::FARCALL32m, Convert_Mem5_2, { MCK_lcalll, MCK__STAR_, MCK_Mem } },
+ { X86::FARCALL32i, Convert_Imm1_1_Imm1_2, { MCK_lcalll, MCK_Imm, MCK_Imm } },
+ { X86::FARCALL64, Convert_Mem5_2, { MCK_lcallq, MCK__STAR_, MCK_Mem } },
+ { X86::FARCALL16m, Convert_Mem5_2, { MCK_lcallw, MCK__STAR_, MCK_Mem } },
+ { X86::FARCALL16i, Convert_Imm1_1_Imm1_2, { MCK_lcallw, MCK_Imm, MCK_Imm } },
+ { X86::LDDQUrm, Convert_Reg1_2_Mem5_1, { MCK_lddqu, MCK_Mem, MCK_FR32 } },
+ { X86::LEA64_32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
+ { X86::LEA32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
+ { X86::LEA64r, Convert_Reg1_2_Mem4_1, { MCK_leaq, MCK_Mem, MCK_GR64 } },
+ { X86::LEA16r, Convert_Reg1_2_Mem4_1, { MCK_leaw, MCK_Mem, MCK_GR16 } },
+ { X86::FARJMP32m, Convert_Mem5_2, { MCK_ljmpl, MCK__STAR_, MCK_Mem } },
+ { X86::FARJMP32i, Convert_Imm1_1_Imm1_2, { MCK_ljmpl, MCK_Imm, MCK_Imm } },
+ { X86::FARJMP64, Convert_Mem5_2, { MCK_ljmpq, MCK__STAR_, MCK_Mem } },
+ { X86::FARJMP16m, Convert_Mem5_2, { MCK_ljmpw, MCK__STAR_, MCK_Mem } },
+ { X86::FARJMP16i, Convert_Imm1_1_Imm1_2, { MCK_ljmpw, MCK_Imm, MCK_Imm } },
+ { X86::MASKMOVDQU, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
+ { X86::MASKMOVDQU64, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_MASKMOVQ64, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_MASKMOVQ, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
+ { X86::MAXPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxpd, MCK_FR32, MCK_FR32 } },
+ { X86::MAXPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxpd, MCK_Mem, MCK_FR32 } },
+ { X86::MAXPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxps, MCK_FR32, MCK_FR32 } },
+ { X86::MAXPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxps, MCK_Mem, MCK_FR32 } },
+ { X86::MAXSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxsd, MCK_FR32, MCK_FR32 } },
+ { X86::MAXSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxsd, MCK_Mem, MCK_FR32 } },
+ { X86::MAXSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxss, MCK_FR32, MCK_FR32 } },
+ { X86::MAXSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxss, MCK_Mem, MCK_FR32 } },
+ { X86::MINPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_minpd, MCK_FR32, MCK_FR32 } },
+ { X86::MINPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_minpd, MCK_Mem, MCK_FR32 } },
+ { X86::MINPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_minps, MCK_FR32, MCK_FR32 } },
+ { X86::MINPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_minps, MCK_Mem, MCK_FR32 } },
+ { X86::MINSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_minsd, MCK_FR32, MCK_FR32 } },
+ { X86::MINSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_minsd, MCK_Mem, MCK_FR32 } },
+ { X86::MINSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_minss, MCK_FR32, MCK_FR32 } },
+ { X86::MINSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_minss, MCK_Mem, MCK_FR32 } },
+ { X86::MOV64ri, Convert_Reg1_2_Imm1_1, { MCK_movabsq, MCK_Imm, MCK_GR64 } },
+ { X86::MOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
+ { X86::FsMOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPDmr, Convert_Mem5_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_Mem } },
+ { X86::FsMOVAPDrm, Convert_Reg1_2_Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVAPDrm, Convert_Reg1_2_Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
+ { X86::FsMOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPSmr, Convert_Mem5_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_Mem } },
+ { X86::MOVAPSrm, Convert_Reg1_2_Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
+ { X86::FsMOVAPSrm, Convert_Reg1_2_Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
+ { X86::MOV8ao8, Convert_Imm1_2, { MCK_movb, MCK_AL, MCK_Imm } },
+ { X86::MOV8rr_NOREX, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_GR8_NOREX } },
+ { X86::MOV8mr_NOREX, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_Mem } },
+ { X86::MOV8rr, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
+ { X86::MOV8mr, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_Mem } },
+ { X86::MOV8o8a, Convert_Imm1_1, { MCK_movb, MCK_Imm, MCK_AL } },
+ { X86::MOV8ri, Convert_Reg1_2_Imm1_1, { MCK_movb, MCK_Imm, MCK_GR8 } },
+ { X86::MOV8mi, Convert_Mem5_2_Imm1_1, { MCK_movb, MCK_Imm, MCK_Mem } },
+ { X86::MOV8rm_NOREX, Convert_Reg1_2_Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8_NOREX } },
+ { X86::MOV8rm, Convert_Reg1_2_Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8 } },
+ { X86::MMX_MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
+ { X86::MMX_MOVD64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
+ { X86::MOVDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MOVDI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MMX_MOVD64rrv164, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
+ { X86::MMX_MOVD64to64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
+ { X86::MOV64toSDrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MOV64toPQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MOVZQI2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MMX_MOVD64from64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR64 } },
+ { X86::MMX_MOVD64mr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_Mem } },
+ { X86::MOVSS2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
+ { X86::MOVPDI2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
+ { X86::MOVSDto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
+ { X86::MOVPQIto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
+ { X86::MOVPDI2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSS2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
+ { X86::MMX_MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MMX_MOVD64rm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDI2SSrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movddup, MCK_FR32, MCK_FR32 } },
+ { X86::MOVDDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movddup, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_MOVDQ2Qrr, Convert_Reg1_2_Reg1_1, { MCK_movdq2q, MCK_FR32, MCK_VR64 } },
+ { X86::MOVDQArr, Convert_Reg1_2_Reg1_1, { MCK_movdqa, MCK_FR32, MCK_FR32 } },
+ { X86::MOVDQAmr, Convert_Mem5_2_Reg1_1, { MCK_movdqa, MCK_FR32, MCK_Mem } },
+ { X86::MOVDQArm, Convert_Reg1_2_Mem5_1, { MCK_movdqa, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDQUmr, Convert_Mem5_2_Reg1_1, { MCK_movdqu, MCK_FR32, MCK_Mem } },
+ { X86::MOVDQUrm, Convert_Reg1_2_Mem5_1, { MCK_movdqu, MCK_Mem, MCK_FR32 } },
+ { X86::MOVHLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movhlps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVHPDmr, Convert_Mem5_2_Reg1_1, { MCK_movhpd, MCK_FR32, MCK_Mem } },
+ { X86::MOVHPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_movhpd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVHPSmr, Convert_Mem5_2_Reg1_1, { MCK_movhps, MCK_FR32, MCK_Mem } },
+ { X86::MOVHPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_movhps, MCK_Mem, MCK_FR32 } },
+ { X86::MOV32ao32, Convert_Imm1_2, { MCK_movl, MCK_EAX, MCK_Imm } },
+ { X86::MOV32rr, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
+ { X86::MOV32mr, Convert_Mem5_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_Mem } },
+ { X86::MOV32o32a, Convert_Imm1_1, { MCK_movl, MCK_Imm, MCK_EAX } },
+ { X86::MOV32ri, Convert_Reg1_2_Imm1_1, { MCK_movl, MCK_Imm, MCK_GR32 } },
+ { X86::MOV32mi, Convert_Mem5_2_Imm1_1, { MCK_movl, MCK_Imm, MCK_Mem } },
+ { X86::MOV32rm, Convert_Reg1_2_Mem5_1, { MCK_movl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVLHPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movlhps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLPDmr, Convert_Mem5_2_Reg1_1, { MCK_movlpd, MCK_FR32, MCK_Mem } },
+ { X86::MOVLPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_movlpd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVLPSmr, Convert_Mem5_2_Reg1_1, { MCK_movlps, MCK_FR32, MCK_Mem } },
+ { X86::MOVLPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_movlps, MCK_Mem, MCK_FR32 } },
+ { X86::MOVMSKPDrr, Convert_Reg1_2_Reg1_1, { MCK_movmskpd, MCK_FR32, MCK_GR32 } },
+ { X86::MOVMSKPSrr, Convert_Reg1_2_Reg1_1, { MCK_movmskps, MCK_FR32, MCK_GR32 } },
+ { X86::MOVNTDQmr, Convert_Mem5_2_Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
+ { X86::MOVNTDQArm, Convert_Reg1_2_Mem5_1, { MCK_movntdqa, MCK_Mem, MCK_FR32 } },
+ { X86::MOVNTImr, Convert_Mem5_2_Reg1_1, { MCK_movnti, MCK_GR32, MCK_Mem } },
+ { X86::MOVNTPDmr, Convert_Mem5_2_Reg1_1, { MCK_movntpd, MCK_FR32, MCK_Mem } },
+ { X86::MOVNTPSmr, Convert_Mem5_2_Reg1_1, { MCK_movntps, MCK_FR32, MCK_Mem } },
+ { X86::MMX_MOVNTQmr, Convert_Mem5_2_Reg1_1, { MCK_movntq, MCK_VR64, MCK_Mem } },
+ { X86::MOV64ao8, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
+ { X86::MOV64ao32, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
+ { X86::MOV64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
+ { X86::MOV64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_Mem } },
+ { X86::MMX_MOVQ64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_MOVQ64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
+ { X86::MOVZPQILo2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSDto64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOVPQI2QImr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOVLQ128mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOV64o8a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
+ { X86::MOV64o32a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
+ { X86::MOV64ri32, Convert_Reg1_2_Imm1_1, { MCK_movq, MCK_Imm, MCK_GR64 } },
+ { X86::MOV64mi32, Convert_Mem5_2_Imm1_1, { MCK_movq, MCK_Imm, MCK_Mem } },
+ { X86::MOV64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_GR64 } },
+ { X86::MMX_MOVQ64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_VR64 } },
+ { X86::MOV64toSDrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOVQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZPQILo2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_MOVQ2DQrr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_MOVQ2FR64rr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MOVSX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbl, MCK_GR8, MCK_GR32 } },
+ { X86::MOVSX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVSX64rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbq, MCK_GR8, MCK_GR64 } },
+ { X86::MOVSX64rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVSDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPD2SDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLSD2PDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSD2PDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPD2SDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSHDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSHDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSLDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSLDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movsldup, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSX64rr32, Convert_Reg1_2_Reg1_1, { MCK_movslq, MCK_GR32, MCK_GR64 } },
+ { X86::MOVSX64rm32, Convert_Reg1_2_Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVSS2PSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLSS2PSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPS2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVPS2SSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVSSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
+ { X86::MOVSX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVSX64rr16, Convert_Reg1_2_Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
+ { X86::MOVSX64rm16, Convert_Reg1_2_Mem5_1, { MCK_movswq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVUPDrr, Convert_Reg1_2_Reg1_1, { MCK_movupd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVUPDmr, Convert_Mem5_2_Reg1_1, { MCK_movupd, MCK_FR32, MCK_Mem } },
+ { X86::MOVUPDrm, Convert_Reg1_2_Mem5_1, { MCK_movupd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVUPSrr, Convert_Reg1_2_Reg1_1, { MCK_movups, MCK_FR32, MCK_FR32 } },
+ { X86::MOVUPSmr, Convert_Mem5_2_Reg1_1, { MCK_movups, MCK_FR32, MCK_Mem } },
+ { X86::MOVUPSrm, Convert_Reg1_2_Mem5_1, { MCK_movups, MCK_Mem, MCK_FR32 } },
+ { X86::MOV16ao16, Convert_Imm1_2, { MCK_movw, MCK_AX, MCK_Imm } },
+ { X86::MOV16rr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
+ { X86::MOV16sr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_SEGMENT_REG } },
+ { X86::MOV16mr, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_Mem } },
+ { X86::MOV64sr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR64, MCK_SEGMENT_REG } },
+ { X86::MOV16rs, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_GR16 } },
+ { X86::MOV64rs, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_GR64 } },
+ { X86::MOV16ms, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_Mem } },
+ { X86::MOV64ms, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_Mem } },
+ { X86::MOV16o16a, Convert_Imm1_1, { MCK_movw, MCK_Imm, MCK_AX } },
+ { X86::MOV16ri, Convert_Reg1_2_Imm1_1, { MCK_movw, MCK_Imm, MCK_GR16 } },
+ { X86::MOV16mi, Convert_Mem5_2_Imm1_1, { MCK_movw, MCK_Imm, MCK_Mem } },
+ { X86::MOV16rm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_GR16 } },
+ { X86::MOV16sm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_SEGMENT_REG } },
+ { X86::MOV64sm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_SEGMENT_REG } },
+ { X86::MOVZX32_NOREXrr8, Convert_Reg1_2_Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32_NOREX } },
+ { X86::MOVZX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32 } },
+ { X86::MOVZX32_NOREXrm8, Convert_Reg1_2_Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32_NOREX } },
+ { X86::MOVZX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVZX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movzwl, MCK_GR16, MCK_GR32 } },
+ { X86::MOVZX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movzwl, MCK_Mem, MCK_GR32 } },
+ { X86::MULPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulpd, MCK_FR32, MCK_FR32 } },
+ { X86::MULPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulpd, MCK_Mem, MCK_FR32 } },
+ { X86::MULPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulps, MCK_FR32, MCK_FR32 } },
+ { X86::MULPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulps, MCK_Mem, MCK_FR32 } },
+ { X86::MULSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulsd, MCK_FR32, MCK_FR32 } },
+ { X86::MULSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulsd, MCK_Mem, MCK_FR32 } },
+ { X86::MULSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulss, MCK_FR32, MCK_FR32 } },
+ { X86::MULSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulss, MCK_Mem, MCK_FR32 } },
+ { X86::OR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
+ { X86::OR8mr, Convert_Mem5_2_Reg1_1, { MCK_orb, MCK_GR8, MCK_Mem } },
+ { X86::OR8i8, Convert_Imm1_1, { MCK_orb, MCK_Imm, MCK_AL } },
+ { X86::OR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_orb, MCK_Imm, MCK_GR8 } },
+ { X86::OR8mi, Convert_Mem5_2_Imm1_1, { MCK_orb, MCK_Imm, MCK_Mem } },
+ { X86::OR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_orb, MCK_Mem, MCK_GR8 } },
+ { X86::OR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
+ { X86::OR32mr, Convert_Mem5_2_Reg1_1, { MCK_orl, MCK_GR32, MCK_Mem } },
+ { X86::OR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::OR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::OR32i32, Convert_Imm1_1, { MCK_orl, MCK_Imm, MCK_EAX } },
+ { X86::OR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_orl, MCK_Imm, MCK_GR32 } },
+ { X86::OR32mi, Convert_Mem5_2_Imm1_1, { MCK_orl, MCK_Imm, MCK_Mem } },
+ { X86::OR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_orl, MCK_Mem, MCK_GR32 } },
+ { X86::ORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
+ { X86::ORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
+ { X86::ORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
+ { X86::FsORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::ORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::OR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
+ { X86::OR64mr, Convert_Mem5_2_Reg1_1, { MCK_orq, MCK_GR64, MCK_Mem } },
+ { X86::OR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::OR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::OR64i32, Convert_Imm1_1, { MCK_orq, MCK_Imm, MCK_RAX } },
+ { X86::OR64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_orq, MCK_Imm, MCK_GR64 } },
+ { X86::OR64mi32, Convert_Mem5_2_Imm1_1, { MCK_orq, MCK_Imm, MCK_Mem } },
+ { X86::OR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_orq, MCK_Mem, MCK_GR64 } },
+ { X86::OR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
+ { X86::OR16mr, Convert_Mem5_2_Reg1_1, { MCK_orw, MCK_GR16, MCK_Mem } },
+ { X86::OR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::OR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::OR16i16, Convert_Imm1_1, { MCK_orw, MCK_Imm, MCK_AX } },
+ { X86::OR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_orw, MCK_Imm, MCK_GR16 } },
+ { X86::OR16mi, Convert_Mem5_2_Imm1_1, { MCK_orw, MCK_Imm, MCK_Mem } },
+ { X86::OR16rm, Convert_Reg1_2_ImpMem5_1, { MCK_orw, MCK_Mem, MCK_GR16 } },
+ { X86::OUT8rr, Convert, { MCK_outb, MCK_AL, MCK_DX } },
+ { X86::OUT8ir, Convert_ImmSExt81_2, { MCK_outb, MCK_AL, MCK_ImmSExt8 } },
+ { X86::OUT32rr, Convert, { MCK_outl, MCK_EAX, MCK_DX } },
+ { X86::OUT32ir, Convert_ImmSExt81_2, { MCK_outl, MCK_EAX, MCK_ImmSExt8 } },
+ { X86::OUT16rr, Convert, { MCK_outw, MCK_AX, MCK_DX } },
+ { X86::OUT16ir, Convert_ImmSExt81_2, { MCK_outw, MCK_AX, MCK_ImmSExt8 } },
+ { X86::PABSBrr64, Convert_Reg1_2_Reg1_1, { MCK_pabsb, MCK_VR64, MCK_VR64 } },
+ { X86::PABSBrr128, Convert_Reg1_2_Reg1_1, { MCK_pabsb, MCK_FR32, MCK_FR32 } },
+ { X86::PABSBrm64, Convert_Reg1_2_Mem5_1, { MCK_pabsb, MCK_Mem, MCK_VR64 } },
+ { X86::PABSBrm128, Convert_Reg1_2_Mem5_1, { MCK_pabsb, MCK_Mem, MCK_FR32 } },
+ { X86::PABSDrr64, Convert_Reg1_2_Reg1_1, { MCK_pabsd, MCK_VR64, MCK_VR64 } },
+ { X86::PABSDrr128, Convert_Reg1_2_Reg1_1, { MCK_pabsd, MCK_FR32, MCK_FR32 } },
+ { X86::PABSDrm64, Convert_Reg1_2_Mem5_1, { MCK_pabsd, MCK_Mem, MCK_VR64 } },
+ { X86::PABSDrm128, Convert_Reg1_2_Mem5_1, { MCK_pabsd, MCK_Mem, MCK_FR32 } },
+ { X86::PABSWrr64, Convert_Reg1_2_Reg1_1, { MCK_pabsw, MCK_VR64, MCK_VR64 } },
+ { X86::PABSWrr128, Convert_Reg1_2_Reg1_1, { MCK_pabsw, MCK_FR32, MCK_FR32 } },
+ { X86::PABSWrm64, Convert_Reg1_2_Mem5_1, { MCK_pabsw, MCK_Mem, MCK_VR64 } },
+ { X86::PABSWrm128, Convert_Reg1_2_Mem5_1, { MCK_pabsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PACKSSDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_packssdw, MCK_VR64, MCK_VR64 } },
+ { X86::PACKSSDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_packssdw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PACKSSDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_packssdw, MCK_Mem, MCK_VR64 } },
+ { X86::PACKSSDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_packssdw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PACKSSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packsswb, MCK_VR64, MCK_VR64 } },
+ { X86::PACKSSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packsswb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PACKSSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packsswb, MCK_Mem, MCK_VR64 } },
+ { X86::PACKSSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packsswb, MCK_Mem, MCK_FR32 } },
+ { X86::PACKUSDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_packusdw, MCK_FR32, MCK_FR32 } },
+ { X86::PACKUSDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_packusdw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PACKUSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packuswb, MCK_VR64, MCK_VR64 } },
+ { X86::PACKUSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packuswb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PACKUSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packuswb, MCK_Mem, MCK_VR64 } },
+ { X86::PACKUSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packuswb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddb, MCK_VR64, MCK_VR64 } },
+ { X86::PADDBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddb, MCK_Mem, MCK_VR64 } },
+ { X86::PADDBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDDrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddd, MCK_VR64, MCK_VR64 } },
+ { X86::PADDDrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDDrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddd, MCK_Mem, MCK_VR64 } },
+ { X86::PADDDrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddq, MCK_VR64, MCK_VR64 } },
+ { X86::PADDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddq, MCK_Mem, MCK_VR64 } },
+ { X86::PADDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsb, MCK_VR64, MCK_VR64 } },
+ { X86::PADDSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsb, MCK_Mem, MCK_VR64 } },
+ { X86::PADDSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsw, MCK_VR64, MCK_VR64 } },
+ { X86::PADDSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsw, MCK_Mem, MCK_VR64 } },
+ { X86::PADDSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusb, MCK_VR64, MCK_VR64 } },
+ { X86::PADDUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusb, MCK_Mem, MCK_VR64 } },
+ { X86::PADDUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusw, MCK_VR64, MCK_VR64 } },
+ { X86::PADDUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusw, MCK_Mem, MCK_VR64 } },
+ { X86::PADDUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddw, MCK_VR64, MCK_VR64 } },
+ { X86::PADDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddw, MCK_Mem, MCK_VR64 } },
+ { X86::PADDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PANDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pand, MCK_VR64, MCK_VR64 } },
+ { X86::PANDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pand, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PANDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pand, MCK_Mem, MCK_VR64 } },
+ { X86::PANDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pand, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PANDNrr, Convert_Reg1_2_ImpReg1_1, { MCK_pandn, MCK_VR64, MCK_VR64 } },
+ { X86::PANDNrr, Convert_Reg1_2_ImpReg1_1, { MCK_pandn, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PANDNrm, Convert_Reg1_2_ImpMem5_1, { MCK_pandn, MCK_Mem, MCK_VR64 } },
+ { X86::PANDNrm, Convert_Reg1_2_ImpMem5_1, { MCK_pandn, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PAVGBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgb, MCK_VR64, MCK_VR64 } },
+ { X86::PAVGBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PAVGBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgb, MCK_Mem, MCK_VR64 } },
+ { X86::PAVGBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PAVGWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgw, MCK_VR64, MCK_VR64 } },
+ { X86::PAVGWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PAVGWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgw, MCK_Mem, MCK_VR64 } },
+ { X86::PAVGWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPEQBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqb, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPEQBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPEQBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqb, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPEQBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPEQDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqd, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPEQDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPEQDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqd, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPEQDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqd, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPEQQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqq, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPEQQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPEQWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqw, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPEQWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPEQWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqw, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPEQWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPGTBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtb, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPGTBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPGTBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtb, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPGTBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPGTDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtd, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPGTDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPGTDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtd, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPGTDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtd, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPGTQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtq, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPGTQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPGTWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtw, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPGTWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPGTWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtw, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPGTWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtw, MCK_Mem, MCK_FR32 } },
+ { X86::PHADDDrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phaddd, MCK_VR64, MCK_VR64 } },
+ { X86::PHADDDrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phaddd, MCK_FR32, MCK_FR32 } },
+ { X86::PHADDDrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phaddd, MCK_Mem, MCK_VR64 } },
+ { X86::PHADDDrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phaddd, MCK_Mem, MCK_FR32 } },
+ { X86::PHADDSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phaddsw, MCK_VR64, MCK_VR64 } },
+ { X86::PHADDSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phaddsw, MCK_FR32, MCK_FR32 } },
+ { X86::PHADDSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phaddsw, MCK_Mem, MCK_VR64 } },
+ { X86::PHADDSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phaddsw, MCK_Mem, MCK_FR32 } },
+ { X86::PHADDWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phaddw, MCK_VR64, MCK_VR64 } },
+ { X86::PHADDWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phaddw, MCK_FR32, MCK_FR32 } },
+ { X86::PHADDWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phaddw, MCK_Mem, MCK_VR64 } },
+ { X86::PHADDWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phaddw, MCK_Mem, MCK_FR32 } },
+ { X86::PHMINPOSUWrr128, Convert_Reg1_2_Reg1_1, { MCK_phminposuw, MCK_FR32, MCK_FR32 } },
+ { X86::PHMINPOSUWrm128, Convert_Reg1_2_Mem5_1, { MCK_phminposuw, MCK_Mem, MCK_FR32 } },
+ { X86::PHSUBDrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phsubd, MCK_VR64, MCK_VR64 } },
+ { X86::PHSUBDrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phsubd, MCK_FR32, MCK_FR32 } },
+ { X86::PHSUBDrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phsubd, MCK_Mem, MCK_VR64 } },
+ { X86::PHSUBDrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phsubd, MCK_Mem, MCK_FR32 } },
+ { X86::PHSUBSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phsubsw, MCK_VR64, MCK_VR64 } },
+ { X86::PHSUBSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phsubsw, MCK_FR32, MCK_FR32 } },
+ { X86::PHSUBSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phsubsw, MCK_Mem, MCK_VR64 } },
+ { X86::PHSUBSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phsubsw, MCK_Mem, MCK_FR32 } },
+ { X86::PHSUBWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phsubw, MCK_VR64, MCK_VR64 } },
+ { X86::PHSUBWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phsubw, MCK_FR32, MCK_FR32 } },
+ { X86::PHSUBWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phsubw, MCK_Mem, MCK_VR64 } },
+ { X86::PHSUBWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phsubw, MCK_Mem, MCK_FR32 } },
+ { X86::PMADDUBSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddubsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMADDUBSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddubsw, MCK_FR32, MCK_FR32 } },
+ { X86::PMADDUBSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddubsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMADDUBSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddubsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMADDWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddwd, MCK_VR64, MCK_VR64 } },
+ { X86::PMADDWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddwd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMADDWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddwd, MCK_Mem, MCK_VR64 } },
+ { X86::PMADDWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddwd, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsb, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsb, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsd, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMAXSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMAXSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMAXSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMAXSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMAXUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxub, MCK_VR64, MCK_VR64 } },
+ { X86::PMAXUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxub, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMAXUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxub, MCK_Mem, MCK_VR64 } },
+ { X86::PMAXUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxub, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXUDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxud, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXUDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxud, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxuw, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxuw, MCK_Mem, MCK_FR32 } },
+ { X86::PMINSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsb, MCK_FR32, MCK_FR32 } },
+ { X86::PMINSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsb, MCK_Mem, MCK_FR32 } },
+ { X86::PMINSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsd, MCK_FR32, MCK_FR32 } },
+ { X86::PMINSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMINSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMINSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMINSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMINSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMINUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminub, MCK_VR64, MCK_VR64 } },
+ { X86::PMINUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminub, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMINUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminub, MCK_Mem, MCK_VR64 } },
+ { X86::PMINUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminub, MCK_Mem, MCK_FR32 } },
+ { X86::PMINUDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminud, MCK_FR32, MCK_FR32 } },
+ { X86::PMINUDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminud, MCK_Mem, MCK_FR32 } },
+ { X86::PMINUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminuw, MCK_FR32, MCK_FR32 } },
+ { X86::PMINUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminuw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMOVMSKBrr, Convert_Reg1_2_Reg1_1, { MCK_pmovmskb, MCK_VR64, MCK_GR32 } },
+ { X86::PMOVMSKBrr, Convert_Reg1_2_Reg1_1, { MCK_pmovmskb, MCK_FR32, MCK_GR32 } },
+ { X86::PMOVSXBDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxbd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXBDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxbd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXBQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxbq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXBQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxbq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXBWrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxbw, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXBWrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxbw, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXDQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxdq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXDQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxdq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXWDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxwd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXWDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxwd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXWQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxwq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXWQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxwq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXBDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxbd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXBDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxbd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXBQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxbq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXBQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxbq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXBWrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxbw, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXBWrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxbw, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXDQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxdq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXDQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxdq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXWDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxwd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXWDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxwd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXWQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxwq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXWQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxwq, MCK_Mem, MCK_FR32 } },
+ { X86::PMULDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuldq, MCK_FR32, MCK_FR32 } },
+ { X86::PMULDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuldq, MCK_Mem, MCK_FR32 } },
+ { X86::PMULHRSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhrsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULHRSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhrsw, MCK_FR32, MCK_FR32 } },
+ { X86::PMULHRSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhrsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULHRSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhrsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULHUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhuw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULHUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhuw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULHUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhuw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULHUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhuw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULHWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULHWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULHWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULHWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhw, MCK_Mem, MCK_FR32 } },
+ { X86::PMULLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulld, MCK_FR32, MCK_FR32 } },
+ { X86::PMULLDrr_int, Convert_Reg1_2_ImpReg1_1, { MCK_pmulld, MCK_FR32, MCK_FR32 } },
+ { X86::PMULLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulld, MCK_Mem, MCK_FR32 } },
+ { X86::PMULLDrm_int, Convert_Reg1_2_ImpMem5_1, { MCK_pmulld, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmullw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmullw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmullw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmullw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULUDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuludq, MCK_VR64, MCK_VR64 } },
+ { X86::PMULUDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuludq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULUDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuludq, MCK_Mem, MCK_VR64 } },
+ { X86::PMULUDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuludq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PORrr, Convert_Reg1_2_ImpReg1_1, { MCK_por, MCK_VR64, MCK_VR64 } },
+ { X86::PORrr, Convert_Reg1_2_ImpReg1_1, { MCK_por, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PORrm, Convert_Reg1_2_ImpMem5_1, { MCK_por, MCK_Mem, MCK_VR64 } },
+ { X86::PORrm, Convert_Reg1_2_ImpMem5_1, { MCK_por, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSADBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psadbw, MCK_VR64, MCK_VR64 } },
+ { X86::PSADBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psadbw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSADBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psadbw, MCK_Mem, MCK_VR64 } },
+ { X86::PSADBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psadbw, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFBrr64, Convert_Reg1_2_ImpReg1_1, { MCK_pshufb, MCK_VR64, MCK_VR64 } },
+ { X86::PSHUFBrr128, Convert_Reg1_2_ImpReg1_1, { MCK_pshufb, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFBrm64, Convert_Reg1_2_ImpMem5_1, { MCK_pshufb, MCK_Mem, MCK_VR64 } },
+ { X86::PSHUFBrm128, Convert_Reg1_2_ImpMem5_1, { MCK_pshufb, MCK_Mem, MCK_FR32 } },
+ { X86::PSIGNBrr64, Convert_Reg1_2_ImpReg1_1, { MCK_psignb, MCK_VR64, MCK_VR64 } },
+ { X86::PSIGNBrr128, Convert_Reg1_2_ImpReg1_1, { MCK_psignb, MCK_FR32, MCK_FR32 } },
+ { X86::PSIGNBrm64, Convert_Reg1_2_ImpMem5_1, { MCK_psignb, MCK_Mem, MCK_VR64 } },
+ { X86::PSIGNBrm128, Convert_Reg1_2_ImpMem5_1, { MCK_psignb, MCK_Mem, MCK_FR32 } },
+ { X86::PSIGNDrr64, Convert_Reg1_2_ImpReg1_1, { MCK_psignd, MCK_VR64, MCK_VR64 } },
+ { X86::PSIGNDrr128, Convert_Reg1_2_ImpReg1_1, { MCK_psignd, MCK_FR32, MCK_FR32 } },
+ { X86::PSIGNDrm64, Convert_Reg1_2_ImpMem5_1, { MCK_psignd, MCK_Mem, MCK_VR64 } },
+ { X86::PSIGNDrm128, Convert_Reg1_2_ImpMem5_1, { MCK_psignd, MCK_Mem, MCK_FR32 } },
+ { X86::PSIGNWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_psignw, MCK_VR64, MCK_VR64 } },
+ { X86::PSIGNWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_psignw, MCK_FR32, MCK_FR32 } },
+ { X86::PSIGNWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_psignw, MCK_Mem, MCK_VR64 } },
+ { X86::PSIGNWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_psignw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSLLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pslld, MCK_VR64, MCK_VR64 } },
+ { X86::PSLLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pslld, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSLLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_pslld, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSLLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_pslld, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pslld, MCK_Mem, MCK_VR64 } },
+ { X86::PSLLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pslld, MCK_Mem, MCK_FR32 } },
+ { X86::PSLLDQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_pslldq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllq, MCK_VR64, MCK_VR64 } },
+ { X86::PSLLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSLLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllq, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSLLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllq, MCK_Mem, MCK_VR64 } },
+ { X86::PSLLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSLLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllw, MCK_VR64, MCK_VR64 } },
+ { X86::PSLLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSLLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllw, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSLLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllw, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllw, MCK_Mem, MCK_VR64 } },
+ { X86::PSLLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRADrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrad, MCK_VR64, MCK_VR64 } },
+ { X86::PSRADrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrad, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRADri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrad, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRADri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrad, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRADrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrad, MCK_Mem, MCK_VR64 } },
+ { X86::PSRADrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrad, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRAWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psraw, MCK_VR64, MCK_VR64 } },
+ { X86::PSRAWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psraw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRAWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psraw, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRAWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psraw, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRAWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psraw, MCK_Mem, MCK_VR64 } },
+ { X86::PSRAWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psraw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrld, MCK_VR64, MCK_VR64 } },
+ { X86::PSRLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrld, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrld, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrld, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrld, MCK_Mem, MCK_VR64 } },
+ { X86::PSRLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrld, MCK_Mem, MCK_FR32 } },
+ { X86::PSRLDQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrldq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlq, MCK_VR64, MCK_VR64 } },
+ { X86::PSRLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlq, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlq, MCK_Mem, MCK_VR64 } },
+ { X86::PSRLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlw, MCK_VR64, MCK_VR64 } },
+ { X86::PSRLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlw, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlw, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlw, MCK_Mem, MCK_VR64 } },
+ { X86::PSRLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubb, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubb, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubd, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubd, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubq, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubq, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsb, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsb, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsw, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsw, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusb, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusb, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusw, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusw, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubw, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubw, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubw, MCK_Mem, MCK_FR32 } },
+ { X86::PTESTrr, Convert_Reg1_2_Reg1_1, { MCK_ptest, MCK_FR32, MCK_FR32 } },
+ { X86::PTESTrm, Convert_Reg1_2_Mem5_1, { MCK_ptest, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKHBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhbw, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKHBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhbw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKHBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhbw, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKHBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhbw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKHDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhdq, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKHDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhdq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKHDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhdq, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKHDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhdq, MCK_Mem, MCK_FR32 } },
+ { X86::PUNPCKHQDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhqdq, MCK_FR32, MCK_FR32 } },
+ { X86::PUNPCKHQDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhqdq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKHWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhwd, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKHWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhwd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKHWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhwd, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKHWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhwd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKLBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklbw, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKLBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklbw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKLBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklbw, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKLBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklbw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKLDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckldq, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKLDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckldq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKLDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckldq, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKLDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckldq, MCK_Mem, MCK_FR32 } },
+ { X86::PUNPCKLQDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklqdq, MCK_FR32, MCK_FR32 } },
+ { X86::PUNPCKLQDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklqdq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKLWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklwd, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKLWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklwd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKLWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklwd, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKLWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklwd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PXORrr, Convert_Reg1_2_ImpReg1_1, { MCK_pxor, MCK_VR64, MCK_VR64 } },
+ { X86::PXORrr, Convert_Reg1_2_ImpReg1_1, { MCK_pxor, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PXORrm, Convert_Reg1_2_ImpMem5_1, { MCK_pxor, MCK_Mem, MCK_VR64 } },
+ { X86::PXORrm, Convert_Reg1_2_ImpMem5_1, { MCK_pxor, MCK_Mem, MCK_FR32 } },
+ { X86::RCL8r1, Convert_Reg1_2Imp, { MCK_rclb, MCK_1, MCK_GR8 } },
+ { X86::RCL8m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclb, MCK_1, MCK_Mem } },
+ { X86::RCL8rCL, Convert_Reg1_2Imp, { MCK_rclb, MCK_CL, MCK_GR8 } },
+ { X86::RCL8mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclb, MCK_CL, MCK_Mem } },
+ { X86::RCL8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rclb, MCK_Imm, MCK_GR8 } },
+ { X86::RCL8mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rclb, MCK_Imm, MCK_Mem } },
+ { X86::RCL32r1, Convert_Reg1_2Imp, { MCK_rcll, MCK_1, MCK_GR32 } },
+ { X86::RCL32m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcll, MCK_1, MCK_Mem } },
+ { X86::RCL32rCL, Convert_Reg1_2Imp, { MCK_rcll, MCK_CL, MCK_GR32 } },
+ { X86::RCL32mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcll, MCK_CL, MCK_Mem } },
+ { X86::RCL32ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcll, MCK_Imm, MCK_GR32 } },
+ { X86::RCL32mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcll, MCK_Imm, MCK_Mem } },
+ { X86::RCL64r1, Convert_Reg1_2Imp, { MCK_rclq, MCK_1, MCK_GR64 } },
+ { X86::RCL64m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclq, MCK_1, MCK_Mem } },
+ { X86::RCL64rCL, Convert_Reg1_2Imp, { MCK_rclq, MCK_CL, MCK_GR64 } },
+ { X86::RCL64mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclq, MCK_CL, MCK_Mem } },
+ { X86::RCL64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rclq, MCK_Imm, MCK_GR64 } },
+ { X86::RCL64mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rclq, MCK_Imm, MCK_Mem } },
+ { X86::RCL16r1, Convert_Reg1_2Imp, { MCK_rclw, MCK_1, MCK_GR16 } },
+ { X86::RCL16m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclw, MCK_1, MCK_Mem } },
+ { X86::RCL16rCL, Convert_Reg1_2Imp, { MCK_rclw, MCK_CL, MCK_GR16 } },
+ { X86::RCL16mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclw, MCK_CL, MCK_Mem } },
+ { X86::RCL16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rclw, MCK_Imm, MCK_GR16 } },
+ { X86::RCL16mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rclw, MCK_Imm, MCK_Mem } },
+ { X86::RCPPSr, Convert_Reg1_2_Reg1_1, { MCK_rcpps, MCK_FR32, MCK_FR32 } },
+ { X86::RCPPSm, Convert_Reg1_2_Mem5_1, { MCK_rcpps, MCK_Mem, MCK_FR32 } },
+ { X86::RCPSSr, Convert_Reg1_2_Reg1_1, { MCK_rcpss, MCK_FR32, MCK_FR32 } },
+ { X86::RCPSSm, Convert_Reg1_2_Mem5_1, { MCK_rcpss, MCK_Mem, MCK_FR32 } },
+ { X86::RCR8r1, Convert_Reg1_2Imp, { MCK_rcrb, MCK_1, MCK_GR8 } },
+ { X86::RCR8m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrb, MCK_1, MCK_Mem } },
+ { X86::RCR8rCL, Convert_Reg1_2Imp, { MCK_rcrb, MCK_CL, MCK_GR8 } },
+ { X86::RCR8mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrb, MCK_CL, MCK_Mem } },
+ { X86::RCR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrb, MCK_Imm, MCK_GR8 } },
+ { X86::RCR8mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrb, MCK_Imm, MCK_Mem } },
+ { X86::RCR32r1, Convert_Reg1_2Imp, { MCK_rcrl, MCK_1, MCK_GR32 } },
+ { X86::RCR32m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrl, MCK_1, MCK_Mem } },
+ { X86::RCR32rCL, Convert_Reg1_2Imp, { MCK_rcrl, MCK_CL, MCK_GR32 } },
+ { X86::RCR32mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrl, MCK_CL, MCK_Mem } },
+ { X86::RCR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrl, MCK_Imm, MCK_GR32 } },
+ { X86::RCR32mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrl, MCK_Imm, MCK_Mem } },
+ { X86::RCR64r1, Convert_Reg1_2Imp, { MCK_rcrq, MCK_1, MCK_GR64 } },
+ { X86::RCR64m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrq, MCK_1, MCK_Mem } },
+ { X86::RCR64rCL, Convert_Reg1_2Imp, { MCK_rcrq, MCK_CL, MCK_GR64 } },
+ { X86::RCR64mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrq, MCK_CL, MCK_Mem } },
+ { X86::RCR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrq, MCK_Imm, MCK_GR64 } },
+ { X86::RCR64mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrq, MCK_Imm, MCK_Mem } },
+ { X86::RCR16r1, Convert_Reg1_2Imp, { MCK_rcrw, MCK_1, MCK_GR16 } },
+ { X86::RCR16m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrw, MCK_1, MCK_Mem } },
+ { X86::RCR16rCL, Convert_Reg1_2Imp, { MCK_rcrw, MCK_CL, MCK_GR16 } },
+ { X86::RCR16mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrw, MCK_CL, MCK_Mem } },
+ { X86::RCR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrw, MCK_Imm, MCK_GR16 } },
+ { X86::RCR16mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrw, MCK_Imm, MCK_Mem } },
+ { X86::ROL8rCL, Convert_Reg1_2Imp, { MCK_rolb, MCK_CL, MCK_GR8 } },
+ { X86::ROL8mCL, Convert_Mem5_2, { MCK_rolb, MCK_CL, MCK_Mem } },
+ { X86::ROL8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rolb, MCK_Imm, MCK_GR8 } },
+ { X86::ROL8mi, Convert_Mem5_2_Imm1_1, { MCK_rolb, MCK_Imm, MCK_Mem } },
+ { X86::ROL32rCL, Convert_Reg1_2Imp, { MCK_roll, MCK_CL, MCK_GR32 } },
+ { X86::ROL32mCL, Convert_Mem5_2, { MCK_roll, MCK_CL, MCK_Mem } },
+ { X86::ROL32ri, Convert_Reg1_2_ImpImm1_1, { MCK_roll, MCK_Imm, MCK_GR32 } },
+ { X86::ROL32mi, Convert_Mem5_2_Imm1_1, { MCK_roll, MCK_Imm, MCK_Mem } },
+ { X86::ROL64rCL, Convert_Reg1_2Imp, { MCK_rolq, MCK_CL, MCK_GR64 } },
+ { X86::ROL64mCL, Convert_Mem5_2, { MCK_rolq, MCK_CL, MCK_Mem } },
+ { X86::ROL64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rolq, MCK_Imm, MCK_GR64 } },
+ { X86::ROL64mi, Convert_Mem5_2_Imm1_1, { MCK_rolq, MCK_Imm, MCK_Mem } },
+ { X86::ROL16rCL, Convert_Reg1_2Imp, { MCK_rolw, MCK_CL, MCK_GR16 } },
+ { X86::ROL16mCL, Convert_Mem5_2, { MCK_rolw, MCK_CL, MCK_Mem } },
+ { X86::ROL16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rolw, MCK_Imm, MCK_GR16 } },
+ { X86::ROL16mi, Convert_Mem5_2_Imm1_1, { MCK_rolw, MCK_Imm, MCK_Mem } },
+ { X86::ROR8rCL, Convert_Reg1_2Imp, { MCK_rorb, MCK_CL, MCK_GR8 } },
+ { X86::ROR8mCL, Convert_Mem5_2, { MCK_rorb, MCK_CL, MCK_Mem } },
+ { X86::ROR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorb, MCK_Imm, MCK_GR8 } },
+ { X86::ROR8mi, Convert_Mem5_2_Imm1_1, { MCK_rorb, MCK_Imm, MCK_Mem } },
+ { X86::ROR32rCL, Convert_Reg1_2Imp, { MCK_rorl, MCK_CL, MCK_GR32 } },
+ { X86::ROR32mCL, Convert_Mem5_2, { MCK_rorl, MCK_CL, MCK_Mem } },
+ { X86::ROR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorl, MCK_Imm, MCK_GR32 } },
+ { X86::ROR32mi, Convert_Mem5_2_Imm1_1, { MCK_rorl, MCK_Imm, MCK_Mem } },
+ { X86::ROR64rCL, Convert_Reg1_2Imp, { MCK_rorq, MCK_CL, MCK_GR64 } },
+ { X86::ROR64mCL, Convert_Mem5_2, { MCK_rorq, MCK_CL, MCK_Mem } },
+ { X86::ROR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorq, MCK_Imm, MCK_GR64 } },
+ { X86::ROR64mi, Convert_Mem5_2_Imm1_1, { MCK_rorq, MCK_Imm, MCK_Mem } },
+ { X86::ROR16rCL, Convert_Reg1_2Imp, { MCK_rorw, MCK_CL, MCK_GR16 } },
+ { X86::ROR16mCL, Convert_Mem5_2, { MCK_rorw, MCK_CL, MCK_Mem } },
+ { X86::ROR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorw, MCK_Imm, MCK_GR16 } },
+ { X86::ROR16mi, Convert_Mem5_2_Imm1_1, { MCK_rorw, MCK_Imm, MCK_Mem } },
+ { X86::RSQRTPSr, Convert_Reg1_2_Reg1_1, { MCK_rsqrtps, MCK_FR32, MCK_FR32 } },
+ { X86::RSQRTPSm, Convert_Reg1_2_Mem5_1, { MCK_rsqrtps, MCK_Mem, MCK_FR32 } },
+ { X86::RSQRTSSr, Convert_Reg1_2_Reg1_1, { MCK_rsqrtss, MCK_FR32, MCK_FR32 } },
+ { X86::RSQRTSSm, Convert_Reg1_2_Mem5_1, { MCK_rsqrtss, MCK_Mem, MCK_FR32 } },
+ { X86::SAR8rCL, Convert_Reg1_2Imp, { MCK_sarb, MCK_CL, MCK_GR8 } },
+ { X86::SAR8mCL, Convert_Mem5_2, { MCK_sarb, MCK_CL, MCK_Mem } },
+ { X86::SAR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarb, MCK_Imm, MCK_GR8 } },
+ { X86::SAR8mi, Convert_Mem5_2_Imm1_1, { MCK_sarb, MCK_Imm, MCK_Mem } },
+ { X86::SAR32rCL, Convert_Reg1_2Imp, { MCK_sarl, MCK_CL, MCK_GR32 } },
+ { X86::SAR32mCL, Convert_Mem5_2, { MCK_sarl, MCK_CL, MCK_Mem } },
+ { X86::SAR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarl, MCK_Imm, MCK_GR32 } },
+ { X86::SAR32mi, Convert_Mem5_2_Imm1_1, { MCK_sarl, MCK_Imm, MCK_Mem } },
+ { X86::SAR64rCL, Convert_Reg1_2Imp, { MCK_sarq, MCK_CL, MCK_GR64 } },
+ { X86::SAR64mCL, Convert_Mem5_2, { MCK_sarq, MCK_CL, MCK_Mem } },
+ { X86::SAR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarq, MCK_Imm, MCK_GR64 } },
+ { X86::SAR64mi, Convert_Mem5_2_Imm1_1, { MCK_sarq, MCK_Imm, MCK_Mem } },
+ { X86::SAR16rCL, Convert_Reg1_2Imp, { MCK_sarw, MCK_CL, MCK_GR16 } },
+ { X86::SAR16mCL, Convert_Mem5_2, { MCK_sarw, MCK_CL, MCK_Mem } },
+ { X86::SAR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarw, MCK_Imm, MCK_GR16 } },
+ { X86::SAR16mi, Convert_Mem5_2_Imm1_1, { MCK_sarw, MCK_Imm, MCK_Mem } },
+ { X86::SBB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
+ { X86::SBB8mr, Convert_Mem5_2_Reg1_1, { MCK_sbbb, MCK_GR8, MCK_Mem } },
+ { X86::SBB8i8, Convert_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_AL } },
+ { X86::SBB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbb, MCK_Imm, MCK_GR8 } },
+ { X86::SBB8mi, Convert_Mem5_2_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_Mem } },
+ { X86::SBB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbb, MCK_Mem, MCK_GR8 } },
+ { X86::SBB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
+ { X86::SBB32mr, Convert_Mem5_2_Reg1_1, { MCK_sbbl, MCK_GR32, MCK_Mem } },
+ { X86::SBB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::SBB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SBB32i32, Convert_Imm1_1, { MCK_sbbl, MCK_Imm, MCK_EAX } },
+ { X86::SBB32ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbl, MCK_Imm, MCK_GR32 } },
+ { X86::SBB32mi, Convert_Mem5_2_Imm1_1, { MCK_sbbl, MCK_Imm, MCK_Mem } },
+ { X86::SBB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbl, MCK_Mem, MCK_GR32 } },
+ { X86::SBB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
+ { X86::SBB64mr, Convert_Mem5_2_Reg1_1, { MCK_sbbq, MCK_GR64, MCK_Mem } },
+ { X86::SBB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::SBB64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SBB64i32, Convert_Imm1_1, { MCK_sbbq, MCK_Imm, MCK_RAX } },
+ { X86::SBB64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_sbbq, MCK_Imm, MCK_GR64 } },
+ { X86::SBB64mi32, Convert_Mem5_2_Imm1_1, { MCK_sbbq, MCK_Imm, MCK_Mem } },
+ { X86::SBB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbq, MCK_Mem, MCK_GR64 } },
+ { X86::SBB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
+ { X86::SBB16mr, Convert_Mem5_2_Reg1_1, { MCK_sbbw, MCK_GR16, MCK_Mem } },
+ { X86::SBB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::SBB16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SBB16i16, Convert_Imm1_1, { MCK_sbbw, MCK_Imm, MCK_AX } },
+ { X86::SBB16ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbw, MCK_Imm, MCK_GR16 } },
+ { X86::SBB16mi, Convert_Mem5_2_Imm1_1, { MCK_sbbw, MCK_Imm, MCK_Mem } },
+ { X86::SBB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbw, MCK_Mem, MCK_GR16 } },
+ { X86::SHL8rCL, Convert_Reg1_2Imp, { MCK_shlb, MCK_CL, MCK_GR8 } },
+ { X86::SHL8mCL, Convert_Mem5_2, { MCK_shlb, MCK_CL, MCK_Mem } },
+ { X86::SHL8ri, Convert_Reg1_2_ImpImm1_1, { MCK_shlb, MCK_Imm, MCK_GR8 } },
+ { X86::SHL8mi, Convert_Mem5_2_Imm1_1, { MCK_shlb, MCK_Imm, MCK_Mem } },
+ { X86::SHL32rCL, Convert_Reg1_2Imp, { MCK_shll, MCK_CL, MCK_GR32 } },
+ { X86::SHL32mCL, Convert_Mem5_2, { MCK_shll, MCK_CL, MCK_Mem } },
+ { X86::SHL32ri, Convert_Reg1_2_ImpImm1_1, { MCK_shll, MCK_Imm, MCK_GR32 } },
+ { X86::SHL32mi, Convert_Mem5_2_Imm1_1, { MCK_shll, MCK_Imm, MCK_Mem } },
+ { X86::SHL64rCL, Convert_Reg1_2Imp, { MCK_shlq, MCK_CL, MCK_GR64 } },
+ { X86::SHL64mCL, Convert_Mem5_2, { MCK_shlq, MCK_CL, MCK_Mem } },
+ { X86::SHL64ri, Convert_Reg1_2_ImpImm1_1, { MCK_shlq, MCK_Imm, MCK_GR64 } },
+ { X86::SHL64mi, Convert_Mem5_2_Imm1_1, { MCK_shlq, MCK_Imm, MCK_Mem } },
+ { X86::SHL16rCL, Convert_Reg1_2Imp, { MCK_shlw, MCK_CL, MCK_GR16 } },
+ { X86::SHL16mCL, Convert_Mem5_2, { MCK_shlw, MCK_CL, MCK_Mem } },
+ { X86::SHL16ri, Convert_Reg1_2_ImpImm1_1, { MCK_shlw, MCK_Imm, MCK_GR16 } },
+ { X86::SHL16mi, Convert_Mem5_2_Imm1_1, { MCK_shlw, MCK_Imm, MCK_Mem } },
+ { X86::SHR8rCL, Convert_Reg1_2Imp, { MCK_shrb, MCK_CL, MCK_GR8 } },
+ { X86::SHR8mCL, Convert_Mem5_2, { MCK_shrb, MCK_CL, MCK_Mem } },
+ { X86::SHR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrb, MCK_Imm, MCK_GR8 } },
+ { X86::SHR8mi, Convert_Mem5_2_Imm1_1, { MCK_shrb, MCK_Imm, MCK_Mem } },
+ { X86::SHR32rCL, Convert_Reg1_2Imp, { MCK_shrl, MCK_CL, MCK_GR32 } },
+ { X86::SHR32mCL, Convert_Mem5_2, { MCK_shrl, MCK_CL, MCK_Mem } },
+ { X86::SHR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrl, MCK_Imm, MCK_GR32 } },
+ { X86::SHR32mi, Convert_Mem5_2_Imm1_1, { MCK_shrl, MCK_Imm, MCK_Mem } },
+ { X86::SHR64rCL, Convert_Reg1_2Imp, { MCK_shrq, MCK_CL, MCK_GR64 } },
+ { X86::SHR64mCL, Convert_Mem5_2, { MCK_shrq, MCK_CL, MCK_Mem } },
+ { X86::SHR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrq, MCK_Imm, MCK_GR64 } },
+ { X86::SHR64mi, Convert_Mem5_2_Imm1_1, { MCK_shrq, MCK_Imm, MCK_Mem } },
+ { X86::SHR16rCL, Convert_Reg1_2Imp, { MCK_shrw, MCK_CL, MCK_GR16 } },
+ { X86::SHR16mCL, Convert_Mem5_2, { MCK_shrw, MCK_CL, MCK_Mem } },
+ { X86::SHR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrw, MCK_Imm, MCK_GR16 } },
+ { X86::SHR16mi, Convert_Mem5_2_Imm1_1, { MCK_shrw, MCK_Imm, MCK_Mem } },
+ { X86::SQRTPDr, Convert_Reg1_2_Reg1_1, { MCK_sqrtpd, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTPDm, Convert_Reg1_2_Mem5_1, { MCK_sqrtpd, MCK_Mem, MCK_FR32 } },
+ { X86::SQRTPSr, Convert_Reg1_2_Reg1_1, { MCK_sqrtps, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTPSm, Convert_Reg1_2_Mem5_1, { MCK_sqrtps, MCK_Mem, MCK_FR32 } },
+ { X86::SQRTSDr, Convert_Reg1_2_Reg1_1, { MCK_sqrtsd, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTSDm, Convert_Reg1_2_Mem5_1, { MCK_sqrtsd, MCK_Mem, MCK_FR32 } },
+ { X86::SQRTSSr, Convert_Reg1_2_Reg1_1, { MCK_sqrtss, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTSSm, Convert_Reg1_2_Mem5_1, { MCK_sqrtss, MCK_Mem, MCK_FR32 } },
+ { X86::SUB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
+ { X86::SUB8mr, Convert_Mem5_2_Reg1_1, { MCK_subb, MCK_GR8, MCK_Mem } },
+ { X86::SUB8i8, Convert_Imm1_1, { MCK_subb, MCK_Imm, MCK_AL } },
+ { X86::SUB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_subb, MCK_Imm, MCK_GR8 } },
+ { X86::SUB8mi, Convert_Mem5_2_Imm1_1, { MCK_subb, MCK_Imm, MCK_Mem } },
+ { X86::SUB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_subb, MCK_Mem, MCK_GR8 } },
+ { X86::SUB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
+ { X86::SUB32mr, Convert_Mem5_2_Reg1_1, { MCK_subl, MCK_GR32, MCK_Mem } },
+ { X86::SUB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::SUB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SUB32i32, Convert_Imm1_1, { MCK_subl, MCK_Imm, MCK_EAX } },
+ { X86::SUB32ri, Convert_Reg1_2_ImpImm1_1, { MCK_subl, MCK_Imm, MCK_GR32 } },
+ { X86::SUB32mi, Convert_Mem5_2_Imm1_1, { MCK_subl, MCK_Imm, MCK_Mem } },
+ { X86::SUB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_subl, MCK_Mem, MCK_GR32 } },
+ { X86::SUBPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_subpd, MCK_FR32, MCK_FR32 } },
+ { X86::SUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_subpd, MCK_Mem, MCK_FR32 } },
+ { X86::SUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subps, MCK_FR32, MCK_FR32 } },
+ { X86::SUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subps, MCK_Mem, MCK_FR32 } },
+ { X86::SUB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
+ { X86::SUB64mr, Convert_Mem5_2_Reg1_1, { MCK_subq, MCK_GR64, MCK_Mem } },
+ { X86::SUB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::SUB64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SUB64i32, Convert_Imm1_1, { MCK_subq, MCK_Imm, MCK_RAX } },
+ { X86::SUB64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_subq, MCK_Imm, MCK_GR64 } },
+ { X86::SUB64mi32, Convert_Mem5_2_Imm1_1, { MCK_subq, MCK_Imm, MCK_Mem } },
+ { X86::SUB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_subq, MCK_Mem, MCK_GR64 } },
+ { X86::SUBSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_subsd, MCK_FR32, MCK_FR32 } },
+ { X86::SUBSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_subsd, MCK_Mem, MCK_FR32 } },
+ { X86::SUBSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subss, MCK_FR32, MCK_FR32 } },
+ { X86::SUBSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subss, MCK_Mem, MCK_FR32 } },
+ { X86::SUB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
+ { X86::SUB16mr, Convert_Mem5_2_Reg1_1, { MCK_subw, MCK_GR16, MCK_Mem } },
+ { X86::SUB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::SUB16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SUB16i16, Convert_Imm1_1, { MCK_subw, MCK_Imm, MCK_AX } },
+ { X86::SUB16ri, Convert_Reg1_2_ImpImm1_1, { MCK_subw, MCK_Imm, MCK_GR16 } },
+ { X86::SUB16mi, Convert_Mem5_2_Imm1_1, { MCK_subw, MCK_Imm, MCK_Mem } },
+ { X86::SUB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_subw, MCK_Mem, MCK_GR16 } },
+ { X86::TEST8rr, Convert_Reg1_2_Reg1_1, { MCK_testb, MCK_GR8, MCK_GR8 } },
+ { X86::TEST8i8, Convert_Imm1_1, { MCK_testb, MCK_Imm, MCK_AL } },
+ { X86::TEST8ri, Convert_Reg1_2_Imm1_1, { MCK_testb, MCK_Imm, MCK_GR8 } },
+ { X86::TEST8mi, Convert_Mem5_2_Imm1_1, { MCK_testb, MCK_Imm, MCK_Mem } },
+ { X86::TEST8rm, Convert_Reg1_2_Mem5_1, { MCK_testb, MCK_Mem, MCK_GR8 } },
+ { X86::TEST32rr, Convert_Reg1_2_Reg1_1, { MCK_testl, MCK_GR32, MCK_GR32 } },
+ { X86::TEST32i32, Convert_Imm1_1, { MCK_testl, MCK_Imm, MCK_EAX } },
+ { X86::TEST32ri, Convert_Reg1_2_Imm1_1, { MCK_testl, MCK_Imm, MCK_GR32 } },
+ { X86::TEST32mi, Convert_Mem5_2_Imm1_1, { MCK_testl, MCK_Imm, MCK_Mem } },
+ { X86::TEST32rm, Convert_Reg1_2_Mem5_1, { MCK_testl, MCK_Mem, MCK_GR32 } },
+ { X86::TEST64rr, Convert_Reg1_2_Reg1_1, { MCK_testq, MCK_GR64, MCK_GR64 } },
+ { X86::TEST64i32, Convert_Imm1_1, { MCK_testq, MCK_Imm, MCK_RAX } },
+ { X86::TEST64ri32, Convert_Reg1_2_Imm1_1, { MCK_testq, MCK_Imm, MCK_GR64 } },
+ { X86::TEST64mi32, Convert_Mem5_2_Imm1_1, { MCK_testq, MCK_Imm, MCK_Mem } },
+ { X86::TEST64rm, Convert_Reg1_2_Mem5_1, { MCK_testq, MCK_Mem, MCK_GR64 } },
+ { X86::TEST16rr, Convert_Reg1_2_Reg1_1, { MCK_testw, MCK_GR16, MCK_GR16 } },
+ { X86::TEST16i16, Convert_Imm1_1, { MCK_testw, MCK_Imm, MCK_AX } },
+ { X86::TEST16ri, Convert_Reg1_2_Imm1_1, { MCK_testw, MCK_Imm, MCK_GR16 } },
+ { X86::TEST16mi, Convert_Mem5_2_Imm1_1, { MCK_testw, MCK_Imm, MCK_Mem } },
+ { X86::TEST16rm, Convert_Reg1_2_Mem5_1, { MCK_testw, MCK_Mem, MCK_GR16 } },
+ { X86::UCOMISDrr, Convert_Reg1_2_Reg1_1, { MCK_ucomisd, MCK_FR32, MCK_FR32 } },
+ { X86::UCOMISDrm, Convert_Reg1_2_Mem5_1, { MCK_ucomisd, MCK_Mem, MCK_FR32 } },
+ { X86::UCOMISSrr, Convert_Reg1_2_Reg1_1, { MCK_ucomiss, MCK_FR32, MCK_FR32 } },
+ { X86::UCOMISSrm, Convert_Reg1_2_Mem5_1, { MCK_ucomiss, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKHPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpckhpd, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKHPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpckhpd, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKHPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpckhps, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKHPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpckhps, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpcklpd, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKLPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpcklpd, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpcklps, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKLPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpcklps, MCK_Mem, MCK_FR32 } },
+ { X86::XCHG64rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchg, MCK_GR64, MCK_Mem } },
+ { X86::XCHG8rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchgb, MCK_GR8, MCK_Mem } },
+ { X86::XCHG32rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchgl, MCK_GR32, MCK_Mem } },
+ { X86::XCHG16rm, Convert_ImpMem5_2_Reg1_1, { MCK_xchgw, MCK_GR16, MCK_Mem } },
+ { X86::XOR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
+ { X86::XOR8mr, Convert_Mem5_2_Reg1_1, { MCK_xorb, MCK_GR8, MCK_Mem } },
+ { X86::XOR8i8, Convert_Imm1_1, { MCK_xorb, MCK_Imm, MCK_AL } },
+ { X86::XOR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorb, MCK_Imm, MCK_GR8 } },
+ { X86::XOR8mi, Convert_Mem5_2_Imm1_1, { MCK_xorb, MCK_Imm, MCK_Mem } },
+ { X86::XOR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorb, MCK_Mem, MCK_GR8 } },
+ { X86::XOR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
+ { X86::XOR32mr, Convert_Mem5_2_Reg1_1, { MCK_xorl, MCK_GR32, MCK_Mem } },
+ { X86::XOR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::XOR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::XOR32i32, Convert_Imm1_1, { MCK_xorl, MCK_Imm, MCK_EAX } },
+ { X86::XOR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorl, MCK_Imm, MCK_GR32 } },
+ { X86::XOR32mi, Convert_Mem5_2_Imm1_1, { MCK_xorl, MCK_Imm, MCK_Mem } },
+ { X86::XOR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorl, MCK_Mem, MCK_GR32 } },
+ { X86::XORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsXORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
+ { X86::XORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsXORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
+ { X86::XORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
+ { X86::FsXORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
+ { X86::FsXORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
+ { X86::XORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
+ { X86::XOR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
+ { X86::XOR64mr, Convert_Mem5_2_Reg1_1, { MCK_xorq, MCK_GR64, MCK_Mem } },
+ { X86::XOR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::XOR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::XOR64i32, Convert_Imm1_1, { MCK_xorq, MCK_Imm, MCK_RAX } },
+ { X86::XOR64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_xorq, MCK_Imm, MCK_GR64 } },
+ { X86::XOR64mi32, Convert_Mem5_2_Imm1_1, { MCK_xorq, MCK_Imm, MCK_Mem } },
+ { X86::XOR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorq, MCK_Mem, MCK_GR64 } },
+ { X86::XOR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
+ { X86::XOR16mr, Convert_Mem5_2_Reg1_1, { MCK_xorw, MCK_GR16, MCK_Mem } },
+ { X86::XOR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::XOR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::XOR16i16, Convert_Imm1_1, { MCK_xorw, MCK_Imm, MCK_AX } },
+ { X86::XOR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorw, MCK_Imm, MCK_GR16 } },
+ { X86::XOR16mi, Convert_Mem5_2_Imm1_1, { MCK_xorw, MCK_Imm, MCK_Mem } },
+ { X86::XOR16rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorw, MCK_Mem, MCK_GR16 } },
+ { X86::BLENDPDrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_blendpd, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDPDrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_blendpd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::BLENDPSrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_blendps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDPSrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_blendps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::BLENDVPDrr0, Convert_Reg1_3_ImpReg1_2, { MCK_blendvpd, MCK_XMM0, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDVPDrm0, Convert_Reg1_3_ImpMem5_2, { MCK_blendvpd, MCK_XMM0, MCK_Mem, MCK_FR32 } },
+ { X86::BLENDVPSrr0, Convert_Reg1_3_ImpReg1_2, { MCK_blendvps, MCK_XMM0, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDVPSrm0, Convert_Reg1_3_ImpMem5_2, { MCK_blendvps, MCK_XMM0, MCK_Mem, MCK_FR32 } },
+ { X86::DPPDrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_dppd, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::DPPDrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_dppd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::DPPSrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_dpps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::DPPSrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_dpps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::EXTRACTPSrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_extractps, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::EXTRACTPSmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_extractps, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::IMUL32rri8, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_imull, MCK_ImmSExt8, MCK_GR32, MCK_GR32 } },
+ { X86::IMUL32rmi8, Convert_Reg1_3_Mem5_2_ImmSExt81_1, { MCK_imull, MCK_ImmSExt8, MCK_Mem, MCK_GR32 } },
+ { X86::IMUL32rri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_imull, MCK_Imm, MCK_GR32, MCK_GR32 } },
+ { X86::IMUL32rmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_imull, MCK_Imm, MCK_Mem, MCK_GR32 } },
+ { X86::IMUL64rri8, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_imulq, MCK_ImmSExt8, MCK_GR64, MCK_GR64 } },
+ { X86::IMUL64rmi8, Convert_Reg1_3_Mem5_2_ImmSExt81_1, { MCK_imulq, MCK_ImmSExt8, MCK_Mem, MCK_GR64 } },
+ { X86::IMUL64rri32, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_imulq, MCK_Imm, MCK_GR64, MCK_GR64 } },
+ { X86::IMUL64rmi32, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_imulq, MCK_Imm, MCK_Mem, MCK_GR64 } },
+ { X86::IMUL16rri8, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_imulw, MCK_ImmSExt8, MCK_GR16, MCK_GR16 } },
+ { X86::IMUL16rmi8, Convert_Reg1_3_Mem5_2_ImmSExt81_1, { MCK_imulw, MCK_ImmSExt8, MCK_Mem, MCK_GR16 } },
+ { X86::IMUL16rri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_imulw, MCK_Imm, MCK_GR16, MCK_GR16 } },
+ { X86::IMUL16rmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_imulw, MCK_Imm, MCK_Mem, MCK_GR16 } },
+ { X86::INSERTPSrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_insertps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::INSERTPSrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_insertps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::MPSADBWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_mpsadbw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::MPSADBWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_mpsadbw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PALIGNR64rr, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_VR64, MCK_VR64 } },
+ { X86::PALIGNR128rr, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PALIGNR64rm, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_Mem, MCK_VR64 } },
+ { X86::PALIGNR128rm, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PBLENDVBrr0, Convert_Reg1_3_ImpReg1_2, { MCK_pblendvb, MCK_XMM0, MCK_FR32, MCK_FR32 } },
+ { X86::PBLENDVBrm0, Convert_Reg1_3_ImpMem5_2, { MCK_pblendvb, MCK_XMM0, MCK_Mem, MCK_FR32 } },
+ { X86::PBLENDWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::PBLENDWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PEXTRBrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::PEXTRBmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::PEXTRDrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrd, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::PEXTRDmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrd, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::PEXTRQrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrq, MCK_ImmSExt8, MCK_FR32, MCK_GR64 } },
+ { X86::PEXTRQmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrq, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::MMX_PEXTRWri, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_VR64, MCK_GR32 } },
+ { X86::PEXTRWri, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::PEXTRWmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::PINSRBrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrb, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
+ { X86::PINSRBrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrb, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PINSRDrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrd, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
+ { X86::PINSRDrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PINSRQrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrq, MCK_ImmSExt8, MCK_GR64, MCK_FR32 } },
+ { X86::PINSRQrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrq, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PINSRWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_GR32, MCK_VR64 } },
+ { X86::PINSRWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
+ { X86::MMX_PINSRWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_Mem, MCK_VR64 } },
+ { X86::PINSRWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFDri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshufd, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFDmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshufd, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFHWri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshufhw, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFHWmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshufhw, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFLWri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshuflw, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFLWmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshuflw, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSHUFWri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshufw, MCK_Imm, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_PSHUFWmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshufw, MCK_Imm, MCK_Mem, MCK_VR64 } },
+ { X86::SHLD32rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shldl, MCK_CL, MCK_GR32, MCK_GR32 } },
+ { X86::SHLD32mrCL, Convert_Mem5_3_Reg1_2, { MCK_shldl, MCK_CL, MCK_GR32, MCK_Mem } },
+ { X86::SHLD32rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shldl, MCK_Imm, MCK_GR32, MCK_GR32 } },
+ { X86::SHLD32mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shldl, MCK_Imm, MCK_GR32, MCK_Mem } },
+ { X86::SHLD64rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shldq, MCK_CL, MCK_GR64, MCK_GR64 } },
+ { X86::SHLD64mrCL, Convert_Mem5_3_Reg1_2, { MCK_shldq, MCK_CL, MCK_GR64, MCK_Mem } },
+ { X86::SHLD64rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shldq, MCK_Imm, MCK_GR64, MCK_GR64 } },
+ { X86::SHLD64mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shldq, MCK_Imm, MCK_GR64, MCK_Mem } },
+ { X86::SHLD16rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shldw, MCK_CL, MCK_GR16, MCK_GR16 } },
+ { X86::SHLD16mrCL, Convert_Mem5_3_Reg1_2, { MCK_shldw, MCK_CL, MCK_GR16, MCK_Mem } },
+ { X86::SHLD16rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shldw, MCK_Imm, MCK_GR16, MCK_GR16 } },
+ { X86::SHLD16mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shldw, MCK_Imm, MCK_GR16, MCK_Mem } },
+ { X86::SHRD32rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shrdl, MCK_CL, MCK_GR32, MCK_GR32 } },
+ { X86::SHRD32mrCL, Convert_Mem5_3_Reg1_2, { MCK_shrdl, MCK_CL, MCK_GR32, MCK_Mem } },
+ { X86::SHRD32rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shrdl, MCK_Imm, MCK_GR32, MCK_GR32 } },
+ { X86::SHRD32mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shrdl, MCK_Imm, MCK_GR32, MCK_Mem } },
+ { X86::SHRD64rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shrdq, MCK_CL, MCK_GR64, MCK_GR64 } },
+ { X86::SHRD64mrCL, Convert_Mem5_3_Reg1_2, { MCK_shrdq, MCK_CL, MCK_GR64, MCK_Mem } },
+ { X86::SHRD64rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shrdq, MCK_Imm, MCK_GR64, MCK_GR64 } },
+ { X86::SHRD64mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shrdq, MCK_Imm, MCK_GR64, MCK_Mem } },
+ { X86::SHRD16rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shrdw, MCK_CL, MCK_GR16, MCK_GR16 } },
+ { X86::SHRD16mrCL, Convert_Mem5_3_Reg1_2, { MCK_shrdw, MCK_CL, MCK_GR16, MCK_Mem } },
+ { X86::SHRD16rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shrdw, MCK_Imm, MCK_GR16, MCK_GR16 } },
+ { X86::SHRD16mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shrdw, MCK_Imm, MCK_GR16, MCK_Mem } },
+ { X86::SHUFPDrri, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shufpd, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::SHUFPDrmi, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_shufpd, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::SHUFPSrri, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shufps, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::SHUFPSrmi, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_shufps, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::CMPPDrri, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_pd, MCK_FR32, MCK_FR32 } },
+ { X86::CMPPDrmi, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_pd, MCK_Mem, MCK_FR32 } },
+ { X86::CMPPSrri, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ps, MCK_FR32, MCK_FR32 } },
+ { X86::CMPPSrmi, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ps, MCK_Mem, MCK_FR32 } },
+ { X86::CMPSDrr, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_sd, MCK_FR32, MCK_FR32 } },
+ { X86::CMPSDrm, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_sd, MCK_Mem, MCK_FR32 } },
+ { X86::CMPSSrr, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ss, MCK_FR32, MCK_FR32 } },
+ { X86::CMPSSrm, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ss, MCK_Mem, MCK_FR32 } },
+ };
+
+ // Eliminate obvious mismatches.
+ if (Operands.size() > 5)
+ return true;
+
+ // Compute the class list for this operand vector.
+ MatchClassKind Classes[5];
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ Classes[i] = ClassifyOperand(Operands[i]);
+
+ // Check for invalid operands before matching.
+ if (Classes[i] == InvalidMatchClass)
+ return true;
+ }
+
+ // Mark unused classes.
+ for (unsigned i = Operands.size(), e = 5; i != e; ++i)
+ Classes[i] = InvalidMatchClass;
+
+ // Search the table.
+ for (const MatchEntry *it = MatchTable, *ie = MatchTable + 1775; it != ie; ++it) {
+ if (!IsSubclass(Classes[0], it->Classes[0]))
+ continue;
+ if (!IsSubclass(Classes[1], it->Classes[1]))
+ continue;
+ if (!IsSubclass(Classes[2], it->Classes[2]))
+ continue;
+ if (!IsSubclass(Classes[3], it->Classes[3]))
+ continue;
+ if (!IsSubclass(Classes[4], it->Classes[4]))
+ continue;
+
+ return ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
+ }
+
+ return true;
+}
+
diff --git a/libclamav/c++/X86GenAsmWriter.inc b/libclamav/c++/X86GenAsmWriter.inc
new file mode 100644
index 0000000..4dad678
--- /dev/null
+++ b/libclamav/c++/X86GenAsmWriter.inc
@@ -0,0 +1,3022 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Assembly Writer Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
+ static const unsigned OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // DBG_LABEL
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 1U, // ABS_F
+ 0U, // ABS_Fp32
+ 0U, // ABS_Fp64
+ 0U, // ABS_Fp80
+ 67108870U, // ADC16i16
+ 135266310U, // ADC16mi
+ 135266310U, // ADC16mi8
+ 135266310U, // ADC16mr
+ 203423750U, // ADC16ri
+ 203423750U, // ADC16ri8
+ 270532614U, // ADC16rm
+ 203423750U, // ADC16rr
+ 70254604U, // ADC32i32
+ 135331852U, // ADC32mi
+ 135331852U, // ADC32mi8
+ 135331852U, // ADC32mr
+ 203423756U, // ADC32ri
+ 203423756U, // ADC32ri8
+ 337641484U, // ADC32rm
+ 203423756U, // ADC32rr
+ 71303186U, // ADC64i32
+ 135397394U, // ADC64mi32
+ 135397394U, // ADC64mi8
+ 135397394U, // ADC64mr
+ 203423762U, // ADC64ri32
+ 203423762U, // ADC64ri8
+ 404750354U, // ADC64rm
+ 203423762U, // ADC64rr
+ 72351768U, // ADC8i8
+ 135462936U, // ADC8mi
+ 135462936U, // ADC8mr
+ 203423768U, // ADC8ri
+ 471859224U, // ADC8rm
+ 203423768U, // ADC8rr
+ 67108894U, // ADD16i16
+ 135266334U, // ADD16mi
+ 135266334U, // ADD16mi8
+ 135266334U, // ADD16mr
+ 203423774U, // ADD16mrmrr
+ 203423774U, // ADD16ri
+ 203423774U, // ADD16ri8
+ 270532638U, // ADD16rm
+ 203423774U, // ADD16rr
+ 70254628U, // ADD32i32
+ 135331876U, // ADD32mi
+ 135331876U, // ADD32mi8
+ 135331876U, // ADD32mr
+ 203423780U, // ADD32mrmrr
+ 203423780U, // ADD32ri
+ 203423780U, // ADD32ri8
+ 337641508U, // ADD32rm
+ 203423780U, // ADD32rr
+ 71303210U, // ADD64i32
+ 135397418U, // ADD64mi32
+ 135397418U, // ADD64mi8
+ 135397418U, // ADD64mr
+ 203423780U, // ADD64mrmrr
+ 203423786U, // ADD64ri32
+ 203423786U, // ADD64ri8
+ 404750378U, // ADD64rm
+ 203423786U, // ADD64rr
+ 72351792U, // ADD8i8
+ 135462960U, // ADD8mi
+ 135462960U, // ADD8mr
+ 203423792U, // ADD8mrmrr
+ 203423792U, // ADD8ri
+ 471859248U, // ADD8rm
+ 203423792U, // ADD8rr
+ 536870966U, // ADDPDrm
+ 203423798U, // ADDPDrr
+ 536870973U, // ADDPSrm
+ 203423805U, // ADDPSrr
+ 603979844U, // ADDSDrm
+ 603979844U, // ADDSDrm_Int
+ 203423812U, // ADDSDrr
+ 203423812U, // ADDSDrr_Int
+ 671088715U, // ADDSSrm
+ 671088715U, // ADDSSrm_Int
+ 203423819U, // ADDSSrr
+ 203423819U, // ADDSSrr_Int
+ 536870994U, // ADDSUBPDrm
+ 203423826U, // ADDSUBPDrr
+ 536871004U, // ADDSUBPSrm
+ 203423836U, // ADDSUBPSrr
+ 738197606U, // ADD_F32m
+ 805306477U, // ADD_F64m
+ 872415348U, // ADD_FI16m
+ 945815676U, // ADD_FI32m
+ 73400452U, // ADD_FPrST0
+ 73400459U, // ADD_FST0r
+ 0U, // ADD_Fp32
+ 0U, // ADD_Fp32m
+ 0U, // ADD_Fp64
+ 0U, // ADD_Fp64m
+ 0U, // ADD_Fp64m32
+ 0U, // ADD_Fp80
+ 0U, // ADD_Fp80m32
+ 0U, // ADD_Fp80m64
+ 0U, // ADD_FpI16m32
+ 0U, // ADD_FpI16m64
+ 0U, // ADD_FpI16m80
+ 0U, // ADD_FpI32m32
+ 0U, // ADD_FpI32m64
+ 0U, // ADD_FpI32m80
+ 73400465U, // ADD_FrST0
+ 159U, // ADJCALLSTACKDOWN32
+ 159U, // ADJCALLSTACKDOWN64
+ 177U, // ADJCALLSTACKUP32
+ 177U, // ADJCALLSTACKUP64
+ 67109057U, // AND16i16
+ 135266497U, // AND16mi
+ 135266497U, // AND16mi8
+ 135266497U, // AND16mr
+ 203423937U, // AND16ri
+ 203423937U, // AND16ri8
+ 270532801U, // AND16rm
+ 203423937U, // AND16rr
+ 70254791U, // AND32i32
+ 135332039U, // AND32mi
+ 135332039U, // AND32mi8
+ 135332039U, // AND32mr
+ 203423943U, // AND32ri
+ 203423943U, // AND32ri8
+ 337641671U, // AND32rm
+ 203423943U, // AND32rr
+ 71303373U, // AND64i32
+ 135397581U, // AND64mi32
+ 135397581U, // AND64mi8
+ 135397581U, // AND64mr
+ 203423949U, // AND64ri32
+ 203423949U, // AND64ri8
+ 404750541U, // AND64rm
+ 203423949U, // AND64rr
+ 72351955U, // AND8i8
+ 135463123U, // AND8mi
+ 135463123U, // AND8mr
+ 203423955U, // AND8ri
+ 471859411U, // AND8rm
+ 203423955U, // AND8rr
+ 536871129U, // ANDNPDrm
+ 203423961U, // ANDNPDrr
+ 536871137U, // ANDNPSrm
+ 203423969U, // ANDNPSrr
+ 536871145U, // ANDPDrm
+ 203423977U, // ANDPDrr
+ 536871152U, // ANDPSrm
+ 203423984U, // ANDPSrr
+ 247U, // ATOMADD6432
+ 268U, // ATOMAND16
+ 287U, // ATOMAND32
+ 306U, // ATOMAND64
+ 325U, // ATOMAND6432
+ 346U, // ATOMAND8
+ 364U, // ATOMMAX16
+ 383U, // ATOMMAX32
+ 402U, // ATOMMAX64
+ 421U, // ATOMMIN16
+ 440U, // ATOMMIN32
+ 459U, // ATOMMIN64
+ 478U, // ATOMNAND16
+ 498U, // ATOMNAND32
+ 518U, // ATOMNAND64
+ 538U, // ATOMNAND6432
+ 560U, // ATOMNAND8
+ 579U, // ATOMOR16
+ 597U, // ATOMOR32
+ 615U, // ATOMOR64
+ 633U, // ATOMOR6432
+ 653U, // ATOMOR8
+ 670U, // ATOMSUB6432
+ 691U, // ATOMSWAP6432
+ 713U, // ATOMUMAX16
+ 733U, // ATOMUMAX32
+ 753U, // ATOMUMAX64
+ 773U, // ATOMUMIN16
+ 793U, // ATOMUMIN32
+ 813U, // ATOMUMIN64
+ 833U, // ATOMXOR16
+ 852U, // ATOMXOR32
+ 871U, // ATOMXOR64
+ 890U, // ATOMXOR6432
+ 911U, // ATOMXOR8
+ 1013973921U, // BLENDPDrmi
+ 1073742753U, // BLENDPDrri
+ 1013973930U, // BLENDPSrmi
+ 1073742762U, // BLENDPSrri
+ 1140851635U, // BLENDVPDrm0
+ 203424691U, // BLENDVPDrr0
+ 1140851652U, // BLENDVPSrm0
+ 203424708U, // BLENDVPSrr0
+ 1207960533U, // BSF16rm
+ 1281360853U, // BSF16rr
+ 1342178267U, // BSF32rm
+ 1281360859U, // BSF32rr
+ 1409287137U, // BSF64rm
+ 1281360865U, // BSF64rr
+ 1207960551U, // BSR16rm
+ 1281360871U, // BSR16rr
+ 1342178285U, // BSR32rm
+ 1281360877U, // BSR32rr
+ 1409287155U, // BSR64rm
+ 1281360883U, // BSR64rr
+ 73401337U, // BSWAP32r
+ 73401345U, // BSWAP64r
+ 135267337U, // BT16mi8
+ 1281360905U, // BT16ri8
+ 1281360905U, // BT16rr
+ 135332878U, // BT32mi8
+ 1281360910U, // BT32ri8
+ 1281360910U, // BT32rr
+ 135398419U, // BT64mi8
+ 1281360915U, // BT64ri8
+ 1281360915U, // BT64rr
+ 945816600U, // CALL32m
+ 73401368U, // CALL32r
+ 1476396056U, // CALL64m
+ 1549796383U, // CALL64pcrel32
+ 73401368U, // CALL64r
+ 1549796383U, // CALLpcrel32
+ 1061U, // CBW
+ 1066U, // CDQ
+ 1071U, // CDQE
+ 1076U, // CHS_F
+ 0U, // CHS_Fp32
+ 0U, // CHS_Fp64
+ 0U, // CHS_Fp80
+ 1610613817U, // CLFLUSH
+ 270533698U, // CMOVA16rm
+ 203424834U, // CMOVA16rr
+ 337642562U, // CMOVA32rm
+ 203424834U, // CMOVA32rr
+ 404751426U, // CMOVA64rm
+ 203424834U, // CMOVA64rr
+ 270533705U, // CMOVAE16rm
+ 203424841U, // CMOVAE16rr
+ 337642569U, // CMOVAE32rm
+ 203424841U, // CMOVAE32rr
+ 404751433U, // CMOVAE64rm
+ 203424841U, // CMOVAE64rr
+ 270533713U, // CMOVB16rm
+ 203424849U, // CMOVB16rr
+ 337642577U, // CMOVB32rm
+ 203424849U, // CMOVB32rr
+ 404751441U, // CMOVB64rm
+ 203424849U, // CMOVB64rr
+ 270533720U, // CMOVBE16rm
+ 203424856U, // CMOVBE16rr
+ 337642584U, // CMOVBE32rm
+ 203424856U, // CMOVBE32rr
+ 404751448U, // CMOVBE64rm
+ 203424856U, // CMOVBE64rr
+ 75498592U, // CMOVBE_F
+ 0U, // CMOVBE_Fp32
+ 0U, // CMOVBE_Fp64
+ 0U, // CMOVBE_Fp80
+ 75498601U, // CMOVB_F
+ 0U, // CMOVB_Fp32
+ 0U, // CMOVB_Fp64
+ 0U, // CMOVB_Fp80
+ 270533745U, // CMOVE16rm
+ 203424881U, // CMOVE16rr
+ 337642609U, // CMOVE32rm
+ 203424881U, // CMOVE32rr
+ 404751473U, // CMOVE64rm
+ 203424881U, // CMOVE64rr
+ 75498616U, // CMOVE_F
+ 0U, // CMOVE_Fp32
+ 0U, // CMOVE_Fp64
+ 0U, // CMOVE_Fp80
+ 270533760U, // CMOVG16rm
+ 203424896U, // CMOVG16rr
+ 337642624U, // CMOVG32rm
+ 203424896U, // CMOVG32rr
+ 404751488U, // CMOVG64rm
+ 203424896U, // CMOVG64rr
+ 270533767U, // CMOVGE16rm
+ 203424903U, // CMOVGE16rr
+ 337642631U, // CMOVGE32rm
+ 203424903U, // CMOVGE32rr
+ 404751495U, // CMOVGE64rm
+ 203424903U, // CMOVGE64rr
+ 270533775U, // CMOVL16rm
+ 203424911U, // CMOVL16rr
+ 337642639U, // CMOVL32rm
+ 203424911U, // CMOVL32rr
+ 404751503U, // CMOVL64rm
+ 203424911U, // CMOVL64rr
+ 270533782U, // CMOVLE16rm
+ 203424918U, // CMOVLE16rr
+ 337642646U, // CMOVLE32rm
+ 203424918U, // CMOVLE32rr
+ 404751510U, // CMOVLE64rm
+ 203424918U, // CMOVLE64rr
+ 75498654U, // CMOVNBE_F
+ 0U, // CMOVNBE_Fp32
+ 0U, // CMOVNBE_Fp64
+ 0U, // CMOVNBE_Fp80
+ 75498664U, // CMOVNB_F
+ 0U, // CMOVNB_Fp32
+ 0U, // CMOVNB_Fp64
+ 0U, // CMOVNB_Fp80
+ 270533809U, // CMOVNE16rm
+ 203424945U, // CMOVNE16rr
+ 337642673U, // CMOVNE32rm
+ 203424945U, // CMOVNE32rr
+ 404751537U, // CMOVNE64rm
+ 203424945U, // CMOVNE64rr
+ 75498681U, // CMOVNE_F
+ 0U, // CMOVNE_Fp32
+ 0U, // CMOVNE_Fp64
+ 0U, // CMOVNE_Fp80
+ 270533826U, // CMOVNO16rm
+ 203424962U, // CMOVNO16rr
+ 337642690U, // CMOVNO32rm
+ 203424962U, // CMOVNO32rr
+ 404751554U, // CMOVNO64rm
+ 203424962U, // CMOVNO64rr
+ 270533834U, // CMOVNP16rm
+ 203424970U, // CMOVNP16rr
+ 337642698U, // CMOVNP32rm
+ 203424970U, // CMOVNP32rr
+ 404751562U, // CMOVNP64rm
+ 203424970U, // CMOVNP64rr
+ 75498706U, // CMOVNP_F
+ 0U, // CMOVNP_Fp32
+ 0U, // CMOVNP_Fp64
+ 0U, // CMOVNP_Fp80
+ 270533851U, // CMOVNS16rm
+ 203424987U, // CMOVNS16rr
+ 337642715U, // CMOVNS32rm
+ 203424987U, // CMOVNS32rr
+ 404751579U, // CMOVNS64rm
+ 203424987U, // CMOVNS64rr
+ 270533859U, // CMOVO16rm
+ 203424995U, // CMOVO16rr
+ 337642723U, // CMOVO32rm
+ 203424995U, // CMOVO32rr
+ 404751587U, // CMOVO64rm
+ 203424995U, // CMOVO64rr
+ 270533866U, // CMOVP16rm
+ 203425002U, // CMOVP16rr
+ 337642730U, // CMOVP32rm
+ 203425002U, // CMOVP32rr
+ 404751594U, // CMOVP64rm
+ 203425002U, // CMOVP64rr
+ 75498737U, // CMOVP_F
+ 0U, // CMOVP_Fp32
+ 0U, // CMOVP_Fp64
+ 0U, // CMOVP_Fp80
+ 270533882U, // CMOVS16rm
+ 203425018U, // CMOVS16rr
+ 337642746U, // CMOVS32rm
+ 203425018U, // CMOVS32rr
+ 404751610U, // CMOVS64rm
+ 203425018U, // CMOVS64rr
+ 1281U, // CMOV_FR32
+ 1300U, // CMOV_FR64
+ 1319U, // CMOV_GR8
+ 1337U, // CMOV_V1I64
+ 1357U, // CMOV_V2F64
+ 1377U, // CMOV_V2I64
+ 1397U, // CMOV_V4F32
+ 67110281U, // CMP16i16
+ 135267721U, // CMP16mi
+ 135267721U, // CMP16mi8
+ 135267721U, // CMP16mr
+ 1281361289U, // CMP16mrmrr
+ 1281361289U, // CMP16ri
+ 1281361289U, // CMP16ri8
+ 1207960969U, // CMP16rm
+ 1281361289U, // CMP16rr
+ 70256015U, // CMP32i32
+ 135333263U, // CMP32mi
+ 135333263U, // CMP32mi8
+ 135333263U, // CMP32mr
+ 1281361295U, // CMP32mrmrr
+ 1281361295U, // CMP32ri
+ 1281361295U, // CMP32ri8
+ 1342178703U, // CMP32rm
+ 1281361295U, // CMP32rr
+ 71304597U, // CMP64i32
+ 135398805U, // CMP64mi32
+ 135398805U, // CMP64mi8
+ 135398805U, // CMP64mr
+ 1281361301U, // CMP64mrmrr
+ 1281361301U, // CMP64ri32
+ 1281361301U, // CMP64ri8
+ 1409287573U, // CMP64rm
+ 1281361301U, // CMP64rr
+ 72353179U, // CMP8i8
+ 135464347U, // CMP8mi
+ 135464347U, // CMP8mr
+ 1281361307U, // CMP8mrmrr
+ 1281361307U, // CMP8ri
+ 1684014491U, // CMP8rm
+ 1281361307U, // CMP8rr
+ 1754531233U, // CMPPDrmi
+ 1821705633U, // CMPPDrri
+ 1755579809U, // CMPPSrmi
+ 1822754209U, // CMPPSrri
+ 1445U, // CMPS16
+ 1451U, // CMPS32
+ 1457U, // CMPS64
+ 1463U, // CMPS8
+ 1756759457U, // CMPSDrm
+ 1823802785U, // CMPSDrr
+ 1757873569U, // CMPSSrm
+ 1824851361U, // CMPSSrr
+ 1879049661U, // COMISDrm
+ 1281361341U, // COMISDrr
+ 1477U, // COS_F
+ 0U, // COS_Fp32
+ 0U, // COS_Fp64
+ 0U, // COS_Fp80
+ 1482U, // CQO
+ 282592719U, // CRC32m16
+ 349701583U, // CRC32m32
+ 483919311U, // CRC32m8
+ 215483855U, // CRC32r16
+ 215483855U, // CRC32r32
+ 215483855U, // CRC32r8
+ 416810447U, // CRC64m64
+ 215483855U, // CRC64r64
+ 1879049687U, // CVTDQ2PDrm
+ 1281361367U, // CVTDQ2PDrr
+ 1879049697U, // CVTDQ2PSrm
+ 1281361377U, // CVTDQ2PSrr
+ 1879049707U, // CVTPD2DQrm
+ 1281361387U, // CVTPD2DQrr
+ 1879049717U, // CVTPS2DQrm
+ 1281361397U, // CVTPS2DQrr
+ 1946158591U, // CVTSD2SSrm
+ 1281361407U, // CVTSD2SSrr
+ 1409287689U, // CVTSI2SD64rm
+ 1281361417U, // CVTSI2SD64rr
+ 1342178836U, // CVTSI2SDrm
+ 1281361428U, // CVTSI2SDrr
+ 1409287710U, // CVTSI2SS64rm
+ 1281361438U, // CVTSI2SS64rr
+ 1342178857U, // CVTSI2SSrm
+ 1281361449U, // CVTSI2SSrr
+ 2013267507U, // CVTSS2SDrm
+ 1281361459U, // CVTSS2SDrr
+ 1946158653U, // CVTTSD2SI64rm
+ 1281361469U, // CVTTSD2SI64rr
+ 1946158665U, // CVTTSD2SIrm
+ 1281361481U, // CVTTSD2SIrr
+ 2013267540U, // CVTTSS2SI64rm
+ 1281361492U, // CVTTSS2SI64rr
+ 2013267552U, // CVTTSS2SIrm
+ 1281361504U, // CVTTSS2SIrr
+ 1643U, // CWD
+ 1648U, // CWDE
+ 872416885U, // DEC16m
+ 73401973U, // DEC16r
+ 945817211U, // DEC32m
+ 73401979U, // DEC32r
+ 872416885U, // DEC64_16m
+ 73401973U, // DEC64_16r
+ 945817211U, // DEC64_32m
+ 73401979U, // DEC64_32r
+ 1476396673U, // DEC64m
+ 73401985U, // DEC64r
+ 1610614407U, // DEC8m
+ 73401991U, // DEC8r
+ 872416909U, // DIV16m
+ 73401997U, // DIV16r
+ 945817235U, // DIV32m
+ 73402003U, // DIV32r
+ 1476396697U, // DIV64m
+ 73402009U, // DIV64r
+ 1610614431U, // DIV8m
+ 73402015U, // DIV8r
+ 536872613U, // DIVPDrm
+ 203425445U, // DIVPDrr
+ 536872620U, // DIVPSrm
+ 203425452U, // DIVPSrr
+ 738199219U, // DIVR_F32m
+ 805308091U, // DIVR_F64m
+ 872416963U, // DIVR_FI16m
+ 945817292U, // DIVR_FI32m
+ 73402069U, // DIVR_FPrST0
+ 73402076U, // DIVR_FST0r
+ 0U, // DIVR_Fp32m
+ 0U, // DIVR_Fp64m
+ 0U, // DIVR_Fp64m32
+ 0U, // DIVR_Fp80m32
+ 0U, // DIVR_Fp80m64
+ 0U, // DIVR_FpI16m32
+ 0U, // DIVR_FpI16m64
+ 0U, // DIVR_FpI16m80
+ 0U, // DIVR_FpI32m32
+ 0U, // DIVR_FpI32m64
+ 0U, // DIVR_FpI32m80
+ 73402083U, // DIVR_FrST0
+ 603981553U, // DIVSDrm
+ 603981553U, // DIVSDrm_Int
+ 203425521U, // DIVSDrr
+ 203425521U, // DIVSDrr_Int
+ 671090424U, // DIVSSrm
+ 671090424U, // DIVSSrm_Int
+ 203425528U, // DIVSSrr
+ 203425528U, // DIVSSrr_Int
+ 738199295U, // DIV_F32m
+ 805308166U, // DIV_F64m
+ 872417037U, // DIV_FI16m
+ 945817365U, // DIV_FI32m
+ 73402141U, // DIV_FPrST0
+ 73402149U, // DIV_FST0r
+ 0U, // DIV_Fp32
+ 0U, // DIV_Fp32m
+ 0U, // DIV_Fp64
+ 0U, // DIV_Fp64m
+ 0U, // DIV_Fp64m32
+ 0U, // DIV_Fp80
+ 0U, // DIV_Fp80m32
+ 0U, // DIV_Fp80m64
+ 0U, // DIV_FpI16m32
+ 0U, // DIV_FpI16m64
+ 0U, // DIV_FpI16m80
+ 0U, // DIV_FpI32m32
+ 0U, // DIV_FpI32m64
+ 0U, // DIV_FpI32m80
+ 73402155U, // DIV_FrST0
+ 1013974842U, // DPPDrmi
+ 1073743674U, // DPPDrri
+ 1013974848U, // DPPSrmi
+ 1073743680U, // DPPSrri
+ 73402182U, // EH_RETURN
+ 73402182U, // EH_RETURN64
+ 68749149U, // ENTER
+ 2095712100U, // EXTRACTPSmr
+ 215680868U, // EXTRACTPSrr
+ 68749167U, // FARCALL16i
+ 2147485559U, // FARCALL16m
+ 68749184U, // FARCALL32i
+ 2147485576U, // FARCALL32m
+ 2147485585U, // FARCALL64
+ 68749210U, // FARJMP16i
+ 2147485601U, // FARJMP16m
+ 68749225U, // FARJMP32i
+ 2147485616U, // FARJMP32m
+ 2147485624U, // FARJMP64
+ 738199488U, // FBLDm
+ 738199494U, // FBSTPm
+ 738199501U, // FCOM32m
+ 805308365U, // FCOM64m
+ 738199507U, // FCOMP32m
+ 805308371U, // FCOMP64m
+ 872417242U, // FICOM16m
+ 945817570U, // FICOM32m
+ 872417258U, // FICOMP16m
+ 945817587U, // FICOMP32m
+ 945817596U, // FISTTP32m
+ 872417285U, // FLDCW16m
+ 738199564U, // FLDENVm
+ 872417300U, // FNSTCW16m
+ 2076U, // FNSTSW8r
+ 2083U, // FP32_TO_INT16_IN_MEM
+ 2114U, // FP32_TO_INT32_IN_MEM
+ 2145U, // FP32_TO_INT64_IN_MEM
+ 2176U, // FP64_TO_INT16_IN_MEM
+ 2207U, // FP64_TO_INT32_IN_MEM
+ 2238U, // FP64_TO_INT64_IN_MEM
+ 2269U, // FP80_TO_INT16_IN_MEM
+ 2300U, // FP80_TO_INT32_IN_MEM
+ 2331U, // FP80_TO_INT64_IN_MEM
+ 2362U, // FP_REG_KILL
+ 738199880U, // FRSTORm
+ 738199888U, // FSAVEm
+ 738199895U, // FSTENVm
+ 738199903U, // FSTSWm
+ 1342179686U, // FS_MOV32rm
+ 0U, // FpGET_ST0_32
+ 0U, // FpGET_ST0_64
+ 0U, // FpGET_ST0_80
+ 0U, // FpGET_ST1_32
+ 0U, // FpGET_ST1_64
+ 0U, // FpGET_ST1_80
+ 0U, // FpSET_ST0_32
+ 0U, // FpSET_ST0_64
+ 0U, // FpSET_ST0_80
+ 0U, // FpSET_ST1_32
+ 0U, // FpSET_ST1_64
+ 0U, // FpSET_ST1_80
+ 536871129U, // FsANDNPDrm
+ 203423961U, // FsANDNPDrr
+ 536871137U, // FsANDNPSrm
+ 203423969U, // FsANDNPSrr
+ 536871145U, // FsANDPDrm
+ 203423977U, // FsANDPDrr
+ 536871152U, // FsANDPSrm
+ 203423984U, // FsANDPSrr
+ 68946288U, // FsFLD0SD
+ 68946288U, // FsFLD0SS
+ 1879050614U, // FsMOVAPDrm
+ 1281362294U, // FsMOVAPDrr
+ 1879050622U, // FsMOVAPSrm
+ 1281362302U, // FsMOVAPSrr
+ 536873350U, // FsORPDrm
+ 203426182U, // FsORPDrr
+ 536873356U, // FsORPSrm
+ 203426188U, // FsORPSrr
+ 536873362U, // FsXORPDrm
+ 203426194U, // FsXORPDrr
+ 536873369U, // FsXORPSrm
+ 203426201U, // FsXORPSrr
+ 1342179744U, // GS_MOV32rm
+ 536873386U, // HADDPDrm
+ 203426218U, // HADDPDrr
+ 536873394U, // HADDPSrm
+ 203426226U, // HADDPSrr
+ 536873402U, // HSUBPDrm
+ 203426234U, // HSUBPDrr
+ 536873410U, // HSUBPSrm
+ 203426242U, // HSUBPSrr
+ 872417738U, // IDIV16m
+ 73402826U, // IDIV16r
+ 945818065U, // IDIV32m
+ 73402833U, // IDIV32r
+ 1476397528U, // IDIV64m
+ 73402840U, // IDIV64r
+ 1610615263U, // IDIV8m
+ 73402847U, // IDIV8r
+ 872417766U, // ILD_F16m
+ 945818093U, // ILD_F32m
+ 1476397556U, // ILD_F64m
+ 0U, // ILD_Fp16m32
+ 0U, // ILD_Fp16m64
+ 0U, // ILD_Fp16m80
+ 0U, // ILD_Fp32m32
+ 0U, // ILD_Fp32m64
+ 0U, // ILD_Fp32m80
+ 0U, // ILD_Fp64m32
+ 0U, // ILD_Fp64m64
+ 0U, // ILD_Fp64m80
+ 872417788U, // IMUL16m
+ 73402876U, // IMUL16r
+ 270535164U, // IMUL16rm
+ 2096826876U, // IMUL16rmi
+ 2096826876U, // IMUL16rmi8
+ 203426300U, // IMUL16rr
+ 215681532U, // IMUL16rri
+ 215681532U, // IMUL16rri8
+ 945818115U, // IMUL32m
+ 73402883U, // IMUL32r
+ 337644035U, // IMUL32rm
+ 2097875459U, // IMUL32rmi
+ 2097875459U, // IMUL32rmi8
+ 203426307U, // IMUL32rr
+ 215681539U, // IMUL32rri
+ 215681539U, // IMUL32rri8
+ 1476397578U, // IMUL64m
+ 73402890U, // IMUL64r
+ 404752906U, // IMUL64rm
+ 2098924042U, // IMUL64rmi32
+ 2098924042U, // IMUL64rmi8
+ 203426314U, // IMUL64rr
+ 215681546U, // IMUL64rri32
+ 215681546U, // IMUL64rri8
+ 1610615313U, // IMUL8m
+ 73402897U, // IMUL8r
+ 67111448U, // IN16ri
+ 2589U, // IN16rr
+ 70257194U, // IN32ri
+ 2607U, // IN32rr
+ 72354365U, // IN8ri
+ 2626U, // IN8rr
+ 872417871U, // INC16m
+ 73402959U, // INC16r
+ 945818197U, // INC32m
+ 73402965U, // INC32r
+ 872417871U, // INC64_16m
+ 73402959U, // INC64_16r
+ 945818197U, // INC64_32m
+ 73402965U, // INC64_32r
+ 1476397659U, // INC64m
+ 73402971U, // INC64r
+ 1610615393U, // INC8m
+ 73402977U, // INC8r
+ 1025509991U, // INSERTPSrm
+ 1073744487U, // INSERTPSrr
+ 73402993U, // INT
+ 2678U, // INT3
+ 872417916U, // ISTT_FP16m
+ 945817596U, // ISTT_FP32m
+ 1476397701U, // ISTT_FP64m
+ 0U, // ISTT_Fp16m32
+ 0U, // ISTT_Fp16m64
+ 0U, // ISTT_Fp16m80
+ 0U, // ISTT_Fp32m32
+ 0U, // ISTT_Fp32m64
+ 0U, // ISTT_Fp32m80
+ 0U, // ISTT_Fp64m32
+ 0U, // ISTT_Fp64m64
+ 0U, // ISTT_Fp64m80
+ 872417935U, // IST_F16m
+ 945818262U, // IST_F32m
+ 872417949U, // IST_FP16m
+ 945818277U, // IST_FP32m
+ 1476397741U, // IST_FP64m
+ 0U, // IST_Fp16m32
+ 0U, // IST_Fp16m64
+ 0U, // IST_Fp16m80
+ 0U, // IST_Fp32m32
+ 0U, // IST_Fp32m64
+ 0U, // IST_Fp32m80
+ 0U, // IST_Fp64m32
+ 0U, // IST_Fp64m64
+ 0U, // IST_Fp64m80
+ 1756759457U, // Int_CMPSDrm
+ 1823802785U, // Int_CMPSDrr
+ 1757873569U, // Int_CMPSSrm
+ 1824851361U, // Int_CMPSSrr
+ 1879049661U, // Int_COMISDrm
+ 1281361341U, // Int_COMISDrr
+ 1879050934U, // Int_COMISSrm
+ 1281362614U, // Int_COMISSrr
+ 1409287639U, // Int_CVTDQ2PDrm
+ 1281361367U, // Int_CVTDQ2PDrr
+ 2214594017U, // Int_CVTDQ2PSrm
+ 1281361377U, // Int_CVTDQ2PSrr
+ 1879049707U, // Int_CVTPD2DQrm
+ 1281361387U, // Int_CVTPD2DQrr
+ 1879050942U, // Int_CVTPD2PIrm
+ 1281362622U, // Int_CVTPD2PIrr
+ 1879050952U, // Int_CVTPD2PSrm
+ 1281362632U, // Int_CVTPD2PSrr
+ 1409288914U, // Int_CVTPI2PDrm
+ 1281362642U, // Int_CVTPI2PDrr
+ 404753116U, // Int_CVTPI2PSrm
+ 203426524U, // Int_CVTPI2PSrr
+ 1879049717U, // Int_CVTPS2DQrm
+ 1281361397U, // Int_CVTPS2DQrr
+ 1946159846U, // Int_CVTPS2PDrm
+ 1281362662U, // Int_CVTPS2PDrr
+ 1946159856U, // Int_CVTPS2PIrm
+ 1281362672U, // Int_CVTPS2PIrr
+ 1879051002U, // Int_CVTSD2SI64rm
+ 1281362682U, // Int_CVTSD2SI64rr
+ 1879051013U, // Int_CVTSD2SIrm
+ 1281362693U, // Int_CVTSD2SIrr
+ 603981311U, // Int_CVTSD2SSrm
+ 203425279U, // Int_CVTSD2SSrr
+ 404751881U, // Int_CVTSI2SD64rm
+ 203425289U, // Int_CVTSI2SD64rr
+ 337643028U, // Int_CVTSI2SDrm
+ 203425300U, // Int_CVTSI2SDrr
+ 404751902U, // Int_CVTSI2SS64rm
+ 203425310U, // Int_CVTSI2SS64rr
+ 337643049U, // Int_CVTSI2SSrm
+ 203425321U, // Int_CVTSI2SSrr
+ 671090227U, // Int_CVTSS2SDrm
+ 203425331U, // Int_CVTSS2SDrr
+ 2013268751U, // Int_CVTSS2SI64rm
+ 1281362703U, // Int_CVTSS2SI64rr
+ 2013268762U, // Int_CVTSS2SIrm
+ 1281362714U, // Int_CVTSS2SIrr
+ 1879051044U, // Int_CVTTPD2DQrm
+ 1281362724U, // Int_CVTTPD2DQrr
+ 1879051055U, // Int_CVTTPD2PIrm
+ 1281362735U, // Int_CVTTPD2PIrr
+ 1879051066U, // Int_CVTTPS2DQrm
+ 1281362746U, // Int_CVTTPS2DQrr
+ 1946159941U, // Int_CVTTPS2PIrm
+ 1281362757U, // Int_CVTTPS2PIrr
+ 1879049789U, // Int_CVTTSD2SI64rm
+ 1281361469U, // Int_CVTTSD2SI64rr
+ 1879049801U, // Int_CVTTSD2SIrm
+ 1281361481U, // Int_CVTTSD2SIrr
+ 2013267540U, // Int_CVTTSS2SI64rm
+ 1281361492U, // Int_CVTTSS2SI64rr
+ 2013267552U, // Int_CVTTSS2SIrm
+ 1281361504U, // Int_CVTTSS2SIrr
+ 1879051088U, // Int_UCOMISDrm
+ 1281362768U, // Int_UCOMISDrr
+ 1879051097U, // Int_UCOMISSrm
+ 1281362777U, // Int_UCOMISSrr
+ 1549798242U, // JA
+ 1549798242U, // JA8
+ 1549798246U, // JAE
+ 1549798246U, // JAE8
+ 1549798251U, // JB
+ 1549798251U, // JB8
+ 1549798255U, // JBE
+ 1549798255U, // JBE8
+ 1549798260U, // JCXZ8
+ 1549798266U, // JE
+ 1549798266U, // JE8
+ 1549798270U, // JG
+ 1549798270U, // JG8
+ 1549798274U, // JGE
+ 1549798274U, // JGE8
+ 1549798279U, // JL
+ 1549798279U, // JL8
+ 1549798283U, // JLE
+ 1549798283U, // JLE8
+ 1549798288U, // JMP
+ 945818517U, // JMP32m
+ 73403285U, // JMP32r
+ 1476397980U, // JMP64m
+ 73403292U, // JMP64r
+ 1549798288U, // JMP8
+ 1549798307U, // JNE
+ 1549798307U, // JNE8
+ 1549798312U, // JNO
+ 1549798312U, // JNO8
+ 1549798317U, // JNP
+ 1549798317U, // JNP8
+ 1549798322U, // JNS
+ 1549798322U, // JNS8
+ 1549798327U, // JO
+ 1549798327U, // JO8
+ 1549798331U, // JP
+ 1549798331U, // JP8
+ 1549798335U, // JS
+ 1549798335U, // JS8
+ 3011U, // LAHF
+ 1207962568U, // LAR16rm
+ 1281362888U, // LAR16rr
+ 1207962574U, // LAR32rm
+ 1281362894U, // LAR32rr
+ 1207962580U, // LAR64rm
+ 1281362900U, // LAR64rr
+ 135269338U, // LCMPXCHG16
+ 135334890U, // LCMPXCHG32
+ 154143738U, // LCMPXCHG64
+ 135465994U, // LCMPXCHG8
+ 945818650U, // LCMPXCHG8B
+ 2214595627U, // LDDQUrm
+ 945818674U, // LDMXCSR
+ 3131U, // LD_F0
+ 3136U, // LD_F1
+ 738200645U, // LD_F32m
+ 805309515U, // LD_F64m
+ 2281704529U, // LD_F80m
+ 0U, // LD_Fp032
+ 0U, // LD_Fp064
+ 0U, // LD_Fp080
+ 0U, // LD_Fp132
+ 0U, // LD_Fp164
+ 0U, // LD_Fp180
+ 0U, // LD_Fp32m
+ 0U, // LD_Fp32m64
+ 0U, // LD_Fp32m80
+ 0U, // LD_Fp64m
+ 0U, // LD_Fp64m80
+ 0U, // LD_Fp80m
+ 73403479U, // LD_Frr
+ 2348813404U, // LEA16r
+ 2348813410U, // LEA32r
+ 2415922274U, // LEA64_32r
+ 2483031144U, // LEA64r
+ 3182U, // LEAVE
+ 3182U, // LEAVE64
+ 3188U, // LFENCE
+ 135269499U, // LOCK_ADD16mi
+ 135269499U, // LOCK_ADD16mi8
+ 135269499U, // LOCK_ADD16mr
+ 135335047U, // LOCK_ADD32mi
+ 135335047U, // LOCK_ADD32mi8
+ 135335047U, // LOCK_ADD32mr
+ 135400595U, // LOCK_ADD64mi32
+ 135400595U, // LOCK_ADD64mi8
+ 135400595U, // LOCK_ADD64mr
+ 135466143U, // LOCK_ADD8mi
+ 135466143U, // LOCK_ADD8mr
+ 872418475U, // LOCK_DEC16m
+ 945818807U, // LOCK_DEC32m
+ 1476398275U, // LOCK_DEC64m
+ 1610616015U, // LOCK_DEC8m
+ 872418523U, // LOCK_INC16m
+ 945818855U, // LOCK_INC32m
+ 1476398323U, // LOCK_INC64m
+ 1610616063U, // LOCK_INC8m
+ 135269643U, // LOCK_SUB16mi
+ 135269643U, // LOCK_SUB16mi8
+ 135269643U, // LOCK_SUB16mr
+ 135335191U, // LOCK_SUB32mi
+ 135335191U, // LOCK_SUB32mi8
+ 135335191U, // LOCK_SUB32mr
+ 135400739U, // LOCK_SUB64mi32
+ 135400739U, // LOCK_SUB64mi8
+ 135400739U, // LOCK_SUB64mr
+ 135466287U, // LOCK_SUB8mi
+ 135466287U, // LOCK_SUB8mr
+ 3387U, // LODSB
+ 3393U, // LODSD
+ 3399U, // LODSQ
+ 3405U, // LODSW
+ 1549798739U, // LOOP
+ 1549798745U, // LOOPE
+ 1549798752U, // LOOPNE
+ 3432U, // LRET
+ 73403757U, // LRETI
+ 2096631155U, // LXADD16
+ 2097679744U, // LXADD32
+ 2098728333U, // LXADD64
+ 2101349785U, // LXADD8
+ 1281363366U, // MASKMOVDQU
+ 1281363366U, // MASKMOVDQU64
+ 536874418U, // MAXPDrm
+ 536874418U, // MAXPDrm_Int
+ 203427250U, // MAXPDrr
+ 203427250U, // MAXPDrr_Int
+ 536874425U, // MAXPSrm
+ 536874425U, // MAXPSrm_Int
+ 203427257U, // MAXPSrr
+ 203427257U, // MAXPSrr_Int
+ 603983296U, // MAXSDrm
+ 603983296U, // MAXSDrm_Int
+ 203427264U, // MAXSDrr
+ 203427264U, // MAXSDrr_Int
+ 671092167U, // MAXSSrm
+ 671092167U, // MAXSSrm_Int
+ 203427271U, // MAXSSrr
+ 203427271U, // MAXSSrr_Int
+ 3534U, // MFENCE
+ 536874453U, // MINPDrm
+ 536874453U, // MINPDrm_Int
+ 203427285U, // MINPDrr
+ 203427285U, // MINPDrr_Int
+ 536874460U, // MINPSrm
+ 536874460U, // MINPSrm_Int
+ 203427292U, // MINPSrr
+ 203427292U, // MINPSrr_Int
+ 603983331U, // MINSDrm
+ 603983331U, // MINSDrm_Int
+ 203427299U, // MINSDrr
+ 203427299U, // MINSDrr_Int
+ 671092202U, // MINSSrm
+ 671092202U, // MINSSrm_Int
+ 203427306U, // MINSSrr
+ 203427306U, // MINSSrr_Int
+ 1879050942U, // MMX_CVTPD2PIrm
+ 1281362622U, // MMX_CVTPD2PIrr
+ 1409288914U, // MMX_CVTPI2PDrm
+ 1281362642U, // MMX_CVTPI2PDrr
+ 1409288924U, // MMX_CVTPI2PSrm
+ 1281362652U, // MMX_CVTPI2PSrr
+ 1946159856U, // MMX_CVTPS2PIrm
+ 1281362672U, // MMX_CVTPS2PIrr
+ 1879051055U, // MMX_CVTTPD2PIrm
+ 1281362735U, // MMX_CVTTPD2PIrr
+ 1946159941U, // MMX_CVTTPS2PIrm
+ 1281362757U, // MMX_CVTTPS2PIrr
+ 3569U, // MMX_EMMS
+ 3574U, // MMX_FEMMS
+ 1281363452U, // MMX_MASKMOVQ
+ 1281363452U, // MMX_MASKMOVQ64
+ 1281363462U, // MMX_MOVD64from64rr
+ 135335430U, // MMX_MOVD64mr
+ 1342180870U, // MMX_MOVD64rm
+ 1281363462U, // MMX_MOVD64rr
+ 1281363462U, // MMX_MOVD64rrv164
+ 1281363462U, // MMX_MOVD64to64rr
+ 1281363468U, // MMX_MOVDQ2Qrr
+ 135400981U, // MMX_MOVNTQmr
+ 1281363485U, // MMX_MOVQ2DQrr
+ 1281363485U, // MMX_MOVQ2FR64rr
+ 135400998U, // MMX_MOVQ64mr
+ 1409289766U, // MMX_MOVQ64rm
+ 1281363494U, // MMX_MOVQ64rr
+ 1342180870U, // MMX_MOVZDI2PDIrm
+ 1281363462U, // MMX_MOVZDI2PDIrr
+ 404753964U, // MMX_PACKSSDWrm
+ 203427372U, // MMX_PACKSSDWrr
+ 404753974U, // MMX_PACKSSWBrm
+ 203427382U, // MMX_PACKSSWBrr
+ 404753984U, // MMX_PACKUSWBrm
+ 203427392U, // MMX_PACKUSWBrr
+ 404753994U, // MMX_PADDBrm
+ 203427402U, // MMX_PADDBrr
+ 404754001U, // MMX_PADDDrm
+ 203427409U, // MMX_PADDDrr
+ 404754008U, // MMX_PADDQrm
+ 203427416U, // MMX_PADDQrr
+ 404754015U, // MMX_PADDSBrm
+ 203427423U, // MMX_PADDSBrr
+ 404754023U, // MMX_PADDSWrm
+ 203427431U, // MMX_PADDSWrr
+ 404754031U, // MMX_PADDUSBrm
+ 203427439U, // MMX_PADDUSBrr
+ 404754040U, // MMX_PADDUSWrm
+ 203427448U, // MMX_PADDUSWrr
+ 404754049U, // MMX_PADDWrm
+ 203427457U, // MMX_PADDWrr
+ 404754056U, // MMX_PANDNrm
+ 203427464U, // MMX_PANDNrr
+ 404754063U, // MMX_PANDrm
+ 203427471U, // MMX_PANDrr
+ 404754069U, // MMX_PAVGBrm
+ 203427477U, // MMX_PAVGBrr
+ 404754076U, // MMX_PAVGWrm
+ 203427484U, // MMX_PAVGWrr
+ 404754083U, // MMX_PCMPEQBrm
+ 203427491U, // MMX_PCMPEQBrr
+ 404754092U, // MMX_PCMPEQDrm
+ 203427500U, // MMX_PCMPEQDrr
+ 404754101U, // MMX_PCMPEQWrm
+ 203427509U, // MMX_PCMPEQWrr
+ 404754110U, // MMX_PCMPGTBrm
+ 203427518U, // MMX_PCMPGTBrr
+ 404754119U, // MMX_PCMPGTDrm
+ 203427527U, // MMX_PCMPGTDrr
+ 404754128U, // MMX_PCMPGTWrm
+ 203427536U, // MMX_PCMPGTWrr
+ 215682777U, // MMX_PEXTRWri
+ 1028656865U, // MMX_PINSRWrmi
+ 1073745633U, // MMX_PINSRWrri
+ 404754153U, // MMX_PMADDWDrm
+ 203427561U, // MMX_PMADDWDrr
+ 404754162U, // MMX_PMAXSWrm
+ 203427570U, // MMX_PMAXSWrr
+ 404754170U, // MMX_PMAXUBrm
+ 203427578U, // MMX_PMAXUBrr
+ 404754178U, // MMX_PMINSWrm
+ 203427586U, // MMX_PMINSWrr
+ 404754186U, // MMX_PMINUBrm
+ 203427594U, // MMX_PMINUBrr
+ 1281363730U, // MMX_PMOVMSKBrr
+ 404754204U, // MMX_PMULHUWrm
+ 203427612U, // MMX_PMULHUWrr
+ 404754213U, // MMX_PMULHWrm
+ 203427621U, // MMX_PMULHWrr
+ 404754221U, // MMX_PMULLWrm
+ 203427629U, // MMX_PMULLWrr
+ 404754229U, // MMX_PMULUDQrm
+ 203427637U, // MMX_PMULUDQrr
+ 404754238U, // MMX_PORrm
+ 203427646U, // MMX_PORrr
+ 404754243U, // MMX_PSADBWrm
+ 203427651U, // MMX_PSADBWrr
+ 2098925387U, // MMX_PSHUFWmi
+ 215682891U, // MMX_PSHUFWri
+ 203427667U, // MMX_PSLLDri
+ 404754259U, // MMX_PSLLDrm
+ 203427667U, // MMX_PSLLDrr
+ 203427674U, // MMX_PSLLQri
+ 404754266U, // MMX_PSLLQrm
+ 203427674U, // MMX_PSLLQrr
+ 203427681U, // MMX_PSLLWri
+ 404754273U, // MMX_PSLLWrm
+ 203427681U, // MMX_PSLLWrr
+ 203427688U, // MMX_PSRADri
+ 404754280U, // MMX_PSRADrm
+ 203427688U, // MMX_PSRADrr
+ 203427695U, // MMX_PSRAWri
+ 404754287U, // MMX_PSRAWrm
+ 203427695U, // MMX_PSRAWrr
+ 203427702U, // MMX_PSRLDri
+ 404754294U, // MMX_PSRLDrm
+ 203427702U, // MMX_PSRLDrr
+ 203427709U, // MMX_PSRLQri
+ 404754301U, // MMX_PSRLQrm
+ 203427709U, // MMX_PSRLQrr
+ 203427716U, // MMX_PSRLWri
+ 404754308U, // MMX_PSRLWrm
+ 203427716U, // MMX_PSRLWrr
+ 404754315U, // MMX_PSUBBrm
+ 203427723U, // MMX_PSUBBrr
+ 404754322U, // MMX_PSUBDrm
+ 203427730U, // MMX_PSUBDrr
+ 404754329U, // MMX_PSUBQrm
+ 203427737U, // MMX_PSUBQrr
+ 404754336U, // MMX_PSUBSBrm
+ 203427744U, // MMX_PSUBSBrr
+ 404754344U, // MMX_PSUBSWrm
+ 203427752U, // MMX_PSUBSWrr
+ 404754352U, // MMX_PSUBUSBrm
+ 203427760U, // MMX_PSUBUSBrr
+ 404754361U, // MMX_PSUBUSWrm
+ 203427769U, // MMX_PSUBUSWrr
+ 404754370U, // MMX_PSUBWrm
+ 203427778U, // MMX_PSUBWrr
+ 404754377U, // MMX_PUNPCKHBWrm
+ 203427785U, // MMX_PUNPCKHBWrr
+ 404754388U, // MMX_PUNPCKHDQrm
+ 203427796U, // MMX_PUNPCKHDQrr
+ 404754399U, // MMX_PUNPCKHWDrm
+ 203427807U, // MMX_PUNPCKHWDrr
+ 404754410U, // MMX_PUNPCKLBWrm
+ 203427818U, // MMX_PUNPCKLBWrr
+ 404754421U, // MMX_PUNPCKLDQrm
+ 203427829U, // MMX_PUNPCKLDQrr
+ 404754432U, // MMX_PUNPCKLWDrm
+ 203427840U, // MMX_PUNPCKLWDrr
+ 404752752U, // MMX_PXORrm
+ 203426160U, // MMX_PXORrr
+ 68946288U, // MMX_V_SET0
+ 68947628U, // MMX_V_SETALLONES
+ 4107U, // MONITOR
+ 73404435U, // MOV16ao16
+ 135270430U, // MOV16mi
+ 135270430U, // MOV16mr
+ 135270430U, // MOV16ms
+ 67112990U, // MOV16o16a
+ 0U, // MOV16r0
+ 1281363998U, // MOV16ri
+ 1207963678U, // MOV16rm
+ 1281363998U, // MOV16rr
+ 1281363998U, // MOV16rs
+ 1207963678U, // MOV16sm
+ 1281363998U, // MOV16sr
+ 73404452U, // MOV32ao32
+ 135335984U, // MOV32mi
+ 135335984U, // MOV32mr
+ 70258736U, // MOV32o32a
+ 68948022U, // MOV32r0
+ 1281364016U, // MOV32ri
+ 1342181424U, // MOV32rm
+ 1281364016U, // MOV32rr
+ 1409290300U, // MOV64FSrm
+ 1409290310U, // MOV64GSrm
+ 73404496U, // MOV64ao32
+ 73404496U, // MOV64ao8
+ 135400998U, // MOV64mi32
+ 135400998U, // MOV64mr
+ 135401502U, // MOV64ms
+ 71306790U, // MOV64o32a
+ 71306790U, // MOV64o8a
+ 1281364060U, // MOV64ri
+ 1281363494U, // MOV64ri32
+ 0U, // MOV64ri64i32
+ 1409289766U, // MOV64rm
+ 1281363494U, // MOV64rr
+ 1281363998U, // MOV64rs
+ 1409290270U, // MOV64sm
+ 1281363998U, // MOV64sr
+ 1281363462U, // MOV64toPQIrr
+ 1409289766U, // MOV64toSDrm
+ 1281363462U, // MOV64toSDrr
+ 73404517U, // MOV8ao8
+ 135467120U, // MOV8mi
+ 135467120U, // MOV8mr
+ 135483504U, // MOV8mr_NOREX
+ 72355952U, // MOV8o8a
+ 68948086U, // MOV8r0
+ 1281364080U, // MOV8ri
+ 1684017264U, // MOV8rm
+ 1700794480U, // MOV8rm_NOREX
+ 1281364080U, // MOV8rr
+ 1298141296U, // MOV8rr_NOREX
+ 136120694U, // MOVAPDmr
+ 1879050614U, // MOVAPDrm
+ 1281362294U, // MOVAPDrr
+ 136120702U, // MOVAPSmr
+ 1879050622U, // MOVAPSrm
+ 1281362302U, // MOVAPSrr
+ 1946161276U, // MOVDDUPrm
+ 1281364092U, // MOVDDUPrr
+ 1342180870U, // MOVDI2PDIrm
+ 1281363462U, // MOVDI2PDIrr
+ 1342180870U, // MOVDI2SSrm
+ 1281363462U, // MOVDI2SSrr
+ 136188037U, // MOVDQAmr
+ 2214596741U, // MOVDQArm
+ 1281364101U, // MOVDQArr
+ 136188045U, // MOVDQUmr
+ 136188045U, // MOVDQUmr_Int
+ 2214596749U, // MOVDQUrm
+ 2214596749U, // MOVDQUrm_Int
+ 203427989U, // MOVHLPSrr
+ 136253598U, // MOVHPDmr
+ 603984030U, // MOVHPDrm
+ 136253606U, // MOVHPSmr
+ 603984038U, // MOVHPSrm
+ 203428014U, // MOVLHPSrr
+ 136253623U, // MOVLPDmr
+ 603984055U, // MOVLPDrm
+ 203428031U, // MOVLPDrr
+ 136253638U, // MOVLPSmr
+ 603984070U, // MOVLPSrm
+ 203428046U, // MOVLPSrr
+ 135400998U, // MOVLQ128mr
+ 203428031U, // MOVLSD2PDrr
+ 203428046U, // MOVLSS2PSrr
+ 1281364181U, // MOVMSKPDrr
+ 1281364191U, // MOVMSKPSrr
+ 2214596841U, // MOVNTDQArm
+ 136122611U, // MOVNTDQmr
+ 135336188U, // MOVNTImr
+ 136188164U, // MOVNTPDmr
+ 136188173U, // MOVNTPSmr
+ 0U, // MOVPC32r
+ 136253631U, // MOVPD2SDmr
+ 1281364159U, // MOVPD2SDrr
+ 135335430U, // MOVPDI2DImr
+ 1281363462U, // MOVPDI2DIrr
+ 135400998U, // MOVPQI2QImr
+ 1281363462U, // MOVPQIto64rr
+ 135925966U, // MOVPS2SSmr
+ 1281364174U, // MOVPS2SSrr
+ 1409289766U, // MOVQI2PQIrm
+ 1946161343U, // MOVSD2PDrm
+ 1281364159U, // MOVSD2PDrr
+ 136253631U, // MOVSDmr
+ 1946161343U, // MOVSDrm
+ 1281364159U, // MOVSDrr
+ 135400998U, // MOVSDto64mr
+ 1281363462U, // MOVSDto64rr
+ 1879052566U, // MOVSHDUPrm
+ 1281364246U, // MOVSHDUPrr
+ 1879052576U, // MOVSLDUPrm
+ 1281364256U, // MOVSLDUPrr
+ 135335430U, // MOVSS2DImr
+ 1281363462U, // MOVSS2DIrr
+ 2013270222U, // MOVSS2PSrm
+ 1281364174U, // MOVSS2PSrr
+ 135925966U, // MOVSSmr
+ 2013270222U, // MOVSSrm
+ 1281364174U, // MOVSSrr
+ 0U, // MOVSX16rm8
+ 0U, // MOVSX16rr8
+ 1207963946U, // MOVSX32rm16
+ 1684017458U, // MOVSX32rm8
+ 1281364266U, // MOVSX32rr16
+ 1281364274U, // MOVSX32rr8
+ 1207963962U, // MOVSX64rm16
+ 1342181698U, // MOVSX64rm32
+ 1684017482U, // MOVSX64rm8
+ 1281364282U, // MOVSX64rr16
+ 1281364290U, // MOVSX64rr32
+ 1281364298U, // MOVSX64rr8
+ 136122706U, // MOVUPDmr
+ 136122706U, // MOVUPDmr_Int
+ 1879052626U, // MOVUPDrm
+ 1879052626U, // MOVUPDrm_Int
+ 1281364306U, // MOVUPDrr
+ 136122714U, // MOVUPSmr
+ 136122714U, // MOVUPSmr_Int
+ 1879052634U, // MOVUPSrm
+ 1879052634U, // MOVUPSrm_Int
+ 1281364314U, // MOVUPSrr
+ 1342180870U, // MOVZDI2PDIrm
+ 1281363462U, // MOVZDI2PDIrr
+ 2214596134U, // MOVZPQILo2PQIrm
+ 1281363494U, // MOVZPQILo2PQIrr
+ 1409289766U, // MOVZQI2PQIrm
+ 1281363462U, // MOVZQI2PQIrr
+ 1946161343U, // MOVZSD2PDrm
+ 2013270222U, // MOVZSS2PSrm
+ 0U, // MOVZX16rm8
+ 0U, // MOVZX16rr8
+ 1700794722U, // MOVZX32_NOREXrm8
+ 1298141538U, // MOVZX32_NOREXrr8
+ 1207964010U, // MOVZX32rm16
+ 1684017506U, // MOVZX32rm8
+ 1281364330U, // MOVZX32rr16
+ 1281364322U, // MOVZX32rr8
+ 0U, // MOVZX64rm16
+ 0U, // MOVZX64rm32
+ 0U, // MOVZX64rm8
+ 0U, // MOVZX64rr16
+ 0U, // MOVZX64rr32
+ 0U, // MOVZX64rr8
+ 0U, // MOV_Fp3232
+ 0U, // MOV_Fp3264
+ 0U, // MOV_Fp3280
+ 0U, // MOV_Fp6432
+ 0U, // MOV_Fp6464
+ 0U, // MOV_Fp6480
+ 0U, // MOV_Fp8032
+ 0U, // MOV_Fp8064
+ 0U, // MOV_Fp8080
+ 1013977458U, // MPSADBWrmi
+ 1073746290U, // MPSADBWrri
+ 872419707U, // MUL16m
+ 73404795U, // MUL16r
+ 945820033U, // MUL32m
+ 73404801U, // MUL32r
+ 1476399495U, // MUL64m
+ 73404807U, // MUL64r
+ 1610617229U, // MUL8m
+ 73404813U, // MUL8r
+ 536875411U, // MULPDrm
+ 203428243U, // MULPDrr
+ 536875418U, // MULPSrm
+ 203428250U, // MULPSrr
+ 603984289U, // MULSDrm
+ 603984289U, // MULSDrm_Int
+ 203428257U, // MULSDrr
+ 203428257U, // MULSDrr_Int
+ 671093160U, // MULSSrm
+ 671093160U, // MULSSrm_Int
+ 203428264U, // MULSSrr
+ 203428264U, // MULSSrr_Int
+ 738202031U, // MUL_F32m
+ 805310902U, // MUL_F64m
+ 872419773U, // MUL_FI16m
+ 945820101U, // MUL_FI32m
+ 73404877U, // MUL_FPrST0
+ 73404884U, // MUL_FST0r
+ 0U, // MUL_Fp32
+ 0U, // MUL_Fp32m
+ 0U, // MUL_Fp64
+ 0U, // MUL_Fp64m
+ 0U, // MUL_Fp64m32
+ 0U, // MUL_Fp80
+ 0U, // MUL_Fp80m32
+ 0U, // MUL_Fp80m64
+ 0U, // MUL_FpI16m32
+ 0U, // MUL_FpI16m64
+ 0U, // MUL_FpI16m80
+ 0U, // MUL_FpI32m32
+ 0U, // MUL_FpI32m64
+ 0U, // MUL_FpI32m80
+ 73404890U, // MUL_FrST0
+ 4584U, // MWAIT
+ 872419822U, // NEG16m
+ 73404910U, // NEG16r
+ 945820148U, // NEG32m
+ 73404916U, // NEG32r
+ 1476399610U, // NEG64m
+ 73404922U, // NEG64r
+ 1610617344U, // NEG8m
+ 73404928U, // NEG8r
+ 4614U, // NOOP
+ 945820170U, // NOOPL
+ 872419856U, // NOT16m
+ 73404944U, // NOT16r
+ 945820182U, // NOT32m
+ 73404950U, // NOT32r
+ 1476399644U, // NOT64m
+ 73404956U, // NOT64r
+ 1610617378U, // NOT8m
+ 73404962U, // NOT8r
+ 67113512U, // OR16i16
+ 135270952U, // OR16mi
+ 135270952U, // OR16mi8
+ 135270952U, // OR16mr
+ 203428392U, // OR16ri
+ 203428392U, // OR16ri8
+ 270537256U, // OR16rm
+ 203428392U, // OR16rr
+ 70259245U, // OR32i32
+ 135336493U, // OR32mi
+ 135336493U, // OR32mi8
+ 135336493U, // OR32mr
+ 203428397U, // OR32ri
+ 203428397U, // OR32ri8
+ 337646125U, // OR32rm
+ 203428397U, // OR32rr
+ 71307826U, // OR64i32
+ 135402034U, // OR64mi32
+ 135402034U, // OR64mi8
+ 135402034U, // OR64mr
+ 203428402U, // OR64ri32
+ 203428402U, // OR64ri8
+ 404754994U, // OR64rm
+ 203428402U, // OR64rr
+ 72356407U, // OR8i8
+ 135467575U, // OR8mi
+ 135467575U, // OR8mr
+ 203428407U, // OR8ri
+ 471863863U, // OR8rm
+ 203428407U, // OR8rr
+ 536873350U, // ORPDrm
+ 203426182U, // ORPDrr
+ 536873356U, // ORPSrm
+ 203426188U, // ORPSrr
+ 73404988U, // OUT16ir
+ 4679U, // OUT16rr
+ 73405013U, // OUT32ir
+ 4705U, // OUT32rr
+ 73405040U, // OUT8ir
+ 4731U, // OUT8rr
+ 2214597257U, // PABSBrm128
+ 1409290889U, // PABSBrm64
+ 1281364617U, // PABSBrr128
+ 1281364617U, // PABSBrr64
+ 2214597264U, // PABSDrm128
+ 1409290896U, // PABSDrm64
+ 1281364624U, // PABSDrr128
+ 1281364624U, // PABSDrr64
+ 2214597271U, // PABSWrm128
+ 1409290903U, // PABSWrm64
+ 1281364631U, // PABSWrr128
+ 1281364631U, // PABSWrr64
+ 1140854316U, // PACKSSDWrm
+ 203427372U, // PACKSSDWrr
+ 1140854326U, // PACKSSWBrm
+ 203427382U, // PACKSSWBrr
+ 1140855454U, // PACKUSDWrm
+ 203428510U, // PACKUSDWrr
+ 1140854336U, // PACKUSWBrm
+ 203427392U, // PACKUSWBrr
+ 1140854346U, // PADDBrm
+ 203427402U, // PADDBrr
+ 1140854353U, // PADDDrm
+ 203427409U, // PADDDrr
+ 1140854360U, // PADDQrm
+ 203427416U, // PADDQrr
+ 1140854367U, // PADDSBrm
+ 203427423U, // PADDSBrr
+ 1140854375U, // PADDSWrm
+ 203427431U, // PADDSWrr
+ 1140854383U, // PADDUSBrm
+ 203427439U, // PADDUSBrr
+ 1140854392U, // PADDUSWrm
+ 203427448U, // PADDUSWrr
+ 1140854401U, // PADDWrm
+ 203427457U, // PADDWrr
+ 1013977768U, // PALIGNR128rm
+ 1073746600U, // PALIGNR128rr
+ 1030754984U, // PALIGNR64rm
+ 1073746600U, // PALIGNR64rr
+ 1140854408U, // PANDNrm
+ 203427464U, // PANDNrr
+ 1140854415U, // PANDrm
+ 203427471U, // PANDrr
+ 1140854421U, // PAVGBrm
+ 203427477U, // PAVGBrr
+ 1140854428U, // PAVGWrm
+ 203427484U, // PAVGWrr
+ 1140855473U, // PBLENDVBrm0
+ 203428529U, // PBLENDVBrr0
+ 1013977794U, // PBLENDWrmi
+ 1073746626U, // PBLENDWrri
+ 1140854435U, // PCMPEQBrm
+ 203427491U, // PCMPEQBrr
+ 1140854444U, // PCMPEQDrm
+ 203427500U, // PCMPEQDrr
+ 1140855499U, // PCMPEQQrm
+ 203428555U, // PCMPEQQrr
+ 1140854453U, // PCMPEQWrm
+ 203427509U, // PCMPEQWrr
+ 2105545428U, // PCMPESTRIArm
+ 215683796U, // PCMPESTRIArr
+ 2105545428U, // PCMPESTRICrm
+ 215683796U, // PCMPESTRICrr
+ 2105545428U, // PCMPESTRIOrm
+ 215683796U, // PCMPESTRIOrr
+ 2105545428U, // PCMPESTRISrm
+ 215683796U, // PCMPESTRISrr
+ 2105545428U, // PCMPESTRIZrm
+ 215683796U, // PCMPESTRIZrr
+ 2105545428U, // PCMPESTRIrm
+ 215683796U, // PCMPESTRIrr
+ 4831U, // PCMPESTRM128MEM
+ 4855U, // PCMPESTRM128REG
+ 2105545487U, // PCMPESTRM128rm
+ 215683855U, // PCMPESTRM128rr
+ 1140854462U, // PCMPGTBrm
+ 203427518U, // PCMPGTBrr
+ 1140854471U, // PCMPGTDrm
+ 203427527U, // PCMPGTDrr
+ 1140855578U, // PCMPGTQrm
+ 203428634U, // PCMPGTQrr
+ 1140854480U, // PCMPGTWrm
+ 203427536U, // PCMPGTWrr
+ 2105545507U, // PCMPISTRIArm
+ 215683875U, // PCMPISTRIArr
+ 2105545507U, // PCMPISTRICrm
+ 215683875U, // PCMPISTRICrr
+ 2105545507U, // PCMPISTRIOrm
+ 215683875U, // PCMPISTRIOrr
+ 2105545507U, // PCMPISTRISrm
+ 215683875U, // PCMPISTRISrr
+ 2105545507U, // PCMPISTRIZrm
+ 215683875U, // PCMPISTRIZrr
+ 2105545507U, // PCMPISTRIrm
+ 215683875U, // PCMPISTRIrr
+ 4910U, // PCMPISTRM128MEM
+ 4934U, // PCMPISTRM128REG
+ 2105545566U, // PCMPISTRM128rm
+ 215683934U, // PCMPISTRM128rr
+ 2095256425U, // PEXTRBmr
+ 215683945U, // PEXTRBrr
+ 2095125361U, // PEXTRDmr
+ 215683953U, // PEXTRDrr
+ 2095190905U, // PEXTRQmr
+ 215683961U, // PEXTRQrr
+ 2095058649U, // PEXTRWmr
+ 215682777U, // PEXTRWri
+ 1140855681U, // PHADDDrm128
+ 404755329U, // PHADDDrm64
+ 203428737U, // PHADDDrr128
+ 203428737U, // PHADDDrr64
+ 1140855689U, // PHADDSWrm128
+ 404755337U, // PHADDSWrm64
+ 203428745U, // PHADDSWrr128
+ 203428745U, // PHADDSWrr64
+ 1140855698U, // PHADDWrm128
+ 404755346U, // PHADDWrm64
+ 203428754U, // PHADDWrr128
+ 203428754U, // PHADDWrr64
+ 2214597530U, // PHMINPOSUWrm128
+ 1281364890U, // PHMINPOSUWrr128
+ 1140855718U, // PHSUBDrm128
+ 404755366U, // PHSUBDrm64
+ 203428774U, // PHSUBDrr128
+ 203428774U, // PHSUBDrr64
+ 1140855726U, // PHSUBSWrm128
+ 404755374U, // PHSUBSWrm64
+ 203428782U, // PHSUBSWrr128
+ 203428782U, // PHSUBSWrr64
+ 1140855735U, // PHSUBWrm128
+ 404755383U, // PHSUBWrm64
+ 203428791U, // PHSUBWrr128
+ 203428791U, // PHSUBWrr64
+ 1032852415U, // PINSRBrm
+ 1073746879U, // PINSRBrr
+ 1033900999U, // PINSRDrm
+ 1073746887U, // PINSRDrr
+ 1030755279U, // PINSRQrm
+ 1073746895U, // PINSRQrr
+ 1028656865U, // PINSRWrmi
+ 1073745633U, // PINSRWrri
+ 1140855767U, // PMADDUBSWrm128
+ 404755415U, // PMADDUBSWrm64
+ 203428823U, // PMADDUBSWrr128
+ 203428823U, // PMADDUBSWrr64
+ 1140854505U, // PMADDWDrm
+ 203427561U, // PMADDWDrr
+ 1140855778U, // PMAXSBrm
+ 203428834U, // PMAXSBrr
+ 1140855786U, // PMAXSDrm
+ 203428842U, // PMAXSDrr
+ 1140854514U, // PMAXSWrm
+ 203427570U, // PMAXSWrr
+ 1140854522U, // PMAXUBrm
+ 203427578U, // PMAXUBrr
+ 1140855794U, // PMAXUDrm
+ 203428850U, // PMAXUDrr
+ 1140855802U, // PMAXUWrm
+ 203428858U, // PMAXUWrr
+ 1140855810U, // PMINSBrm
+ 203428866U, // PMINSBrr
+ 1140855818U, // PMINSDrm
+ 203428874U, // PMINSDrr
+ 1140854530U, // PMINSWrm
+ 203427586U, // PMINSWrr
+ 1140854538U, // PMINUBrm
+ 203427594U, // PMINUBrr
+ 1140855826U, // PMINUDrm
+ 203428882U, // PMINUDrr
+ 1140855834U, // PMINUWrm
+ 203428890U, // PMINUWrr
+ 1281363730U, // PMOVMSKBrr
+ 1342182434U, // PMOVSXBDrm
+ 1281365026U, // PMOVSXBDrr
+ 1207964716U, // PMOVSXBQrm
+ 1281365036U, // PMOVSXBQrr
+ 1409291318U, // PMOVSXBWrm
+ 1281365046U, // PMOVSXBWrr
+ 1409291328U, // PMOVSXDQrm
+ 1281365056U, // PMOVSXDQrr
+ 1409291338U, // PMOVSXWDrm
+ 1281365066U, // PMOVSXWDrr
+ 1342182484U, // PMOVSXWQrm
+ 1281365076U, // PMOVSXWQrr
+ 1342182494U, // PMOVZXBDrm
+ 1281365086U, // PMOVZXBDrr
+ 1207964776U, // PMOVZXBQrm
+ 1281365096U, // PMOVZXBQrr
+ 1409291378U, // PMOVZXBWrm
+ 1281365106U, // PMOVZXBWrr
+ 1409291388U, // PMOVZXDQrm
+ 1281365116U, // PMOVZXDQrr
+ 1409291398U, // PMOVZXWDrm
+ 1281365126U, // PMOVZXWDrr
+ 1342182544U, // PMOVZXWQrm
+ 1281365136U, // PMOVZXWQrr
+ 1140855962U, // PMULDQrm
+ 203429018U, // PMULDQrr
+ 1140855970U, // PMULHRSWrm128
+ 404755618U, // PMULHRSWrm64
+ 203429026U, // PMULHRSWrr128
+ 203429026U, // PMULHRSWrr64
+ 1140854556U, // PMULHUWrm
+ 203427612U, // PMULHUWrr
+ 1140854565U, // PMULHWrm
+ 203427621U, // PMULHWrr
+ 1140855980U, // PMULLDrm
+ 1140855980U, // PMULLDrm_int
+ 203429036U, // PMULLDrr
+ 203429036U, // PMULLDrr_int
+ 1140854573U, // PMULLWrm
+ 203427629U, // PMULLWrr
+ 1140854581U, // PMULUDQrm
+ 203427637U, // PMULUDQrr
+ 73405620U, // POP16r
+ 872420532U, // POP16rmm
+ 73405620U, // POP16rmr
+ 73405626U, // POP32r
+ 945820858U, // POP32rmm
+ 73405626U, // POP32rmr
+ 73405632U, // POP64r
+ 1476400320U, // POP64rmm
+ 73405632U, // POP64rmr
+ 5318U, // POPFD
+ 5318U, // POPFQ
+ 1140854590U, // PORrm
+ 203427646U, // PORrr
+ 1610618059U, // PREFETCHNTA
+ 1610618072U, // PREFETCHT0
+ 1610618084U, // PREFETCHT1
+ 1610618096U, // PREFETCHT2
+ 1140854595U, // PSADBWrm
+ 203427651U, // PSADBWrr
+ 1140856060U, // PSHUFBrm128
+ 404755708U, // PSHUFBrm64
+ 203429116U, // PSHUFBrr128
+ 203429116U, // PSHUFBrr64
+ 2105545988U, // PSHUFDmi
+ 215684356U, // PSHUFDri
+ 2105545996U, // PSHUFHWmi
+ 215684364U, // PSHUFHWri
+ 2105546005U, // PSHUFLWmi
+ 215684373U, // PSHUFLWri
+ 1140856094U, // PSIGNBrm128
+ 404755742U, // PSIGNBrm64
+ 203429150U, // PSIGNBrr128
+ 203429150U, // PSIGNBrr64
+ 1140856102U, // PSIGNDrm128
+ 404755750U, // PSIGNDrm64
+ 203429158U, // PSIGNDrr128
+ 203429158U, // PSIGNDrr64
+ 1140856110U, // PSIGNWrm128
+ 404755758U, // PSIGNWrm64
+ 203429166U, // PSIGNWrr128
+ 203429166U, // PSIGNWrr64
+ 203429174U, // PSLLDQri
+ 203427667U, // PSLLDri
+ 1140854611U, // PSLLDrm
+ 203427667U, // PSLLDrr
+ 203427674U, // PSLLQri
+ 1140854618U, // PSLLQrm
+ 203427674U, // PSLLQrr
+ 203427681U, // PSLLWri
+ 1140854625U, // PSLLWrm
+ 203427681U, // PSLLWrr
+ 203427688U, // PSRADri
+ 1140854632U, // PSRADrm
+ 203427688U, // PSRADrr
+ 203427695U, // PSRAWri
+ 1140854639U, // PSRAWrm
+ 203427695U, // PSRAWrr
+ 203429182U, // PSRLDQri
+ 203427702U, // PSRLDri
+ 1140854646U, // PSRLDrm
+ 203427702U, // PSRLDrr
+ 203427709U, // PSRLQri
+ 1140854653U, // PSRLQrm
+ 203427709U, // PSRLQrr
+ 203427716U, // PSRLWri
+ 1140854660U, // PSRLWrm
+ 203427716U, // PSRLWrr
+ 1140854667U, // PSUBBrm
+ 203427723U, // PSUBBrr
+ 1140854674U, // PSUBDrm
+ 203427730U, // PSUBDrr
+ 1140854681U, // PSUBQrm
+ 203427737U, // PSUBQrr
+ 1140854688U, // PSUBSBrm
+ 203427744U, // PSUBSBrr
+ 1140854696U, // PSUBSWrm
+ 203427752U, // PSUBSWrr
+ 1140854704U, // PSUBUSBrm
+ 203427760U, // PSUBUSBrr
+ 1140854713U, // PSUBUSWrm
+ 203427769U, // PSUBUSWrr
+ 1140854722U, // PSUBWrm
+ 203427778U, // PSUBWrr
+ 2214597958U, // PTESTrm
+ 1281365318U, // PTESTrr
+ 1140854729U, // PUNPCKHBWrm
+ 203427785U, // PUNPCKHBWrr
+ 1140854740U, // PUNPCKHDQrm
+ 203427796U, // PUNPCKHDQrr
+ 1140856142U, // PUNPCKHQDQrm
+ 203429198U, // PUNPCKHQDQrr
+ 1140854751U, // PUNPCKHWDrm
+ 203427807U, // PUNPCKHWDrr
+ 1140854762U, // PUNPCKLBWrm
+ 203427818U, // PUNPCKLBWrr
+ 1140854773U, // PUNPCKLDQrm
+ 203427829U, // PUNPCKLDQrr
+ 1140856154U, // PUNPCKLQDQrm
+ 203429210U, // PUNPCKLQDQrr
+ 1140854784U, // PUNPCKLWDrm
+ 203427840U, // PUNPCKLWDrr
+ 73405798U, // PUSH16r
+ 872420710U, // PUSH16rmm
+ 73405798U, // PUSH16rmr
+ 73405805U, // PUSH32i16
+ 73405805U, // PUSH32i32
+ 73405805U, // PUSH32i8
+ 73405805U, // PUSH32r
+ 945821037U, // PUSH32rmm
+ 73405805U, // PUSH32rmr
+ 73405812U, // PUSH64i16
+ 73405812U, // PUSH64i32
+ 73405812U, // PUSH64i8
+ 73405812U, // PUSH64r
+ 1476400500U, // PUSH64rmm
+ 73405812U, // PUSH64rmr
+ 5499U, // PUSHFD
+ 5499U, // PUSHFQ
+ 1140853104U, // PXORrm
+ 203426160U, // PXORrr
+ 872420737U, // RCL16m1
+ 872420746U, // RCL16mCL
+ 2578453909U, // RCL16mi
+ 73405825U, // RCL16r1
+ 73405834U, // RCL16rCL
+ 203429269U, // RCL16ri
+ 945821083U, // RCL32m1
+ 945821092U, // RCL32mCL
+ 2579502511U, // RCL32mi
+ 73405851U, // RCL32r1
+ 73405860U, // RCL32rCL
+ 203429295U, // RCL32ri
+ 1476400565U, // RCL64m1
+ 1476400574U, // RCL64mCL
+ 2580551113U, // RCL64mi
+ 73405877U, // RCL64r1
+ 73405886U, // RCL64rCL
+ 203429321U, // RCL64ri
+ 1610618319U, // RCL8m1
+ 1610618328U, // RCL8mCL
+ 2581599715U, // RCL8mi
+ 73405903U, // RCL8r1
+ 73405912U, // RCL8rCL
+ 203429347U, // RCL8ri
+ 1879053801U, // RCPPSm
+ 1879053801U, // RCPPSm_Int
+ 1281365481U, // RCPPSr
+ 1281365481U, // RCPPSr_Int
+ 2013271536U, // RCPSSm
+ 2013271536U, // RCPSSm_Int
+ 1281365488U, // RCPSSr
+ 1281365488U, // RCPSSr_Int
+ 872420855U, // RCR16m1
+ 872420864U, // RCR16mCL
+ 2578454027U, // RCR16mi
+ 73405943U, // RCR16r1
+ 73405952U, // RCR16rCL
+ 203429387U, // RCR16ri
+ 945821201U, // RCR32m1
+ 945821210U, // RCR32mCL
+ 2579502629U, // RCR32mi
+ 73405969U, // RCR32r1
+ 73405978U, // RCR32rCL
+ 203429413U, // RCR32ri
+ 1476400683U, // RCR64m1
+ 1476400692U, // RCR64mCL
+ 2580551231U, // RCR64mi
+ 73405995U, // RCR64r1
+ 73406004U, // RCR64rCL
+ 203429439U, // RCR64ri
+ 1610618437U, // RCR8m1
+ 1610618446U, // RCR8mCL
+ 2581599833U, // RCR8mi
+ 73406021U, // RCR8r1
+ 73406030U, // RCR8rCL
+ 203429465U, // RCR8ri
+ 5727U, // RDTSC
+ 5733U, // REP_MOVSB
+ 5743U, // REP_MOVSD
+ 5753U, // REP_MOVSQ
+ 5763U, // REP_MOVSW
+ 5773U, // REP_STOSB
+ 5783U, // REP_STOSD
+ 5793U, // REP_STOSQ
+ 5803U, // REP_STOSW
+ 5813U, // RET
+ 73406137U, // RETI
+ 872421054U, // ROL16m1
+ 872421060U, // ROL16mCL
+ 135272126U, // ROL16mi
+ 73406142U, // ROL16r1
+ 73406148U, // ROL16rCL
+ 203429566U, // ROL16ri
+ 945821391U, // ROL32m1
+ 945821397U, // ROL32mCL
+ 135337679U, // ROL32mi
+ 73406159U, // ROL32r1
+ 73406165U, // ROL32rCL
+ 203429583U, // ROL32ri
+ 1476400864U, // ROL64m1
+ 1476400870U, // ROL64mCL
+ 135403232U, // ROL64mi
+ 73406176U, // ROL64r1
+ 73406182U, // ROL64rCL
+ 203429600U, // ROL64ri
+ 1610618609U, // ROL8m1
+ 1610618615U, // ROL8mCL
+ 135468785U, // ROL8mi
+ 73406193U, // ROL8r1
+ 73406199U, // ROL8rCL
+ 203429617U, // ROL8ri
+ 872421122U, // ROR16m1
+ 872421128U, // ROR16mCL
+ 135272194U, // ROR16mi
+ 73406210U, // ROR16r1
+ 73406216U, // ROR16rCL
+ 203429634U, // ROR16ri
+ 945821459U, // ROR32m1
+ 945821465U, // ROR32mCL
+ 135337747U, // ROR32mi
+ 73406227U, // ROR32r1
+ 73406233U, // ROR32rCL
+ 203429651U, // ROR32ri
+ 1476400932U, // ROR64m1
+ 1476400938U, // ROR64mCL
+ 135403300U, // ROR64mi
+ 73406244U, // ROR64r1
+ 73406250U, // ROR64rCL
+ 203429668U, // ROR64ri
+ 1610618677U, // ROR8m1
+ 1610618683U, // ROR8mCL
+ 135468853U, // ROR8mi
+ 73406261U, // ROR8r1
+ 73406267U, // ROR8rCL
+ 203429685U, // ROR8ri
+ 2112886598U, // ROUNDPDm_Int
+ 215684934U, // ROUNDPDr_Int
+ 2112886607U, // ROUNDPSm_Int
+ 215684943U, // ROUNDPSr_Int
+ 1040193368U, // ROUNDSDm_Int
+ 1073747800U, // ROUNDSDr_Int
+ 1025513313U, // ROUNDSSm_Int
+ 1073747809U, // ROUNDSSr_Int
+ 1879054186U, // RSQRTPSm
+ 1879054186U, // RSQRTPSm_Int
+ 1281365866U, // RSQRTPSr
+ 1281365866U, // RSQRTPSr_Int
+ 2013271923U, // RSQRTSSm
+ 2013271923U, // RSQRTSSm_Int
+ 1281365875U, // RSQRTSSr
+ 1281365875U, // RSQRTSSr_Int
+ 6012U, // SAHF
+ 872421249U, // SAR16m1
+ 872421255U, // SAR16mCL
+ 135272321U, // SAR16mi
+ 73406337U, // SAR16r1
+ 73406343U, // SAR16rCL
+ 203429761U, // SAR16ri
+ 945821586U, // SAR32m1
+ 945821592U, // SAR32mCL
+ 135337874U, // SAR32mi
+ 73406354U, // SAR32r1
+ 73406360U, // SAR32rCL
+ 203429778U, // SAR32ri
+ 1476401059U, // SAR64m1
+ 1476401065U, // SAR64mCL
+ 135403427U, // SAR64mi
+ 73406371U, // SAR64r1
+ 73406377U, // SAR64rCL
+ 203429795U, // SAR64ri
+ 1610618804U, // SAR8m1
+ 1610618810U, // SAR8mCL
+ 135468980U, // SAR8mi
+ 73406388U, // SAR8r1
+ 73406394U, // SAR8rCL
+ 203429812U, // SAR8ri
+ 67114949U, // SBB16i16
+ 135272389U, // SBB16mi
+ 135272389U, // SBB16mi8
+ 135272389U, // SBB16mr
+ 203429829U, // SBB16ri
+ 203429829U, // SBB16ri8
+ 270538693U, // SBB16rm
+ 203429829U, // SBB16rr
+ 70260683U, // SBB32i32
+ 135337931U, // SBB32mi
+ 135337931U, // SBB32mi8
+ 135337931U, // SBB32mr
+ 203429835U, // SBB32ri
+ 203429835U, // SBB32ri8
+ 337647563U, // SBB32rm
+ 203429835U, // SBB32rr
+ 71309265U, // SBB64i32
+ 135403473U, // SBB64mi32
+ 135403473U, // SBB64mi8
+ 135403473U, // SBB64mr
+ 203429841U, // SBB64ri32
+ 203429841U, // SBB64ri8
+ 404756433U, // SBB64rm
+ 203429841U, // SBB64rr
+ 72357847U, // SBB8i8
+ 135469015U, // SBB8mi
+ 135469015U, // SBB8mr
+ 203429847U, // SBB8ri
+ 471865303U, // SBB8rm
+ 203429847U, // SBB8rr
+ 6109U, // SCAS16
+ 6115U, // SCAS32
+ 6121U, // SCAS64
+ 6127U, // SCAS8
+ 1610618869U, // SETAEm
+ 73406453U, // SETAEr
+ 1610618876U, // SETAm
+ 73406460U, // SETAr
+ 1610618882U, // SETBEm
+ 73406466U, // SETBEr
+ 68949957U, // SETB_C16r
+ 68949963U, // SETB_C32r
+ 68949969U, // SETB_C64r
+ 68949975U, // SETB_C8r
+ 1610618889U, // SETBm
+ 73406473U, // SETBr
+ 1610618895U, // SETEm
+ 73406479U, // SETEr
+ 1610618901U, // SETGEm
+ 73406485U, // SETGEr
+ 1610618908U, // SETGm
+ 73406492U, // SETGr
+ 1610618914U, // SETLEm
+ 73406498U, // SETLEr
+ 1610618921U, // SETLm
+ 73406505U, // SETLr
+ 1610618927U, // SETNEm
+ 73406511U, // SETNEr
+ 1610618934U, // SETNOm
+ 73406518U, // SETNOr
+ 1610618941U, // SETNPm
+ 73406525U, // SETNPr
+ 1610618948U, // SETNSm
+ 73406532U, // SETNSr
+ 1610618955U, // SETOm
+ 73406539U, // SETOr
+ 1610618961U, // SETPm
+ 73406545U, // SETPr
+ 1610618967U, // SETSm
+ 73406551U, // SETSr
+ 6237U, // SFENCE
+ 872421476U, // SHL16m1
+ 872421482U, // SHL16mCL
+ 135272548U, // SHL16mi
+ 73406564U, // SHL16r1
+ 73406570U, // SHL16rCL
+ 203429988U, // SHL16ri
+ 945821813U, // SHL32m1
+ 945821819U, // SHL32mCL
+ 135338101U, // SHL32mi
+ 73406581U, // SHL32r1
+ 73406587U, // SHL32rCL
+ 203430005U, // SHL32ri
+ 1476401286U, // SHL64m1
+ 1476401292U, // SHL64mCL
+ 135403654U, // SHL64mi
+ 73406615U, // SHL64r1
+ 73406604U, // SHL64rCL
+ 203430022U, // SHL64ri
+ 1610619037U, // SHL8m1
+ 1610619043U, // SHL8mCL
+ 135469213U, // SHL8mi
+ 73406621U, // SHL8r1
+ 73406627U, // SHL8rCL
+ 203430045U, // SHL8ri
+ 135272622U, // SHLD16mrCL
+ 2095061178U, // SHLD16mri8
+ 203430062U, // SHLD16rrCL
+ 1073748154U, // SHLD16rri8
+ 135338177U, // SHLD32mrCL
+ 2095126733U, // SHLD32mri8
+ 203430081U, // SHLD32rrCL
+ 1073748173U, // SHLD32rri8
+ 135403732U, // SHLD64mrCL
+ 2095192288U, // SHLD64mri8
+ 203430100U, // SHLD64rrCL
+ 1073748192U, // SHLD64rri8
+ 872421607U, // SHR16m1
+ 872421613U, // SHR16mCL
+ 135272679U, // SHR16mi
+ 73406695U, // SHR16r1
+ 73406701U, // SHR16rCL
+ 203430119U, // SHR16ri
+ 945821944U, // SHR32m1
+ 945821950U, // SHR32mCL
+ 135338232U, // SHR32mi
+ 73406712U, // SHR32r1
+ 73406718U, // SHR32rCL
+ 203430136U, // SHR32ri
+ 1476401303U, // SHR64m1
+ 1476401417U, // SHR64mCL
+ 135403671U, // SHR64mi
+ 73406615U, // SHR64r1
+ 73406729U, // SHR64rCL
+ 203430039U, // SHR64ri
+ 1610619156U, // SHR8m1
+ 1610619162U, // SHR8mCL
+ 135469332U, // SHR8mi
+ 73406740U, // SHR8r1
+ 73406746U, // SHR8rCL
+ 203430164U, // SHR8ri
+ 135272741U, // SHRD16mrCL
+ 2095061297U, // SHRD16mri8
+ 203430181U, // SHRD16rrCL
+ 1073748273U, // SHRD16rri8
+ 135338296U, // SHRD32mrCL
+ 2095126852U, // SHRD32mri8
+ 203430200U, // SHRD32rrCL
+ 1073748292U, // SHRD32rri8
+ 135403851U, // SHRD64mrCL
+ 2095192407U, // SHRD64mri8
+ 203430219U, // SHRD64rrCL
+ 1073748311U, // SHRD64rri8
+ 1041242462U, // SHUFPDrmi
+ 1073748318U, // SHUFPDrri
+ 1041242470U, // SHUFPSrmi
+ 1073748326U, // SHUFPSrri
+ 6510U, // SIN_F
+ 0U, // SIN_Fp32
+ 0U, // SIN_Fp64
+ 0U, // SIN_Fp80
+ 1879054707U, // SQRTPDm
+ 1879054707U, // SQRTPDm_Int
+ 1281366387U, // SQRTPDr
+ 1281366387U, // SQRTPDr_Int
+ 1879054715U, // SQRTPSm
+ 1879054715U, // SQRTPSm_Int
+ 1281366395U, // SQRTPSr
+ 1281366395U, // SQRTPSr_Int
+ 1946163587U, // SQRTSDm
+ 1946163587U, // SQRTSDm_Int
+ 1281366403U, // SQRTSDr
+ 1281366403U, // SQRTSDr_Int
+ 2013272459U, // SQRTSSm
+ 2013272459U, // SQRTSSm_Int
+ 1281366411U, // SQRTSSr
+ 1281366411U, // SQRTSSr_Int
+ 6547U, // SQRT_F
+ 0U, // SQRT_Fp32
+ 0U, // SQRT_Fp64
+ 0U, // SQRT_Fp80
+ 945822105U, // STMXCSR
+ 738204066U, // ST_F32m
+ 805312936U, // ST_F64m
+ 738204078U, // ST_FP32m
+ 805312949U, // ST_FP64m
+ 2281707964U, // ST_FP80m
+ 73406915U, // ST_FPrr
+ 0U, // ST_Fp32m
+ 0U, // ST_Fp64m
+ 0U, // ST_Fp64m32
+ 0U, // ST_Fp80m32
+ 0U, // ST_Fp80m64
+ 0U, // ST_FpP32m
+ 0U, // ST_FpP64m
+ 0U, // ST_FpP64m32
+ 0U, // ST_FpP80m
+ 0U, // ST_FpP80m32
+ 0U, // ST_FpP80m64
+ 73406921U, // ST_Frr
+ 67115470U, // SUB16i16
+ 135272910U, // SUB16mi
+ 135272910U, // SUB16mi8
+ 135272910U, // SUB16mr
+ 203430350U, // SUB16ri
+ 203430350U, // SUB16ri8
+ 270539214U, // SUB16rm
+ 203430350U, // SUB16rr
+ 70261204U, // SUB32i32
+ 135338452U, // SUB32mi
+ 135338452U, // SUB32mi8
+ 135338452U, // SUB32mr
+ 203430356U, // SUB32ri
+ 203430356U, // SUB32ri8
+ 337648084U, // SUB32rm
+ 203430356U, // SUB32rr
+ 71309786U, // SUB64i32
+ 135403994U, // SUB64mi32
+ 135403994U, // SUB64mi8
+ 135403994U, // SUB64mr
+ 203430362U, // SUB64ri32
+ 203430362U, // SUB64ri8
+ 404756954U, // SUB64rm
+ 203430362U, // SUB64rr
+ 72358368U, // SUB8i8
+ 135469536U, // SUB8mi
+ 135469536U, // SUB8mr
+ 203430368U, // SUB8ri
+ 471865824U, // SUB8rm
+ 203430368U, // SUB8rr
+ 536877542U, // SUBPDrm
+ 203430374U, // SUBPDrr
+ 536877549U, // SUBPSrm
+ 203430381U, // SUBPSrr
+ 738204148U, // SUBR_F32m
+ 805313020U, // SUBR_F64m
+ 872421892U, // SUBR_FI16m
+ 945822221U, // SUBR_FI32m
+ 73406998U, // SUBR_FPrST0
+ 73407005U, // SUBR_FST0r
+ 0U, // SUBR_Fp32m
+ 0U, // SUBR_Fp64m
+ 0U, // SUBR_Fp64m32
+ 0U, // SUBR_Fp80m32
+ 0U, // SUBR_Fp80m64
+ 0U, // SUBR_FpI16m32
+ 0U, // SUBR_FpI16m64
+ 0U, // SUBR_FpI16m80
+ 0U, // SUBR_FpI32m32
+ 0U, // SUBR_FpI32m64
+ 0U, // SUBR_FpI32m80
+ 73407012U, // SUBR_FrST0
+ 603986482U, // SUBSDrm
+ 603986482U, // SUBSDrm_Int
+ 203430450U, // SUBSDrr
+ 203430450U, // SUBSDrr_Int
+ 671095353U, // SUBSSrm
+ 671095353U, // SUBSSrm_Int
+ 203430457U, // SUBSSrr
+ 203430457U, // SUBSSrr_Int
+ 738204224U, // SUB_F32m
+ 805313095U, // SUB_F64m
+ 872421966U, // SUB_FI16m
+ 945822294U, // SUB_FI32m
+ 73407070U, // SUB_FPrST0
+ 73407078U, // SUB_FST0r
+ 0U, // SUB_Fp32
+ 0U, // SUB_Fp32m
+ 0U, // SUB_Fp64
+ 0U, // SUB_Fp64m
+ 0U, // SUB_Fp64m32
+ 0U, // SUB_Fp80
+ 0U, // SUB_Fp80m32
+ 0U, // SUB_Fp80m64
+ 0U, // SUB_FpI16m32
+ 0U, // SUB_FpI16m64
+ 0U, // SUB_FpI16m80
+ 0U, // SUB_FpI32m32
+ 0U, // SUB_FpI32m64
+ 0U, // SUB_FpI32m80
+ 73407084U, // SUB_FrST0
+ 6779U, // SYSCALL
+ 6787U, // SYSENTER
+ 6796U, // SYSEXIT
+ 6796U, // SYSEXIT64
+ 6804U, // SYSRET
+ 1579158416U, // TAILJMPd
+ 975182491U, // TAILJMPm
+ 102763413U, // TAILJMPr
+ 102763420U, // TAILJMPr64
+ 103815841U, // TCRETURNdi
+ 103815841U, // TCRETURNdi64
+ 103815841U, // TCRETURNri
+ 103815841U, // TCRETURNri64
+ 67115693U, // TEST16i16
+ 135273133U, // TEST16mi
+ 1281366701U, // TEST16ri
+ 1207966381U, // TEST16rm
+ 1281366701U, // TEST16rr
+ 70261428U, // TEST32i32
+ 135338676U, // TEST32mi
+ 1281366708U, // TEST32ri
+ 1342184116U, // TEST32rm
+ 1281366708U, // TEST32rr
+ 71310011U, // TEST64i32
+ 135404219U, // TEST64mi32
+ 1281366715U, // TEST64ri32
+ 1409292987U, // TEST64rm
+ 1281366715U, // TEST64rr
+ 72358594U, // TEST8i8
+ 135469762U, // TEST8mi
+ 1281366722U, // TEST8ri
+ 1684019906U, // TEST8rm
+ 1281366722U, // TEST8rr
+ 2617248866U, // TLS_addr32
+ 2684361417U, // TLS_addr64
+ 6875U, // TRAP
+ 6879U, // TST_F
+ 0U, // TST_Fp32
+ 0U, // TST_Fp64
+ 0U, // TST_Fp80
+ 1946159952U, // UCOMISDrm
+ 1281362768U, // UCOMISDrr
+ 2013268825U, // UCOMISSrm
+ 1281362777U, // UCOMISSrr
+ 75504356U, // UCOM_FIPr
+ 75504365U, // UCOM_FIr
+ 6901U, // UCOM_FPPr
+ 73407229U, // UCOM_FPr
+ 0U, // UCOM_FpIr32
+ 0U, // UCOM_FpIr64
+ 0U, // UCOM_FpIr80
+ 0U, // UCOM_Fpr32
+ 0U, // UCOM_Fpr64
+ 0U, // UCOM_Fpr80
+ 73407237U, // UCOM_Fr
+ 536877836U, // UNPCKHPDrm
+ 203430668U, // UNPCKHPDrr
+ 536877846U, // UNPCKHPSrm
+ 203430678U, // UNPCKHPSrr
+ 536877856U, // UNPCKLPDrm
+ 203430688U, // UNPCKLPDrr
+ 536877866U, // UNPCKLPSrm
+ 203430698U, // UNPCKLPSrr
+ 68786996U, // VASTART_SAVE_XMM_REGS
+ 68946329U, // V_SET0
+ 68947628U, // V_SETALLONES
+ 6988U, // WAIT
+ 1476396056U, // WINCALL64m
+ 1549796383U, // WINCALL64pcrel32
+ 73401368U, // WINCALL64r
+ 2096634705U, // XCHG16rm
+ 2097683288U, // XCHG32rm
+ 2098731871U, // XCHG64rm
+ 2101353317U, // XCHG8rm
+ 73407340U, // XCH_F
+ 67115890U, // XOR16i16
+ 135273330U, // XOR16mi
+ 135273330U, // XOR16mi8
+ 135273330U, // XOR16mr
+ 203430770U, // XOR16ri
+ 203430770U, // XOR16ri8
+ 270539634U, // XOR16rm
+ 203430770U, // XOR16rr
+ 70258742U, // XOR32i32
+ 135335990U, // XOR32mi
+ 135335990U, // XOR32mi8
+ 135335990U, // XOR32mr
+ 203427894U, // XOR32ri
+ 203427894U, // XOR32ri8
+ 337645622U, // XOR32rm
+ 203427894U, // XOR32rr
+ 71310200U, // XOR64i32
+ 135404408U, // XOR64mi32
+ 135404408U, // XOR64mi8
+ 135404408U, // XOR64mr
+ 203430776U, // XOR64ri32
+ 203430776U, // XOR64ri8
+ 404757368U, // XOR64rm
+ 203430776U, // XOR64rr
+ 72355958U, // XOR8i8
+ 135467126U, // XOR8mi
+ 135467126U, // XOR8mr
+ 203427958U, // XOR8ri
+ 471863414U, // XOR8rm
+ 203427958U, // XOR8rr
+ 536873362U, // XORPDrm
+ 203426194U, // XORPDrr
+ 536873369U, // XORPSrm
+ 203426201U, // XORPSrr
+ 0U
+ };
+
+ const char *AsmStrs =
+ "fabs\000adcw\t\000adcl\t\000adcq\t\000adcb\t\000addw\t\000addl\t\000add"
+ "q\t\000addb\t\000addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t"
+ "\000addsubps\t\000fadds\t\000faddl\t\000fiadds\t\000fiaddl\t\000faddp\t"
+ "\000fadd\t\000fadd\t%st(0), \000#ADJCALLSTACKDOWN\000#ADJCALLSTACKUP\000"
+ "andw\t\000andl\t\000andq\t\000andb\t\000andnpd\t\000andnps\t\000andpd\t"
+ "\000andps\t\000#ATOMADD6432 PSEUDO!\000#ATOMAND16 PSEUDO!\000#ATOMAND32"
+ " PSEUDO!\000#ATOMAND64 PSEUDO!\000#ATOMAND6432 PSEUDO!\000#ATOMAND8 PSE"
+ "UDO!\000#ATOMMAX16 PSEUDO!\000#ATOMMAX32 PSEUDO!\000#ATOMMAX64 PSEUDO!\000"
+ "#ATOMMIN16 PSEUDO!\000#ATOMMIN32 PSEUDO!\000#ATOMMIN64 PSEUDO!\000#ATOM"
+ "NAND16 PSEUDO!\000#ATOMNAND32 PSEUDO!\000#ATOMNAND64 PSEUDO!\000#ATOMNA"
+ "ND6432 PSEUDO!\000#ATOMNAND8 PSEUDO!\000#ATOMOR16 PSEUDO!\000#ATOMOR32 "
+ "PSEUDO!\000#ATOMOR64 PSEUDO!\000#ATOMOR6432 PSEUDO!\000#ATOMOR8 PSEUDO!"
+ "\000#ATOMSUB6432 PSEUDO!\000#ATOMSWAP6432 PSEUDO!\000#ATOMUMAX16 PSEUDO"
+ "!\000#ATOMUMAX32 PSEUDO!\000#ATOMUMAX64 PSEUDO!\000#ATOMUMIN16 PSEUDO!\000"
+ "#ATOMUMIN32 PSEUDO!\000#ATOMUMIN64 PSEUDO!\000#ATOMXOR16 PSEUDO!\000#AT"
+ "OMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000#ATOMXOR6432 PSEUDO!\000#ATOMX"
+ "OR8 PSEUDO!\000blendpd\t\000blendps\t\000blendvpd\t%xmm0, \000blendvps\t"
+ "%xmm0, \000bsfw\t\000bsfl\t\000bsfq\t\000bsrw\t\000bsrl\t\000bsrq\t\000"
+ "bswapl\t\000bswapq\t\000btw\t\000btl\t\000btq\t\000call\t*\000call\t\000"
+ "cbtw\000cltd\000cltq\000fchs\000clflush\t\000cmova\t\000cmovae\t\000cmo"
+ "vb\t\000cmovbe\t\000fcmovbe\t\000fcmovb\t\000cmove\t\000fcmove\t\000cmo"
+ "vg\t\000cmovge\t\000cmovl\t\000cmovle\t\000fcmovnbe\t\000fcmovnb\t\000c"
+ "movne\t\000fcmovne\t\000cmovno\t\000cmovnp\t\000fcmovnu\t\000cmovns\t\000"
+ "cmovo\t\000cmovp\t\000fcmovu\t \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CM"
+ "OV_FR64 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2"
+ "F64 PSEUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmpw\t\000"
+ "cmpl\t\000cmpq\t\000cmpb\t\000cmp\000cmpsw\000cmpsl\000cmpsq\000cmpsb\000"
+ "comisd\t\000fcos\000cqto\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000cvt"
+ "pd2dq\t\000cvtps2dq\t\000cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvt"
+ "si2ssq\t\000cvtsi2ss\t\000cvtss2sd\t\000cvttsd2siq\t\000cvttsd2si\t\000"
+ "cvttss2siq\t\000cvttss2si\t\000cwtd\000cwtl\000decw\t\000decl\t\000decq"
+ "\t\000decb\t\000divw\t\000divl\t\000divq\t\000divb\t\000divpd\t\000divp"
+ "s\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000fidivrl\t\000fdivp\t\000fdi"
+ "vr\t\000fdiv\t%st(0), \000divsd\t\000divss\t\000fdivs\t\000fdivl\t\000f"
+ "idivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdivr\t%st(0), \000dppd\t\000"
+ "dpps\t\000ret\t#eh_return, addr: \000enter\t\000extractps\t\000lcallw\t"
+ "\000lcallw\t*\000lcalll\t\000lcalll\t*\000lcallq\t*\000ljmpw\t\000ljmpw"
+ "\t*\000ljmpl\t\000ljmpl\t*\000ljmpq\t*\000fbld\t\000fbstp\t\000fcom\t\000"
+ "fcomp\t\000ficomw\t\000ficoml\t\000ficompw\t\000ficompl\t\000fisttpl\t\000"
+ "fldcw\t\000fldenv\t\000fnstcw\t\000fnstsw\000##FP32_TO_INT16_IN_MEM PSE"
+ "UDO!\000##FP32_TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO"
+ "!\000##FP64_TO_INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000"
+ "##FP64_TO_INT64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##F"
+ "P80_TO_INT32_IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000##FP_R"
+ "EG_KILL\000frstor\t\000fsave\t\000fstenv\t\000fstsw\t\000movl\t%fs:\000"
+ "pxor\t\000movapd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t\000xorps\t"
+ "\000movl\t%gs:\000haddpd\t\000haddps\t\000hsubpd\t\000hsubps\t\000idivw"
+ "\t\000idivl\t\000idivq\t\000idivb\t\000filds\t\000fildl\t\000fildll\t\000"
+ "imulw\t\000imull\t\000imulq\t\000imulb\t\000inw\t\000inw\t%dx, %ax\000i"
+ "nl\t\000inl\t%dx, %eax\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000"
+ "incq\t\000incb\t\000insertps\t\000int\t\000int\t3\000fisttps\t\000fistt"
+ "pll\t\000fists\t\000fistl\t\000fistps\t\000fistpl\t\000fistpll\t\000com"
+ "iss\t\000cvtpd2pi\t\000cvtpd2ps\t\000cvtpi2pd\t\000cvtpi2ps\t\000cvtps2"
+ "pd\t\000cvtps2pi\t\000cvtsd2siq\t\000cvtsd2si\t\000cvtss2siq\t\000cvtss"
+ "2si\t\000cvttpd2dq\t\000cvttpd2pi\t\000cvttps2dq\t\000cvttps2pi\t\000uc"
+ "omisd\t\000ucomiss\t\000ja\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t"
+ "\000jg\t\000jge\t\000jl\t\000jle\t\000jmp\t\000jmpl\t*\000jmpq\t*\000jn"
+ "e\t\000jno\t\000jnp\t\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000larw\t"
+ "\000larl\t\000larq\t\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000loc"
+ "k\n\tcmpxchgq\t\000lock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddqu\t"
+ "\000ldmxcsr\t\000fldz\000fld1\000flds\t\000fldl\t\000fldt\t\000fld\t\000"
+ "leaw\t\000leal\t\000leaq\t\000leave\000lfence\000lock\n\taddw\t\000lock"
+ "\n\taddl\t\000lock\n\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000loc"
+ "k\n\tdecl\t\000lock\n\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000lo"
+ "ck\n\tincl\t\000lock\n\tincq\t\000lock\n\tincb\t\000lock\n\tsubw\t\000l"
+ "ock\n\tsubl\t\000lock\n\tsubq\t\000lock\n\tsubb\t\000lodsb\000lodsd\000"
+ "lodsq\000lodsw\000loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lo"
+ "ck\n\txaddw\t\000lock\n\txaddl\t\000lock\n\txadd\t\000lock\n\txaddb\t\000"
+ "maskmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000m"
+ "inpd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000"
+ "movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000"
+ "packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000"
+ "paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000p"
+ "avgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000"
+ "pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t"
+ "\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmul"
+ "hw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld"
+ "\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000"
+ "psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psu"
+ "busb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckh"
+ "wd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t\000monitor\000movw\t%"
+ "ax, \000movw\t\000movl\t%eax, \000movl\t\000xorl\t\000movq\t%fs:\000mov"
+ "q\t%gs:\000movq\t%rax, \000movabsq\t\000movb\t%al, \000movb\t\000xorb\t"
+ "\000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhp"
+ "s\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000movms"
+ "kpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t"
+ "\000movntps\t\000movshdup\t\000movsldup\t\000movswl\t\000movsbl\t\000mo"
+ "vswq\t\000movslq\t\000movsbq\t\000movupd\t\000movups\t\000movzbl\t\000m"
+ "ovzwl\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb\t\000mulpd\t"
+ "\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000fmull\t\000fimuls\t\000"
+ "fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000mwait\000negw\t\000n"
+ "egl\t\000negq\t\000negb\t\000nop\000nopl\t\000notw\t\000notl\t\000notq\t"
+ "\000notb\t\000orw\t\000orl\t\000orq\t\000orb\t\000outw\t%ax, \000outw\t"
+ "%ax, %dx\000outl\t%eax, \000outl\t%eax, %dx\000outb\t%al, \000outb\t%al"
+ ", %dx\000pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pb"
+ "lendvb\t%xmm0, \000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM1"
+ "28rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000"
+ "pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pc"
+ "mpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000"
+ "phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb"
+ "\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pm"
+ "axud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000p"
+ "movsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pm"
+ "ovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmo"
+ "vzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000"
+ "popl\t\000popq\t\000popf\000prefetchnta\t\000prefetcht0\t\000prefetcht1"
+ "\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000"
+ "psignb\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000"
+ "punpckhqdq\t\000punpcklqdq\t\000pushw\t\000pushl\t\000pushq\t\000pushf\000"
+ "rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%cl, \000rcll\t"
+ "\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rclb\t%cl, \000r"
+ "clb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000rcrw\t\000rc"
+ "rl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl, \000rcrq\t\000"
+ "rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdtsc\000rep;movsb\000rep;movsl\000"
+ "rep;movsq\000rep;movsw\000rep;stosb\000rep;stosl\000rep;stosq\000rep;st"
+ "osw\000ret\000ret\t\000rolw\t\000rolw\t%cl, \000roll\t\000roll\t%cl, \000"
+ "rolq\t\000rolq\t%cl, \000rolb\t\000rolb\t%cl, \000rorw\t\000rorw\t%cl, "
+ "\000rorl\t\000rorl\t%cl, \000rorq\t\000rorq\t%cl, \000rorb\t\000rorb\t%"
+ "cl, \000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsqrtps\t\000"
+ "rsqrtss\t\000sahf\000sarw\t\000sarw\t%cl, \000sarl\t\000sarl\t%cl, \000"
+ "sarq\t\000sarq\t%cl, \000sarb\t\000sarb\t%cl, \000sbbw\t\000sbbl\t\000s"
+ "bbq\t\000sbbb\t\000scasw\000scasl\000scasq\000scasb\000setae\t\000seta\t"
+ "\000setbe\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl"
+ "\t\000setne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000s"
+ "ets\t\000sfence\000shlw\t\000shlw\t%cl, \000shll\t\000shll\t%cl, \000sh"
+ "lq\t\000shlq\t%cl, \000shrq\t\000shlb\t\000shlb\t%cl, \000shldw\t%cl, \000"
+ "shldw\t\000shldl\t%cl, \000shldl\t\000shldq\t%cl, \000shldq\t\000shrw\t"
+ "\000shrw\t%cl, \000shrl\t\000shrl\t%cl, \000shrq\t%cl, \000shrb\t\000sh"
+ "rb\t%cl, \000shrdw\t%cl, \000shrdw\t\000shrdl\t%cl, \000shrdl\t\000shrd"
+ "q\t%cl, \000shrdq\t\000shufpd\t\000shufps\t\000fsin\000sqrtpd\t\000sqrt"
+ "ps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000stmxcsr\t\000fsts\t\000fstl\t\000"
+ "fstps\t\000fstpl\t\000fstpt\t\000fstp\t\000fst\t\000subw\t\000subl\t\000"
+ "subq\t\000subb\t\000subpd\t\000subps\t\000fsubrs\t\000fsubrl\t\000fisub"
+ "rs\t\000fisubrl\t\000fsubp\t\000fsubr\t\000fsub\t%st(0), \000subsd\t\000"
+ "subss\t\000fsubs\t\000fsubl\t\000fisubs\t\000fisubl\t\000fsubrp\t\000fs"
+ "ub\t\000fsubr\t%st(0), \000syscall\000sysenter\000sysexit\000sysret\000"
+ "jmp\t*\000#TC_RETURN \000testw\t\000testl\t\000testq\t\000testb\t\000.b"
+ "yte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000fucompp\000"
+ "fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000unpckl"
+ "ps\t\000#VASTART_SAVE_XMM_REGS \000wait\000xchgw\t\000xchgl\t\000xchg\t"
+ "\000xchgb\t\000fxch\t\000xorw\t\000xorq\t\000";
+
+
+#ifndef NO_ASM_WRITER_BOILERPLATE
+ if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+ printInlineAsm(MI);
+ return;
+ } else if (MI->isLabel()) {
+ printLabel(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ printImplicitDef(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
+ printKill(MI);
+ return;
+ }
+
+
+#endif
+ O << "\t";
+
+ // Emit the opcode for the instruction.
+ unsigned Bits = OpInfo[MI->getOpcode()];
+ assert(Bits != 0 && "Cannot print this instruction.");
+ O << AsmStrs+(Bits & 8191)-1;
+
+
+ // Fragment 0 encoded into 6 bits for 41 unique commands.
+ switch ((Bits >> 26) & 63) {
+ default: // unreachable.
+ case 0:
+ // ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTACKUP32, ADJCA...
+ return;
+ break;
+ case 1:
+ // ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i32, ADD64i32, AD...
+ printOperand(MI, 0);
+ break;
+ case 2:
+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC...
+ printOperand(MI, 5);
+ break;
+ case 3:
+ // ADC16ri, ADC16ri8, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64ri32, ADC...
+ printOperand(MI, 2);
+ O << ", ";
+ break;
+ case 4:
+ // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r...
+ printi16mem(MI, 2);
+ O << ", ";
+ break;
+ case 5:
+ // ADC32rm, ADD32rm, AND32rm, CMOVA32rm, CMOVAE32rm, CMOVB32rm, CMOVBE32r...
+ printi32mem(MI, 2);
+ O << ", ";
+ break;
+ case 6:
+ // ADC64rm, ADD64rm, AND64rm, CMOVA64rm, CMOVAE64rm, CMOVB64rm, CMOVBE64r...
+ printi64mem(MI, 2);
+ O << ", ";
+ break;
+ case 7:
+ // ADC8rm, ADD8rm, AND8rm, CRC32m8, OR8rm, SBB8rm, SUB8rm, XOR8rm
+ printi8mem(MI, 2);
+ O << ", ";
+ break;
+ case 8:
+ // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,...
+ printf128mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 9:
+ // ADDSDrm, ADDSDrm_Int, DIVSDrm, DIVSDrm_Int, Int_CVTSD2SSrm, MAXSDrm, M...
+ printf64mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 10:
+ // ADDSSrm, ADDSSrm_Int, DIVSSrm, DIVSSrm_Int, Int_CVTSS2SDrm, MAXSSrm, M...
+ printf32mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 11:
+ // ADD_F32m, DIVR_F32m, DIV_F32m, FBLDm, FBSTPm, FCOM32m, FCOMP32m, FLDEN...
+ printf32mem(MI, 0);
+ return;
+ break;
+ case 12:
+ // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MUL_F64m, S...
+ printf64mem(MI, 0);
+ return;
+ break;
+ case 13:
+ // ADD_FI16m, DEC16m, DEC64_16m, DIV16m, DIVR_FI16m, DIV_FI16m, FICOM16m,...
+ printi16mem(MI, 0);
+ return;
+ break;
+ case 14:
+ // ADD_FI32m, CALL32m, DEC32m, DEC64_32m, DIV32m, DIVR_FI32m, DIV_FI32m, ...
+ printi32mem(MI, 0);
+ break;
+ case 15:
+ // BLENDPDrmi, BLENDPSrmi, DPPDrmi, DPPSrmi, INSERTPSrm, MMX_PINSRWrmi, M...
+ printOperand(MI, 7);
+ O << ", ";
+ break;
+ case 16:
+ // BLENDPDrri, BLENDPSrri, DPPDrri, DPPSrri, INSERTPSrr, MMX_PINSRWrri, M...
+ printOperand(MI, 3);
+ O << ", ";
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 17:
+ // BLENDVPDrm0, BLENDVPSrm0, PACKSSDWrm, PACKSSWBrm, PACKUSDWrm, PACKUSWB...
+ printi128mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 18:
+ // BSF16rm, BSR16rm, CMP16rm, LAR16rm, LAR32rm, LAR64rm, MOV16rm, MOV16sm...
+ printi16mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 19:
+ // BSF16rr, BSF32rr, BSF64rr, BSR16rr, BSR32rr, BSR64rr, BT16ri8, BT16rr,...
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ break;
+ case 20:
+ // BSF32rm, BSR32rm, CMP32rm, CVTSI2SDrm, CVTSI2SSrm, FS_MOV32rm, GS_MOV3...
+ printi32mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 21:
+ // BSF64rm, BSR64rm, CMP64rm, CVTSI2SD64rm, CVTSI2SS64rm, Int_CVTDQ2PDrm,...
+ printi64mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 22:
+ // CALL64m, DEC64m, DIV64m, IDIV64m, ILD_F64m, IMUL64m, INC64m, ISTT_FP64...
+ printi64mem(MI, 0);
+ return;
+ break;
+ case 23:
+ // CALL64pcrel32, CALLpcrel32, JA, JA8, JAE, JAE8, JB, JB8, JBE, JBE8, JC...
+ print_pcrel_imm(MI, 0);
+ break;
+ case 24:
+ // CLFLUSH, DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, LOCK_DEC8m, LOCK_INC8m, ...
+ printi8mem(MI, 0);
+ return;
+ break;
+ case 25:
+ // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX32rm8, MOVSX64rm8, MOVZX32_NOREXrm8...
+ printi8mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ break;
+ case 26:
+ // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSSrm, Int_CMPSDrm, Int_CMPSSrm
+ printSSECC(MI, 7);
+ break;
+ case 27:
+ // CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr
+ printSSECC(MI, 3);
+ break;
+ case 28:
+ // COMISDrm, CVTDQ2PDrm, CVTDQ2PSrm, CVTPD2DQrm, CVTPS2DQrm, FsMOVAPDrm, ...
+ printf128mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 29:
+ // CVTSD2SSrm, CVTTSD2SI64rm, CVTTSD2SIrm, Int_CVTPS2PDrm, Int_CVTPS2PIrm...
+ printf64mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 30:
+ // CVTSS2SDrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_CVTSS2SI64rm, Int_CVTSS2SI...
+ printf32mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 31:
+ // EXTRACTPSmr, IMUL16rmi, IMUL16rmi8, IMUL32rmi, IMUL32rmi8, IMUL64rmi32...
+ printOperand(MI, 6);
+ O << ", ";
+ break;
+ case 32:
+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64
+ printopaquemem(MI, 0);
+ return;
+ break;
+ case 33:
+ // Int_CVTDQ2PSrm, LDDQUrm, MOVDQArm, MOVDQUrm, MOVDQUrm_Int, MOVNTDQArm,...
+ printi128mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 34:
+ // LD_F80m, ST_FP80m
+ printf80mem(MI, 0);
+ return;
+ break;
+ case 35:
+ // LEA16r, LEA32r
+ printlea32mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 36:
+ // LEA64_32r
+ printlea64_32mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 37:
+ // LEA64r
+ printlea64mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 38:
+ // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi
+ printOperand(MI, 10);
+ O << ", ";
+ break;
+ case 39:
+ // TLS_addr32
+ printlea32mem(MI, 0);
+ O << ", %eax; call\t___tls_get_addr at PLT";
+ return;
+ break;
+ case 40:
+ // TLS_addr64
+ printlea64mem(MI, 0);
+ O << "(%rip), %rdi; .word\t0x6666; rex64; call\t__tls_get_addr at PLT";
+ return;
+ break;
+ }
+
+
+ // Fragment 1 encoded into 6 bits for 36 unique commands.
+ switch ((Bits >> 20) & 63) {
+ default: // unreachable.
+ case 0:
+ // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, MOV16o16a, OR16i16, SB...
+ O << ", %ax";
+ return;
+ break;
+ case 1:
+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC...
+ O << ", ";
+ break;
+ case 2:
+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32...
+ printOperand(MI, 0);
+ return;
+ break;
+ case 3:
+ // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, MOV32o32a, OR32i32, SB...
+ O << ", %eax";
+ return;
+ break;
+ case 4:
+ // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64o32a, MOV64o8a, OR64i32, ...
+ O << ", %rax";
+ return;
+ break;
+ case 5:
+ // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, MOV8o8a, OR8i8, SBB8i8, SUB8i8,...
+ O << ", %al";
+ return;
+ break;
+ case 6:
+ // ADD_FI32m, ADD_FPrST0, ADD_FST0r, ADD_FrST0, BSF16rr, BSF32rr, BSF64rr...
+ return;
+ break;
+ case 7:
+ // BLENDPDrmi, BLENDPSrmi, DPPDrmi, DPPSrmi, MPSADBWrmi, PALIGNR128rm, PB...
+ printi128mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 8:
+ // CMOVBE_F, CMOVB_F, CMOVE_F, CMOVNBE_F, CMOVNB_F, CMOVNE_F, CMOVNP_F, C...
+ O << ", %st(0)";
+ return;
+ break;
+ case 9:
+ // CMPPDrmi, CMPPDrri
+ O << "pd\t";
+ break;
+ case 10:
+ // CMPPSrmi, CMPPSrri
+ O << "ps\t";
+ break;
+ case 11:
+ // CMPSDrm, CMPSDrr, Int_CMPSDrm, Int_CMPSDrr
+ O << "sd\t";
+ break;
+ case 12:
+ // CMPSSrm, CMPSSrr, Int_CMPSSrm, Int_CMPSSrr
+ O << "ss\t";
+ break;
+ case 13:
+ // CRC32m16, CRC32m32, CRC32m8, CRC32r16, CRC32r32, CRC32r8, CRC64m64, CR...
+ printOperand(MI, 1);
+ break;
+ case 14:
+ // EXTRACTPSmr, PEXTRBmr, PEXTRDmr, PEXTRQmr, PEXTRWmr, SHLD16mri8, SHLD3...
+ printOperand(MI, 5);
+ O << ", ";
+ break;
+ case 15:
+ // IMUL16rmi, IMUL16rmi8, LXADD16, XCHG16rm
+ printi16mem(MI, 1);
+ break;
+ case 16:
+ // IMUL32rmi, IMUL32rmi8, LXADD32, XCHG32rm
+ printi32mem(MI, 1);
+ break;
+ case 17:
+ // IMUL64rmi32, IMUL64rmi8, LXADD64, MMX_PSHUFWmi, XCHG64rm
+ printi64mem(MI, 1);
+ break;
+ case 18:
+ // INSERTPSrm, ROUNDSSm_Int
+ printf32mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 19:
+ // LCMPXCHG64
+ O << ',';
+ printi64mem(MI, 0);
+ return;
+ break;
+ case 20:
+ // LXADD8, XCHG8rm
+ printi8mem(MI, 1);
+ return;
+ break;
+ case 21:
+ // MMX_PINSRWrmi, PINSRWrmi
+ printi16mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 22:
+ // MOV8rm_NOREX, MOV8rr_NOREX, MOVZX32_NOREXrm8, MOVZX32_NOREXrr8
+ O << " # NOREX";
+ return;
+ break;
+ case 23:
+ // PALIGNR64rm, PINSRQrm
+ printi64mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 24:
+ // PCMPESTRIArm, PCMPESTRICrm, PCMPESTRIOrm, PCMPESTRISrm, PCMPESTRIZrm, ...
+ printi128mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 25:
+ // PINSRBrm
+ printi8mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 26:
+ // PINSRDrm
+ printi32mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 27:
+ // RCL16mi, RCR16mi
+ printi16mem(MI, 0);
+ return;
+ break;
+ case 28:
+ // RCL32mi, RCR32mi
+ printi32mem(MI, 0);
+ return;
+ break;
+ case 29:
+ // RCL64mi, RCR64mi
+ printi64mem(MI, 0);
+ return;
+ break;
+ case 30:
+ // RCL8mi, RCR8mi
+ printi8mem(MI, 0);
+ return;
+ break;
+ case 31:
+ // ROUNDPDm_Int, ROUNDPSm_Int
+ printf128mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 32:
+ // ROUNDSDm_Int
+ printf64mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 33:
+ // SHUFPDrmi, SHUFPSrmi
+ printf128mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 34:
+ // TAILJMPd, TAILJMPm, TAILJMPr, TAILJMPr64
+ O << " # TAILCALL";
+ return;
+ break;
+ case 35:
+ // TCRETURNdi, TCRETURNdi64, TCRETURNri, TCRETURNri64
+ O << ' ';
+ printOperand(MI, 1);
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 4 bits for 16 unique commands.
+ switch ((Bits >> 16) & 15) {
+ default: // unreachable.
+ case 0:
+ // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16...
+ printi16mem(MI, 0);
+ return;
+ break;
+ case 1:
+ // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32...
+ printi32mem(MI, 0);
+ return;
+ break;
+ case 2:
+ // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,...
+ printi64mem(MI, 0);
+ return;
+ break;
+ case 3:
+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, LCMPXC...
+ printi8mem(MI, 0);
+ break;
+ case 4:
+ // CMPPDrmi, CMPPSrmi
+ printf128mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 5:
+ // CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 6:
+ // CMPSDrm, Int_CMPSDrm
+ printf64mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 7:
+ // CMPSSrm, Int_CMPSSrm
+ printf32mem(MI, 2);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 8:
+ // CRC32m16, CRC32m32, CRC32m8, CRC32r16, CRC32r32, CRC32r8, CRC64m64, CR...
+ return;
+ break;
+ case 9:
+ // ENTER, FARCALL16i, FARCALL32i, FARJMP16i, FARJMP32i, VASTART_SAVE_XMM_...
+ printOperand(MI, 1);
+ break;
+ case 10:
+ // EXTRACTPSmr, MOVPS2SSmr, MOVSSmr
+ printf32mem(MI, 0);
+ return;
+ break;
+ case 11:
+ // EXTRACTPSrr, IMUL16rmi, IMUL16rmi8, IMUL16rri, IMUL16rri8, IMUL32rmi, ...
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 12:
+ // FsFLD0SD, FsFLD0SS, MMX_V_SET0, MMX_V_SETALLONES, MOV32r0, MOV8r0, SET...
+ printOperand(MI, 0);
+ return;
+ break;
+ case 13:
+ // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
+ printf128mem(MI, 0);
+ return;
+ break;
+ case 14:
+ // MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
+ printi128mem(MI, 0);
+ return;
+ break;
+ case 15:
+ // MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVPD2SDmr, MOVSDmr
+ printf64mem(MI, 0);
+ return;
+ break;
+ }
+
+
+ // Fragment 3 encoded into 2 bits for 3 unique commands.
+ switch ((Bits >> 14) & 3) {
+ default: // unreachable.
+ case 0:
+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, ENTER,...
+ return;
+ break;
+ case 1:
+ // MOV8mr_NOREX
+ O << " # NOREX";
+ return;
+ break;
+ case 2:
+ // VASTART_SAVE_XMM_REGS
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) {
+ assert(RegNo && RegNo < 134 && "Invalid register number!");
+
+ static const unsigned RegAsmOffset[] = {
+ 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, 40,
+ 43, 47, 50, 53, 56, 60, 64, 68, 72, 76, 80, 86, 90, 93,
+ 97, 101, 105, 109, 113, 117, 121, 125, 129, 132, 135, 138, 142, 146,
+ 150, 154, 158, 162, 166, 170, 174, 179, 184, 189, 193, 198, 203, 208,
+ 212, 217, 222, 227, 231, 236, 241, 246, 250, 255, 260, 265, 269, 274,
+ 279, 284, 287, 291, 295, 299, 302, 306, 310, 314, 318, 322, 326, 330,
+ 334, 338, 342, 346, 350, 353, 357, 360, 364, 367, 373, 379, 385, 391,
+ 397, 403, 409, 415, 420, 425, 431, 437, 443, 449, 455, 461, 466, 471,
+ 476, 481, 486, 491, 496, 501, 506, 511, 517, 523, 529, 535, 541, 547,
+ 552, 557, 562, 567, 572, 577, 582, 0
+ };
+
+ const char *AsmStrs =
+ "ah\000al\000ax\000bh\000bl\000bp\000bpl\000bx\000ch\000cl\000cs\000cx\000"
+ "dh\000di\000dil\000dl\000ds\000dx\000eax\000ebp\000ebx\000ecx\000edi\000"
+ "edx\000flags\000eip\000es\000esi\000esp\000fp0\000fp1\000fp2\000fp3\000"
+ "fp4\000fp5\000fp6\000fs\000gs\000ip\000mm0\000mm1\000mm2\000mm3\000mm4\000"
+ "mm5\000mm6\000mm7\000r10\000r10b\000r10d\000r10w\000r11\000r11b\000r11d"
+ "\000r11w\000r12\000r12b\000r12d\000r12w\000r13\000r13b\000r13d\000r13w\000"
+ "r14\000r14b\000r14d\000r14w\000r15\000r15b\000r15d\000r15w\000r8\000r8b"
+ "\000r8d\000r8w\000r9\000r9b\000r9d\000r9w\000rax\000rbp\000rbx\000rcx\000"
+ "rdi\000rdx\000rip\000rsi\000rsp\000si\000sil\000sp\000spl\000ss\000st(0"
+ ")\000st(1)\000st(2)\000st(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm"
+ "0\000xmm1\000xmm10\000xmm11\000xmm12\000xmm13\000xmm14\000xmm15\000xmm2"
+ "\000xmm3\000xmm4\000xmm5\000xmm6\000xmm7\000xmm8\000xmm9\000ymm0\000ymm"
+ "1\000ymm10\000ymm11\000ymm12\000ymm13\000ymm14\000ymm15\000ymm2\000ymm3"
+ "\000ymm4\000ymm5\000ymm6\000ymm7\000ymm8\000ymm9\000";
+ return AsmStrs+RegAsmOffset[RegNo-1];
+}
diff --git a/libclamav/c++/X86GenAsmWriter1.inc b/libclamav/c++/X86GenAsmWriter1.inc
new file mode 100644
index 0000000..9113f72
--- /dev/null
+++ b/libclamav/c++/X86GenAsmWriter1.inc
@@ -0,0 +1,3083 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Assembly Writer Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
+ static const unsigned OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // DBG_LABEL
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 1U, // ABS_F
+ 0U, // ABS_Fp32
+ 0U, // ABS_Fp64
+ 0U, // ABS_Fp80
+ 134217734U, // ADC16i16
+ 272629776U, // ADC16mi
+ 272629776U, // ADC16mi8
+ 272629776U, // ADC16mr
+ 138543120U, // ADC16ri
+ 138543120U, // ADC16ri8
+ 138674192U, // ADC16rm
+ 138543120U, // ADC16rr
+ 134217749U, // ADC32i32
+ 406847504U, // ADC32mi
+ 406847504U, // ADC32mi8
+ 406847504U, // ADC32mr
+ 138543120U, // ADC32ri
+ 138543120U, // ADC32ri8
+ 138805264U, // ADC32rm
+ 138543120U, // ADC32rr
+ 134217760U, // ADC64i32
+ 541065232U, // ADC64mi32
+ 541065232U, // ADC64mi8
+ 541065232U, // ADC64mr
+ 138543120U, // ADC64ri32
+ 138543120U, // ADC64ri8
+ 138936336U, // ADC64rm
+ 138543120U, // ADC64rr
+ 134217771U, // ADC8i8
+ 675282960U, // ADC8mi
+ 675282960U, // ADC8mr
+ 138543120U, // ADC8ri
+ 139067408U, // ADC8rm
+ 138543120U, // ADC8rr
+ 134217781U, // ADD16i16
+ 272629823U, // ADD16mi
+ 272629823U, // ADD16mi8
+ 272629823U, // ADD16mr
+ 138543167U, // ADD16mrmrr
+ 138543167U, // ADD16ri
+ 138543167U, // ADD16ri8
+ 138674239U, // ADD16rm
+ 138543167U, // ADD16rr
+ 134217796U, // ADD32i32
+ 406847551U, // ADD32mi
+ 406847551U, // ADD32mi8
+ 406847551U, // ADD32mr
+ 138543167U, // ADD32mrmrr
+ 138543167U, // ADD32ri
+ 138543167U, // ADD32ri8
+ 138805311U, // ADD32rm
+ 138543167U, // ADD32rr
+ 134217807U, // ADD64i32
+ 541065279U, // ADD64mi32
+ 541065279U, // ADD64mi8
+ 541065279U, // ADD64mr
+ 138543167U, // ADD64mrmrr
+ 138543167U, // ADD64ri32
+ 138543167U, // ADD64ri8
+ 138936383U, // ADD64rm
+ 138543167U, // ADD64rr
+ 134217818U, // ADD8i8
+ 675283007U, // ADD8mi
+ 675283007U, // ADD8mr
+ 138543167U, // ADD8mrmrr
+ 138543167U, // ADD8ri
+ 139067455U, // ADD8rm
+ 138543167U, // ADD8rr
+ 139198564U, // ADDPDrm
+ 138543204U, // ADDPDrr
+ 139198571U, // ADDPSrm
+ 138543211U, // ADDPSrr
+ 139329650U, // ADDSDrm
+ 139329650U, // ADDSDrm_Int
+ 138543218U, // ADDSDrr
+ 138543218U, // ADDSDrr_Int
+ 139460729U, // ADDSSrm
+ 139460729U, // ADDSSrm_Int
+ 138543225U, // ADDSSrr
+ 138543225U, // ADDSSrr_Int
+ 139198592U, // ADDSUBPDrm
+ 138543232U, // ADDSUBPDrr
+ 139198602U, // ADDSUBPSrm
+ 138543242U, // ADDSUBPSrr
+ 805306516U, // ADD_F32m
+ 939524244U, // ADD_F64m
+ 268435610U, // ADD_FI16m
+ 402653338U, // ADD_FI32m
+ 134217889U, // ADD_FPrST0
+ 134217876U, // ADD_FST0r
+ 0U, // ADD_Fp32
+ 0U, // ADD_Fp32m
+ 0U, // ADD_Fp64
+ 0U, // ADD_Fp64m
+ 0U, // ADD_Fp64m32
+ 0U, // ADD_Fp80
+ 0U, // ADD_Fp80m32
+ 0U, // ADD_Fp80m64
+ 0U, // ADD_FpI16m32
+ 0U, // ADD_FpI16m64
+ 0U, // ADD_FpI16m80
+ 0U, // ADD_FpI32m32
+ 0U, // ADD_FpI32m64
+ 0U, // ADD_FpI32m80
+ 142606484U, // ADD_FrST0
+ 168U, // ADJCALLSTACKDOWN32
+ 168U, // ADJCALLSTACKDOWN64
+ 186U, // ADJCALLSTACKUP32
+ 186U, // ADJCALLSTACKUP64
+ 134217930U, // AND16i16
+ 272629972U, // AND16mi
+ 272629972U, // AND16mi8
+ 272629972U, // AND16mr
+ 138543316U, // AND16ri
+ 138543316U, // AND16ri8
+ 138674388U, // AND16rm
+ 138543316U, // AND16rr
+ 134217945U, // AND32i32
+ 406847700U, // AND32mi
+ 406847700U, // AND32mi8
+ 406847700U, // AND32mr
+ 138543316U, // AND32ri
+ 138543316U, // AND32ri8
+ 138805460U, // AND32rm
+ 138543316U, // AND32rr
+ 134217956U, // AND64i32
+ 541065428U, // AND64mi32
+ 541065428U, // AND64mi8
+ 541065428U, // AND64mr
+ 138543316U, // AND64ri32
+ 138543316U, // AND64ri8
+ 138936532U, // AND64rm
+ 138543316U, // AND64rr
+ 134217967U, // AND8i8
+ 675283156U, // AND8mi
+ 675283156U, // AND8mr
+ 138543316U, // AND8ri
+ 139067604U, // AND8rm
+ 138543316U, // AND8rr
+ 139198713U, // ANDNPDrm
+ 138543353U, // ANDNPDrr
+ 139198721U, // ANDNPSrm
+ 138543361U, // ANDNPSrr
+ 139198729U, // ANDPDrm
+ 138543369U, // ANDPDrr
+ 139198736U, // ANDPSrm
+ 138543376U, // ANDPSrr
+ 279U, // ATOMADD6432
+ 300U, // ATOMAND16
+ 319U, // ATOMAND32
+ 338U, // ATOMAND64
+ 357U, // ATOMAND6432
+ 378U, // ATOMAND8
+ 396U, // ATOMMAX16
+ 415U, // ATOMMAX32
+ 434U, // ATOMMAX64
+ 453U, // ATOMMIN16
+ 472U, // ATOMMIN32
+ 491U, // ATOMMIN64
+ 510U, // ATOMNAND16
+ 530U, // ATOMNAND32
+ 550U, // ATOMNAND64
+ 570U, // ATOMNAND6432
+ 592U, // ATOMNAND8
+ 611U, // ATOMOR16
+ 629U, // ATOMOR32
+ 647U, // ATOMOR64
+ 665U, // ATOMOR6432
+ 685U, // ATOMOR8
+ 702U, // ATOMSUB6432
+ 723U, // ATOMSWAP6432
+ 745U, // ATOMUMAX16
+ 765U, // ATOMUMAX32
+ 785U, // ATOMUMAX64
+ 805U, // ATOMUMIN16
+ 825U, // ATOMUMIN32
+ 845U, // ATOMUMIN64
+ 865U, // ATOMXOR16
+ 884U, // ATOMXOR32
+ 903U, // ATOMXOR64
+ 922U, // ATOMXOR6432
+ 943U, // ATOMXOR8
+ 139609025U, // BLENDPDrmi
+ 138560449U, // BLENDPDrri
+ 139609034U, // BLENDPSrmi
+ 138560458U, // BLENDPSrri
+ 139625427U, // BLENDVPDrm0
+ 138576851U, // BLENDVPDrr0
+ 139625437U, // BLENDVPSrm0
+ 138576861U, // BLENDVPSrr0
+ 139723751U, // BSF16rm
+ 139854823U, // BSF16rr
+ 139985895U, // BSF32rm
+ 139854823U, // BSF32rr
+ 140116967U, // BSF64rm
+ 139854823U, // BSF64rr
+ 139723756U, // BSR16rm
+ 139854828U, // BSR16rr
+ 139985900U, // BSR32rm
+ 139854828U, // BSR32rr
+ 140116972U, // BSR64rm
+ 139854828U, // BSR64rr
+ 134218737U, // BSWAP32r
+ 134218737U, // BSWAP64r
+ 272630776U, // BT16mi8
+ 139854840U, // BT16ri8
+ 139854840U, // BT16rr
+ 406848504U, // BT32mi8
+ 139854840U, // BT32ri8
+ 139854840U, // BT32rr
+ 541066232U, // BT64mi8
+ 139854840U, // BT64ri8
+ 139854840U, // BT64rr
+ 402654204U, // CALL32m
+ 134218748U, // CALL32r
+ 536871932U, // CALL64m
+ 1073742844U, // CALL64pcrel32
+ 134218748U, // CALL64r
+ 1073742844U, // CALLpcrel32
+ 1026U, // CBW
+ 1030U, // CDQ
+ 1034U, // CDQE
+ 1039U, // CHS_F
+ 0U, // CHS_Fp32
+ 0U, // CHS_Fp64
+ 0U, // CHS_Fp80
+ 671089684U, // CLFLUSH
+ 138675229U, // CMOVA16rm
+ 138544157U, // CMOVA16rr
+ 138806301U, // CMOVA32rm
+ 138544157U, // CMOVA32rr
+ 138937373U, // CMOVA64rm
+ 138544157U, // CMOVA64rr
+ 138675236U, // CMOVAE16rm
+ 138544164U, // CMOVAE16rr
+ 138806308U, // CMOVAE32rm
+ 138544164U, // CMOVAE32rr
+ 138937380U, // CMOVAE64rm
+ 138544164U, // CMOVAE64rr
+ 138675244U, // CMOVB16rm
+ 138544172U, // CMOVB16rr
+ 138806316U, // CMOVB32rm
+ 138544172U, // CMOVB32rr
+ 138937388U, // CMOVB64rm
+ 138544172U, // CMOVB64rr
+ 138675251U, // CMOVBE16rm
+ 138544179U, // CMOVBE16rr
+ 138806323U, // CMOVBE32rm
+ 138544179U, // CMOVBE32rr
+ 138937395U, // CMOVBE64rm
+ 138544179U, // CMOVBE64rr
+ 134218811U, // CMOVBE_F
+ 0U, // CMOVBE_Fp32
+ 0U, // CMOVBE_Fp64
+ 0U, // CMOVBE_Fp80
+ 134218828U, // CMOVB_F
+ 0U, // CMOVB_Fp32
+ 0U, // CMOVB_Fp64
+ 0U, // CMOVB_Fp80
+ 138675292U, // CMOVE16rm
+ 138544220U, // CMOVE16rr
+ 138806364U, // CMOVE32rm
+ 138544220U, // CMOVE32rr
+ 138937436U, // CMOVE64rm
+ 138544220U, // CMOVE64rr
+ 134218851U, // CMOVE_F
+ 0U, // CMOVE_Fp32
+ 0U, // CMOVE_Fp64
+ 0U, // CMOVE_Fp80
+ 138675315U, // CMOVG16rm
+ 138544243U, // CMOVG16rr
+ 138806387U, // CMOVG32rm
+ 138544243U, // CMOVG32rr
+ 138937459U, // CMOVG64rm
+ 138544243U, // CMOVG64rr
+ 138675322U, // CMOVGE16rm
+ 138544250U, // CMOVGE16rr
+ 138806394U, // CMOVGE32rm
+ 138544250U, // CMOVGE32rr
+ 138937466U, // CMOVGE64rm
+ 138544250U, // CMOVGE64rr
+ 138675330U, // CMOVL16rm
+ 138544258U, // CMOVL16rr
+ 138806402U, // CMOVL32rm
+ 138544258U, // CMOVL32rr
+ 138937474U, // CMOVL64rm
+ 138544258U, // CMOVL64rr
+ 138675337U, // CMOVLE16rm
+ 138544265U, // CMOVLE16rr
+ 138806409U, // CMOVLE32rm
+ 138544265U, // CMOVLE32rr
+ 138937481U, // CMOVLE64rm
+ 138544265U, // CMOVLE64rr
+ 134218897U, // CMOVNBE_F
+ 0U, // CMOVNBE_Fp32
+ 0U, // CMOVNBE_Fp64
+ 0U, // CMOVNBE_Fp80
+ 134218915U, // CMOVNB_F
+ 0U, // CMOVNB_Fp32
+ 0U, // CMOVNB_Fp64
+ 0U, // CMOVNB_Fp80
+ 138675380U, // CMOVNE16rm
+ 138544308U, // CMOVNE16rr
+ 138806452U, // CMOVNE32rm
+ 138544308U, // CMOVNE32rr
+ 138937524U, // CMOVNE64rm
+ 138544308U, // CMOVNE64rr
+ 134218940U, // CMOVNE_F
+ 0U, // CMOVNE_Fp32
+ 0U, // CMOVNE_Fp64
+ 0U, // CMOVNE_Fp80
+ 138675405U, // CMOVNO16rm
+ 138544333U, // CMOVNO16rr
+ 138806477U, // CMOVNO32rm
+ 138544333U, // CMOVNO32rr
+ 138937549U, // CMOVNO64rm
+ 138544333U, // CMOVNO64rr
+ 138675413U, // CMOVNP16rm
+ 138544341U, // CMOVNP16rr
+ 138806485U, // CMOVNP32rm
+ 138544341U, // CMOVNP32rr
+ 138937557U, // CMOVNP64rm
+ 138544341U, // CMOVNP64rr
+ 134218973U, // CMOVNP_F
+ 0U, // CMOVNP_Fp32
+ 0U, // CMOVNP_Fp64
+ 0U, // CMOVNP_Fp80
+ 138675438U, // CMOVNS16rm
+ 138544366U, // CMOVNS16rr
+ 138806510U, // CMOVNS32rm
+ 138544366U, // CMOVNS32rr
+ 138937582U, // CMOVNS64rm
+ 138544366U, // CMOVNS64rr
+ 138675446U, // CMOVO16rm
+ 138544374U, // CMOVO16rr
+ 138806518U, // CMOVO32rm
+ 138544374U, // CMOVO32rr
+ 138937590U, // CMOVO64rm
+ 138544374U, // CMOVO64rr
+ 138675453U, // CMOVP16rm
+ 138544381U, // CMOVP16rr
+ 138806525U, // CMOVP32rm
+ 138544381U, // CMOVP32rr
+ 138937597U, // CMOVP64rm
+ 138544381U, // CMOVP64rr
+ 134219012U, // CMOVP_F
+ 0U, // CMOVP_Fp32
+ 0U, // CMOVP_Fp64
+ 0U, // CMOVP_Fp80
+ 138675477U, // CMOVS16rm
+ 138544405U, // CMOVS16rr
+ 138806549U, // CMOVS32rm
+ 138544405U, // CMOVS32rr
+ 138937621U, // CMOVS64rm
+ 138544405U, // CMOVS64rr
+ 1308U, // CMOV_FR32
+ 1327U, // CMOV_FR64
+ 1346U, // CMOV_GR8
+ 1364U, // CMOV_V1I64
+ 1384U, // CMOV_V2F64
+ 1404U, // CMOV_V2I64
+ 1424U, // CMOV_V4F32
+ 134219172U, // CMP16i16
+ 272631214U, // CMP16mi
+ 272631214U, // CMP16mi8
+ 272631214U, // CMP16mr
+ 139855278U, // CMP16mrmrr
+ 139855278U, // CMP16ri
+ 139855278U, // CMP16ri8
+ 139724206U, // CMP16rm
+ 139855278U, // CMP16rr
+ 134219187U, // CMP32i32
+ 406848942U, // CMP32mi
+ 406848942U, // CMP32mi8
+ 406848942U, // CMP32mr
+ 139855278U, // CMP32mrmrr
+ 139855278U, // CMP32ri
+ 139855278U, // CMP32ri8
+ 139986350U, // CMP32rm
+ 139855278U, // CMP32rr
+ 134219198U, // CMP64i32
+ 541066670U, // CMP64mi32
+ 541066670U, // CMP64mi8
+ 541066670U, // CMP64mr
+ 139855278U, // CMP64mrmrr
+ 139855278U, // CMP64ri32
+ 139855278U, // CMP64ri8
+ 140117422U, // CMP64rm
+ 139855278U, // CMP64rr
+ 134219209U, // CMP8i8
+ 675284398U, // CMP8mi
+ 675284398U, // CMP8mr
+ 139855278U, // CMP8mrmrr
+ 139855278U, // CMP8ri
+ 140248494U, // CMP8rm
+ 139855278U, // CMP8rr
+ 1221330387U, // CMPPDrmi
+ 1354892755U, // CMPPDrri
+ 1225524691U, // CMPPSrmi
+ 1359087059U, // CMPPSrri
+ 1495U, // CMPS16
+ 1495U, // CMPS32
+ 1495U, // CMPS64
+ 1495U, // CMPS8
+ 1229850067U, // CMPSDrm
+ 1363281363U, // CMPSDrr
+ 1234175443U, // CMPSSrm
+ 1367475667U, // CMPSSrr
+ 140379612U, // COMISDrm
+ 139855324U, // COMISDrr
+ 1508U, // COS_F
+ 0U, // COS_Fp32
+ 0U, // COS_Fp64
+ 0U, // COS_Fp80
+ 1513U, // CQO
+ 1505756653U, // CRC32m16
+ 1509950957U, // CRC32m32
+ 1514145261U, // CRC32m8
+ 1518339565U, // CRC32r16
+ 1518339565U, // CRC32r32
+ 1518339565U, // CRC32r8
+ 1522533869U, // CRC64m64
+ 1518339565U, // CRC64r64
+ 140379637U, // CVTDQ2PDrm
+ 139855349U, // CVTDQ2PDrr
+ 140379647U, // CVTDQ2PSrm
+ 139855359U, // CVTDQ2PSrr
+ 140379657U, // CVTPD2DQrm
+ 139855369U, // CVTPD2DQrr
+ 140379667U, // CVTPS2DQrm
+ 139855379U, // CVTPS2DQrr
+ 140510749U, // CVTSD2SSrm
+ 139855389U, // CVTSD2SSrr
+ 140117543U, // CVTSI2SD64rm
+ 139855399U, // CVTSI2SD64rr
+ 139986471U, // CVTSI2SDrm
+ 139855399U, // CVTSI2SDrr
+ 140117553U, // CVTSI2SS64rm
+ 139855409U, // CVTSI2SS64rr
+ 139986481U, // CVTSI2SSrm
+ 139855409U, // CVTSI2SSrr
+ 140641851U, // CVTSS2SDrm
+ 139855419U, // CVTSS2SDrr
+ 140510789U, // CVTTSD2SI64rm
+ 139855429U, // CVTTSD2SI64rr
+ 140510789U, // CVTTSD2SIrm
+ 139855429U, // CVTTSD2SIrr
+ 140641872U, // CVTTSS2SI64rm
+ 139855440U, // CVTTSS2SI64rr
+ 140641872U, // CVTTSS2SIrm
+ 139855440U, // CVTTSS2SIrr
+ 1627U, // CWD
+ 1631U, // CWDE
+ 268437092U, // DEC16m
+ 134219364U, // DEC16r
+ 402654820U, // DEC32m
+ 134219364U, // DEC32r
+ 268437092U, // DEC64_16m
+ 134219364U, // DEC64_16r
+ 402654820U, // DEC64_32m
+ 134219364U, // DEC64_32r
+ 536872548U, // DEC64m
+ 134219364U, // DEC64r
+ 671090276U, // DEC8m
+ 134219364U, // DEC8r
+ 268437097U, // DIV16m
+ 134219369U, // DIV16r
+ 402654825U, // DIV32m
+ 134219369U, // DIV32r
+ 536872553U, // DIV64m
+ 134219369U, // DIV64r
+ 671090281U, // DIV8m
+ 134219369U, // DIV8r
+ 139200110U, // DIVPDrm
+ 138544750U, // DIVPDrr
+ 139200117U, // DIVPSrm
+ 138544757U, // DIVPSrr
+ 805308028U, // DIVR_F32m
+ 939525756U, // DIVR_F64m
+ 268437123U, // DIVR_FI16m
+ 402654851U, // DIVR_FI32m
+ 134219403U, // DIVR_FPrST0
+ 134219388U, // DIVR_FST0r
+ 0U, // DIVR_Fp32m
+ 0U, // DIVR_Fp64m
+ 0U, // DIVR_Fp64m32
+ 0U, // DIVR_Fp80m32
+ 0U, // DIVR_Fp80m64
+ 0U, // DIVR_FpI16m32
+ 0U, // DIVR_FpI16m64
+ 0U, // DIVR_FpI16m80
+ 0U, // DIVR_FpI32m32
+ 0U, // DIVR_FpI32m64
+ 0U, // DIVR_FpI32m80
+ 142607996U, // DIVR_FrST0
+ 139331219U, // DIVSDrm
+ 139331219U, // DIVSDrm_Int
+ 138544787U, // DIVSDrr
+ 138544787U, // DIVSDrr_Int
+ 139462298U, // DIVSSrm
+ 139462298U, // DIVSSrm_Int
+ 138544794U, // DIVSSrr
+ 138544794U, // DIVSSrr_Int
+ 805308065U, // DIV_F32m
+ 939525793U, // DIV_F64m
+ 268437159U, // DIV_FI16m
+ 402654887U, // DIV_FI32m
+ 134219438U, // DIV_FPrST0
+ 134219425U, // DIV_FST0r
+ 0U, // DIV_Fp32
+ 0U, // DIV_Fp32m
+ 0U, // DIV_Fp64
+ 0U, // DIV_Fp64m
+ 0U, // DIV_Fp64m32
+ 0U, // DIV_Fp80
+ 0U, // DIV_Fp80m32
+ 0U, // DIV_Fp80m64
+ 0U, // DIV_FpI16m32
+ 0U, // DIV_FpI16m64
+ 0U, // DIV_FpI16m80
+ 0U, // DIV_FpI32m32
+ 0U, // DIV_FpI32m64
+ 0U, // DIV_FpI32m80
+ 142608033U, // DIV_FrST0
+ 139609781U, // DPPDrmi
+ 138561205U, // DPPDrri
+ 139609787U, // DPPSrmi
+ 138561211U, // DPPSrri
+ 134219457U, // EH_RETURN
+ 134219457U, // EH_RETURN64
+ 139855576U, // ENTER
+ 809518815U, // EXTRACTPSmr
+ 139871967U, // EXTRACTPSrr
+ 139855594U, // FARCALL16i
+ 1610614506U, // FARCALL16m
+ 139855594U, // FARCALL32i
+ 1610614506U, // FARCALL32m
+ 1610614506U, // FARCALL64
+ 139855601U, // FARJMP16i
+ 1610614513U, // FARJMP16m
+ 139855601U, // FARJMP32i
+ 1610614513U, // FARJMP32m
+ 1610614513U, // FARJMP64
+ 805308151U, // FBLDm
+ 805308157U, // FBSTPm
+ 805308164U, // FCOM32m
+ 939525892U, // FCOM64m
+ 805308170U, // FCOMP32m
+ 939525898U, // FCOMP64m
+ 268437265U, // FICOM16m
+ 402654993U, // FICOM32m
+ 268437272U, // FICOMP16m
+ 402655000U, // FICOMP32m
+ 402655008U, // FISTTP32m
+ 268437288U, // FLDCW16m
+ 805308207U, // FLDENVm
+ 268437303U, // FNSTCW16m
+ 1855U, // FNSTSW8r
+ 1862U, // FP32_TO_INT16_IN_MEM
+ 1893U, // FP32_TO_INT32_IN_MEM
+ 1924U, // FP32_TO_INT64_IN_MEM
+ 1955U, // FP64_TO_INT16_IN_MEM
+ 1986U, // FP64_TO_INT32_IN_MEM
+ 2017U, // FP64_TO_INT64_IN_MEM
+ 2048U, // FP80_TO_INT16_IN_MEM
+ 2079U, // FP80_TO_INT32_IN_MEM
+ 2110U, // FP80_TO_INT64_IN_MEM
+ 2141U, // FP_REG_KILL
+ 805308523U, // FRSTORm
+ 805308531U, // FSAVEm
+ 805308538U, // FSTENVm
+ 805308546U, // FSTSWm
+ 1795164297U, // FS_MOV32rm
+ 0U, // FpGET_ST0_32
+ 0U, // FpGET_ST0_64
+ 0U, // FpGET_ST0_80
+ 0U, // FpGET_ST1_32
+ 0U, // FpGET_ST1_64
+ 0U, // FpGET_ST1_80
+ 0U, // FpSET_ST0_32
+ 0U, // FpSET_ST0_64
+ 0U, // FpSET_ST0_80
+ 0U, // FpSET_ST1_32
+ 0U, // FpSET_ST1_64
+ 0U, // FpSET_ST1_80
+ 139198713U, // FsANDNPDrm
+ 138543353U, // FsANDNPDrr
+ 139198721U, // FsANDNPSrm
+ 138543361U, // FsANDNPSrr
+ 139198729U, // FsANDPDrm
+ 138543369U, // FsANDPDrr
+ 139198736U, // FsANDPSrm
+ 138543376U, // FsANDPSrr
+ 140773523U, // FsFLD0SD
+ 140773523U, // FsFLD0SS
+ 140380313U, // FsMOVAPDrm
+ 139856025U, // FsMOVAPDrr
+ 140380321U, // FsMOVAPSrm
+ 139856033U, // FsMOVAPSrr
+ 139200681U, // FsORPDrm
+ 138545321U, // FsORPDrr
+ 139200687U, // FsORPSrm
+ 138545327U, // FsORPSrr
+ 139200693U, // FsXORPDrm
+ 138545333U, // FsXORPDrr
+ 139200700U, // FsXORPSrm
+ 138545340U, // FsXORPSrr
+ 1795164355U, // GS_MOV32rm
+ 139200717U, // HADDPDrm
+ 138545357U, // HADDPDrr
+ 139200725U, // HADDPSrm
+ 138545365U, // HADDPSrr
+ 139200733U, // HSUBPDrm
+ 138545373U, // HSUBPDrr
+ 139200741U, // HSUBPSrm
+ 138545381U, // HSUBPSrr
+ 268437741U, // IDIV16m
+ 134220013U, // IDIV16r
+ 402655469U, // IDIV32m
+ 134220013U, // IDIV32r
+ 536873197U, // IDIV64m
+ 134220013U, // IDIV64r
+ 671090925U, // IDIV8m
+ 134220013U, // IDIV8r
+ 268437747U, // ILD_F16m
+ 402655475U, // ILD_F32m
+ 536873203U, // ILD_F64m
+ 0U, // ILD_Fp16m32
+ 0U, // ILD_Fp16m64
+ 0U, // ILD_Fp16m80
+ 0U, // ILD_Fp32m32
+ 0U, // ILD_Fp32m64
+ 0U, // ILD_Fp32m80
+ 0U, // ILD_Fp64m32
+ 0U, // ILD_Fp64m64
+ 0U, // ILD_Fp64m80
+ 268437753U, // IMUL16m
+ 134220025U, // IMUL16r
+ 138676473U, // IMUL16rm
+ 139741433U, // IMUL16rmi
+ 139741433U, // IMUL16rmi8
+ 138545401U, // IMUL16rr
+ 139872505U, // IMUL16rri
+ 139872505U, // IMUL16rri8
+ 402655481U, // IMUL32m
+ 134220025U, // IMUL32r
+ 138807545U, // IMUL32rm
+ 140003577U, // IMUL32rmi
+ 140003577U, // IMUL32rmi8
+ 138545401U, // IMUL32rr
+ 139872505U, // IMUL32rri
+ 139872505U, // IMUL32rri8
+ 536873209U, // IMUL64m
+ 134220025U, // IMUL64r
+ 138938617U, // IMUL64rm
+ 140134649U, // IMUL64rmi32
+ 140134649U, // IMUL64rmi8
+ 138545401U, // IMUL64rr
+ 139872505U, // IMUL64rri32
+ 139872505U, // IMUL64rri8
+ 671090937U, // IMUL8m
+ 134220025U, // IMUL8r
+ 134220031U, // IN16ri
+ 2312U, // IN16rr
+ 134220052U, // IN32ri
+ 2334U, // IN32rr
+ 134220075U, // IN8ri
+ 2356U, // IN8rr
+ 268437824U, // INC16m
+ 134220096U, // INC16r
+ 402655552U, // INC32m
+ 134220096U, // INC32r
+ 268437824U, // INC64_16m
+ 134220096U, // INC64_16r
+ 402655552U, // INC64_32m
+ 134220096U, // INC64_32r
+ 536873280U, // INC64m
+ 134220096U, // INC64r
+ 671091008U, // INC8m
+ 134220096U, // INC8r
+ 139479365U, // INSERTPSrm
+ 138561861U, // INSERTPSrr
+ 134220111U, // INT
+ 2388U, // INT3
+ 268437280U, // ISTT_FP16m
+ 402655008U, // ISTT_FP32m
+ 536872736U, // ISTT_FP64m
+ 0U, // ISTT_Fp16m32
+ 0U, // ISTT_Fp16m64
+ 0U, // ISTT_Fp16m80
+ 0U, // ISTT_Fp32m32
+ 0U, // ISTT_Fp32m64
+ 0U, // ISTT_Fp32m80
+ 0U, // ISTT_Fp64m32
+ 0U, // ISTT_Fp64m64
+ 0U, // ISTT_Fp64m80
+ 268437850U, // IST_F16m
+ 402655578U, // IST_F32m
+ 268437856U, // IST_FP16m
+ 402655584U, // IST_FP32m
+ 536873312U, // IST_FP64m
+ 0U, // IST_Fp16m32
+ 0U, // IST_Fp16m64
+ 0U, // IST_Fp16m80
+ 0U, // IST_Fp32m32
+ 0U, // IST_Fp32m64
+ 0U, // IST_Fp32m80
+ 0U, // IST_Fp64m32
+ 0U, // IST_Fp64m64
+ 0U, // IST_Fp64m80
+ 1229850067U, // Int_CMPSDrm
+ 1363281363U, // Int_CMPSDrr
+ 1234175443U, // Int_CMPSSrm
+ 1367475667U, // Int_CMPSSrr
+ 140379612U, // Int_COMISDrm
+ 139855324U, // Int_COMISDrr
+ 140380519U, // Int_COMISSrm
+ 139856231U, // Int_COMISSrr
+ 140117493U, // Int_CVTDQ2PDrm
+ 139855349U, // Int_CVTDQ2PDrr
+ 140903935U, // Int_CVTDQ2PSrm
+ 139855359U, // Int_CVTDQ2PSrr
+ 140379657U, // Int_CVTPD2DQrm
+ 139855369U, // Int_CVTPD2DQrr
+ 140380527U, // Int_CVTPD2PIrm
+ 139856239U, // Int_CVTPD2PIrr
+ 140380537U, // Int_CVTPD2PSrm
+ 139856249U, // Int_CVTPD2PSrr
+ 140118403U, // Int_CVTPI2PDrm
+ 139856259U, // Int_CVTPI2PDrr
+ 138938765U, // Int_CVTPI2PSrm
+ 138545549U, // Int_CVTPI2PSrr
+ 140379667U, // Int_CVTPS2DQrm
+ 139855379U, // Int_CVTPS2DQrr
+ 140511639U, // Int_CVTPS2PDrm
+ 139856279U, // Int_CVTPS2PDrr
+ 140511649U, // Int_CVTPS2PIrm
+ 139856289U, // Int_CVTPS2PIrr
+ 140380587U, // Int_CVTSD2SI64rm
+ 139856299U, // Int_CVTSD2SI64rr
+ 140380587U, // Int_CVTSD2SIrm
+ 139856299U, // Int_CVTSD2SIrr
+ 139331101U, // Int_CVTSD2SSrm
+ 138544669U, // Int_CVTSD2SSrr
+ 138937895U, // Int_CVTSI2SD64rm
+ 138544679U, // Int_CVTSI2SD64rr
+ 138806823U, // Int_CVTSI2SDrm
+ 138544679U, // Int_CVTSI2SDrr
+ 138937905U, // Int_CVTSI2SS64rm
+ 138544689U, // Int_CVTSI2SS64rr
+ 138806833U, // Int_CVTSI2SSrm
+ 138544689U, // Int_CVTSI2SSrr
+ 139462203U, // Int_CVTSS2SDrm
+ 138544699U, // Int_CVTSS2SDrr
+ 140642741U, // Int_CVTSS2SI64rm
+ 139856309U, // Int_CVTSS2SI64rr
+ 140642741U, // Int_CVTSS2SIrm
+ 139856309U, // Int_CVTSS2SIrr
+ 140380607U, // Int_CVTTPD2DQrm
+ 139856319U, // Int_CVTTPD2DQrr
+ 140380618U, // Int_CVTTPD2PIrm
+ 139856330U, // Int_CVTTPD2PIrr
+ 140380629U, // Int_CVTTPS2DQrm
+ 139856341U, // Int_CVTTPS2DQrr
+ 140511712U, // Int_CVTTPS2PIrm
+ 139856352U, // Int_CVTTPS2PIrr
+ 140379717U, // Int_CVTTSD2SI64rm
+ 139855429U, // Int_CVTTSD2SI64rr
+ 140379717U, // Int_CVTTSD2SIrm
+ 139855429U, // Int_CVTTSD2SIrr
+ 140641872U, // Int_CVTTSS2SI64rm
+ 139855440U, // Int_CVTTSS2SI64rr
+ 140641872U, // Int_CVTTSS2SIrm
+ 139855440U, // Int_CVTTSS2SIrr
+ 140380651U, // Int_UCOMISDrm
+ 139856363U, // Int_UCOMISDrr
+ 140380660U, // Int_UCOMISSrm
+ 139856372U, // Int_UCOMISSrr
+ 1073744381U, // JA
+ 1073744381U, // JA8
+ 1073744385U, // JAE
+ 1073744385U, // JAE8
+ 1073744390U, // JB
+ 1073744390U, // JB8
+ 1073744394U, // JBE
+ 1073744394U, // JBE8
+ 1073744399U, // JCXZ8
+ 1073744405U, // JE
+ 1073744405U, // JE8
+ 1073744409U, // JG
+ 1073744409U, // JG8
+ 1073744413U, // JGE
+ 1073744413U, // JGE8
+ 1073744418U, // JL
+ 1073744418U, // JL8
+ 1073744422U, // JLE
+ 1073744422U, // JLE8
+ 1073744427U, // JMP
+ 402655787U, // JMP32m
+ 134220331U, // JMP32r
+ 536873515U, // JMP64m
+ 134220331U, // JMP64r
+ 1073744427U, // JMP8
+ 1073744432U, // JNE
+ 1073744432U, // JNE8
+ 1073744437U, // JNO
+ 1073744437U, // JNO8
+ 1073744442U, // JNP
+ 1073744442U, // JNP8
+ 1073744447U, // JNS
+ 1073744447U, // JNS8
+ 1073744452U, // JO
+ 1073744452U, // JO8
+ 1073744456U, // JP
+ 1073744456U, // JP8
+ 1073744460U, // JS
+ 1073744460U, // JS8
+ 2640U, // LAHF
+ 139725397U, // LAR16rm
+ 139856469U, // LAR16rr
+ 139725397U, // LAR32rm
+ 139856469U, // LAR32rr
+ 139725397U, // LAR64rm
+ 139856469U, // LAR64rr
+ 272632410U, // LCMPXCHG16
+ 406850138U, // LCMPXCHG32
+ 1879050857U, // LCMPXCHG64
+ 675285594U, // LCMPXCHG8
+ 402655865U, // LCMPXCHG8B
+ 140905098U, // LDDQUrm
+ 402655889U, // LDMXCSR
+ 2714U, // LD_F0
+ 2719U, // LD_F1
+ 805309092U, // LD_F32m
+ 939526820U, // LD_F64m
+ 2013268644U, // LD_F80m
+ 0U, // LD_Fp032
+ 0U, // LD_Fp064
+ 0U, // LD_Fp080
+ 0U, // LD_Fp132
+ 0U, // LD_Fp164
+ 0U, // LD_Fp180
+ 0U, // LD_Fp32m
+ 0U, // LD_Fp32m64
+ 0U, // LD_Fp32m80
+ 0U, // LD_Fp64m
+ 0U, // LD_Fp64m80
+ 0U, // LD_Fp80m
+ 134220452U, // LD_Frr
+ 141036201U, // LEA16r
+ 141036201U, // LEA32r
+ 141167273U, // LEA64_32r
+ 141298345U, // LEA64r
+ 2734U, // LEAVE
+ 2734U, // LEAVE64
+ 2740U, // LFENCE
+ 272632507U, // LOCK_ADD16mi
+ 272632507U, // LOCK_ADD16mi8
+ 272632507U, // LOCK_ADD16mr
+ 406850235U, // LOCK_ADD32mi
+ 406850235U, // LOCK_ADD32mi8
+ 406850235U, // LOCK_ADD32mr
+ 541067963U, // LOCK_ADD64mi32
+ 541067963U, // LOCK_ADD64mi8
+ 541067963U, // LOCK_ADD64mr
+ 675285691U, // LOCK_ADD8mi
+ 675285691U, // LOCK_ADD8mr
+ 268438214U, // LOCK_DEC16m
+ 402655942U, // LOCK_DEC32m
+ 536873670U, // LOCK_DEC64m
+ 671091398U, // LOCK_DEC8m
+ 268438225U, // LOCK_INC16m
+ 402655953U, // LOCK_INC32m
+ 536873681U, // LOCK_INC64m
+ 671091409U, // LOCK_INC8m
+ 272632540U, // LOCK_SUB16mi
+ 272632540U, // LOCK_SUB16mi8
+ 272632540U, // LOCK_SUB16mr
+ 406850268U, // LOCK_SUB32mi
+ 406850268U, // LOCK_SUB32mi8
+ 406850268U, // LOCK_SUB32mr
+ 541067996U, // LOCK_SUB64mi32
+ 541067996U, // LOCK_SUB64mi8
+ 541067996U, // LOCK_SUB64mr
+ 675285724U, // LOCK_SUB8mi
+ 675285724U, // LOCK_SUB8mr
+ 2791U, // LODSB
+ 2797U, // LODSD
+ 2803U, // LODSQ
+ 2809U, // LODSW
+ 1073744639U, // LOOP
+ 1073744645U, // LOOPE
+ 1073744652U, // LOOPNE
+ 2836U, // LRET
+ 134220569U, // LRETI
+ 2147486495U, // LXADD16
+ 1799359263U, // LXADD32
+ 2281704223U, // LXADD64
+ 2415921951U, // LXADD8
+ 139856683U, // MASKMOVDQU
+ 139856683U, // MASKMOVDQU64
+ 139201335U, // MAXPDrm
+ 139201335U, // MAXPDrm_Int
+ 138545975U, // MAXPDrr
+ 138545975U, // MAXPDrr_Int
+ 139201342U, // MAXPSrm
+ 139201342U, // MAXPSrm_Int
+ 138545982U, // MAXPSrr
+ 138545982U, // MAXPSrr_Int
+ 139332421U, // MAXSDrm
+ 139332421U, // MAXSDrm_Int
+ 138545989U, // MAXSDrr
+ 138545989U, // MAXSDrr_Int
+ 139463500U, // MAXSSrm
+ 139463500U, // MAXSSrm_Int
+ 138545996U, // MAXSSrr
+ 138545996U, // MAXSSrr_Int
+ 2899U, // MFENCE
+ 139201370U, // MINPDrm
+ 139201370U, // MINPDrm_Int
+ 138546010U, // MINPDrr
+ 138546010U, // MINPDrr_Int
+ 139201377U, // MINPSrm
+ 139201377U, // MINPSrm_Int
+ 138546017U, // MINPSrr
+ 138546017U, // MINPSrr_Int
+ 139332456U, // MINSDrm
+ 139332456U, // MINSDrm_Int
+ 138546024U, // MINSDrr
+ 138546024U, // MINSDrr_Int
+ 139463535U, // MINSSrm
+ 139463535U, // MINSSrm_Int
+ 138546031U, // MINSSrr
+ 138546031U, // MINSSrr_Int
+ 140380527U, // MMX_CVTPD2PIrm
+ 139856239U, // MMX_CVTPD2PIrr
+ 140118403U, // MMX_CVTPI2PDrm
+ 139856259U, // MMX_CVTPI2PDrr
+ 140118413U, // MMX_CVTPI2PSrm
+ 139856269U, // MMX_CVTPI2PSrr
+ 140511649U, // MMX_CVTPS2PIrm
+ 139856289U, // MMX_CVTPS2PIrr
+ 140380618U, // MMX_CVTTPD2PIrm
+ 139856330U, // MMX_CVTTPD2PIrr
+ 140511712U, // MMX_CVTTPS2PIrm
+ 139856352U, // MMX_CVTTPS2PIrr
+ 2934U, // MMX_EMMS
+ 2939U, // MMX_FEMMS
+ 139856769U, // MMX_MASKMOVQ
+ 139856769U, // MMX_MASKMOVQ64
+ 139856779U, // MMX_MOVD64from64rr
+ 406850443U, // MMX_MOVD64mr
+ 139987851U, // MMX_MOVD64rm
+ 139856779U, // MMX_MOVD64rr
+ 139856779U, // MMX_MOVD64rrv164
+ 139856779U, // MMX_MOVD64to64rr
+ 139856785U, // MMX_MOVDQ2Qrr
+ 541068186U, // MMX_MOVNTQmr
+ 139856802U, // MMX_MOVQ2DQrr
+ 139856802U, // MMX_MOVQ2FR64rr
+ 541068203U, // MMX_MOVQ64mr
+ 140118955U, // MMX_MOVQ64rm
+ 139856811U, // MMX_MOVQ64rr
+ 139987851U, // MMX_MOVZDI2PDIrm
+ 139856779U, // MMX_MOVZDI2PDIrr
+ 138939313U, // MMX_PACKSSDWrm
+ 138546097U, // MMX_PACKSSDWrr
+ 138939323U, // MMX_PACKSSWBrm
+ 138546107U, // MMX_PACKSSWBrr
+ 138939333U, // MMX_PACKUSWBrm
+ 138546117U, // MMX_PACKUSWBrr
+ 138939343U, // MMX_PADDBrm
+ 138546127U, // MMX_PADDBrr
+ 138939350U, // MMX_PADDDrm
+ 138546134U, // MMX_PADDDrr
+ 138939357U, // MMX_PADDQrm
+ 138546141U, // MMX_PADDQrr
+ 138939364U, // MMX_PADDSBrm
+ 138546148U, // MMX_PADDSBrr
+ 138939372U, // MMX_PADDSWrm
+ 138546156U, // MMX_PADDSWrr
+ 138939380U, // MMX_PADDUSBrm
+ 138546164U, // MMX_PADDUSBrr
+ 138939389U, // MMX_PADDUSWrm
+ 138546173U, // MMX_PADDUSWrr
+ 138939398U, // MMX_PADDWrm
+ 138546182U, // MMX_PADDWrr
+ 138939405U, // MMX_PANDNrm
+ 138546189U, // MMX_PANDNrr
+ 138939412U, // MMX_PANDrm
+ 138546196U, // MMX_PANDrr
+ 138939418U, // MMX_PAVGBrm
+ 138546202U, // MMX_PAVGBrr
+ 138939425U, // MMX_PAVGWrm
+ 138546209U, // MMX_PAVGWrr
+ 138939432U, // MMX_PCMPEQBrm
+ 138546216U, // MMX_PCMPEQBrr
+ 138939441U, // MMX_PCMPEQDrm
+ 138546225U, // MMX_PCMPEQDrr
+ 138939450U, // MMX_PCMPEQWrm
+ 138546234U, // MMX_PCMPEQWrr
+ 138939459U, // MMX_PCMPGTBrm
+ 138546243U, // MMX_PCMPGTBrr
+ 138939468U, // MMX_PCMPGTDrm
+ 138546252U, // MMX_PCMPGTDrr
+ 138939477U, // MMX_PCMPGTWrm
+ 138546261U, // MMX_PCMPGTWrr
+ 139873374U, // MMX_PEXTRWri
+ 138693734U, // MMX_PINSRWrmi
+ 138562662U, // MMX_PINSRWrri
+ 138939502U, // MMX_PMADDWDrm
+ 138546286U, // MMX_PMADDWDrr
+ 138939511U, // MMX_PMAXSWrm
+ 138546295U, // MMX_PMAXSWrr
+ 138939519U, // MMX_PMAXUBrm
+ 138546303U, // MMX_PMAXUBrr
+ 138939527U, // MMX_PMINSWrm
+ 138546311U, // MMX_PMINSWrr
+ 138939535U, // MMX_PMINUBrm
+ 138546319U, // MMX_PMINUBrr
+ 139857047U, // MMX_PMOVMSKBrr
+ 138939553U, // MMX_PMULHUWrm
+ 138546337U, // MMX_PMULHUWrr
+ 138939562U, // MMX_PMULHWrm
+ 138546346U, // MMX_PMULHWrr
+ 138939570U, // MMX_PMULLWrm
+ 138546354U, // MMX_PMULLWrr
+ 138939578U, // MMX_PMULUDQrm
+ 138546362U, // MMX_PMULUDQrr
+ 138939587U, // MMX_PORrm
+ 138546371U, // MMX_PORrr
+ 138939592U, // MMX_PSADBWrm
+ 138546376U, // MMX_PSADBWrr
+ 140135632U, // MMX_PSHUFWmi
+ 139873488U, // MMX_PSHUFWri
+ 138546392U, // MMX_PSLLDri
+ 138939608U, // MMX_PSLLDrm
+ 138546392U, // MMX_PSLLDrr
+ 138546399U, // MMX_PSLLQri
+ 138939615U, // MMX_PSLLQrm
+ 138546399U, // MMX_PSLLQrr
+ 138546406U, // MMX_PSLLWri
+ 138939622U, // MMX_PSLLWrm
+ 138546406U, // MMX_PSLLWrr
+ 138546413U, // MMX_PSRADri
+ 138939629U, // MMX_PSRADrm
+ 138546413U, // MMX_PSRADrr
+ 138546420U, // MMX_PSRAWri
+ 138939636U, // MMX_PSRAWrm
+ 138546420U, // MMX_PSRAWrr
+ 138546427U, // MMX_PSRLDri
+ 138939643U, // MMX_PSRLDrm
+ 138546427U, // MMX_PSRLDrr
+ 138546434U, // MMX_PSRLQri
+ 138939650U, // MMX_PSRLQrm
+ 138546434U, // MMX_PSRLQrr
+ 138546441U, // MMX_PSRLWri
+ 138939657U, // MMX_PSRLWrm
+ 138546441U, // MMX_PSRLWrr
+ 138939664U, // MMX_PSUBBrm
+ 138546448U, // MMX_PSUBBrr
+ 138939671U, // MMX_PSUBDrm
+ 138546455U, // MMX_PSUBDrr
+ 138939678U, // MMX_PSUBQrm
+ 138546462U, // MMX_PSUBQrr
+ 138939685U, // MMX_PSUBSBrm
+ 138546469U, // MMX_PSUBSBrr
+ 138939693U, // MMX_PSUBSWrm
+ 138546477U, // MMX_PSUBSWrr
+ 138939701U, // MMX_PSUBUSBrm
+ 138546485U, // MMX_PSUBUSBrr
+ 138939710U, // MMX_PSUBUSWrm
+ 138546494U, // MMX_PSUBUSWrr
+ 138939719U, // MMX_PSUBWrm
+ 138546503U, // MMX_PSUBWrr
+ 138939726U, // MMX_PUNPCKHBWrm
+ 138546510U, // MMX_PUNPCKHBWrr
+ 138939737U, // MMX_PUNPCKHDQrm
+ 138546521U, // MMX_PUNPCKHDQrr
+ 138939748U, // MMX_PUNPCKHWDrm
+ 138546532U, // MMX_PUNPCKHWDrr
+ 138939759U, // MMX_PUNPCKLBWrm
+ 138546543U, // MMX_PUNPCKLBWrr
+ 138939770U, // MMX_PUNPCKLDQrm
+ 138546554U, // MMX_PUNPCKLDQrr
+ 138939781U, // MMX_PUNPCKLWDrm
+ 138546565U, // MMX_PUNPCKLWDrr
+ 138938515U, // MMX_PXORrm
+ 138545299U, // MMX_PXORrr
+ 140773523U, // MMX_V_SET0
+ 140774449U, // MMX_V_SETALLONES
+ 3472U, // MONITOR
+ 192941464U, // MOV16ao16
+ 272633240U, // MOV16mi
+ 272633240U, // MOV16mr
+ 272633240U, // MOV16ms
+ 134221213U, // MOV16o16a
+ 0U, // MOV16r0
+ 139857304U, // MOV16ri
+ 139726232U, // MOV16rm
+ 139857304U, // MOV16rr
+ 139857304U, // MOV16rs
+ 139726232U, // MOV16sm
+ 139857304U, // MOV16sr
+ 197135768U, // MOV32ao32
+ 406850968U, // MOV32mi
+ 406850968U, // MOV32mr
+ 134221223U, // MOV32o32a
+ 140774834U, // MOV32r0
+ 139857304U, // MOV32ri
+ 139988376U, // MOV32rm
+ 139857304U, // MOV32rr
+ 2550140343U, // MOV64FSrm
+ 2550140353U, // MOV64GSrm
+ 201330072U, // MOV64ao32
+ 201330072U, // MOV64ao8
+ 541068696U, // MOV64mi32
+ 541068696U, // MOV64mr
+ 541068696U, // MOV64ms
+ 134221259U, // MOV64o32a
+ 134221259U, // MOV64o8a
+ 139857366U, // MOV64ri
+ 139857304U, // MOV64ri32
+ 0U, // MOV64ri64i32
+ 140119448U, // MOV64rm
+ 139857304U, // MOV64rr
+ 139857304U, // MOV64rs
+ 140119448U, // MOV64sm
+ 139857304U, // MOV64sr
+ 139856811U, // MOV64toPQIrr
+ 140118955U, // MOV64toSDrm
+ 139856811U, // MOV64toSDrr
+ 205524376U, // MOV8ao8
+ 675286424U, // MOV8mi
+ 675286424U, // MOV8mr
+ 675335576U, // MOV8mr_NOREX
+ 134221278U, // MOV8o8a
+ 140774834U, // MOV8r0
+ 139857304U, // MOV8ri
+ 140250520U, // MOV8rm
+ 140299672U, // MOV8rm_NOREX
+ 139857304U, // MOV8rr
+ 139906456U, // MOV8rr_NOREX
+ 2684356761U, // MOVAPDmr
+ 140380313U, // MOVAPDrm
+ 139856025U, // MOVAPDrr
+ 2684356769U, // MOVAPSmr
+ 140380321U, // MOVAPSrm
+ 139856033U, // MOVAPSrr
+ 140512744U, // MOVDDUPrm
+ 139857384U, // MOVDDUPrr
+ 139987851U, // MOVDI2PDIrm
+ 139856779U, // MOVDI2PDIrr
+ 139987851U, // MOVDI2SSrm
+ 139856779U, // MOVDI2SSrr
+ 2818575857U, // MOVDQAmr
+ 140905969U, // MOVDQArm
+ 139857393U, // MOVDQArr
+ 2818575865U, // MOVDQUmr
+ 2818575865U, // MOVDQUmr_Int
+ 140905977U, // MOVDQUrm
+ 140905977U, // MOVDQUrm_Int
+ 138546689U, // MOVHLPSrr
+ 943721994U, // MOVHPDmr
+ 139333130U, // MOVHPDrm
+ 943722002U, // MOVHPSmr
+ 139333138U, // MOVHPSrm
+ 138546714U, // MOVLHPSrr
+ 943722019U, // MOVLPDmr
+ 139333155U, // MOVLPDrm
+ 138546731U, // MOVLPDrr
+ 943722034U, // MOVLPSmr
+ 139333170U, // MOVLPSrm
+ 138546746U, // MOVLPSrr
+ 541068203U, // MOVLQ128mr
+ 138546731U, // MOVLSD2PDrr
+ 138546746U, // MOVLSS2PSrr
+ 139857473U, // MOVMSKPDrr
+ 139857483U, // MOVMSKPSrr
+ 140906069U, // MOVNTDQArm
+ 2684358239U, // MOVNTDQmr
+ 406851176U, // MOVNTImr
+ 2818575984U, // MOVNTPDmr
+ 2818575993U, // MOVNTPSmr
+ 0U, // MOVPC32r
+ 943722027U, // MOVPD2SDmr
+ 139857451U, // MOVPD2SDrr
+ 406850443U, // MOVPDI2DImr
+ 139856779U, // MOVPDI2DIrr
+ 541068203U, // MOVPQI2QImr
+ 139856811U, // MOVPQIto64rr
+ 809504314U, // MOVPS2SSmr
+ 139857466U, // MOVPS2SSrr
+ 140118955U, // MOVQI2PQIrm
+ 140512811U, // MOVSD2PDrm
+ 139857451U, // MOVSD2PDrr
+ 943722027U, // MOVSDmr
+ 140512811U, // MOVSDrm
+ 139857451U, // MOVSDrr
+ 541068203U, // MOVSDto64mr
+ 139856811U, // MOVSDto64rr
+ 140381826U, // MOVSHDUPrm
+ 139857538U, // MOVSHDUPrr
+ 140381836U, // MOVSLDUPrm
+ 139857548U, // MOVSLDUPrr
+ 406850443U, // MOVSS2DImr
+ 139856779U, // MOVSS2DIrr
+ 140643898U, // MOVSS2PSrm
+ 139857466U, // MOVSS2PSrr
+ 809504314U, // MOVSSmr
+ 140643898U, // MOVSSrm
+ 139857466U, // MOVSSrr
+ 0U, // MOVSX16rm8
+ 0U, // MOVSX16rr8
+ 139726486U, // MOVSX32rm16
+ 140250774U, // MOVSX32rm8
+ 139857558U, // MOVSX32rr16
+ 139857558U, // MOVSX32rr8
+ 139726486U, // MOVSX64rm16
+ 139988637U, // MOVSX64rm32
+ 140250774U, // MOVSX64rm8
+ 139857558U, // MOVSX64rr16
+ 139857565U, // MOVSX64rr32
+ 139857558U, // MOVSX64rr8
+ 2684358309U, // MOVUPDmr
+ 2684358309U, // MOVUPDmr_Int
+ 140381861U, // MOVUPDrm
+ 140381861U, // MOVUPDrm_Int
+ 139857573U, // MOVUPDrr
+ 2684358317U, // MOVUPSmr
+ 2684358317U, // MOVUPSmr_Int
+ 140381869U, // MOVUPSrm
+ 140381869U, // MOVUPSrm_Int
+ 139857581U, // MOVUPSrr
+ 139987851U, // MOVZDI2PDIrm
+ 139856779U, // MOVZDI2PDIrr
+ 140905387U, // MOVZPQILo2PQIrm
+ 139856811U, // MOVZPQILo2PQIrr
+ 140118955U, // MOVZQI2PQIrm
+ 139856811U, // MOVZQI2PQIrr
+ 140512811U, // MOVZSD2PDrm
+ 140643898U, // MOVZSS2PSrm
+ 0U, // MOVZX16rm8
+ 0U, // MOVZX16rr8
+ 140299957U, // MOVZX32_NOREXrm8
+ 139906741U, // MOVZX32_NOREXrr8
+ 139726517U, // MOVZX32rm16
+ 140250805U, // MOVZX32rm8
+ 139857589U, // MOVZX32rr16
+ 139857589U, // MOVZX32rr8
+ 0U, // MOVZX64rm16
+ 0U, // MOVZX64rm32
+ 0U, // MOVZX64rm8
+ 0U, // MOVZX64rr16
+ 0U, // MOVZX64rr32
+ 0U, // MOVZX64rr8
+ 0U, // MOV_Fp3232
+ 0U, // MOV_Fp3264
+ 0U, // MOV_Fp3280
+ 0U, // MOV_Fp6432
+ 0U, // MOV_Fp6464
+ 0U, // MOV_Fp6480
+ 0U, // MOV_Fp8032
+ 0U, // MOV_Fp8064
+ 0U, // MOV_Fp8080
+ 139611836U, // MPSADBWrmi
+ 138563260U, // MPSADBWrri
+ 268439237U, // MUL16m
+ 134221509U, // MUL16r
+ 402656965U, // MUL32m
+ 134221509U, // MUL32r
+ 536874693U, // MUL64m
+ 134221509U, // MUL64r
+ 671092421U, // MUL8m
+ 134221509U, // MUL8r
+ 139202250U, // MULPDrm
+ 138546890U, // MULPDrr
+ 139202257U, // MULPSrm
+ 138546897U, // MULPSrr
+ 139333336U, // MULSDrm
+ 139333336U, // MULSDrm_Int
+ 138546904U, // MULSDrr
+ 138546904U, // MULSDrr_Int
+ 139464415U, // MULSSrm
+ 139464415U, // MULSSrm_Int
+ 138546911U, // MULSSrr
+ 138546911U, // MULSSrr_Int
+ 805310182U, // MUL_F32m
+ 939527910U, // MUL_F64m
+ 268439276U, // MUL_FI16m
+ 402657004U, // MUL_FI32m
+ 134221555U, // MUL_FPrST0
+ 134221542U, // MUL_FST0r
+ 0U, // MUL_Fp32
+ 0U, // MUL_Fp32m
+ 0U, // MUL_Fp64
+ 0U, // MUL_Fp64m
+ 0U, // MUL_Fp64m32
+ 0U, // MUL_Fp80
+ 0U, // MUL_Fp80m32
+ 0U, // MUL_Fp80m64
+ 0U, // MUL_FpI16m32
+ 0U, // MUL_FpI16m64
+ 0U, // MUL_FpI16m80
+ 0U, // MUL_FpI32m32
+ 0U, // MUL_FpI32m64
+ 0U, // MUL_FpI32m80
+ 142610150U, // MUL_FrST0
+ 3834U, // MWAIT
+ 268439296U, // NEG16m
+ 134221568U, // NEG16r
+ 402657024U, // NEG32m
+ 134221568U, // NEG32r
+ 536874752U, // NEG64m
+ 134221568U, // NEG64r
+ 671092480U, // NEG8m
+ 134221568U, // NEG8r
+ 3845U, // NOOP
+ 402657033U, // NOOPL
+ 268439311U, // NOT16m
+ 134221583U, // NOT16r
+ 402657039U, // NOT32m
+ 134221583U, // NOT32r
+ 536874767U, // NOT64m
+ 134221583U, // NOT64r
+ 671092495U, // NOT8m
+ 134221583U, // NOT8r
+ 134221588U, // OR16i16
+ 272633629U, // OR16mi
+ 272633629U, // OR16mi8
+ 272633629U, // OR16mr
+ 138546973U, // OR16ri
+ 138546973U, // OR16ri8
+ 138678045U, // OR16rm
+ 138546973U, // OR16rr
+ 134221601U, // OR32i32
+ 406851357U, // OR32mi
+ 406851357U, // OR32mi8
+ 406851357U, // OR32mr
+ 138546973U, // OR32ri
+ 138546973U, // OR32ri8
+ 138809117U, // OR32rm
+ 138546973U, // OR32rr
+ 134221611U, // OR64i32
+ 541069085U, // OR64mi32
+ 541069085U, // OR64mi8
+ 541069085U, // OR64mr
+ 138546973U, // OR64ri32
+ 138546973U, // OR64ri8
+ 138940189U, // OR64rm
+ 138546973U, // OR64rr
+ 134221621U, // OR8i8
+ 675286813U, // OR8mi
+ 675286813U, // OR8mr
+ 138546973U, // OR8ri
+ 139071261U, // OR8rm
+ 138546973U, // OR8rr
+ 139200681U, // ORPDrm
+ 138545321U, // ORPDrr
+ 139200687U, // ORPSrm
+ 138545327U, // ORPSrr
+ 209719102U, // OUT16ir
+ 3907U, // OUT16rr
+ 213913406U, // OUT32ir
+ 3920U, // OUT32rr
+ 218107710U, // OUT8ir
+ 3934U, // OUT8rr
+ 140906347U, // PABSBrm128
+ 140119915U, // PABSBrm64
+ 139857771U, // PABSBrr128
+ 139857771U, // PABSBrr64
+ 140906354U, // PABSDrm128
+ 140119922U, // PABSDrm64
+ 139857778U, // PABSDrr128
+ 139857778U, // PABSDrr64
+ 140906361U, // PABSWrm128
+ 140119929U, // PABSWrm64
+ 139857785U, // PABSWrr128
+ 139857785U, // PABSWrr64
+ 139594673U, // PACKSSDWrm
+ 138546097U, // PACKSSDWrr
+ 139594683U, // PACKSSWBrm
+ 138546107U, // PACKSSWBrr
+ 139595648U, // PACKUSDWrm
+ 138547072U, // PACKUSDWrr
+ 139594693U, // PACKUSWBrm
+ 138546117U, // PACKUSWBrr
+ 139594703U, // PADDBrm
+ 138546127U, // PADDBrr
+ 139594710U, // PADDDrm
+ 138546134U, // PADDDrr
+ 139594717U, // PADDQrm
+ 138546141U, // PADDQrr
+ 139594724U, // PADDSBrm
+ 138546148U, // PADDSBrr
+ 139594732U, // PADDSWrm
+ 138546156U, // PADDSWrr
+ 139594740U, // PADDUSBrm
+ 138546164U, // PADDUSBrr
+ 139594749U, // PADDUSWrm
+ 138546173U, // PADDUSWrr
+ 139594758U, // PADDWrm
+ 138546182U, // PADDWrr
+ 139612042U, // PALIGNR128rm
+ 138563466U, // PALIGNR128rr
+ 138956682U, // PALIGNR64rm
+ 138563466U, // PALIGNR64rr
+ 139594765U, // PANDNrm
+ 138546189U, // PANDNrr
+ 139594772U, // PANDrm
+ 138546196U, // PANDrr
+ 139594778U, // PAVGBrm
+ 138546202U, // PAVGBrr
+ 139594785U, // PAVGWrm
+ 138546209U, // PAVGWrr
+ 139628435U, // PBLENDVBrm0
+ 138579859U, // PBLENDVBrr0
+ 139612061U, // PBLENDWrmi
+ 138563485U, // PBLENDWrri
+ 139594792U, // PCMPEQBrm
+ 138546216U, // PCMPEQBrr
+ 139594801U, // PCMPEQDrm
+ 138546225U, // PCMPEQDrr
+ 139595686U, // PCMPEQQrm
+ 138547110U, // PCMPEQQrr
+ 139594810U, // PCMPEQWrm
+ 138546234U, // PCMPEQWrr
+ 140922799U, // PCMPESTRIArm
+ 139874223U, // PCMPESTRIArr
+ 140922799U, // PCMPESTRICrm
+ 139874223U, // PCMPESTRICrr
+ 140922799U, // PCMPESTRIOrm
+ 139874223U, // PCMPESTRIOrr
+ 140922799U, // PCMPESTRISrm
+ 139874223U, // PCMPESTRISrr
+ 140922799U, // PCMPESTRIZrm
+ 139874223U, // PCMPESTRIZrr
+ 140922799U, // PCMPESTRIrm
+ 139874223U, // PCMPESTRIrr
+ 4026U, // PCMPESTRM128MEM
+ 4050U, // PCMPESTRM128REG
+ 140922858U, // PCMPESTRM128rm
+ 139874282U, // PCMPESTRM128rr
+ 139594819U, // PCMPGTBrm
+ 138546243U, // PCMPGTBrr
+ 139594828U, // PCMPGTDrm
+ 138546252U, // PCMPGTDrr
+ 139595765U, // PCMPGTQrm
+ 138547189U, // PCMPGTQrr
+ 139594837U, // PCMPGTWrm
+ 138546261U, // PCMPGTWrr
+ 140922878U, // PCMPISTRIArm
+ 139874302U, // PCMPISTRIArr
+ 140922878U, // PCMPISTRICrm
+ 139874302U, // PCMPISTRICrr
+ 140922878U, // PCMPISTRIOrm
+ 139874302U, // PCMPISTRIOrr
+ 140922878U, // PCMPISTRISrm
+ 139874302U, // PCMPISTRISrr
+ 140922878U, // PCMPISTRIZrm
+ 139874302U, // PCMPISTRIZrr
+ 140922878U, // PCMPISTRIrm
+ 139874302U, // PCMPISTRIrr
+ 4105U, // PCMPISTRM128MEM
+ 4129U, // PCMPISTRM128REG
+ 140922937U, // PCMPISTRM128rm
+ 139874361U, // PCMPISTRM128rr
+ 675303492U, // PEXTRBmr
+ 139874372U, // PEXTRBrr
+ 406868044U, // PEXTRDmr
+ 139874380U, // PEXTRDrr
+ 541085780U, // PEXTRQmr
+ 139874388U, // PEXTRQrr
+ 272649310U, // PEXTRWmr
+ 139873374U, // PEXTRWri
+ 139595868U, // PHADDDrm128
+ 138940508U, // PHADDDrm64
+ 138547292U, // PHADDDrr128
+ 138547292U, // PHADDDrr64
+ 139595876U, // PHADDSWrm128
+ 138940516U, // PHADDSWrm64
+ 138547300U, // PHADDSWrr128
+ 138547300U, // PHADDSWrr64
+ 139595885U, // PHADDWrm128
+ 138940525U, // PHADDWrm64
+ 138547309U, // PHADDWrr128
+ 138547309U, // PHADDWrr64
+ 140906613U, // PHMINPOSUWrm128
+ 139858037U, // PHMINPOSUWrr128
+ 139595905U, // PHSUBDrm128
+ 138940545U, // PHSUBDrm64
+ 138547329U, // PHSUBDrr128
+ 138547329U, // PHSUBDrr64
+ 139595913U, // PHSUBSWrm128
+ 138940553U, // PHSUBSWrm64
+ 138547337U, // PHSUBSWrr128
+ 138547337U, // PHSUBSWrr64
+ 139595922U, // PHSUBWrm128
+ 138940562U, // PHSUBWrm64
+ 138547346U, // PHSUBWrr128
+ 138547346U, // PHSUBWrr64
+ 139088026U, // PINSRBrm
+ 138563738U, // PINSRBrr
+ 138825890U, // PINSRDrm
+ 138563746U, // PINSRDrr
+ 138956970U, // PINSRQrm
+ 138563754U, // PINSRQrr
+ 138693734U, // PINSRWrmi
+ 138562662U, // PINSRWrri
+ 139595954U, // PMADDUBSWrm128
+ 138940594U, // PMADDUBSWrm64
+ 138547378U, // PMADDUBSWrr128
+ 138547378U, // PMADDUBSWrr64
+ 139594862U, // PMADDWDrm
+ 138546286U, // PMADDWDrr
+ 139595965U, // PMAXSBrm
+ 138547389U, // PMAXSBrr
+ 139595973U, // PMAXSDrm
+ 138547397U, // PMAXSDrr
+ 139594871U, // PMAXSWrm
+ 138546295U, // PMAXSWrr
+ 139594879U, // PMAXUBrm
+ 138546303U, // PMAXUBrr
+ 139595981U, // PMAXUDrm
+ 138547405U, // PMAXUDrr
+ 139595989U, // PMAXUWrm
+ 138547413U, // PMAXUWrr
+ 139595997U, // PMINSBrm
+ 138547421U, // PMINSBrr
+ 139596005U, // PMINSDrm
+ 138547429U, // PMINSDrr
+ 139594887U, // PMINSWrm
+ 138546311U, // PMINSWrr
+ 139594895U, // PMINUBrm
+ 138546319U, // PMINUBrr
+ 139596013U, // PMINUDrm
+ 138547437U, // PMINUDrr
+ 139596021U, // PMINUWrm
+ 138547445U, // PMINUWrr
+ 139857047U, // PMOVMSKBrr
+ 139989245U, // PMOVSXBDrm
+ 139858173U, // PMOVSXBDrr
+ 139727111U, // PMOVSXBQrm
+ 139858183U, // PMOVSXBQrr
+ 140120337U, // PMOVSXBWrm
+ 139858193U, // PMOVSXBWrr
+ 140120347U, // PMOVSXDQrm
+ 139858203U, // PMOVSXDQrr
+ 140120357U, // PMOVSXWDrm
+ 139858213U, // PMOVSXWDrr
+ 139989295U, // PMOVSXWQrm
+ 139858223U, // PMOVSXWQrr
+ 139989305U, // PMOVZXBDrm
+ 139858233U, // PMOVZXBDrr
+ 139727171U, // PMOVZXBQrm
+ 139858243U, // PMOVZXBQrr
+ 140120397U, // PMOVZXBWrm
+ 139858253U, // PMOVZXBWrr
+ 140120407U, // PMOVZXDQrm
+ 139858263U, // PMOVZXDQrr
+ 140120417U, // PMOVZXWDrm
+ 139858273U, // PMOVZXWDrr
+ 139989355U, // PMOVZXWQrm
+ 139858283U, // PMOVZXWQrr
+ 139596149U, // PMULDQrm
+ 138547573U, // PMULDQrr
+ 139596157U, // PMULHRSWrm128
+ 138940797U, // PMULHRSWrm64
+ 138547581U, // PMULHRSWrr128
+ 138547581U, // PMULHRSWrr64
+ 139594913U, // PMULHUWrm
+ 138546337U, // PMULHUWrr
+ 139594922U, // PMULHWrm
+ 138546346U, // PMULHWrr
+ 139596167U, // PMULLDrm
+ 139596167U, // PMULLDrm_int
+ 138547591U, // PMULLDrr
+ 138547591U, // PMULLDrr_int
+ 139594930U, // PMULLWrm
+ 138546354U, // PMULLWrr
+ 139594938U, // PMULUDQrm
+ 138546362U, // PMULUDQrr
+ 134222223U, // POP16r
+ 268439951U, // POP16rmm
+ 134222223U, // POP16rmr
+ 134222223U, // POP32r
+ 402657679U, // POP32rmm
+ 134222223U, // POP32rmr
+ 134222223U, // POP64r
+ 536875407U, // POP64rmm
+ 134222223U, // POP64rmr
+ 4500U, // POPFD
+ 4500U, // POPFQ
+ 139594947U, // PORrm
+ 138546371U, // PORrr
+ 671093145U, // PREFETCHNTA
+ 671093158U, // PREFETCHT0
+ 671093170U, // PREFETCHT1
+ 671093182U, // PREFETCHT2
+ 139594952U, // PSADBWrm
+ 138546376U, // PSADBWrr
+ 139596234U, // PSHUFBrm128
+ 138940874U, // PSHUFBrm64
+ 138547658U, // PSHUFBrr128
+ 138547658U, // PSHUFBrr64
+ 140923346U, // PSHUFDmi
+ 139874770U, // PSHUFDri
+ 140923354U, // PSHUFHWmi
+ 139874778U, // PSHUFHWri
+ 140923363U, // PSHUFLWmi
+ 139874787U, // PSHUFLWri
+ 139596268U, // PSIGNBrm128
+ 138940908U, // PSIGNBrm64
+ 138547692U, // PSIGNBrr128
+ 138547692U, // PSIGNBrr64
+ 139596276U, // PSIGNDrm128
+ 138940916U, // PSIGNDrm64
+ 138547700U, // PSIGNDrr128
+ 138547700U, // PSIGNDrr64
+ 139596284U, // PSIGNWrm128
+ 138940924U, // PSIGNWrm64
+ 138547708U, // PSIGNWrr128
+ 138547708U, // PSIGNWrr64
+ 138547716U, // PSLLDQri
+ 138546392U, // PSLLDri
+ 139594968U, // PSLLDrm
+ 138546392U, // PSLLDrr
+ 138546399U, // PSLLQri
+ 139594975U, // PSLLQrm
+ 138546399U, // PSLLQrr
+ 138546406U, // PSLLWri
+ 139594982U, // PSLLWrm
+ 138546406U, // PSLLWrr
+ 138546413U, // PSRADri
+ 139594989U, // PSRADrm
+ 138546413U, // PSRADrr
+ 138546420U, // PSRAWri
+ 139594996U, // PSRAWrm
+ 138546420U, // PSRAWrr
+ 138547724U, // PSRLDQri
+ 138546427U, // PSRLDri
+ 139595003U, // PSRLDrm
+ 138546427U, // PSRLDrr
+ 138546434U, // PSRLQri
+ 139595010U, // PSRLQrm
+ 138546434U, // PSRLQrr
+ 138546441U, // PSRLWri
+ 139595017U, // PSRLWrm
+ 138546441U, // PSRLWrr
+ 139595024U, // PSUBBrm
+ 138546448U, // PSUBBrr
+ 139595031U, // PSUBDrm
+ 138546455U, // PSUBDrr
+ 139595038U, // PSUBQrm
+ 138546462U, // PSUBQrr
+ 139595045U, // PSUBSBrm
+ 138546469U, // PSUBSBrr
+ 139595053U, // PSUBSWrm
+ 138546477U, // PSUBSWrr
+ 139595061U, // PSUBUSBrm
+ 138546485U, // PSUBUSBrr
+ 139595070U, // PSUBUSWrm
+ 138546494U, // PSUBUSWrr
+ 139595079U, // PSUBWrm
+ 138546503U, // PSUBWrr
+ 140907028U, // PTESTrm
+ 139858452U, // PTESTrr
+ 139595086U, // PUNPCKHBWrm
+ 138546510U, // PUNPCKHBWrr
+ 139595097U, // PUNPCKHDQrm
+ 138546521U, // PUNPCKHDQrr
+ 139596316U, // PUNPCKHQDQrm
+ 138547740U, // PUNPCKHQDQrr
+ 139595108U, // PUNPCKHWDrm
+ 138546532U, // PUNPCKHWDrr
+ 139595119U, // PUNPCKLBWrm
+ 138546543U, // PUNPCKLBWrr
+ 139595130U, // PUNPCKLDQrm
+ 138546554U, // PUNPCKLDQrr
+ 139596328U, // PUNPCKLQDQrm
+ 138547752U, // PUNPCKLQDQrr
+ 139595141U, // PUNPCKLWDrm
+ 138546565U, // PUNPCKLWDrr
+ 134222388U, // PUSH16r
+ 268440116U, // PUSH16rmm
+ 134222388U, // PUSH16rmr
+ 134222388U, // PUSH32i16
+ 134222388U, // PUSH32i32
+ 134222388U, // PUSH32i8
+ 134222388U, // PUSH32r
+ 402657844U, // PUSH32rmm
+ 134222388U, // PUSH32rmr
+ 134222388U, // PUSH64i16
+ 134222388U, // PUSH64i32
+ 134222388U, // PUSH64i8
+ 134222388U, // PUSH64r
+ 536875572U, // PUSH64rmm
+ 134222388U, // PUSH64rmr
+ 4666U, // PUSHFD
+ 4666U, // PUSHFQ
+ 139593875U, // PXORrm
+ 138545299U, // PXORrr
+ 356520512U, // RCL16m1
+ 360714816U, // RCL16mCL
+ 275649088U, // RCL16mi
+ 222302784U, // RCL16r1
+ 226497088U, // RCL16rCL
+ 138547776U, // RCL16ri
+ 490738240U, // RCL32m1
+ 494932544U, // RCL32mCL
+ 409866816U, // RCL32mi
+ 222302784U, // RCL32r1
+ 226497088U, // RCL32rCL
+ 138547776U, // RCL32ri
+ 624955968U, // RCL64m1
+ 629150272U, // RCL64mCL
+ 544084544U, // RCL64mi
+ 222302784U, // RCL64r1
+ 226497088U, // RCL64rCL
+ 138547776U, // RCL64ri
+ 759173696U, // RCL8m1
+ 763368000U, // RCL8mCL
+ 678302272U, // RCL8mi
+ 222302784U, // RCL8r1
+ 226497088U, // RCL8rCL
+ 138547776U, // RCL8ri
+ 140382789U, // RCPPSm
+ 140382789U, // RCPPSm_Int
+ 139858501U, // RCPPSr
+ 139858501U, // RCPPSr_Int
+ 140644940U, // RCPSSm
+ 140644940U, // RCPSSm_Int
+ 139858508U, // RCPSSr
+ 139858508U, // RCPSSr_Int
+ 356520531U, // RCR16m1
+ 360714835U, // RCR16mCL
+ 275649107U, // RCR16mi
+ 222302803U, // RCR16r1
+ 226497107U, // RCR16rCL
+ 138547795U, // RCR16ri
+ 490738259U, // RCR32m1
+ 494932563U, // RCR32mCL
+ 409866835U, // RCR32mi
+ 222302803U, // RCR32r1
+ 226497107U, // RCR32rCL
+ 138547795U, // RCR32ri
+ 624955987U, // RCR64m1
+ 629150291U, // RCR64mCL
+ 544084563U, // RCR64mi
+ 222302803U, // RCR64r1
+ 226497107U, // RCR64rCL
+ 138547795U, // RCR64ri
+ 759173715U, // RCR8m1
+ 763368019U, // RCR8mCL
+ 678302291U, // RCR8mi
+ 222302803U, // RCR8r1
+ 226497107U, // RCR8rCL
+ 138547795U, // RCR8ri
+ 4696U, // RDTSC
+ 4702U, // REP_MOVSB
+ 4712U, // REP_MOVSD
+ 4722U, // REP_MOVSQ
+ 4732U, // REP_MOVSW
+ 4742U, // REP_STOSB
+ 4752U, // REP_STOSD
+ 4762U, // REP_STOSQ
+ 4772U, // REP_STOSW
+ 4782U, // RET
+ 134222514U, // RETI
+ 268440247U, // ROL16m1
+ 360714935U, // ROL16mCL
+ 272634551U, // ROL16mi
+ 134222519U, // ROL16r1
+ 226497207U, // ROL16rCL
+ 138547895U, // ROL16ri
+ 402657975U, // ROL32m1
+ 494932663U, // ROL32mCL
+ 406852279U, // ROL32mi
+ 134222519U, // ROL32r1
+ 226497207U, // ROL32rCL
+ 138547895U, // ROL32ri
+ 536875703U, // ROL64m1
+ 633344695U, // ROL64mCL
+ 541070007U, // ROL64mi
+ 134222519U, // ROL64r1
+ 230691511U, // ROL64rCL
+ 138547895U, // ROL64ri
+ 671093431U, // ROL8m1
+ 763368119U, // ROL8mCL
+ 675287735U, // ROL8mi
+ 134222519U, // ROL8r1
+ 226497207U, // ROL8rCL
+ 138547895U, // ROL8ri
+ 268440252U, // ROR16m1
+ 360714940U, // ROR16mCL
+ 272634556U, // ROR16mi
+ 134222524U, // ROR16r1
+ 226497212U, // ROR16rCL
+ 138547900U, // ROR16ri
+ 402657980U, // ROR32m1
+ 494932668U, // ROR32mCL
+ 406852284U, // ROR32mi
+ 134222524U, // ROR32r1
+ 226497212U, // ROR32rCL
+ 138547900U, // ROR32ri
+ 536875708U, // ROR64m1
+ 633344700U, // ROR64mCL
+ 541070012U, // ROR64mi
+ 134222524U, // ROR64r1
+ 230691516U, // ROR64rCL
+ 138547900U, // ROR64ri
+ 671093436U, // ROR8m1
+ 763368124U, // ROR8mCL
+ 675287740U, // ROR8mi
+ 134222524U, // ROR8r1
+ 226497212U, // ROR8rCL
+ 138547900U, // ROR8ri
+ 140399297U, // ROUNDPDm_Int
+ 139875009U, // ROUNDPDr_Int
+ 140399306U, // ROUNDPSm_Int
+ 139875018U, // ROUNDPSr_Int
+ 139350739U, // ROUNDSDm_Int
+ 138564307U, // ROUNDSDr_Int
+ 139481820U, // ROUNDSSm_Int
+ 138564316U, // ROUNDSSr_Int
+ 140382949U, // RSQRTPSm
+ 140382949U, // RSQRTPSm_Int
+ 139858661U, // RSQRTPSr
+ 139858661U, // RSQRTPSr_Int
+ 140645102U, // RSQRTSSm
+ 140645102U, // RSQRTSSm_Int
+ 139858670U, // RSQRTSSr
+ 139858670U, // RSQRTSSr_Int
+ 4855U, // SAHF
+ 268440316U, // SAR16m1
+ 360715004U, // SAR16mCL
+ 272634620U, // SAR16mi
+ 134222588U, // SAR16r1
+ 226497276U, // SAR16rCL
+ 138547964U, // SAR16ri
+ 402658044U, // SAR32m1
+ 494932732U, // SAR32mCL
+ 406852348U, // SAR32mi
+ 134222588U, // SAR32r1
+ 226497276U, // SAR32rCL
+ 138547964U, // SAR32ri
+ 536875772U, // SAR64m1
+ 633344764U, // SAR64mCL
+ 541070076U, // SAR64mi
+ 134222588U, // SAR64r1
+ 230691580U, // SAR64rCL
+ 138547964U, // SAR64ri
+ 671093500U, // SAR8m1
+ 763368188U, // SAR8mCL
+ 675287804U, // SAR8mi
+ 134222588U, // SAR8r1
+ 226497276U, // SAR8rCL
+ 138547964U, // SAR8ri
+ 134222593U, // SBB16i16
+ 272634635U, // SBB16mi
+ 272634635U, // SBB16mi8
+ 272634635U, // SBB16mr
+ 138547979U, // SBB16ri
+ 138547979U, // SBB16ri8
+ 138679051U, // SBB16rm
+ 138547979U, // SBB16rr
+ 134222608U, // SBB32i32
+ 406852363U, // SBB32mi
+ 406852363U, // SBB32mi8
+ 406852363U, // SBB32mr
+ 138547979U, // SBB32ri
+ 138547979U, // SBB32ri8
+ 138810123U, // SBB32rm
+ 138547979U, // SBB32rr
+ 134222619U, // SBB64i32
+ 541070091U, // SBB64mi32
+ 541070091U, // SBB64mi8
+ 541070091U, // SBB64mr
+ 138547979U, // SBB64ri32
+ 138547979U, // SBB64ri8
+ 138941195U, // SBB64rm
+ 138547979U, // SBB64rr
+ 134222630U, // SBB8i8
+ 675287819U, // SBB8mi
+ 675287819U, // SBB8mr
+ 138547979U, // SBB8ri
+ 139072267U, // SBB8rm
+ 138547979U, // SBB8rr
+ 4912U, // SCAS16
+ 4912U, // SCAS32
+ 4912U, // SCAS64
+ 4912U, // SCAS8
+ 671093557U, // SETAEm
+ 134222645U, // SETAEr
+ 671093564U, // SETAm
+ 134222652U, // SETAr
+ 671093570U, // SETBEm
+ 134222658U, // SETBEr
+ 140776203U, // SETB_C16r
+ 140776203U, // SETB_C32r
+ 140776203U, // SETB_C64r
+ 140776203U, // SETB_C8r
+ 671093577U, // SETBm
+ 134222665U, // SETBr
+ 671093583U, // SETEm
+ 134222671U, // SETEr
+ 671093589U, // SETGEm
+ 134222677U, // SETGEr
+ 671093596U, // SETGm
+ 134222684U, // SETGr
+ 671093602U, // SETLEm
+ 134222690U, // SETLEr
+ 671093609U, // SETLm
+ 134222697U, // SETLr
+ 671093615U, // SETNEm
+ 134222703U, // SETNEr
+ 671093622U, // SETNOm
+ 134222710U, // SETNOr
+ 671093629U, // SETNPm
+ 134222717U, // SETNPr
+ 671093636U, // SETNSm
+ 134222724U, // SETNSr
+ 671093643U, // SETOm
+ 134222731U, // SETOr
+ 671093649U, // SETPm
+ 134222737U, // SETPr
+ 671093655U, // SETSm
+ 134222743U, // SETSr
+ 5021U, // SFENCE
+ 268440484U, // SHL16m1
+ 360715172U, // SHL16mCL
+ 272634788U, // SHL16mi
+ 134222756U, // SHL16r1
+ 226497444U, // SHL16rCL
+ 138548132U, // SHL16ri
+ 402658212U, // SHL32m1
+ 494932900U, // SHL32mCL
+ 406852516U, // SHL32mi
+ 134222756U, // SHL32r1
+ 226497444U, // SHL32rCL
+ 138548132U, // SHL32ri
+ 536875940U, // SHL64m1
+ 633344932U, // SHL64mCL
+ 541070244U, // SHL64mi
+ 134222761U, // SHL64r1
+ 230691748U, // SHL64rCL
+ 138548132U, // SHL64ri
+ 671093668U, // SHL8m1
+ 763368356U, // SHL8mCL
+ 675287972U, // SHL8mi
+ 134222756U, // SHL8r1
+ 226497444U, // SHL8rCL
+ 138548132U, // SHL8ri
+ 272700334U, // SHLD16mrCL
+ 272651182U, // SHLD16mri8
+ 138613678U, // SHLD16rrCL
+ 138564526U, // SHLD16rri8
+ 406918062U, // SHLD32mrCL
+ 406868910U, // SHLD32mri8
+ 138613678U, // SHLD32rrCL
+ 138564526U, // SHLD32rri8
+ 541152174U, // SHLD64mrCL
+ 541086638U, // SHLD64mri8
+ 138630062U, // SHLD64rrCL
+ 138564526U, // SHLD64rri8
+ 268440489U, // SHR16m1
+ 360715177U, // SHR16mCL
+ 272634793U, // SHR16mi
+ 134222761U, // SHR16r1
+ 226497449U, // SHR16rCL
+ 138548137U, // SHR16ri
+ 402658217U, // SHR32m1
+ 494932905U, // SHR32mCL
+ 406852521U, // SHR32mi
+ 134222761U, // SHR32r1
+ 226497449U, // SHR32rCL
+ 138548137U, // SHR32ri
+ 536875945U, // SHR64m1
+ 633344937U, // SHR64mCL
+ 541070249U, // SHR64mi
+ 134222761U, // SHR64r1
+ 230691753U, // SHR64rCL
+ 138548137U, // SHR64ri
+ 671093673U, // SHR8m1
+ 763368361U, // SHR8mCL
+ 675287977U, // SHR8mi
+ 134222761U, // SHR8r1
+ 226497449U, // SHR8rCL
+ 138548137U, // SHR8ri
+ 272700340U, // SHRD16mrCL
+ 272651188U, // SHRD16mri8
+ 138613684U, // SHRD16rrCL
+ 138564532U, // SHRD16rri8
+ 406918068U, // SHRD32mrCL
+ 406868916U, // SHRD32mri8
+ 138613684U, // SHRD32rrCL
+ 138564532U, // SHRD32rri8
+ 541152180U, // SHRD64mrCL
+ 541086644U, // SHRD64mri8
+ 138630068U, // SHRD64rrCL
+ 138564532U, // SHRD64rri8
+ 139219898U, // SHUFPDrmi
+ 138564538U, // SHUFPDrri
+ 139219906U, // SHUFPSrmi
+ 138564546U, // SHUFPSrri
+ 5066U, // SIN_F
+ 0U, // SIN_Fp32
+ 0U, // SIN_Fp64
+ 0U, // SIN_Fp80
+ 140383183U, // SQRTPDm
+ 140383183U, // SQRTPDm_Int
+ 139858895U, // SQRTPDr
+ 139858895U, // SQRTPDr_Int
+ 140383191U, // SQRTPSm
+ 140383191U, // SQRTPSm_Int
+ 139858903U, // SQRTPSr
+ 139858903U, // SQRTPSr_Int
+ 140514271U, // SQRTSDm
+ 140514271U, // SQRTSDm_Int
+ 139858911U, // SQRTSDr
+ 139858911U, // SQRTSDr_Int
+ 140645351U, // SQRTSSm
+ 140645351U, // SQRTSSm_Int
+ 139858919U, // SQRTSSr
+ 139858919U, // SQRTSSr_Int
+ 5103U, // SQRT_F
+ 0U, // SQRT_Fp32
+ 0U, // SQRT_Fp64
+ 0U, // SQRT_Fp80
+ 402658293U, // STMXCSR
+ 805311486U, // ST_F32m
+ 939529214U, // ST_F64m
+ 805311491U, // ST_FP32m
+ 939529219U, // ST_FP64m
+ 2013271043U, // ST_FP80m
+ 134222851U, // ST_FPrr
+ 0U, // ST_Fp32m
+ 0U, // ST_Fp64m
+ 0U, // ST_Fp64m32
+ 0U, // ST_Fp80m32
+ 0U, // ST_Fp80m64
+ 0U, // ST_FpP32m
+ 0U, // ST_FpP64m
+ 0U, // ST_FpP64m32
+ 0U, // ST_FpP80m
+ 0U, // ST_FpP80m32
+ 0U, // ST_FpP80m64
+ 134222846U, // ST_Frr
+ 134222857U, // SUB16i16
+ 272634899U, // SUB16mi
+ 272634899U, // SUB16mi8
+ 272634899U, // SUB16mr
+ 138548243U, // SUB16ri
+ 138548243U, // SUB16ri8
+ 138679315U, // SUB16rm
+ 138548243U, // SUB16rr
+ 134222872U, // SUB32i32
+ 406852627U, // SUB32mi
+ 406852627U, // SUB32mi8
+ 406852627U, // SUB32mr
+ 138548243U, // SUB32ri
+ 138548243U, // SUB32ri8
+ 138810387U, // SUB32rm
+ 138548243U, // SUB32rr
+ 134222883U, // SUB64i32
+ 541070355U, // SUB64mi32
+ 541070355U, // SUB64mi8
+ 541070355U, // SUB64mr
+ 138548243U, // SUB64ri32
+ 138548243U, // SUB64ri8
+ 138941459U, // SUB64rm
+ 138548243U, // SUB64rr
+ 134222894U, // SUB8i8
+ 675288083U, // SUB8mi
+ 675288083U, // SUB8mr
+ 138548243U, // SUB8ri
+ 139072531U, // SUB8rm
+ 138548243U, // SUB8rr
+ 139203640U, // SUBPDrm
+ 138548280U, // SUBPDrr
+ 139203647U, // SUBPSrm
+ 138548287U, // SUBPSrr
+ 805311558U, // SUBR_F32m
+ 939529286U, // SUBR_F64m
+ 268440653U, // SUBR_FI16m
+ 402658381U, // SUBR_FI32m
+ 134222933U, // SUBR_FPrST0
+ 134222918U, // SUBR_FST0r
+ 0U, // SUBR_Fp32m
+ 0U, // SUBR_Fp64m
+ 0U, // SUBR_Fp64m32
+ 0U, // SUBR_Fp80m32
+ 0U, // SUBR_Fp80m64
+ 0U, // SUBR_FpI16m32
+ 0U, // SUBR_FpI16m64
+ 0U, // SUBR_FpI16m80
+ 0U, // SUBR_FpI32m32
+ 0U, // SUBR_FpI32m64
+ 0U, // SUBR_FpI32m80
+ 142611526U, // SUBR_FrST0
+ 139334749U, // SUBSDrm
+ 139334749U, // SUBSDrm_Int
+ 138548317U, // SUBSDrr
+ 138548317U, // SUBSDrr_Int
+ 139465828U, // SUBSSrm
+ 139465828U, // SUBSSrm_Int
+ 138548324U, // SUBSSrr
+ 138548324U, // SUBSSrr_Int
+ 805311595U, // SUB_F32m
+ 939529323U, // SUB_F64m
+ 268440689U, // SUB_FI16m
+ 402658417U, // SUB_FI32m
+ 134222968U, // SUB_FPrST0
+ 134222955U, // SUB_FST0r
+ 0U, // SUB_Fp32
+ 0U, // SUB_Fp32m
+ 0U, // SUB_Fp64
+ 0U, // SUB_Fp64m
+ 0U, // SUB_Fp64m32
+ 0U, // SUB_Fp80
+ 0U, // SUB_Fp80m32
+ 0U, // SUB_Fp80m64
+ 0U, // SUB_FpI16m32
+ 0U, // SUB_FpI16m64
+ 0U, // SUB_FpI16m80
+ 0U, // SUB_FpI32m32
+ 0U, // SUB_FpI32m64
+ 0U, // SUB_FpI32m80
+ 142611563U, // SUB_FrST0
+ 5247U, // SYSCALL
+ 5255U, // SYSENTER
+ 5264U, // SYSEXIT
+ 5264U, // SYSEXIT64
+ 5272U, // SYSRET
+ 1174407723U, // TAILJMPd
+ 503319083U, // TAILJMPm
+ 234883627U, // TAILJMPr
+ 234883627U, // TAILJMPr64
+ 239080607U, // TCRETURNdi
+ 239080607U, // TCRETURNdi64
+ 239080607U, // TCRETURNri
+ 239080607U, // TCRETURNri64
+ 134223019U, // TEST16i16
+ 272635062U, // TEST16mi
+ 139859126U, // TEST16ri
+ 139728054U, // TEST16rm
+ 139859126U, // TEST16rr
+ 134223036U, // TEST32i32
+ 406852790U, // TEST32mi
+ 139859126U, // TEST32ri
+ 139990198U, // TEST32rm
+ 139859126U, // TEST32rr
+ 134223048U, // TEST64i32
+ 541070518U, // TEST64mi32
+ 139859126U, // TEST64ri32
+ 140121270U, // TEST64rm
+ 139859126U, // TEST64rr
+ 134223060U, // TEST8i8
+ 675288246U, // TEST8mi
+ 139859126U, // TEST8ri
+ 140252342U, // TEST8rm
+ 139859126U, // TEST8rr
+ 2952795359U, // TLS_addr32
+ 3087013093U, // TLS_addr64
+ 5367U, // TRAP
+ 5371U, // TST_F
+ 0U, // TST_Fp32
+ 0U, // TST_Fp64
+ 0U, // TST_Fp80
+ 140511723U, // UCOMISDrm
+ 139856363U, // UCOMISDrr
+ 140642804U, // UCOMISSrm
+ 139856372U, // UCOMISSrr
+ 134223104U, // UCOM_FIPr
+ 134223121U, // UCOM_FIr
+ 5409U, // UCOM_FPPr
+ 134223145U, // UCOM_FPr
+ 0U, // UCOM_FpIr32
+ 0U, // UCOM_FpIr64
+ 0U, // UCOM_FpIr80
+ 0U, // UCOM_Fpr32
+ 0U, // UCOM_Fpr64
+ 0U, // UCOM_Fpr80
+ 134223153U, // UCOM_Fr
+ 139203896U, // UNPCKHPDrm
+ 138548536U, // UNPCKHPDrr
+ 139203906U, // UNPCKHPSrm
+ 138548546U, // UNPCKHPSrr
+ 139203916U, // UNPCKLPDrm
+ 138548556U, // UNPCKLPDrr
+ 139203926U, // UNPCKLPSrm
+ 138548566U, // UNPCKLPSrr
+ 139875680U, // VASTART_SAVE_XMM_REGS
+ 140773564U, // V_SET0
+ 140774449U, // V_SETALLONES
+ 5496U, // WAIT
+ 536871932U, // WINCALL64m
+ 1073742844U, // WINCALL64pcrel32
+ 134218748U, // WINCALL64r
+ 2147489149U, // XCHG16rm
+ 1799361917U, // XCHG32rm
+ 2281706877U, // XCHG64rm
+ 2415924605U, // XCHG8rm
+ 134223235U, // XCH_F
+ 134223241U, // XOR16i16
+ 272633266U, // XOR16mi
+ 272633266U, // XOR16mi8
+ 272633266U, // XOR16mr
+ 138546610U, // XOR16ri
+ 138546610U, // XOR16ri8
+ 138677682U, // XOR16rm
+ 138546610U, // XOR16rr
+ 134223251U, // XOR32i32
+ 406850994U, // XOR32mi
+ 406850994U, // XOR32mi8
+ 406850994U, // XOR32mr
+ 138546610U, // XOR32ri
+ 138546610U, // XOR32ri8
+ 138808754U, // XOR32rm
+ 138546610U, // XOR32rr
+ 134223262U, // XOR64i32
+ 541068722U, // XOR64mi32
+ 541068722U, // XOR64mi8
+ 541068722U, // XOR64mr
+ 138546610U, // XOR64ri32
+ 138546610U, // XOR64ri8
+ 138939826U, // XOR64rm
+ 138546610U, // XOR64rr
+ 134223273U, // XOR8i8
+ 675286450U, // XOR8mi
+ 675286450U, // XOR8mr
+ 138546610U, // XOR8ri
+ 139070898U, // XOR8rm
+ 138546610U, // XOR8rr
+ 139200693U, // XORPDrm
+ 138545333U, // XORPDrr
+ 139200700U, // XORPSrm
+ 138545340U, // XORPSrr
+ 0U
+ };
+
+ const char *AsmStrs =
+ "fabs\000adc\t%ax, \000adc\t\000adc\t%eax, \000adc\t%rax, \000adc\t%al, "
+ "\000add\t%ax, \000add\t\000add\t%eax, \000add\t%rax, \000add\t%al, \000"
+ "addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t\000addsubps\t\000"
+ "fadd\t\000fiadd\t\000faddp\t\000#ADJCALLSTACKDOWN\000#ADJCALLSTACKUP\000"
+ "and\t%ax, \000and\t\000and\t%eax, \000and\t%rax, \000and\t%al, \000andn"
+ "pd\t\000andnps\t\000andpd\t\000andps\t\000#ATOMADD6432 PSEUDO!\000#ATOM"
+ "AND16 PSEUDO!\000#ATOMAND32 PSEUDO!\000#ATOMAND64 PSEUDO!\000#ATOMAND64"
+ "32 PSEUDO!\000#ATOMAND8 PSEUDO!\000#ATOMMAX16 PSEUDO!\000#ATOMMAX32 PSE"
+ "UDO!\000#ATOMMAX64 PSEUDO!\000#ATOMMIN16 PSEUDO!\000#ATOMMIN32 PSEUDO!\000"
+ "#ATOMMIN64 PSEUDO!\000#ATOMNAND16 PSEUDO!\000#ATOMNAND32 PSEUDO!\000#AT"
+ "OMNAND64 PSEUDO!\000#ATOMNAND6432 PSEUDO!\000#ATOMNAND8 PSEUDO!\000#ATO"
+ "MOR16 PSEUDO!\000#ATOMOR32 PSEUDO!\000#ATOMOR64 PSEUDO!\000#ATOMOR6432 "
+ "PSEUDO!\000#ATOMOR8 PSEUDO!\000#ATOMSUB6432 PSEUDO!\000#ATOMSWAP6432 PS"
+ "EUDO!\000#ATOMUMAX16 PSEUDO!\000#ATOMUMAX32 PSEUDO!\000#ATOMUMAX64 PSEU"
+ "DO!\000#ATOMUMIN16 PSEUDO!\000#ATOMUMIN32 PSEUDO!\000#ATOMUMIN64 PSEUDO"
+ "!\000#ATOMXOR16 PSEUDO!\000#ATOMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000"
+ "#ATOMXOR6432 PSEUDO!\000#ATOMXOR8 PSEUDO!\000blendpd\t\000blendps\t\000"
+ "blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000bt\t\000call\t"
+ "\000cbw\000cdq\000cdqe\000fchs\000clflush\t\000cmova\t\000cmovae\t\000c"
+ "movb\t\000cmovbe\t\000fcmovbe\t%ST(0), \000fcmovb\t%ST(0), \000cmove\t\000"
+ "fcmove\t%ST(0), \000cmovg\t\000cmovge\t\000cmovl\t\000cmovle\t\000fcmov"
+ "nbe\t%ST(0), \000fcmovnb\t%ST(0), \000cmovne\t\000fcmovne\t%ST(0), \000"
+ "cmovno\t\000cmovnp\t\000fcmovnu\t%ST(0), \000cmovns\t\000cmovo\t\000cmo"
+ "vp\t\000fcmovu\t %ST(0), \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CMOV_FR6"
+ "4 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64 PS"
+ "EUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmp\t%ax, \000cm"
+ "p\t\000cmp\t%eax, \000cmp\t%rax, \000cmp\t%al, \000cmp\000cmps\000comis"
+ "d\t\000fcos\000cqo\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t"
+ "\000cvtps2dq\t\000cvtsd2ss\t\000cvtsi2sd\t\000cvtsi2ss\t\000cvtss2sd\t\000"
+ "cvttsd2si\t\000cvttss2si\t\000cwd\000cwde\000dec\t\000div\t\000divpd\t\000"
+ "divps\t\000fdivr\t\000fidivr\t\000fdivrp\t\000divsd\t\000divss\t\000fdi"
+ "v\t\000fidiv\t\000fdivp\t\000dppd\t\000dpps\t\000ret\t#eh_return, addr:"
+ " \000enter\t\000extractps\t\000lcall\t\000ljmp\t\000fbld\t\000fbstp\t\000"
+ "fcom\t\000fcomp\t\000ficom\t\000ficomp\t\000fisttp\t\000fldcw\t\000flde"
+ "nv\t\000fnstcw\t\000fnstsw\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_"
+ "TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_"
+ "INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT"
+ "64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_"
+ "IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000##FP_REG_KILL\000fr"
+ "stor\t\000fsave\t\000fstenv\t\000fstsw\t\000movl\t%fs:\000pxor\t\000mov"
+ "apd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t%g"
+ "s:\000haddpd\t\000haddps\t\000hsubpd\t\000hsubps\t\000idiv\t\000fild\t\000"
+ "imul\t\000in\t%AX, \000in\t%AX, %DX\000in\t%EAX, \000in\t%EAX, %DX\000i"
+ "n\t%AL, \000in\t%AL, %DX\000inc\t\000insertps\t\000int\t\000int\t3\000f"
+ "ist\t\000fistp\t\000comiss\t\000cvtpd2pi\t\000cvtpd2ps\t\000cvtpi2pd\t\000"
+ "cvtpi2ps\t\000cvtps2pd\t\000cvtps2pi\t\000cvtsd2si\t\000cvtss2si\t\000c"
+ "vttpd2dq\t\000cvttpd2pi\t\000cvttps2dq\t\000cvttps2pi\t\000ucomisd\t\000"
+ "ucomiss\t\000ja\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000"
+ "jge\t\000jl\t\000jle\t\000jmp\t\000jne\t\000jno\t\000jnp\t\000jns\t\000"
+ "jo\t\000jp\t\000js\t\000lahf\000lar\t\000lock\n\tcmpxchg\t\000lock\n\tc"
+ "mpxchgq\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000fldz\000fld"
+ "1\000fld\t\000lea\t\000leave\000lfence\000lock\n\tadd\t\000lock\n\tdec\t"
+ "\000lock\n\tinc\t\000lock\n\tsub\t\000lodsb\000lodsd\000lodsq\000lodsw\000"
+ "loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lock\n\txadd\t\000ma"
+ "skmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000min"
+ "pd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000"
+ "movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000"
+ "packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000"
+ "paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000p"
+ "avgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000"
+ "pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t"
+ "\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmul"
+ "hw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld"
+ "\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000"
+ "psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psu"
+ "busb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckh"
+ "wd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t\000monitor\000mov\t\000"
+ "mov\t%ax, \000mov\t%eax, \000xor\t\000movq\t%fs:\000movq\t%gs:\000mov\t"
+ "%rax, \000movabs\t\000mov\t%al, \000movddup\t\000movdqa\t\000movdqu\t\000"
+ "movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000"
+ "movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t\000movntd"
+ "q\t\000movnti\t\000movntpd\t\000movntps\t\000movshdup\t\000movsldup\t\000"
+ "movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadbw\t\000"
+ "mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000fimul\t\000"
+ "fmulp\t\000mwait\000neg\t\000nop\000nopl\t\000not\t\000or\t%ax, \000or\t"
+ "\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX\000"
+ "out\t%DX, %EAX\000out\t%DX, %AL\000pabsb\t\000pabsd\t\000pabsw\t\000pac"
+ "kusdw\t\000palignr\t\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000pcmpest"
+ "ri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm"
+ "\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM"
+ "128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000pha"
+ "ddd\t\000phaddsw\t\000phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t"
+ "\000phsubw\t\000pinsrb\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmax"
+ "sb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pmi"
+ "nud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq"
+ "\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t"
+ "\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000"
+ "pmulld\t\000pop\t\000popf\000prefetchnta\t\000prefetcht0\t\000prefetcht"
+ "1\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000"
+ "psignb\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000"
+ "punpckhqdq\t\000punpcklqdq\t\000push\t\000pushf\000rcl\t\000rcpps\t\000"
+ "rcpss\t\000rcr\t\000rdtsc\000rep movsb\000rep movsd\000rep movsq\000rep"
+ " movsw\000rep stosb\000rep stosd\000rep stosq\000rep stosw\000ret\000re"
+ "t\t\000rol\t\000ror\t\000roundpd\t\000roundps\t\000roundsd\t\000roundss"
+ "\t\000rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000sbb\t%ax, \000sbb\t\000"
+ "sbb\t%eax, \000sbb\t%rax, \000sbb\t%al, \000scas\000setae\t\000seta\t\000"
+ "setbe\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000"
+ "setne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000"
+ "sfence\000shl\t\000shr\t\000shld\t\000shrd\t\000shufpd\t\000shufps\t\000"
+ "fsin\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000stmxcs"
+ "r\t\000fst\t\000fstp\t\000sub\t%ax, \000sub\t\000sub\t%eax, \000sub\t%r"
+ "ax, \000sub\t%al, \000subpd\t\000subps\t\000fsubr\t\000fisubr\t\000fsub"
+ "rp\t\000subsd\t\000subss\t\000fsub\t\000fisub\t\000fsubp\t\000syscall\000"
+ "sysenter\000sysexit\000sysret\000#TC_RETURN \000test\t%ax, \000test\t\000"
+ "test\t%eax, \000test\t%rax, \000test\t%al, \000leal\t\000.byte\t0x66; l"
+ "eaq\t\000ud2\000ftst\000fucomip\t%ST(0), \000fucomi\t%ST(0), \000fucomp"
+ "p\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000u"
+ "npcklps\t\000#VASTART_SAVE_XMM_REGS \000wait\000xchg\t\000fxch\t\000xor"
+ "\t%ax, \000xor\t%eax, \000xor\t%rax, \000xor\t%al, \000";
+
+
+#ifndef NO_ASM_WRITER_BOILERPLATE
+ if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+ printInlineAsm(MI);
+ return;
+ } else if (MI->isLabel()) {
+ printLabel(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ printImplicitDef(MI);
+ return;
+ } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
+ printKill(MI);
+ return;
+ }
+
+
+#endif
+ O << "\t";
+
+ // Emit the opcode for the instruction.
+ unsigned Bits = OpInfo[MI->getOpcode()];
+ assert(Bits != 0 && "Cannot print this instruction.");
+ O << AsmStrs+(Bits & 8191)-1;
+
+
+ // Fragment 0 encoded into 5 bits for 24 unique commands.
+ switch ((Bits >> 27) & 31) {
+ default: // unreachable.
+ case 0:
+ // ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTACKUP32, ADJCA...
+ return;
+ break;
+ case 1:
+ // ADC16i16, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32i32, ADC32ri, ADC3...
+ printOperand(MI, 0);
+ break;
+ case 2:
+ // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, ADD_FI16m, AND...
+ printi16mem(MI, 0);
+ break;
+ case 3:
+ // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, ADD_FI32m, AND...
+ printi32mem(MI, 0);
+ break;
+ case 4:
+ // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,...
+ printi64mem(MI, 0);
+ break;
+ case 5:
+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CLFLUSH, CMP8mi, CMP8m...
+ printi8mem(MI, 0);
+ break;
+ case 6:
+ // ADD_F32m, DIVR_F32m, DIV_F32m, EXTRACTPSmr, FBLDm, FBSTPm, FCOM32m, FC...
+ printf32mem(MI, 0);
+ break;
+ case 7:
+ // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MOVHPDmr, M...
+ printf64mem(MI, 0);
+ break;
+ case 8:
+ // CALL64pcrel32, CALLpcrel32, JA, JA8, JAE, JAE8, JB, JB8, JBE, JBE8, JC...
+ print_pcrel_imm(MI, 0);
+ break;
+ case 9:
+ // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSSrm, Int_CMPSDrm, Int_CMPSSrm
+ printSSECC(MI, 7);
+ break;
+ case 10:
+ // CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr
+ printSSECC(MI, 3);
+ break;
+ case 11:
+ // CRC32m16, CRC32m32, CRC32m8, CRC32r16, CRC32r32, CRC32r8, CRC64m64, CR...
+ printOperand(MI, 1);
+ O << ", ";
+ break;
+ case 12:
+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64
+ printopaquemem(MI, 0);
+ return;
+ break;
+ case 13:
+ // FS_MOV32rm, GS_MOV32rm, LXADD32, XCHG32rm
+ printi32mem(MI, 1);
+ O << ", ";
+ break;
+ case 14:
+ // LCMPXCHG64
+ printOperand(MI, 5);
+ O << ',';
+ printi64mem(MI, 0);
+ return;
+ break;
+ case 15:
+ // LD_F80m, ST_FP80m
+ printf80mem(MI, 0);
+ return;
+ break;
+ case 16:
+ // LXADD16, XCHG16rm
+ printi16mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 6);
+ return;
+ break;
+ case 17:
+ // LXADD64, XCHG64rm
+ printOperand(MI, 6);
+ O << ", ";
+ printi64mem(MI, 1);
+ return;
+ break;
+ case 18:
+ // LXADD8, XCHG8rm
+ printi8mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 6);
+ return;
+ break;
+ case 19:
+ // MOV64FSrm, MOV64GSrm
+ printi64mem(MI, 1);
+ O << ", ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 20:
+ // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
+ printf128mem(MI, 0);
+ O << ", ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case 21:
+ // MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
+ printi128mem(MI, 0);
+ O << ", ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case 22:
+ // TLS_addr32
+ printlea32mem(MI, 0);
+ O << ", %eax; call\t___tls_get_addr at PLT";
+ return;
+ break;
+ case 23:
+ // TLS_addr64
+ printlea64mem(MI, 0);
+ O << "(%rip), %rdi; .word\t0x6666; rex64; call\t__tls_get_addr at PLT";
+ return;
+ break;
+ }
+
+
+ // Fragment 1 encoded into 5 bits for 26 unique commands.
+ switch ((Bits >> 22) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i32, ADD64i32, AD...
+ return;
+ break;
+ case 1:
+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32...
+ O << ", ";
+ break;
+ case 2:
+ // ADD_FrST0, DIVR_FrST0, DIV_FrST0, MUL_FrST0, SUBR_FrST0, SUB_FrST0
+ O << ", %ST(0)";
+ return;
+ break;
+ case 3:
+ // CMPPDrmi, CMPPDrri
+ O << "pd\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 4:
+ // CMPPSrmi, CMPPSrri
+ O << "ps\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 5:
+ // CMPSDrm, CMPSDrr, Int_CMPSDrm, Int_CMPSDrr
+ O << "sd\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 6:
+ // CMPSSrm, CMPSSrr, Int_CMPSSrm, Int_CMPSSrr
+ O << "ss\t";
+ printOperand(MI, 0);
+ O << ", ";
+ break;
+ case 7:
+ // CRC32m16
+ printi16mem(MI, 2);
+ return;
+ break;
+ case 8:
+ // CRC32m32
+ printi32mem(MI, 2);
+ return;
+ break;
+ case 9:
+ // CRC32m8
+ printi8mem(MI, 2);
+ return;
+ break;
+ case 10:
+ // CRC32r16, CRC32r32, CRC32r8, CRC64r64
+ printOperand(MI, 2);
+ return;
+ break;
+ case 11:
+ // CRC64m64
+ printi64mem(MI, 2);
+ return;
+ break;
+ case 12:
+ // FS_MOV32rm, GS_MOV32rm
+ printOperand(MI, 0);
+ return;
+ break;
+ case 13:
+ // LXADD32, XCHG32rm
+ printOperand(MI, 6);
+ return;
+ break;
+ case 14:
+ // MOV16ao16
+ O << ", %ax";
+ return;
+ break;
+ case 15:
+ // MOV32ao32
+ O << ", %eax";
+ return;
+ break;
+ case 16:
+ // MOV64ao32, MOV64ao8
+ O << ", %rax";
+ return;
+ break;
+ case 17:
+ // MOV8ao8
+ O << ", %al";
+ return;
+ break;
+ case 18:
+ // OUT16ir
+ O << ", %AX";
+ return;
+ break;
+ case 19:
+ // OUT32ir
+ O << ", %EAX";
+ return;
+ break;
+ case 20:
+ // OUT8ir
+ O << ", %AL";
+ return;
+ break;
+ case 21:
+ // RCL16m1, RCL16r1, RCL32m1, RCL32r1, RCL64m1, RCL64r1, RCL8m1, RCL8r1, ...
+ O << ", 1";
+ return;
+ break;
+ case 22:
+ // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R...
+ O << ", CL";
+ return;
+ break;
+ case 23:
+ // ROL64mCL, ROL64rCL, ROR64mCL, ROR64rCL, SAR64mCL, SAR64rCL, SHL64mCL, ...
+ O << ", %CL";
+ return;
+ break;
+ case 24:
+ // TAILJMPd, TAILJMPm, TAILJMPr, TAILJMPr64
+ O << " # TAILCALL";
+ return;
+ break;
+ case 25:
+ // TCRETURNdi, TCRETURNdi64, TCRETURNri, TCRETURNri64
+ O << ' ';
+ printOperand(MI, 1);
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 5 bits for 24 unique commands.
+ switch ((Bits >> 17) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC...
+ printOperand(MI, 5);
+ break;
+ case 1:
+ // ADC16ri, ADC16ri8, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64ri32, ADC...
+ printOperand(MI, 2);
+ break;
+ case 2:
+ // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r...
+ printi16mem(MI, 2);
+ break;
+ case 3:
+ // ADC32rm, ADD32rm, AND32rm, CMOVA32rm, CMOVAE32rm, CMOVB32rm, CMOVBE32r...
+ printi32mem(MI, 2);
+ break;
+ case 4:
+ // ADC64rm, ADD64rm, AND64rm, CMOVA64rm, CMOVAE64rm, CMOVB64rm, CMOVBE64r...
+ printi64mem(MI, 2);
+ break;
+ case 5:
+ // ADC8rm, ADD8rm, AND8rm, OR8rm, PINSRBrm, SBB8rm, SUB8rm, XOR8rm
+ printi8mem(MI, 2);
+ break;
+ case 6:
+ // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,...
+ printf128mem(MI, 2);
+ break;
+ case 7:
+ // ADDSDrm, ADDSDrm_Int, CMPSDrm, DIVSDrm, DIVSDrm_Int, Int_CMPSDrm, Int_...
+ printf64mem(MI, 2);
+ break;
+ case 8:
+ // ADDSSrm, ADDSSrm_Int, CMPSSrm, DIVSSrm, DIVSSrm_Int, INSERTPSrm, Int_C...
+ printf32mem(MI, 2);
+ break;
+ case 9:
+ // BLENDPDrmi, BLENDPSrmi, BLENDVPDrm0, BLENDVPSrm0, DPPDrmi, DPPSrmi, MP...
+ printi128mem(MI, 2);
+ break;
+ case 10:
+ // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, LAR16rm, LAR32rm, LA...
+ printi16mem(MI, 1);
+ break;
+ case 11:
+ // BSF16rr, BSF32rr, BSF64rr, BSR16rr, BSR32rr, BSR64rr, BT16ri8, BT16rr,...
+ printOperand(MI, 1);
+ break;
+ case 12:
+ // BSF32rm, BSR32rm, CMP32rm, CVTSI2SDrm, CVTSI2SSrm, IMUL32rmi, IMUL32rm...
+ printi32mem(MI, 1);
+ break;
+ case 13:
+ // BSF64rm, BSR64rm, CMP64rm, CVTSI2SD64rm, CVTSI2SS64rm, IMUL64rmi32, IM...
+ printi64mem(MI, 1);
+ break;
+ case 14:
+ // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX32rm8, MOVSX64rm8, MOVZX32_NOREXrm8...
+ printi8mem(MI, 1);
+ break;
+ case 15:
+ // COMISDrm, CVTDQ2PDrm, CVTDQ2PSrm, CVTPD2DQrm, CVTPS2DQrm, FsMOVAPDrm, ...
+ printf128mem(MI, 1);
+ break;
+ case 16:
+ // CVTSD2SSrm, CVTTSD2SI64rm, CVTTSD2SIrm, Int_CVTPS2PDrm, Int_CVTPS2PIrm...
+ printf64mem(MI, 1);
+ return;
+ break;
+ case 17:
+ // CVTSS2SDrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_CVTSS2SI64rm, Int_CVTSS2SI...
+ printf32mem(MI, 1);
+ return;
+ break;
+ case 18:
+ // FsFLD0SD, FsFLD0SS, MMX_V_SET0, MMX_V_SETALLONES, MOV32r0, MOV8r0, SET...
+ printOperand(MI, 0);
+ return;
+ break;
+ case 19:
+ // Int_CVTDQ2PSrm, LDDQUrm, MOVDQArm, MOVDQUrm, MOVDQUrm_Int, MOVNTDQArm,...
+ printi128mem(MI, 1);
+ break;
+ case 20:
+ // LEA16r, LEA32r
+ printlea32mem(MI, 1);
+ return;
+ break;
+ case 21:
+ // LEA64_32r
+ printlea64_32mem(MI, 1);
+ return;
+ break;
+ case 22:
+ // LEA64r
+ printlea64mem(MI, 1);
+ return;
+ break;
+ case 23:
+ // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi
+ printOperand(MI, 10);
+ return;
+ break;
+ }
+
+
+ // Fragment 3 encoded into 3 bits for 6 unique commands.
+ switch ((Bits >> 14) & 7) {
+ default: // unreachable.
+ case 0:
+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32...
+ return;
+ break;
+ case 1:
+ // BLENDPDrmi, BLENDPDrri, BLENDPSrmi, BLENDPSrri, DPPDrmi, DPPDrri, DPPS...
+ O << ", ";
+ break;
+ case 2:
+ // BLENDVPDrm0, BLENDVPDrr0, BLENDVPSrm0, BLENDVPSrr0, PBLENDVBrm0, PBLEN...
+ O << ", %xmm0";
+ return;
+ break;
+ case 3:
+ // MOV8mr_NOREX, MOV8rm_NOREX, MOV8rr_NOREX, MOVZX32_NOREXrm8, MOVZX32_NO...
+ O << " # NOREX";
+ return;
+ break;
+ case 4:
+ // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHRD16mrCL, SHRD16rrCL...
+ O << ", CL";
+ return;
+ break;
+ case 5:
+ // SHLD64mrCL, SHLD64rrCL, SHRD64mrCL, SHRD64rrCL
+ O << ", %CL";
+ return;
+ break;
+ }
+
+ switch (MI->getOpcode()) {
+ case X86::BLENDPDrmi:
+ case X86::BLENDPDrri:
+ case X86::BLENDPSrmi:
+ case X86::BLENDPSrri:
+ case X86::DPPDrmi:
+ case X86::DPPDrri:
+ case X86::DPPSrmi:
+ case X86::DPPSrri:
+ case X86::EXTRACTPSmr:
+ case X86::EXTRACTPSrr:
+ case X86::IMUL16rmi:
+ case X86::IMUL16rmi8:
+ case X86::IMUL16rri:
+ case X86::IMUL16rri8:
+ case X86::IMUL32rmi:
+ case X86::IMUL32rmi8:
+ case X86::IMUL32rri:
+ case X86::IMUL32rri8:
+ case X86::IMUL64rmi32:
+ case X86::IMUL64rmi8:
+ case X86::IMUL64rri32:
+ case X86::IMUL64rri8:
+ case X86::INSERTPSrm:
+ case X86::INSERTPSrr:
+ case X86::MMX_PEXTRWri:
+ case X86::MMX_PINSRWrmi:
+ case X86::MMX_PINSRWrri:
+ case X86::MMX_PSHUFWmi:
+ case X86::MMX_PSHUFWri:
+ case X86::MPSADBWrmi:
+ case X86::MPSADBWrri:
+ case X86::PALIGNR128rm:
+ case X86::PALIGNR128rr:
+ case X86::PALIGNR64rm:
+ case X86::PALIGNR64rr:
+ case X86::PBLENDWrmi:
+ case X86::PBLENDWrri:
+ case X86::PCMPESTRIArm:
+ case X86::PCMPESTRIArr:
+ case X86::PCMPESTRICrm:
+ case X86::PCMPESTRICrr:
+ case X86::PCMPESTRIOrm:
+ case X86::PCMPESTRIOrr:
+ case X86::PCMPESTRISrm:
+ case X86::PCMPESTRISrr:
+ case X86::PCMPESTRIZrm:
+ case X86::PCMPESTRIZrr:
+ case X86::PCMPESTRIrm:
+ case X86::PCMPESTRIrr:
+ case X86::PCMPESTRM128rm:
+ case X86::PCMPESTRM128rr:
+ case X86::PCMPISTRIArm:
+ case X86::PCMPISTRIArr:
+ case X86::PCMPISTRICrm:
+ case X86::PCMPISTRICrr:
+ case X86::PCMPISTRIOrm:
+ case X86::PCMPISTRIOrr:
+ case X86::PCMPISTRISrm:
+ case X86::PCMPISTRISrr:
+ case X86::PCMPISTRIZrm:
+ case X86::PCMPISTRIZrr:
+ case X86::PCMPISTRIrm:
+ case X86::PCMPISTRIrr:
+ case X86::PCMPISTRM128rm:
+ case X86::PCMPISTRM128rr:
+ case X86::PEXTRBmr:
+ case X86::PEXTRBrr:
+ case X86::PEXTRDmr:
+ case X86::PEXTRDrr:
+ case X86::PEXTRQmr:
+ case X86::PEXTRQrr:
+ case X86::PEXTRWmr:
+ case X86::PEXTRWri:
+ case X86::PINSRBrm:
+ case X86::PINSRBrr:
+ case X86::PINSRDrm:
+ case X86::PINSRDrr:
+ case X86::PINSRQrm:
+ case X86::PINSRQrr:
+ case X86::PINSRWrmi:
+ case X86::PINSRWrri:
+ case X86::PSHUFDmi:
+ case X86::PSHUFDri:
+ case X86::PSHUFHWmi:
+ case X86::PSHUFHWri:
+ case X86::PSHUFLWmi:
+ case X86::PSHUFLWri:
+ case X86::ROUNDPDm_Int:
+ case X86::ROUNDPDr_Int:
+ case X86::ROUNDPSm_Int:
+ case X86::ROUNDPSr_Int:
+ case X86::ROUNDSDm_Int:
+ case X86::ROUNDSDr_Int:
+ case X86::ROUNDSSm_Int:
+ case X86::ROUNDSSr_Int:
+ case X86::SHLD16mri8:
+ case X86::SHLD16rri8:
+ case X86::SHLD32mri8:
+ case X86::SHLD32rri8:
+ case X86::SHLD64mri8:
+ case X86::SHLD64rri8:
+ case X86::SHRD16mri8:
+ case X86::SHRD16rri8:
+ case X86::SHRD32mri8:
+ case X86::SHRD32rri8:
+ case X86::SHRD64mri8:
+ case X86::SHRD64rri8:
+ case X86::SHUFPDrmi:
+ case X86::SHUFPDrri:
+ case X86::SHUFPSrmi:
+ case X86::SHUFPSrri:
+ case X86::VASTART_SAVE_XMM_REGS:
+ switch (MI->getOpcode()) {
+ case X86::BLENDPDrmi:
+ case X86::BLENDPSrmi:
+ case X86::DPPDrmi:
+ case X86::DPPSrmi:
+ case X86::INSERTPSrm:
+ case X86::MMX_PINSRWrmi:
+ case X86::MPSADBWrmi:
+ case X86::PALIGNR128rm:
+ case X86::PALIGNR64rm:
+ case X86::PBLENDWrmi:
+ case X86::PINSRBrm:
+ case X86::PINSRDrm:
+ case X86::PINSRQrm:
+ case X86::PINSRWrmi:
+ case X86::ROUNDSDm_Int:
+ case X86::ROUNDSSm_Int:
+ case X86::SHUFPDrmi:
+ case X86::SHUFPSrmi: printOperand(MI, 7); break;
+ case X86::BLENDPDrri:
+ case X86::BLENDPSrri:
+ case X86::DPPDrri:
+ case X86::DPPSrri:
+ case X86::INSERTPSrr:
+ case X86::MMX_PINSRWrri:
+ case X86::MPSADBWrri:
+ case X86::PALIGNR128rr:
+ case X86::PALIGNR64rr:
+ case X86::PBLENDWrri:
+ case X86::PINSRBrr:
+ case X86::PINSRDrr:
+ case X86::PINSRQrr:
+ case X86::PINSRWrri:
+ case X86::ROUNDSDr_Int:
+ case X86::ROUNDSSr_Int:
+ case X86::SHLD16rri8:
+ case X86::SHLD32rri8:
+ case X86::SHLD64rri8:
+ case X86::SHRD16rri8:
+ case X86::SHRD32rri8:
+ case X86::SHRD64rri8:
+ case X86::SHUFPDrri:
+ case X86::SHUFPSrri: printOperand(MI, 3); break;
+ case X86::EXTRACTPSmr:
+ case X86::IMUL16rmi:
+ case X86::IMUL16rmi8:
+ case X86::IMUL32rmi:
+ case X86::IMUL32rmi8:
+ case X86::IMUL64rmi32:
+ case X86::IMUL64rmi8:
+ case X86::MMX_PSHUFWmi:
+ case X86::PCMPESTRIArm:
+ case X86::PCMPESTRICrm:
+ case X86::PCMPESTRIOrm:
+ case X86::PCMPESTRISrm:
+ case X86::PCMPESTRIZrm:
+ case X86::PCMPESTRIrm:
+ case X86::PCMPESTRM128rm:
+ case X86::PCMPISTRIArm:
+ case X86::PCMPISTRICrm:
+ case X86::PCMPISTRIOrm:
+ case X86::PCMPISTRISrm:
+ case X86::PCMPISTRIZrm:
+ case X86::PCMPISTRIrm:
+ case X86::PCMPISTRM128rm:
+ case X86::PEXTRBmr:
+ case X86::PEXTRDmr:
+ case X86::PEXTRQmr:
+ case X86::PEXTRWmr:
+ case X86::PSHUFDmi:
+ case X86::PSHUFHWmi:
+ case X86::PSHUFLWmi:
+ case X86::ROUNDPDm_Int:
+ case X86::ROUNDPSm_Int:
+ case X86::SHLD16mri8:
+ case X86::SHLD32mri8:
+ case X86::SHLD64mri8:
+ case X86::SHRD16mri8:
+ case X86::SHRD32mri8:
+ case X86::SHRD64mri8: printOperand(MI, 6); break;
+ case X86::EXTRACTPSrr:
+ case X86::IMUL16rri:
+ case X86::IMUL16rri8:
+ case X86::IMUL32rri:
+ case X86::IMUL32rri8:
+ case X86::IMUL64rri32:
+ case X86::IMUL64rri8:
+ case X86::MMX_PEXTRWri:
+ case X86::MMX_PSHUFWri:
+ case X86::PCMPESTRIArr:
+ case X86::PCMPESTRICrr:
+ case X86::PCMPESTRIOrr:
+ case X86::PCMPESTRISrr:
+ case X86::PCMPESTRIZrr:
+ case X86::PCMPESTRIrr:
+ case X86::PCMPESTRM128rr:
+ case X86::PCMPISTRIArr:
+ case X86::PCMPISTRICrr:
+ case X86::PCMPISTRIOrr:
+ case X86::PCMPISTRISrr:
+ case X86::PCMPISTRIZrr:
+ case X86::PCMPISTRIrr:
+ case X86::PCMPISTRM128rr:
+ case X86::PEXTRBrr:
+ case X86::PEXTRDrr:
+ case X86::PEXTRQrr:
+ case X86::PEXTRWri:
+ case X86::PSHUFDri:
+ case X86::PSHUFHWri:
+ case X86::PSHUFLWri:
+ case X86::ROUNDPDr_Int:
+ case X86::ROUNDPSr_Int:
+ case X86::VASTART_SAVE_XMM_REGS: printOperand(MI, 2); break;
+ }
+ return;
+ break;
+ }
+ return;
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *X86IntelInstPrinter::getRegisterName(unsigned RegNo) {
+ assert(RegNo && RegNo < 134 && "Invalid register number!");
+
+ static const unsigned RegAsmOffset[] = {
+ 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, 40,
+ 43, 47, 50, 53, 56, 60, 64, 68, 72, 76, 80, 86, 90, 93,
+ 97, 101, 105, 109, 113, 117, 121, 125, 129, 132, 135, 138, 142, 146,
+ 150, 154, 158, 162, 166, 170, 174, 179, 184, 189, 193, 198, 203, 208,
+ 212, 217, 222, 227, 231, 236, 241, 246, 250, 255, 260, 265, 269, 274,
+ 279, 284, 287, 291, 295, 299, 302, 306, 310, 314, 318, 322, 326, 330,
+ 334, 338, 342, 346, 350, 353, 357, 360, 364, 367, 373, 379, 385, 391,
+ 397, 403, 409, 415, 420, 425, 431, 437, 443, 449, 455, 461, 466, 471,
+ 476, 481, 486, 491, 496, 501, 506, 511, 517, 523, 529, 535, 541, 547,
+ 552, 557, 562, 567, 572, 577, 582, 0
+ };
+
+ const char *AsmStrs =
+ "ah\000al\000ax\000bh\000bl\000bp\000bpl\000bx\000ch\000cl\000cs\000cx\000"
+ "dh\000di\000dil\000dl\000ds\000dx\000eax\000ebp\000ebx\000ecx\000edi\000"
+ "edx\000flags\000eip\000es\000esi\000esp\000fp0\000fp1\000fp2\000fp3\000"
+ "fp4\000fp5\000fp6\000fs\000gs\000ip\000mm0\000mm1\000mm2\000mm3\000mm4\000"
+ "mm5\000mm6\000mm7\000r10\000r10b\000r10d\000r10w\000r11\000r11b\000r11d"
+ "\000r11w\000r12\000r12b\000r12d\000r12w\000r13\000r13b\000r13d\000r13w\000"
+ "r14\000r14b\000r14d\000r14w\000r15\000r15b\000r15d\000r15w\000r8\000r8b"
+ "\000r8d\000r8w\000r9\000r9b\000r9d\000r9w\000rax\000rbp\000rbx\000rcx\000"
+ "rdi\000rdx\000rip\000rsi\000rsp\000si\000sil\000sp\000spl\000ss\000st(0"
+ ")\000st(1)\000st(2)\000st(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm"
+ "0\000xmm1\000xmm10\000xmm11\000xmm12\000xmm13\000xmm14\000xmm15\000xmm2"
+ "\000xmm3\000xmm4\000xmm5\000xmm6\000xmm7\000xmm8\000xmm9\000ymm0\000ymm"
+ "1\000ymm10\000ymm11\000ymm12\000ymm13\000ymm14\000ymm15\000ymm2\000ymm3"
+ "\000ymm4\000ymm5\000ymm6\000ymm7\000ymm8\000ymm9\000";
+ return AsmStrs+RegAsmOffset[RegNo-1];
+}
diff --git a/libclamav/c++/X86GenCallingConv.inc b/libclamav/c++/X86GenCallingConv.inc
new file mode 100644
index 0000000..d9ee7d6
--- /dev/null
+++ b/libclamav/c++/X86GenCallingConv.inc
@@ -0,0 +1,866 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Calling Convention Implementation Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+static bool CC_X86_32_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_32_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_32_FastCC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_32_FastCall(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_Win64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86_32(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86_32_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86_32_Fast(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86_64(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86_64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_X86_Win64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+
+
+static bool CC_X86_32_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (ArgFlags.isNest()) {
+ if (unsigned Reg = State.AllocateReg(X86::ECX)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!State.isVarArg()) {
+ if (ArgFlags.isInReg()) {
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ X86::EAX, X86::EDX, X86::ECX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+ }
+
+ if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_X86_32_Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
+ return false;
+ }
+
+ if (!State.isVarArg()) {
+ if (ArgFlags.isInReg()) {
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE2()) {
+ static const unsigned RegList1[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+ }
+ }
+
+ if (!State.isVarArg()) {
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v2f32) {
+ static const unsigned RegList2[] = {
+ X86::MM0, X86::MM1, X86::MM2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i32 ||
+ LocVT == MVT::f32) {
+ unsigned Offset3 = State.AllocateStack(4, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f64) {
+ unsigned Offset4 = State.AllocateStack(8, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f80) {
+ unsigned Offset5 = State.AllocateStack(
+ State.getTarget().getTargetData()->getTypeAllocSize(LocVT.getTypeForEVT(State.getContext())), 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
+ return false;
+ }
+
+ if (!State.isVarArg()) {
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ static const unsigned RegList6[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList6, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ unsigned Offset7 = State.AllocateStack(16, 16);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v1i64) {
+ unsigned Offset8 = State.AllocateStack(8, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_X86_32_FastCC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
+ return false;
+ }
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (ArgFlags.isNest()) {
+ if (unsigned Reg = State.AllocateReg(X86::EAX)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ X86::ECX, X86::EDX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!State.isVarArg()) {
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE2()) {
+ static const unsigned RegList2[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ unsigned Offset3 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+ }
+
+ if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_X86_32_FastCall(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (ArgFlags.isNest()) {
+ if (unsigned Reg = State.AllocateReg(X86::EAX)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ X86::ECX, X86::EDX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_X86_64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
+ return false;
+ }
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (ArgFlags.isNest()) {
+ if (unsigned Reg = State.AllocateReg(X86::R10)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v1i64) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().isTargetDarwin()) {
+ LocVT = MVT::i64;
+ LocInfo = CCValAssign::BCvt;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 6)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList2[] = {
+ X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 6)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v2f32) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().isTargetDarwin()) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE2()) {
+ LocVT = MVT::v2i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE1()) {
+ static const unsigned RegList3[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i32 ||
+ LocVT == MVT::i64 ||
+ LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ unsigned Offset4 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f80) {
+ unsigned Offset5 = State.AllocateStack(
+ State.getTarget().getTargetData()->getTypeAllocSize(LocVT.getTypeForEVT(State.getContext())),
+ State.getTarget().getTargetData()->getABITypeAlignment(LocVT.getTypeForEVT(State.getContext())));
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ unsigned Offset6 = State.AllocateStack(16, 16);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2f32) {
+ unsigned Offset7 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_X86_Win64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (ArgFlags.isNest()) {
+ if (unsigned Reg = State.AllocateReg(X86::R10)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ LocVT = MVT::i64;
+ LocInfo = CCValAssign::Indirect;
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2f32) {
+ LocVT = MVT::i64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ X86::ECX, X86::EDX, X86::R8D, X86::R9D
+ };
+ static const unsigned RegList2[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList3[] = {
+ X86::RCX, X86::RDX, X86::R8, X86::R9
+ };
+ static const unsigned RegList4[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, RegList4, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ static const unsigned RegList5[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
+ };
+ static const unsigned RegList6[] = {
+ X86::RCX, X86::RDX, X86::R8, X86::R9
+ };
+ if (unsigned Reg = State.AllocateReg(RegList5, RegList6, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32 ||
+ LocVT == MVT::i64 ||
+ LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ unsigned Offset7 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f80) {
+ unsigned Offset8 = State.AllocateStack(
+ State.getTarget().getTargetData()->getTypeAllocSize(LocVT.getTypeForEVT(State.getContext())),
+ State.getTarget().getTargetData()->getABITypeAlignment(LocVT.getTypeForEVT(State.getContext())));
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v1i64) {
+ unsigned Offset9 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (State.getTarget().getSubtarget<X86Subtarget>().is64Bit()) {
+ if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86Common(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8) {
+ static const unsigned RegList1[] = {
+ X86::AL, X86::DL
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i16) {
+ static const unsigned RegList2[] = {
+ X86::AX, X86::DX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList3[] = {
+ X86::EAX, X86::EDX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList4[] = {
+ X86::RAX, X86::RDX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList4, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ static const unsigned RegList5[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList5, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v1i64 ||
+ LocVT == MVT::v2f32) {
+ if (unsigned Reg = State.AllocateReg(X86::MM0)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f80) {
+ static const unsigned RegList6[] = {
+ X86::ST0, X86::ST1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList6, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86_32(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (State.getCallingConv() == CallingConv::Fast) {
+ if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86_32_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isInReg()) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE2()) {
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ static const unsigned RegList1[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+ }
+
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64) {
+ static const unsigned RegList2[] = {
+ X86::ST0, X86::ST1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86_32_Fast(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::f32) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE2()) {
+ static const unsigned RegList1[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE2()) {
+ static const unsigned RegList2[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i8) {
+ static const unsigned RegList3[] = {
+ X86::AL, X86::DL, X86::CL
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i16) {
+ static const unsigned RegList4[] = {
+ X86::AX, X86::DX, X86::CX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList4, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList5[] = {
+ X86::EAX, X86::EDX, X86::ECX
+ };
+ if (unsigned Reg = State.AllocateReg(RegList5, 3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86_64(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (State.getTarget().getSubtarget<X86Subtarget>().isTargetWin64()) {
+ if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86_64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::f32) {
+ static const unsigned RegList1[] = {
+ X86::XMM0, X86::XMM1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const unsigned RegList2[] = {
+ X86::XMM0, X86::XMM1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v1i64) {
+ if (unsigned Reg = State.AllocateReg(X86::RAX)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v2f32) {
+ static const unsigned RegList3[] = {
+ X86::XMM0, X86::XMM1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_X86_Win64_C(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::v8i8 ||
+ LocVT == MVT::v4i16 ||
+ LocVT == MVT::v2i32 ||
+ LocVT == MVT::v1i64) {
+ LocVT = MVT::i64;
+ LocInfo = CCValAssign::BCvt;
+ }
+
+ if (LocVT == MVT::f32) {
+ if (unsigned Reg = State.AllocateReg(X86::XMM0)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (unsigned Reg = State.AllocateReg(X86::XMM0)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
diff --git a/libclamav/c++/X86GenDAGISel.inc b/libclamav/c++/X86GenDAGISel.inc
new file mode 100644
index 0000000..d3b1b43
--- /dev/null
+++ b/libclamav/c++/X86GenDAGISel.inc
@@ -0,0 +1,59391 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// DAG Instruction Selector for the X86 target
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+// *** NOTE: This file is #included into the middle of the target
+// *** instruction selector class. These functions are really methods.
+
+// Include standard, target-independent definitions and methods used
+// by the instruction selector.
+#include "llvm/CodeGen/DAGISelHeader.h"
+
+
+// Node transformations.
+inline SDValue Transform_BYTE_imm(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // Transformation function: imm >> 3
+ return getI32Imm(N->getZExtValue() >> 3);
+
+}
+inline SDValue Transform_MMX_SHUFFLE_get_shuf_imm(SDNode *N) {
+
+ return getI8Imm(X86::getShuffleSHUFImmediate(N));
+
+}
+inline SDValue Transform_SHUFFLE_get_palign_imm(SDNode *N) {
+
+ return getI8Imm(X86::getShufflePALIGNRImmediate(N));
+
+}
+inline SDValue Transform_SHUFFLE_get_pshufhw_imm(SDNode *N) {
+
+ return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
+
+}
+inline SDValue Transform_SHUFFLE_get_pshuflw_imm(SDNode *N) {
+
+ return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
+
+}
+inline SDValue Transform_SHUFFLE_get_shuf_imm(SDNode *N) {
+
+ return getI8Imm(X86::getShuffleSHUFImmediate(N));
+
+}
+
+// Predicate functions.
+inline bool Predicate_alignedload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getAlignment() >= 16;
+
+}
+inline bool Predicate_alignedstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getAlignment() >= 16;
+
+}
+inline bool Predicate_and_su(SDNode *N) {
+
+ return N->hasOneUse();
+
+}
+inline bool Predicate_atomic_cmp_swap_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_cmp_swap_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_cmp_swap_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_cmp_swap_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_add_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_add_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_add_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_add_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_and_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_and_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_and_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_and_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_max_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_max_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_max_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_max_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_min_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_min_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_min_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_min_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_nand_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_nand_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_nand_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_nand_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_or_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_or_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_or_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_or_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_sub_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_sub_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_sub_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_sub_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_umax_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_umax_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_umax_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_umax_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_umin_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_umin_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_umin_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_umin_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_load_xor_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_load_xor_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_load_xor_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_load_xor_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_atomic_swap_16(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_atomic_swap_32(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_atomic_swap_64(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
+}
+inline bool Predicate_atomic_swap_8(SDNode *N) {
+
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_cvtff(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
+
+}
+inline bool Predicate_cvtfs(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
+
+}
+inline bool Predicate_cvtfu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
+
+}
+inline bool Predicate_cvtsf(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
+
+}
+inline bool Predicate_cvtss(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
+
+}
+inline bool Predicate_cvtsu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
+
+}
+inline bool Predicate_cvtuf(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
+
+}
+inline bool Predicate_cvtus(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
+
+}
+inline bool Predicate_cvtuu(SDNode *N) {
+
+ return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
+
+}
+inline bool Predicate_def32(SDNode *N) {
+
+ return N->getOpcode() != ISD::TRUNCATE &&
+ N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
+ N->getOpcode() != ISD::CopyFromReg &&
+ N->getOpcode() != X86ISD::CMOV;
+
+}
+inline bool Predicate_extload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
+
+}
+inline bool Predicate_extloadf32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_extloadf64(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
+
+}
+inline bool Predicate_extloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_extloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_extloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_extloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_fp32imm0(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return N->isExactlyValue(+0.0);
+
+}
+inline bool Predicate_fpimm0(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return N->isExactlyValue(+0.0);
+
+}
+inline bool Predicate_fpimm1(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return N->isExactlyValue(+1.0);
+
+}
+inline bool Predicate_fpimmneg0(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return N->isExactlyValue(-0.0);
+
+}
+inline bool Predicate_fpimmneg1(SDNode *inN) {
+ ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
+
+ return N->isExactlyValue(-1.0);
+
+}
+inline bool Predicate_fsload(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ return PT->getAddressSpace() == 257;
+ return false;
+
+}
+inline bool Predicate_gsload(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ return PT->getAddressSpace() == 256;
+ return false;
+
+}
+inline bool Predicate_i16immSExt8(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
+ // sign extended field.
+ return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
+
+}
+inline bool Predicate_i32immSExt8(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
+ // sign extended field.
+ return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
+
+}
+inline bool Predicate_i64immSExt32(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+ // sign extended field.
+ return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
+
+}
+inline bool Predicate_i64immSExt8(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
+ // sign extended field.
+ return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
+
+}
+inline bool Predicate_i64immZExt32(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+
+ // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+ // unsignedsign extended field.
+ return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
+
+}
+inline bool Predicate_immAllOnes(SDNode *inN) {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
+ return N->isAllOnesValue();
+}
+inline bool Predicate_immAllOnesV(SDNode *N) {
+
+ return ISD::isBuildVectorAllOnes(N);
+
+}
+inline bool Predicate_immAllOnesV_bc(SDNode *N) {
+
+ return ISD::isBuildVectorAllOnes(N);
+
+}
+inline bool Predicate_immAllZerosV(SDNode *N) {
+
+ return ISD::isBuildVectorAllZeros(N);
+
+}
+inline bool Predicate_immAllZerosV_bc(SDNode *N) {
+
+ return ISD::isBuildVectorAllZeros(N);
+
+}
+inline bool Predicate_istore(SDNode *N) {
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_itruncstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_load(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
+
+}
+inline bool Predicate_loadf32(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
+
+}
+inline bool Predicate_loadf64(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
+
+}
+inline bool Predicate_loadf80(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
+
+}
+inline bool Predicate_loadi16(SDNode *N) {
+
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::NON_EXTLOAD)
+ return true;
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 2 && !LD->isVolatile();
+ return false;
+
+}
+inline bool Predicate_loadi16_anyext(SDNode *N) {
+
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 2 && !LD->isVolatile();
+ return false;
+
+}
+inline bool Predicate_loadi32(SDNode *N) {
+
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::NON_EXTLOAD)
+ return true;
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 4 && !LD->isVolatile();
+ return false;
+
+}
+inline bool Predicate_loadi64(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
+
+}
+inline bool Predicate_loadi8(SDNode *N) {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
+
+}
+inline bool Predicate_memop(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getAlignment() >= 16;
+
+}
+inline bool Predicate_memop64(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getAlignment() >= 8;
+
+}
+inline bool Predicate_mmx_pshufw(SDNode *N) {
+
+ return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_mmx_unpckh(SDNode *N) {
+
+ return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_mmx_unpckh_undef(SDNode *N) {
+
+ return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_mmx_unpckl(SDNode *N) {
+
+ return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_mmx_unpckl_undef(SDNode *N) {
+
+ return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movddup(SDNode *N) {
+
+ return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movhlps(SDNode *N) {
+
+ return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movhlps_undef(SDNode *N) {
+
+ return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movl(SDNode *N) {
+
+ return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movlhps(SDNode *N) {
+
+ return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movlp(SDNode *N) {
+
+ return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movshdup(SDNode *N) {
+
+ return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_movsldup(SDNode *N) {
+
+ return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_nvloadi32(SDNode *N) {
+
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ if (LD->isVolatile())
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::NON_EXTLOAD)
+ return true;
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 4;
+ return false;
+
+}
+inline bool Predicate_palign(SDNode *N) {
+
+ return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_post_store(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
+
+}
+inline bool Predicate_post_truncst(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
+
+}
+inline bool Predicate_post_truncstf32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_post_truncsti1(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_post_truncsti16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_post_truncsti32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_post_truncsti8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_pre_store(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+
+}
+inline bool Predicate_pre_truncst(SDNode *N) {
+
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+
+}
+inline bool Predicate_pre_truncstf32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_pre_truncsti1(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_pre_truncsti16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_pre_truncsti32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_pre_truncsti8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_pshufd(SDNode *N) {
+
+ return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_pshufhw(SDNode *N) {
+
+ return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_pshuflw(SDNode *N) {
+
+ return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_sextload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
+
+}
+inline bool Predicate_sextloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_sextloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_sextloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_sextloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_shld(SDNode *N) {
+
+ assert(N->getOpcode() == ISD::OR);
+ return N->getOperand(0).getOpcode() == ISD::SHL &&
+ N->getOperand(1).getOpcode() == ISD::SRL &&
+ isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
+ isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
+ N->getOperand(0).getConstantOperandVal(1) ==
+ N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
+
+}
+inline bool Predicate_shrd(SDNode *N) {
+
+ assert(N->getOpcode() == ISD::OR);
+ return N->getOperand(0).getOpcode() == ISD::SRL &&
+ N->getOperand(1).getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
+ isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
+ N->getOperand(0).getConstantOperandVal(1) ==
+ N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
+
+}
+inline bool Predicate_shufp(SDNode *N) {
+
+ return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_splat_lo(SDNode *N) {
+
+ ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+ return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
+
+}
+inline bool Predicate_srl_su(SDNode *N) {
+
+ return N->hasOneUse();
+
+}
+inline bool Predicate_store(SDNode *N) {
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_trunc_su(SDNode *N) {
+
+ return N->hasOneUse();
+
+}
+inline bool Predicate_truncstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->isTruncatingStore();
+
+}
+inline bool Predicate_truncstoref32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+
+}
+inline bool Predicate_truncstoref64(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
+
+}
+inline bool Predicate_truncstorei16(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_truncstorei32(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_truncstorei8(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+inline bool Predicate_unindexedload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+}
+inline bool Predicate_unindexedstore(SDNode *N) {
+
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+}
+inline bool Predicate_unpckh(SDNode *N) {
+
+ return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_unpckh_undef(SDNode *N) {
+
+ return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_unpckl(SDNode *N) {
+
+ return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_unpckl_undef(SDNode *N) {
+
+ return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
+
+}
+inline bool Predicate_vtFP(SDNode *inN) {
+ VTSDNode *N = cast<VTSDNode>(inN);
+ return N->getVT().isFloatingPoint();
+}
+inline bool Predicate_vtInt(SDNode *inN) {
+ VTSDNode *N = cast<VTSDNode>(inN);
+ return N->getVT().isInteger();
+}
+inline bool Predicate_zextload(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
+
+}
+inline bool Predicate_zextloadi1(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+
+}
+inline bool Predicate_zextloadi16(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+
+}
+inline bool Predicate_zextloadi32(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+
+}
+inline bool Predicate_zextloadi8(SDNode *N) {
+
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+
+}
+
+
+DISABLE_INLINE SDNode *Emit_0(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0);
+}
+DISABLE_INLINE SDNode *Emit_1(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, N1);
+}
+DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_3(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_ISD_ADD_i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
+ // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (add:i8 GR8:i8:$src, 1:i8)
+ // Emits: (INC8r:i8 GR8:i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_0(N, X86::INC8r, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (add:i8 GR8:i8:$src, -1:i8)
+ // Emits: (DEC8r:i8 GR8:i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(-1)) {
+ SDNode *Result = Emit_0(N, X86::DEC8r, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD8rr, MVT::i8);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_6(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+}
+SDNode *Select_ISD_ADD_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
+ // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (add:i16 GR16:i16:$src, 1:i16)
+ // Emits: (INC16r:i16 GR16:i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 1
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_0(N, X86::INC16r, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (add:i16 GR16:i16:$src, -1:i16)
+ // Emits: (DEC16r:i16 GR16:i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 1
+ if (CN1 == INT64_C(-1)) {
+ SDNode *Result = Emit_0(N, X86::DEC16r, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (add:i16 GR16:i16:$src, 1:i16)
+ // Emits: (INC64_16r:i16 GR16:i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_0(N, X86::INC64_16r, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (add:i16 GR16:i16:$src, -1:i16)
+ // Emits: (DEC64_16r:i16 GR16:i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(-1)) {
+ SDNode *Result = Emit_0(N, X86::DEC64_16r, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i16 GR16:i16:$src1, 128:i16)
+ // Emits: (SUB16ri8:i16 GR16:i16:$src1, -128:i16)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(128)) {
+ SDNode *Result = Emit_6(N, X86::SUB16ri8, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::ADD16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (add:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (ADD16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::ADD16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD16rr, MVT::i16);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_7(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2, SDValue &CPTmpN_3) {
+ SDValue Ops0[] = { CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3 };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_8(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_9(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_10(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N10);
+}
+DISABLE_INLINE SDNode *Emit_11(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N00);
+}
+SDNode *Select_ISD_ADD_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tconstpool:i32):$src2))
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tconstpool:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tjumptable:i32):$src2))
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tjumptable:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tglobaladdr:i32):$src2))
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tglobaladdr:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (texternalsym:i32):$src2))
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (texternalsym:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tblockaddress:i32):$src2))
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tblockaddress:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::Wrapper) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (add:i32 (X86Wrapper:i32 (tconstpool:i32):$src2), GR32:i32:$src1)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tconstpool:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (X86Wrapper:i32 (tjumptable:i32):$src2), GR32:i32:$src1)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tjumptable:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (X86Wrapper:i32 (tglobaladdr:i32):$src2), GR32:i32:$src1)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tglobaladdr:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (X86Wrapper:i32 (texternalsym:i32):$src2), GR32:i32:$src1)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (texternalsym:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 (X86Wrapper:i32 (tblockaddress:i32):$src2), GR32:i32:$src1)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (tblockaddress:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (add:i32 GR32:i32:$src, 1:i32)
+ // Emits: (INC32r:i32 GR32:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 1
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_0(N, X86::INC32r, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src, -1:i32)
+ // Emits: (DEC32r:i32 GR32:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 1
+ if (CN1 == INT64_C(-1)) {
+ SDNode *Result = Emit_0(N, X86::DEC32r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (add:i32 GR32:i32:$src, 1:i32)
+ // Emits: (INC64_32r:i32 GR32:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_0(N, X86::INC64_32r, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src, -1:i32)
+ // Emits: (DEC64_32r:i32 GR32:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(-1)) {
+ SDNode *Result = Emit_0(N, X86::DEC64_32r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (add:i32 GR32:i32:$src1, 128:i32)
+ // Emits: (SUB32ri8:i32 GR32:i32:$src1, -128:i32)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(128)) {
+ SDNode *Result = Emit_9(N, X86::SUB32ri8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::ADD32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (add:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD32rr, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_12(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_13(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_14(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFF80000000ULL, MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+}
+SDNode *Select_ISD_ADD_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: lea64addr:i64:$src
+ // Emits: (LEA64r:i64 lea64addr:i64:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (add:i64 GR64:i64:$src, 1:i64)
+ // Emits: (INC64r:i64 GR64:i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_0(N, X86::INC64r, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (add:i64 GR64:i64:$src, -1:i64)
+ // Emits: (DEC64r:i64 GR64:i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ if (CN1 == INT64_C(-1)) {
+ SDNode *Result = Emit_0(N, X86::DEC64r, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (add:i64 GR64:i64:$src1, 128:i64)
+ // Emits: (SUB64ri8:i64 GR64:i64:$src1, -128:i64)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(128)) {
+ SDNode *Result = Emit_13(N, X86::SUB64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (add:i64 GR64:i64:$src1, 2147483648:i64)
+ // Emits: (SUB64ri32:i64 GR64:i64:$src1, -2147483648:i64)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(2147483648)) {
+ SDNode *Result = Emit_14(N, X86::SUB64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (add:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::ADD64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (add:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::ADD64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (add:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_15(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1);
+}
+DISABLE_INLINE SDNode *Emit_16(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_17(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PADDBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PADDBrr, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PADDBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v16i8 (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PADDBrm, MVT::v16i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PADDBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PADDBrr, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PADDWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PADDWrr, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PADDWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PADDWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PADDWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PADDWrr, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
+ // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PADDDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PADDDrr, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PADDDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PADDDrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PADDDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PADDDrr, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v1i64 (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v1i64:$src1)
+ // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PADDQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PADDQrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_18(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_19(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (add:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PADDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PADDQrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (add:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PADDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PADDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_20(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_21(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ SDValue InFlag(ResNode, 2);
+ const SDValue Froms[] = {
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 1)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ InFlag
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_22(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ SDValue InFlag(ResNode, 2);
+ const SDValue Froms[] = {
+ SDValue(N0.getNode(), 1),
+ SDValue(N.getNode(), 1)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ InFlag
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (addc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_21(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (addc:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_23(N, X86::ADD32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (addc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_22(N, X86::ADD32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (addc:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_22(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (addc:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_20(N, X86::ADD32rr, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_24(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDValue InFlag(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (addc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_21(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (addc:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_23(N, X86::ADD64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (addc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_24(N, X86::ADD64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (addc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_24(N, X86::ADD64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (addc:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_20(N, X86::ADD64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_25(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ InFlag = SDValue(ResNode, 2);
+ const SDValue Froms[] = {
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 1)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ InFlag
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ InFlag = SDValue(ResNode, 2);
+ const SDValue Froms[] = {
+ SDValue(N0.getNode(), 1),
+ SDValue(N.getNode(), 1)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ InFlag
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDE_i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (adde:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADC8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::ADC8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (adde:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
+ // Emits: (ADC8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_28(N, X86::ADC8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (adde:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ADC8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_27(N, X86::ADC8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (ADC8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::ADC8rr, MVT::i8);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_29(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDE_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (adde:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADC16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::ADC16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (adde:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
+ // Emits: (ADC16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_28(N, X86::ADC16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (adde:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (ADC16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_29(N, X86::ADC16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (adde:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (ADC16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_29(N, X86::ADC16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (ADC16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::ADC16rr, MVT::i16);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_30(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (adde:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADC32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::ADC32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (adde:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
+ // Emits: (ADC32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_28(N, X86::ADC32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (adde:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (ADC32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_30(N, X86::ADC32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (adde:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (ADC32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_30(N, X86::ADC32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (adde:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (ADC32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::ADC32rr, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_31(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ InFlag = SDValue(ResNode, 1);
+ ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ return ResNode;
+}
+SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (adde:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADC64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::ADC64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (adde:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (ADC64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_28(N, X86::ADC64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (adde:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (ADC64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_31(N, X86::ADC64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (adde:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (ADC64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_31(N, X86::ADC64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (adde:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (ADC64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::ADC64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_AND_i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
+ // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (AND8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND8rr, MVT::i8);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_32(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp3, Tmp4), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_33(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3);
+}
+SDNode *Select_ISD_AND_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
+ // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i16 GR16:i16:$src1, 255:i16)
+ // Emits: (MOVZX16rr8:i16 (EXTRACT_SUBREG:i8 GR16:i16:$src1, 1:i32))
+ // Pattern complexity = 8 cost = 2 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i8, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i16 GR16:i16:$src1, 255:i16)
+ // Emits: (MOVZX16rr8:i16 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src1, GR16_ABCD:i16), 1:i32))
+ // Pattern complexity = 8 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_32(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i16, MVT::i8, MVT::i16);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (AND16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::AND16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (and:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (AND16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::AND16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (AND16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND16rr, MVT::i16);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_34(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_35(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_36(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp3, Tmp4), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_37(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp4), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp7);
+}
+SDNode *Select_ISD_AND_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+
+ // Pattern: (and:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_nvloadi32>>, 255:i32)
+ // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
+ N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_nvloadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_34(N, X86::MOVZX32rm8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_nvloadi32>>, 65535:i32)
+ // Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
+ N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_nvloadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_34(N, X86::MOVZX32rm16, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
+ // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i32)
+ // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
+ // Pattern complexity = 17 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(255)) &&
+ N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_37(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i32)
+ // Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
+ // Pattern complexity = 17 cost = 3 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(255)) &&
+ N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_37(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i32, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i32 GR32:i32:$src1, 65535:i32)
+ // Emits: (MOVZX32rr16:i32 (EXTRACT_SUBREG:i16 GR32:i32:$src1, 3:i32))
+ // Pattern complexity = 8 cost = 2 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_35(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr16, MVT::i16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GR32:i32:$src1, 255:i32)
+ // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 GR32:i32:$src1, 1:i32))
+ // Pattern complexity = 8 cost = 2 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GR32:i32:$src1, 255:i32)
+ // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src1, GR32_ABCD:i32), 1:i32))
+ // Pattern complexity = 8 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0 &&
+ CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_36(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (AND32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::AND32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (and:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (AND32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::AND32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (AND32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND32rr, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_38(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_39(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
+ SDValue Tmp5 = CurDAG->getTargetConstant(X86::GR64_ABCDRegClassID, MVT::i32);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp5), 0);
+ SDValue Tmp7 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp8(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp6, Tmp7), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp8), 0);
+ SDValue Tmp10 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp3, Tmp9, Tmp10);
+}
+SDNode *Select_ISD_AND_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+
+ // Pattern: (and:i64 (srl:i64 GR64:i64:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i64)
+ // Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i64 GR64:i64:$src, GR64_ABCD:i64), 2:i32)), 4:i32)
+ // Pattern complexity = 17 cost = 4 size = 3
+ if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
+ N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp1) {
+ int64_t CN2 = Tmp1->getSExtValue();
+ if (CN2 == INT64_C(8) &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_39(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i64, MVT::i8, MVT::i32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i64 GR64:i64:$src, 4294967295:i64)
+ // Emits: (MOVZX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
+ // Pattern complexity = 8 cost = 2 size = 3
+ if (CheckAndMask(N0, Tmp0, INT64_C(4294967295))) {
+ SDNode *Result = Emit_38(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr32, MVT::i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (and:i64 GR64:i64:$src, 65535:i64)
+ // Emits: (MOVZX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
+ // Pattern complexity = 8 cost = 2 size = 3
+ if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
+ SDNode *Result = Emit_35(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr16, MVT::i16, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (and:i64 GR64:i64:$src, 255:i64)
+ // Emits: (MOVZX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
+ // Pattern complexity = 8 cost = 2 size = 3
+ if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
+ SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr8, MVT::i8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (AND64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::AND64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (AND64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::AND64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (AND64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_40(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N1);
+}
+DISABLE_INLINE SDNode *Emit_41(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_42(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N1);
+}
+DISABLE_INLINE SDNode *Emit_43(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_44(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N01, N1);
+}
+DISABLE_INLINE SDNode *Emit_45(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N0);
+}
+DISABLE_INLINE SDNode *Emit_46(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N11, N0);
+}
+DISABLE_INLINE SDNode *Emit_47(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N01, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_48(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_49(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N11, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_50(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N01, N1);
+}
+DISABLE_INLINE SDNode *Emit_51(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N0);
+}
+DISABLE_INLINE SDNode *Emit_52(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N11, N0);
+}
+DISABLE_INLINE SDNode *Emit_53(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N01, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_54(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_55(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N11, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N010.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_43(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_43(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_43(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_53(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_53(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_53(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode()) &&
+ N110.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_41(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_47(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_48(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_49(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
+ // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_42(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_42(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_42(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_50(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_50(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_50(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode()) &&
+ N110.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDNode *Result = Emit_40(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), VR64:v1i64:$src2)
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_45(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_46(N, X86::MMX_PANDNrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PANDrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PANDrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_56(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_57(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N000, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_58(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10);
+}
+DISABLE_INLINE SDNode *Emit_59(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, N10);
+}
+DISABLE_INLINE SDNode *Emit_60(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N000, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_61(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_62(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N010, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_63(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N100, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_64(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N110, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_65(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N010, N10);
+}
+DISABLE_INLINE SDNode *Emit_66(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100, N00);
+}
+DISABLE_INLINE SDNode *Emit_67(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N110, N00);
+}
+DISABLE_INLINE SDNode *Emit_68(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N010, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_69(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N100, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_70(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N110, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4f32 &&
+ N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_57(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4i32 &&
+ N010.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_62(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N100.getValueType() == MVT::v4f32 &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_63(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)))
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N100.getValueType() == MVT::v4i32 &&
+ N110.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_64(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_60(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_43(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_43(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_43(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N010.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_68(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode()) &&
+ N100.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_69(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_70(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_53(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_53(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_53(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_41(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_47(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_48(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_49(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_56(N, X86::ANDPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_56(N, X86::ANDPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
+ // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_61(N, X86::ANDPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
+ // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_61(N, X86::ANDPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PANDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PANDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N000.getValueType() == MVT::v2f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_59(N, X86::ANDNPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N010.getValueType() == MVT::v2f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_65(N, X86::ANDNPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src2), (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode()) &&
+ N00.getValueType() == MVT::v2f64 &&
+ N100.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_66(N, X86::ANDNPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src2), (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
+ // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N00.getValueType() == MVT::v2f64 &&
+ N110.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_67(N, X86::ANDNPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
+ // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_42(N, X86::ANDNPSrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_42(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_42(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_42(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
+ // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_50(N, X86::ANDNPSrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_51(N, X86::ANDNPSrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_52(N, X86::ANDNPSrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_50(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_50(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N000.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_50(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ if (N100.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getOperand(0);
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDNode *Result = Emit_40(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), VR128:v2i64:$src2)
+ // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDNode *Result = Emit_44(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_45(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
+ // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 10 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_46(N, X86::PANDNrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (ANDPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N00.getValueType() == MVT::v2f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_58(N, X86::ANDPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (ANDPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::ANDPSrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (and:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PANDrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PANDrr, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_71(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+}
+DISABLE_INLINE SDNode *Emit_72(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getDebugLoc(), X86::EFLAGS, N01, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, InFlag);
+}
+SDNode *Select_ISD_ANY_EXTEND_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (anyext:i16 (X86setcc_c:i8 2:i8, EFLAGS:i32))
+ // Emits: (SETB_C16r:i16)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_72(N, X86::SETB_C16r, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (anyext:i16 GR8:i8:$src)
+ // Emits: (MOVZX16rr8:i16 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVZX16rr8, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_73(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp4, Tmp5), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp6);
+}
+SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
+
+ // Pattern: (anyext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
+ // Pattern complexity = 12 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (anyext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
+ // Pattern complexity = 12 cost = 3 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (anyext:i32 (X86setcc_c:i8 2:i8, EFLAGS:i32))
+ // Emits: (SETB_C32r:i32)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_72(N, X86::SETB_C32r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (anyext:i32 GR8:i8:$src)
+ // Emits: (MOVZX32rr8:i32 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVZX32rr8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (anyext:i32 GR16:i16:$src)
+ // Emits: (MOVZX32rr16:i32 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_71(N, X86::MOVZX32rr16, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_74(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_75(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
+ SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp4), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ SDValue Tmp8(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp7), 0);
+ SDValue Tmp9 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp2, Tmp8, Tmp9);
+}
+SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (anyext:i64 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 4:i32)
+ // Pattern complexity = 12 cost = 4 size = 3
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_75(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (anyext:i64 (X86setcc_c:i8 2:i8, EFLAGS:i32))
+ // Emits: (SETB_C64r:i64)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_72(N, X86::SETB_C64r, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (anyext:i64 GR32:i32:$src)
+ // Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_74(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (anyext:i64 GR8:i8:$src)
+ // Emits: (MOVZX64rr8:i64 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVZX64rr8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (anyext:i64 GR16:i16:$src)
+ // Emits: (MOVZX64rr16:i64 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_71(N, X86::MOVZX64rr16, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_add_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::LXADD8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_add_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::LXADD16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_add_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::LXADD32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_add_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::LXADD64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_and_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_and_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_and_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_and_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_MAX_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_max_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_MAX_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_max_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_MAX_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_max_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_MIN_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_min_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_MIN_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_min_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_MIN_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_min_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_nand_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMNAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_nand_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMNAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_nand_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMNAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_nand_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMNAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_or_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_or_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_or_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_or_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_umax_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMUMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_umax_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMUMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_umax_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMUMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_umin_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMUMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_umin_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMUMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_umin_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMUMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_xor_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMXOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_xor_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMXOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_xor_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMXOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_load_xor_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::ATOMXOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_swap_8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::XCHG8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_swap_16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::XCHG16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_swap_32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::XCHG32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ATOMIC_SWAP_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_atomic_swap_64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_76(N, X86::XCHG64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_i32(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::MOVSS2DIrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
+
+ // Pattern: (bitconvert:i64 FR64:f64:$src)
+ // Emits: (MOVSDto64rr:i64 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::MOVSDto64rr, MVT::i64);
+ return Result;
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:i64 VR64:v1i64:$src)
+ // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:i64 VR64:v2i32:$src)
+ // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:i64 VR64:v2f32:$src)
+ // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:i64 VR64:v4i16:$src)
+ // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:i64 VR64:v8i8:$src)
+ // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
+
+ // Pattern: (bitconvert:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (MOVDI2SSrm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_77(N, X86::MOVDI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (bitconvert:f32 GR32:i32:$src)
+ // Emits: (MOVDI2SSrr:f32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::MOVDI2SSrr, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
+
+ // Pattern: (bitconvert:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (MOV64toSDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_77(N, X86::MOV64toSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (bitconvert:f64 GR64:i64:$src)
+ // Emits: (MOV64toSDrr:f64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MOV64toSDrr, MVT::f64);
+ return Result;
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:f64 VR64:v1i64:$src)
+ // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 VR64:v2i32:$src)
+ // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 VR64:v4i16:$src)
+ // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:f64 VR64:v8i8:$src)
+ // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_78(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ReplaceUses(N, N0);
+ return NULL;
+}
+DISABLE_INLINE SDNode *Emit_79(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
+}
+SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v8i8 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
+ // Emits: (MMX_MOVDQ2Qrr:v8i8 VR128:v16i8:$src)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64 &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v8i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (bitconvert:v8i8 VR64:v1i64:$src)
+ // Emits: VR64:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 VR64:v2i32:$src)
+ // Emits: VR64:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 VR64:v2f32:$src)
+ // Emits: VR64:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 VR64:v4i16:$src)
+ // Emits: VR64:v8i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i8 GR64:i64:$src)
+ // Emits: (MMX_MOVD64to64rr:v8i8 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v16i8 VR128:v2i64:$src)
+ // Emits: VR128:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 VR128:v4i32:$src)
+ // Emits: VR128:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 VR128:v8i16:$src)
+ // Emits: VR128:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 VR128:v2f64:$src)
+ // Emits: VR128:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v16i8 VR128:v4f32:$src)
+ // Emits: VR128:v16i8:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4i16 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
+ // Emits: (MMX_MOVDQ2Qrr:v4i16 VR128:v16i8:$src)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64 &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (bitconvert:v4i16 VR64:v1i64:$src)
+ // Emits: VR64:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 VR64:v2i32:$src)
+ // Emits: VR64:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 VR64:v2f32:$src)
+ // Emits: VR64:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 VR64:v8i8:$src)
+ // Emits: VR64:v4i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i16 GR64:i64:$src)
+ // Emits: (MMX_MOVD64to64rr:v4i16 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v8i16 VR128:v2i64:$src)
+ // Emits: VR128:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 VR128:v4i32:$src)
+ // Emits: VR128:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 VR128:v16i8:$src)
+ // Emits: VR128:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 VR128:v2f64:$src)
+ // Emits: VR128:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v8i16 VR128:v4f32:$src)
+ // Emits: VR128:v8i16:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0101_0, SDValue &CPTmpN0101_1, SDValue &CPTmpN0101_2, SDValue &CPTmpN0101_3, SDValue &CPTmpN0101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue Chain010 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N010)->getMemOperand();
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, N0101, N0101, Chain010);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N010.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
+
+ // Pattern: (bitconvert:v2i32 (vector_shuffle:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>)
+ // Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 56 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N0.hasOneUse() &&
+ Predicate_mmx_unpckl(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N00.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N01.hasOneUse()) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::LOAD &&
+ N010.hasOneUse() &&
+ IsLegalAndProfitableToFold(N010.getNode(), N01.getNode(), N.getNode())) {
+ SDValue Chain010 = N010.getOperand(0);
+ if (Predicate_unindexedload(N010.getNode()) &&
+ Predicate_load(N010.getNode())) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue CPTmpN0101_0;
+ SDValue CPTmpN0101_1;
+ SDValue CPTmpN0101_2;
+ SDValue CPTmpN0101_3;
+ SDValue CPTmpN0101_4;
+ if (SelectAddr(N, N0101, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4) &&
+ N0.getValueType() == MVT::v2i32 &&
+ N010.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_80(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2i32 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
+ // Emits: (MMX_MOVDQ2Qrr:v2i32 VR128:v16i8:$src)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64 &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (bitconvert:v2i32 VR64:v1i64:$src)
+ // Emits: VR64:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 VR64:v2f32:$src)
+ // Emits: VR64:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 VR64:v4i16:$src)
+ // Emits: VR64:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 VR64:v8i8:$src)
+ // Emits: VR64:v2i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i32 GR64:i64:$src)
+ // Emits: (MMX_MOVD64to64rr:v2i32 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4i32 VR128:v2i64:$src)
+ // Emits: VR128:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 VR128:v8i16:$src)
+ // Emits: VR128:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 VR128:v16i8:$src)
+ // Emits: VR128:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 VR128:v2f64:$src)
+ // Emits: VR128:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4i32 VR128:v4f32:$src)
+ // Emits: VR128:v4i32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
+
+ // Pattern: (bitconvert:v1i64 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
+ // Emits: (MMX_MOVDQ2Qrr:v1i64 VR128:v2i64:$src)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64 &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_79(N, X86::MMX_MOVDQ2Qrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v1i64 VR64:v2i32:$src)
+ // Emits: VR64:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 VR64:v2f32:$src)
+ // Emits: VR64:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 VR64:v4i16:$src)
+ // Emits: VR64:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 VR64:v8i8:$src)
+ // Emits: VR64:v1i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v1i64 GR64:i64:$src)
+ // Emits: (MMX_MOVD64to64rr:v1i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2i64 VR128:v4i32:$src)
+ // Emits: VR128:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 VR128:v8i16:$src)
+ // Emits: VR128:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 VR128:v16i8:$src)
+ // Emits: VR128:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 VR128:v2f64:$src)
+ // Emits: VR128:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2i64 VR128:v4f32:$src)
+ // Emits: VR128:v2i64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2f32 VR64:v1i64:$src)
+ // Emits: VR64:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 VR64:v2i32:$src)
+ // Emits: VR64:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 VR64:v4i16:$src)
+ // Emits: VR64:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 VR64:v8i8:$src)
+ // Emits: VR64:v2f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f32 GR64:i64:$src)
+ // Emits: (MMX_MOVD64to64rr:v2f32 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v2f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v4f32 VR128:v2i64:$src)
+ // Emits: VR128:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 VR128:v4i32:$src)
+ // Emits: VR128:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 VR128:v8i16:$src)
+ // Emits: VR128:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 VR128:v16i8:$src)
+ // Emits: VR128:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v4f32 VR128:v2f64:$src)
+ // Emits: VR128:v4f32:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (bitconvert:v2f64 VR128:v2i64:$src)
+ // Emits: VR128:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 VR128:v4i32:$src)
+ // Emits: VR128:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 VR128:v8i16:$src)
+ // Emits: VR128:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 VR128:v16i8:$src)
+ // Emits: VR128:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+
+ // Pattern: (bitconvert:v2f64 VR128:v4f32:$src)
+ // Emits: VR128:v2f64:$src
+ // Pattern complexity = 3 cost = 0 size = 0
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_78(N);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
+}
+SDNode *Select_ISD_BR(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BasicBlock) {
+ SDNode *Result = Emit_81(N, X86::JMP);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N1.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain1);
+ Chain1 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ Chain1 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ const SDValue Froms[] = {
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain1.getNode(), Chain1.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_BRIND(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (brind:isVoid (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (JMP32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_82(N, X86::JMP32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (brind:isVoid (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (JMP64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_82(N, X86::JMP64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (brind:isVoid GR32:i32:$dst)
+ // Emits: (JMP32r:isVoid GR32:i32:$dst)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_81(N, X86::JMP32r);
+ return Result;
+ }
+
+ // Pattern: (brind:isVoid GR64:i64:$dst)
+ // Emits: (JMP64r:isVoid GR64:i64:$dst)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_81(N, X86::JMP64r);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BSWAP_i32(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::BSWAP32r, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_BSWAP_i64(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::BSWAP64r, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0);
+}
+SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
+ if ((Subtarget->hasMMX()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
+ if ((Subtarget->hasMMX()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
+ if ((Subtarget->hasMMX())) {
+
+ // Pattern: (build_vector:v2i32)<<P:Predicate_immAllZerosV>>
+ // Emits: (MMX_V_SET0:v2i32)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (build_vector:v2i32)<<P:Predicate_immAllOnesV>>
+ // Emits: (MMX_V_SETALLONES:v2i32)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_immAllOnesV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::MMX_V_SETALLONES, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
+
+ // Pattern: (build_vector:v4i32)<<P:Predicate_immAllZerosV>>
+ // Emits: (V_SET0:v4i32)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (build_vector:v4i32)<<P:Predicate_immAllOnesV>>
+ // Emits: (V_SETALLONES:v4i32)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_immAllOnesV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SETALLONES, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
+ if ((Subtarget->hasMMX()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::MMX_V_SET0, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v4f32(const SDValue &N) {
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_BUILD_VECTOR_v2f64(const SDValue &N) {
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_immAllZerosV(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::V_SET0, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { N1, N2, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
+
+ // Pattern: (X86callseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
+ // Emits: (ADJCALLSTACKUP32:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_84(N, X86::ADJCALLSTACKUP32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86callseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
+ // Emits: (ADJCALLSTACKUP64:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_84(N, X86::ADJCALLSTACKUP64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain);
+ Chain = SDValue(ResNode, 0);
+ SDValue InFlag(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
+
+ // Pattern: (X86callseq_start:isVoid (timm:i32):$amt)
+ // Emits: (ADJCALLSTACKDOWN32:isVoid (timm:i32):$amt)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_85(N, X86::ADJCALLSTACKDOWN32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86callseq_start:isVoid (timm:i32):$amt)
+ // Emits: (ADJCALLSTACKDOWN64:isVoid (timm:i32):$amt)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_85(N, X86::ADJCALLSTACKDOWN64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+}
+SDNode *Select_ISD_Constant_i8(const SDValue &N) {
+
+ // Pattern: 0:i8
+ // Emits: (MOV8r0:i8)
+ // Pattern complexity = 5 cost = 1 size = 3
+ if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
+ SDNode *Result = Emit_83(N, X86::MOV8r0, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (imm:i8):$src
+ // Emits: (MOV8ri:i8 (imm:i8):$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_86(N, X86::MOV8ri, MVT::i8);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+}
+SDNode *Select_ISD_Constant_i16(const SDValue &N) {
+
+ // Pattern: 0:i16
+ // Emits: (MOV16r0:i16)
+ // Pattern complexity = 5 cost = 1 size = 3
+ if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
+ SDNode *Result = Emit_83(N, X86::MOV16r0, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (imm:i16):$src
+ // Emits: (MOV16ri:i16 (imm:i16):$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_87(N, X86::MOV16ri, MVT::i16);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+}
+SDNode *Select_ISD_Constant_i32(const SDValue &N) {
+
+ // Pattern: 0:i32
+ // Emits: (MOV32r0:i32)
+ // Pattern complexity = 5 cost = 1 size = 3
+ if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
+ SDNode *Result = Emit_83(N, X86::MOV32r0, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (imm:i32):$src
+ // Emits: (MOV32ri:i32 (imm:i32):$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_88(N, X86::MOV32ri, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+}
+DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, Tmp1, Tmp2);
+}
+SDNode *Select_ISD_Constant_i64(const SDValue &N) {
+
+ // Pattern: 0:i64
+ // Emits: (SUBREG_TO_REG:i64 0:i64, (MOV32r0:i32), 4:i32)
+ // Pattern complexity = 6 cost = 2 size = 3
+ if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
+ SDNode *Result = Emit_90(N, X86::MOV32r0, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (imm:i64)<<P:Predicate_i64immZExt32>>:$src
+ // Emits: (MOV64ri64i32:i64 (imm:i64):$src)
+ // Pattern complexity = 5 cost = 1 size = 3
+ if (Predicate_i64immZExt32(N.getNode())) {
+ SDNode *Result = Emit_89(N, X86::MOV64ri64i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (imm:i64)<<P:Predicate_i64immSExt32>>:$src
+ // Emits: (MOV64ri32:i64 (imm:i64):$src)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N.getNode())) {
+ SDNode *Result = Emit_89(N, X86::MOV64ri32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (imm:i64):$src
+ // Emits: (MOV64ri:i64 (imm:i64):$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_89(N, X86::MOV64ri, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0);
+}
+SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+
+ // Pattern: (fpimm:f32)<<P:Predicate_fpimm0>>
+ // Emits: (LD_Fp032:f32)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_fpimm0(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::LD_Fp032, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f32)<<P:Predicate_fpimm1>>
+ // Emits: (LD_Fp132:f32)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_fpimm1(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::LD_Fp132, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fpimm:f32)<<P:Predicate_fp32imm0>>
+ // Emits: (FsFLD0SS:f32)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_fp32imm0(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::FsFLD0SS, MVT::f32);
+ return Result;
+ }
+ if ((!Subtarget->hasSSE1())) {
+
+ // Pattern: (fpimm:f32)<<P:Predicate_fpimmneg0>>
+ // Emits: (CHS_Fp32:f32 (LD_Fp032:f32))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_fpimmneg0(N.getNode())) {
+ SDNode *Result = Emit_91(N, X86::LD_Fp032, X86::CHS_Fp32, MVT::f32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f32)<<P:Predicate_fpimmneg1>>
+ // Emits: (CHS_Fp32:f32 (LD_Fp132:f32))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_fpimmneg1(N.getNode())) {
+ SDNode *Result = Emit_91(N, X86::LD_Fp132, X86::CHS_Fp32, MVT::f32, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+
+ // Pattern: (fpimm:f64)<<P:Predicate_fpimm0>>
+ // Emits: (LD_Fp064:f64)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_fpimm0(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::LD_Fp064, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f64)<<P:Predicate_fpimm1>>
+ // Emits: (LD_Fp164:f64)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_fpimm1(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::LD_Fp164, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fpimm:f64)<<P:Predicate_fpimm0>>
+ // Emits: (FsFLD0SD:f64)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_fpimm0(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::FsFLD0SD, MVT::f64);
+ return Result;
+ }
+ if ((!Subtarget->hasSSE2())) {
+
+ // Pattern: (fpimm:f64)<<P:Predicate_fpimmneg0>>
+ // Emits: (CHS_Fp64:f64 (LD_Fp064:f64))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_fpimmneg0(N.getNode())) {
+ SDNode *Result = Emit_91(N, X86::LD_Fp064, X86::CHS_Fp64, MVT::f64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f64)<<P:Predicate_fpimmneg1>>
+ // Emits: (CHS_Fp64:f64 (LD_Fp164:f64))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_fpimmneg1(N.getNode())) {
+ SDNode *Result = Emit_91(N, X86::LD_Fp164, X86::CHS_Fp64, MVT::f64, MVT::f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
+
+ // Pattern: (fpimm:f80)<<P:Predicate_fpimm0>>
+ // Emits: (LD_Fp080:f80)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_fpimm0(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::LD_Fp080, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f80)<<P:Predicate_fpimm1>>
+ // Emits: (LD_Fp180:f80)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_fpimm1(N.getNode())) {
+ SDNode *Result = Emit_83(N, X86::LD_Fp180, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f80)<<P:Predicate_fpimmneg0>>
+ // Emits: (CHS_Fp80:f80 (LD_Fp080:f80))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_fpimmneg0(N.getNode())) {
+ SDNode *Result = Emit_91(N, X86::LD_Fp080, X86::CHS_Fp80, MVT::f80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (fpimm:f80)<<P:Predicate_fpimmneg1>>
+ // Emits: (CHS_Fp80:f80 (LD_Fp180:f80))
+ // Pattern complexity = 4 cost = 2 size = 0
+ if (Predicate_fpimmneg1(N.getNode())) {
+ SDNode *Result = Emit_91(N, X86::LD_Fp180, X86::CHS_Fp80, MVT::f80, MVT::f80);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+}
+DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, Tmp1);
+}
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
+
+ // Pattern: (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2)
+ // Emits: (EXTRACTPSrr:i32 VR128:v4f32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32 &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_94(N, X86::EXTRACTPSrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (vector_extract:i32 VR128:v4i32:$src, 0:iPTR)
+ // Emits: (MOVPDI2DIrr:i32 VR128:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_92(N, X86::MOVPDI2DIrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (extractelt:i32 VR128:v4i32:$src1, (imm:iPTR):$src2)
+ // Emits: (PEXTRDrr:i32 VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_93(N, X86::PEXTRDrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(const SDValue &N) {
+
+ // Pattern: (vector_extract:i64 VR128:v2i64:$src, 0:iPTR)
+ // Emits: (MOVPQIto64rr:i64 VR128:v2i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_92(N, X86::MOVPQIto64rr, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (extractelt:i64 VR128:v2i64:$src1, (imm:iPTR):$src2)
+ // Emits: (PEXTRQrr:i64 VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_93(N, X86::PEXTRQrr, MVT::i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_92(N, X86::MOVPS2SSrr, MVT::f32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_92(N, X86::MOVPD2SDrr, MVT::f64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FABS_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::ABS_Fp32, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FABS_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::ABS_Fp64, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FABS_f80(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::ABS_Fp80, MVT::f80);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N02 = N0.getOperand(2);
+ SDValue N1 = N.getOperand(1);
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_FADD_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
+ // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
+ // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fadd:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
+ // Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fadd:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
+ // Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::FILD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N02 = N0.getOperand(2);
+
+ // Pattern: (fadd:f32 (X86fild:f32 addr:iPTR:$src2, i16:Other), RFP32:f32:$src1)
+ // Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (fadd:f32 (X86fild:f32 addr:iPTR:$src2, i32:Other), RFP32:f32:$src1)
+ // Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (ADD_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::ADD_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fadd:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (ADDSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::ADDSSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FADD_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
+
+ // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
+ // Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
+ // Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N0.getNode()) &&
+ Predicate_extloadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
+ // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fadd:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
+ // Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fadd:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
+ // Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::FILD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N02 = N0.getOperand(2);
+
+ // Pattern: (fadd:f64 (X86fild:f64 addr:iPTR:$src2, i16:Other), RFP64:f64:$src1)
+ // Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (fadd:f64 (X86fild:f64 addr:iPTR:$src2, i32:Other), RFP64:f64:$src1)
+ // Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (ADD_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::ADD_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fadd:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (ADDSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::ADDSDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FADD_f80(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_extload(N1.getNode())) {
+
+ // Pattern: (fadd:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (ADD_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
+ // Emits: (ADD_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_extload(N0.getNode())) {
+
+ // Pattern: (fadd:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP80:f80:$src1)
+ // Emits: (ADD_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp80m32, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>, RFP80:f80:$src1)
+ // Emits: (ADD_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp80m64, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fadd:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
+ // Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fadd:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
+ // Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::FILD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N02 = N0.getOperand(2);
+
+ // Pattern: (fadd:f80 (X86fild:f80 addr:iPTR:$src2, i16:Other), RFP80:f80:$src1)
+ // Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (fadd:f80 (X86fild:f80 addr:iPTR:$src2, i32:Other), RFP80:f80:$src1)
+ // Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Emits: (ADD_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_15(N, X86::ADD_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
+ // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (ADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::ADDPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FADD_v2f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fadd:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
+ // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (ADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::ADDPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FCOS_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::COS_Fp32, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FCOS_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::COS_Fp64, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FCOS_f80(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::COS_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (DIV_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (DIVR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (DIVSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
+ // Emits: (DIV_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::DIV_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
+ // Emits: (DIV_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::DIV_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
+ // Emits: (DIVR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::DIVR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
+ // Emits: (DIVR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::DIVR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (DIV_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::DIV_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (DIVSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::DIVSSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (DIV_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (DIV_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (DIVR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (DIVR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (DIVSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
+ // Emits: (DIV_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::DIV_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
+ // Emits: (DIV_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::DIV_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
+ // Emits: (DIVR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::DIVR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
+ // Emits: (DIVR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::DIVR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (DIV_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::DIV_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (DIVSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::DIVSDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_extload(N1.getNode())) {
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (DIV_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
+ // Emits: (DIV_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (DIVR_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
+ // Emits: (DIVR_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
+ // Emits: (DIV_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::DIV_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
+ // Emits: (DIV_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::DIV_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
+ // Emits: (DIVR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::DIVR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
+ // Emits: (DIVR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::DIVR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Emits: (DIV_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_15(N, X86::DIV_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FDIV_v4f32(const SDValue &N) {
+
+ // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (DIVPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (DIVPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::DIVPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FDIV_v2f64(const SDValue &N) {
+
+ // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (DIVPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (DIVPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::DIVPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
+ // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
+ // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fmul:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
+ // Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fmul:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
+ // Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::FILD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N02 = N0.getOperand(2);
+
+ // Pattern: (fmul:f32 (X86fild:f32 addr:iPTR:$src2, i16:Other), RFP32:f32:$src1)
+ // Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (fmul:f32 (X86fild:f32 addr:iPTR:$src2, i32:Other), RFP32:f32:$src1)
+ // Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (MUL_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MUL_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fmul:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (MULSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MULSSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
+
+ // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
+ // Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
+ // Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N0.getNode()) &&
+ Predicate_extloadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
+ // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fmul:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
+ // Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fmul:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
+ // Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::FILD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N02 = N0.getOperand(2);
+
+ // Pattern: (fmul:f64 (X86fild:f64 addr:iPTR:$src2, i16:Other), RFP64:f64:$src1)
+ // Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (fmul:f64 (X86fild:f64 addr:iPTR:$src2, i32:Other), RFP64:f64:$src1)
+ // Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (MUL_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MUL_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fmul:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (MULSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MULSDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_extload(N1.getNode())) {
+
+ // Pattern: (fmul:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (MUL_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
+ // Emits: (MUL_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_extload(N0.getNode())) {
+
+ // Pattern: (fmul:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP80:f80:$src1)
+ // Emits: (MUL_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp80m32, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>, RFP80:f80:$src1)
+ // Emits: (MUL_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp80m64, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fmul:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
+ // Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fmul:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
+ // Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == X86ISD::FILD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N02 = N0.getOperand(2);
+
+ // Pattern: (fmul:f80 (X86fild:f80 addr:iPTR:$src2, i16:Other), RFP80:f80:$src1)
+ // Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (fmul:f80 (X86fild:f80 addr:iPTR:$src2, i32:Other), RFP80:f80:$src1)
+ // Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Emits: (MUL_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_15(N, X86::MUL_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
+ // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MULPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MULPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FMUL_v2f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fmul:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
+ // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MULPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MULPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::CHS_Fp32, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::CHS_Fp64, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FNEG_f80(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::CHS_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
+
+ // Pattern: (fextend:f64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_77(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fextend:f64 RFP32:f32:$src)
+ // Emits: (MOV_Fp3264:f64 RFP32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::MOV_Fp3264, MVT::f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fextend:f64 FR32:f32:$src)
+ // Emits: (CVTSS2SDrr:f64 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::CVTSS2SDrr, MVT::f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_EXTEND_f80(const SDValue &N) {
+
+ // Pattern: (fextend:f80 RFP32:f32:$src)
+ // Emits: (MOV_Fp3280:f80 RFP32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::MOV_Fp3280, MVT::f80);
+ return Result;
+ }
+ }
+
+ // Pattern: (fextend:f80 RFP64:f64:$src)
+ // Emits: (MOV_Fp6480:f80 RFP64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::MOV_Fp6480, MVT::f80);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
+
+ // Pattern: (fround:f32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (CVTSD2SSrm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_77(N, X86::CVTSD2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (fround:f32 RFP64:f64:$src)
+ // Emits: (MOV_Fp6432:f32 RFP64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::MOV_Fp6432, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fround:f32 RFP80:f80:$src)
+ // Emits: (MOV_Fp8032:f32 RFP80:f80:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_71(N, X86::MOV_Fp8032, MVT::f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fround:f32 FR64:f64:$src)
+ // Emits: (CVTSD2SSrr:f32 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::CVTSD2SSrr, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_ROUND_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_71(N, X86::MOV_Fp8064, MVT::f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (fp_to_sint:i32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (CVTTSS2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_77(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fp_to_sint:i32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (CVTTSD2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_77(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fp_to_sint:i32 FR32:f32:$src)
+ // Emits: (CVTTSS2SIrr:i32 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::CVTTSS2SIrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (fp_to_sint:i32 FR64:f64:$src)
+ // Emits: (CVTTSD2SIrr:i32 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::CVTTSD2SIrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (fp_to_sint:i64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (CVTTSD2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_77(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fp_to_sint:i64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (CVTTSS2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_77(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fp_to_sint:i64 FR64:f64:$src)
+ // Emits: (CVTTSD2SI64rr:i64 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::CVTTSD2SI64rr, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (fp_to_sint:i64 FR32:f32:$src)
+ // Emits: (CVTTSS2SI64rr:i64 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::CVTTSS2SI64rr, MVT::i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_SINT_v2i32(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_71(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FP_TO_SINT_v4i32(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_71(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSIN_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::SIN_Fp32, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSIN_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::SIN_Fp64, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSIN_f80(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::SIN_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
+
+ // Pattern: (fsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SQRTSSm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::SQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsqrt:f32 RFP32:f32:$src)
+ // Emits: (SQRT_Fp32:f32 RFP32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::SQRT_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fsqrt:f32 FR32:f32:$src)
+ // Emits: (SQRTSSr:f32 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::SQRTSSr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
+
+ // Pattern: (fsqrt:f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SQRTSDm:f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::SQRTSDm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsqrt:f64 RFP64:f64:$src)
+ // Emits: (SQRT_Fp64:f64 RFP64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::SQRT_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fsqrt:f64 FR64:f64:$src)
+ // Emits: (SQRTSDr:f64 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::SQRTSDr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSQRT_f80(const SDValue &N) {
+ SDNode *Result = Emit_71(N, X86::SQRT_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FSQRT_v4f32(const SDValue &N) {
+
+ // Pattern: (fsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPSm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsqrt:v4f32 VR128:v4f32:$src)
+ // Emits: (SQRTPSr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::SQRTPSr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSQRT_v2f64(const SDValue &N) {
+
+ // Pattern: (fsqrt:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPDm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsqrt:v2f64 VR128:v2f64:$src)
+ // Emits: (SQRTPDr:v2f64 VR128:v2f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_71(N, X86::SQRTPDr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (SUB_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (SUBR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUBSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
+ // Emits: (SUB_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::SUB_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
+ // Emits: (SUB_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::SUB_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
+ // Emits: (SUBR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::SUBR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
+ // Emits: (SUBR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::SUBR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (SUB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::SUB_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (fsub:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (SUBSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::SUBSSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (SUB_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (SUB_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (SUBR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (SUBR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUBSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
+ // Emits: (SUB_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::SUB_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
+ // Emits: (SUB_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::SUB_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
+ // Emits: (SUBR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::SUBR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
+ // Emits: (SUBR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::SUBR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (SUB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::SUB_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (fsub:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (SUBSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::SUBSDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_extload(N1.getNode())) {
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (SUB_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
+ // Emits: (SUB_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (SUBR_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
+ // Emits: (SUBR_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extloadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::FILD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N12 = N1.getOperand(2);
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
+ // Emits: (SUB_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::SUB_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
+ // Emits: (SUB_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::SUB_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
+ // Emits: (SUBR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_95(N, X86::SUBR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
+ // Emits: (SUBR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 24 cost = 1 size = 0
+ if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_95(N, X86::SUBR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Emits: (SUB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
+ SDNode *Result = Emit_15(N, X86::SUB_Fp80, MVT::f80);
+ return Result;
+}
+
+SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
+
+ // Pattern: (fsub:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (SUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::SUBPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FSUB_v2f64(const SDValue &N) {
+
+ // Pattern: (fsub:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fsub:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (SUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::SUBPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FrameIndex_i32(const SDValue &N) {
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_FrameIndex_i64(const SDValue &N) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp2, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
+
+ // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:iPTR):$src3)
+ // Emits: (PINSRDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRDrr:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_97(N, X86::PINSRDrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
+
+ // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:iPTR):$src3)
+ // Emits: (PINSRQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRQrr:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_97(N, X86::PINSRQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N3, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDI, N4, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ SDValue Ops0[] = { N2, N3, Chain, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::RDI, N4, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ SDValue Ops0[] = { N2, N3, Chain, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::ECX, N3, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::ECX, N2, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N3, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain, InFlag);
+}
+SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_void:isVoid 718:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
+ // Emits: (MOVUPSmr_Int:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(718)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVUPSmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 708:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
+ // Emits: (MOVNTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(708)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVNTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 701:iPTR, addr:iPTR:$src)
+ // Emits: (LDMXCSR:isVoid addr:iPTR:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(701)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_101(N, X86::LDMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 717:iPTR, addr:iPTR:$dst)
+ // Emits: (STMXCSR:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(717)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_101(N, X86::STMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_void:isVoid 596:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
+ // Emits: (MOVUPDmr_Int:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(596)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVUPDmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 595:iPTR, addr:iPTR:$dst, VR128:v16i8:$src)
+ // Emits: (MOVDQUmr_Int:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(595)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVDQUmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 541:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
+ // Emits: (MOVNTPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(541)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVNTPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 539:iPTR, addr:iPTR:$dst, VR128:v2i64:$src)
+ // Emits: (MOVNTDQmr:isVoid addr:iPTR:$dst, VR128:v2i64:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(539)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVNTDQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 540:iPTR, addr:iPTR:$dst, GR32:i32:$src)
+ // Emits: (MOVNTImr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(540)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVNTImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 503:iPTR, addr:iPTR:$src)
+ // Emits: (CLFLUSH:isVoid addr:iPTR:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(503)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_101(N, X86::CLFLUSH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 594:iPTR, addr:iPTR:$dst, VR128:v4i32:$src)
+ // Emits: (MOVLQ128mr:isVoid addr:iPTR:$dst, VR128:v4i32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(594)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MOVLQ128mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 456:iPTR, addr:iPTR:$dst, VR64:v1i64:$src)
+ // Emits: (MMX_MOVNTQmr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(456)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_99(N, X86::MMX_MOVNTQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 714:iPTR)
+ // Emits: (SFENCE:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(714)) {
+ SDNode *Result = Emit_100(N, X86::SFENCE);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(532)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+
+ // Pattern: (intrinsic_void:isVoid 532:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, EDI:i32)
+ // Emits: (MASKMOVDQU:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (N4.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_102(N, X86::MASKMOVDQU);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 532:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, RDI:i64)
+ // Emits: (MASKMOVDQU64:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (N4.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_103(N, X86::MASKMOVDQU64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 529:iPTR)
+ // Emits: (LFENCE:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(529)) {
+ SDNode *Result = Emit_100(N, X86::LFENCE);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 535:iPTR)
+ // Emits: (MFENCE:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(535)) {
+ SDNode *Result = Emit_100(N, X86::MFENCE);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_void:isVoid 611:iPTR, EAX:i32, ECX:i32, EDX:i32)
+ // Emits: (MONITOR:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(611)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_104(N, X86::MONITOR);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 612:iPTR, ECX:i32, EAX:i32)
+ // Emits: (MWAIT:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(612)) {
+ SDNode *Result = Emit_105(N, X86::MWAIT);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_void:isVoid 453:iPTR)
+ // Emits: (MMX_EMMS:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(453)) {
+ SDNode *Result = Emit_100(N, X86::MMX_EMMS);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 454:iPTR)
+ // Emits: (MMX_FEMMS:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(454)) {
+ SDNode *Result = Emit_100(N, X86::MMX_FEMMS);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_void:isVoid 455:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, EDI:i32)
+ // Emits: (MMX_MASKMOVQ:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(455)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_102(N, X86::MMX_MASKMOVQ);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_void:isVoid 455:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, RDI:i64)
+ // Emits: (MMX_MASKMOVQ64:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasMMX()) && (Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(455)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ if (N4.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_103(N, X86::MMX_MASKMOVQ64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1);
+}
+DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Chain2 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Chain2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2);
+}
+DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, N1, N2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Chain2 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp4, Chain2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Chain3 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ Chain3 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ Chain3 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N3)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4, Tmp4, Chain3, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 9);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(672)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(673)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(674)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 675:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(675)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 676:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(676)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 677:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(677)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(664)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(665)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(666)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 667:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(667)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(668)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(669)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 694:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSS2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(694)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 698:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSS2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(698)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 518:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSD2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(518)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 526:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSD2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(526)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 663:iPTR, GR32:i32:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC32m8:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(663)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC32m16:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(660)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 661:iPTR, GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC32m32:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(661)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(672)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_110(N, X86::PCMPISTRIrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(673)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_110(N, X86::PCMPISTRIArr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(674)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_110(N, X86::PCMPISTRICrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 675:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(675)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_110(N, X86::PCMPISTRIOrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 676:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(676)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_110(N, X86::PCMPISTRISrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 677:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(677)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_110(N, X86::PCMPISTRIZrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(664)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPESTRIrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(665)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPESTRIArr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(666)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPESTRICrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 667:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(667)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPESTRIOrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(668)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPESTRISrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(669)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPESTRIZrr);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 694:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTSS2SIrr:i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(694)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTSS2SIrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 698:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTTSS2SIrr:i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(698)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTSS2SIrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 707:iPTR, VR128:v4f32:$src)
+ // Emits: (MOVMSKPSrr:i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(707)) {
+ SDNode *Result = Emit_106(N, X86::MOVMSKPSrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 538:iPTR, VR128:v2f64:$src)
+ // Emits: (MOVMSKPDrr:i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(538)) {
+ SDNode *Result = Emit_106(N, X86::MOVMSKPDrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 518:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTSD2SIrr:i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(518)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTSD2SIrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 526:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTTSD2SIrr:i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(526)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTSD2SIrr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 563:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVMSKBrr:i32 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(563)) {
+ SDNode *Result = Emit_106(N, X86::PMOVMSKBrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i32 663:iPTR, GR32:i32:$src1, GR8:i8:$src2)
+ // Emits: (CRC32r8:i32 GR32:i32:$src1, GR8:i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(663)) {
+ SDNode *Result = Emit_109(N, X86::CRC32r8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, GR16:i16:$src2)
+ // Emits: (CRC32r16:i32 GR32:i32:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(660)) {
+ SDNode *Result = Emit_109(N, X86::CRC32r16, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 661:iPTR, GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (CRC32r32:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(661)) {
+ SDNode *Result = Emit_109(N, X86::CRC32r32, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i32 477:iPTR, VR64:v8i8:$src)
+ // Emits: (MMX_PMOVMSKBrr:i32 VR64:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(477)) {
+ SDNode *Result = Emit_106(N, X86::MMX_PMOVMSKBrr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i64 519:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSD2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(519)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i64 527:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSD2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(527)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i64 695:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSS2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(695)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i64 699:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSS2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(699)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i64 662:iPTR, GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC64m64:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(662)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i64 519:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTSD2SI64rr:i64 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(519)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTSD2SI64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i64 527:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTTSD2SI64rr:i64 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(527)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:i64 695:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTSS2SI64rr:i64 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(695)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTSS2SI64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:i64 699:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTTSS2SI64rr:i64 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(699)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:i64 662:iPTR, GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (CRC64r64:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(662)) {
+ SDNode *Result = Emit_109(N, X86::CRC64r64, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N20 = N2.getOperand(0);
+ SDValue Chain20 = N20.getOperand(0);
+ SDValue N201 = N20.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N20)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Chain20 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_116(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { N2, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i8 726:iPTR, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSBrm64:v8i8 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(726)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_114(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 750:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSHUFBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(750)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_115(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 752:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(752)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_115(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(460)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(462)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 498:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(498)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 500:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(500)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 464:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(464)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 476:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(476)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 474:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(474)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(466)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 469:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(469)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PACKSSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(458)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PACKUSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(459)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(460)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(462)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 464:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(464)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 476:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(476)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 474:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(474)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i8 726:iPTR, VR64:v8i8:$src)
+ // Emits: (PABSBrr64:v8i8 VR64:v8i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(726)) {
+ SDNode *Result = Emit_106(N, X86::PABSBrr64, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 750:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (PSHUFBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(750)) {
+ SDNode *Result = Emit_109(N, X86::PSHUFBrr64, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 752:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (PSIGNBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(752)) {
+ SDNode *Result = Emit_109(N, X86::PSIGNBrr64, MVT::v8i8);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PADDSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(460)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PADDSBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PADDUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(462)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PADDUSBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 498:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PSUBSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(498)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSUBSBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 500:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PSUBUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(500)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 464:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PAVGBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(464)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PAVGBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 476:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PMINUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(476)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMINUBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 474:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PMAXUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(474)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMAXUBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(466)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 469:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(469)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PACKSSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(458)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PACKUSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(459)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N20 = N2.getOperand(0);
+ SDValue Chain20 = N20.getOperand(0);
+ SDValue N201 = N20.getOperand(1);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N20)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Tmp4, Chain20 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N20 = N2.getOperand(0);
+ SDValue Chain20 = N20.getOperand(0);
+ SDValue N201 = N20.getOperand(1);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain20, N.getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
+ Chain20 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N20)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Chain20, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Chain2 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp4, Chain2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Chain3 = N3.getOperand(0);
+ SDValue N31 = N3.getOperand(1);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ Chain3 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ Chain3 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N3)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4, Tmp4, Chain3, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 9);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_125(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { N2, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(622)) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (intrinsic_wo_chain:v16i8 622:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_118(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 622:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1, (imm:i32):$src3)
+ // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_125(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(546)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(548)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 588:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(588)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 590:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(590)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 550:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(550)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 562:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(562)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 560:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(560)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(552)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 555:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(555)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKSSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(544)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKUSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(545)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 727:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PABSBrm128:v16i8 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(727)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_114(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 751:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(751)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 753:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSIGNBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(753)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 635:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(635)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(631)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 624:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v16i8)
+ // Emits: (PBLENDVBrm0:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(624)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_120(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(546)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(548)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 550:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(550)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 562:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(562)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 560:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(560)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 635:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(635)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(631)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 678:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 11 size = 3
+ if (CN1 == INT64_C(678)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 670:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 11 size = 3
+ if (CN1 == INT64_C(670)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain3 = N3.getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_124(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 622:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
+ // Emits: (MPSADBWrri:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(622)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::MPSADBWrri, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 678:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Emits: (PCMPISTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern complexity = 11 cost = 11 size = 3
+ if (CN1 == INT64_C(678)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_121(N, X86::PCMPISTRM128REG, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 670:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
+ // Pattern complexity = 11 cost = 11 size = 3
+ if (CN1 == INT64_C(670)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ if (N5.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::PCMPESTRM128REG, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PADDSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(546)) {
+ SDNode *Result = Emit_109(N, X86::PADDSBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PADDUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(548)) {
+ SDNode *Result = Emit_109(N, X86::PADDUSBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 588:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSUBSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(588)) {
+ SDNode *Result = Emit_109(N, X86::PSUBSBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 590:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSUBUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(590)) {
+ SDNode *Result = Emit_109(N, X86::PSUBUSBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 550:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PAVGBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(550)) {
+ SDNode *Result = Emit_109(N, X86::PAVGBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 562:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PMINUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(562)) {
+ SDNode *Result = Emit_109(N, X86::PMINUBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 560:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PMAXUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(560)) {
+ SDNode *Result = Emit_109(N, X86::PMAXUBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(552)) {
+ SDNode *Result = Emit_109(N, X86::PCMPEQBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 555:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(555)) {
+ SDNode *Result = Emit_109(N, X86::PCMPGTBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PACKSSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(544)) {
+ SDNode *Result = Emit_109(N, X86::PACKSSWBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PACKUSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(545)) {
+ SDNode *Result = Emit_109(N, X86::PACKUSWBrr, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 727:iPTR, VR128:v16i8:$src)
+ // Emits: (PABSBrr128:v16i8 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(727)) {
+ SDNode *Result = Emit_106(N, X86::PABSBrr128, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 751:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(751)) {
+ SDNode *Result = Emit_109(N, X86::PSHUFBrr128, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 753:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSIGNBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(753)) {
+ SDNode *Result = Emit_109(N, X86::PSIGNBrr128, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v16i8 635:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PMINSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(635)) {
+ SDNode *Result = Emit_109(N, X86::PMINSBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PMAXSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(631)) {
+ SDNode *Result = Emit_109(N, X86::PMAXSBrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 624:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, XMM0:v16i8)
+ // Emits: (PBLENDVBrr0:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(624)) {
+ SDNode *Result = Emit_119(N, X86::PBLENDVBrr0, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_126(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp3);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 730:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSWrm64:v4i16 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(730)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_114(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(738)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 736:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(736)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(744)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(742)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 746:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PMADDUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(746)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_115(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 748:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(748)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 756:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(756)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(461)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 463:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(463)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 499:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(499)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 501:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(501)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(478)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 479:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(479)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(465)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(475)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 473:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(473)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(481)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 494:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(494)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 484:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSLLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(484)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 489:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRAWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(489)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(468)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(471)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PACKSSDWrm:v4i16 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(457)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 748:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR64:v4i16:$src1)
+ // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(748)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(461)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 463:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(463)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(478)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 479:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(479)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(465)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(475)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 473:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(473)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(481)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 497:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSRLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(497)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSRLWri, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 487:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSLLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(487)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSLLWri, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 491:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSRAWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(491)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSRAWri, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 730:iPTR, VR64:v4i16:$src)
+ // Emits: (PABSWrr64:v4i16 VR64:v4i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(730)) {
+ SDNode *Result = Emit_106(N, X86::PABSWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PHADDWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(738)) {
+ SDNode *Result = Emit_109(N, X86::PHADDWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 736:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PHADDSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(736)) {
+ SDNode *Result = Emit_109(N, X86::PHADDSWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PHSUBWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(744)) {
+ SDNode *Result = Emit_109(N, X86::PHSUBWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PHSUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(742)) {
+ SDNode *Result = Emit_109(N, X86::PHSUBSWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 746:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PMADDUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(746)) {
+ SDNode *Result = Emit_109(N, X86::PMADDUBSWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 748:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PMULHRSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(748)) {
+ SDNode *Result = Emit_109(N, X86::PMULHRSWrr64, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 756:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (PSIGNWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(756)) {
+ SDNode *Result = Emit_109(N, X86::PSIGNWrr64, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PADDSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(461)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PADDSWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 463:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PADDUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(463)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PADDUSWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 499:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PSUBSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(499)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSUBSWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 501:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PSUBUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(501)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMULHWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(478)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMULHWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 479:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMULHUWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(479)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMULHUWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PAVGWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(465)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PAVGWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMINSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(475)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMINSWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 473:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMAXSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(473)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMAXSWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PSADBWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(481)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSADBWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 494:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSRLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(494)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSRLWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 484:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSLLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(484)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSLLWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 489:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSRAWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(489)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSRAWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PCMPEQWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(468)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PCMPGTWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(471)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PACKSSDWrr:v4i16 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(457)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, Chain100 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10001_0, SDValue &CPTmpN10001_1, SDValue &CPTmpN10001_2, SDValue &CPTmpN10001_3, SDValue &CPTmpN10001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue Chain1000 = N1000.getOperand(0);
+ SDValue N10001 = N1000.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1000)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4, Chain1000 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1000.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_129(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 625:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (PBLENDWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(625)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_118(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_127(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_127(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(547)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 549:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(549)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 589:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(589)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 591:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(591)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 565:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(565)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 564:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(564)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(551)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(561)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 559:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(559)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 572:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSLLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(572)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 584:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(584)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 577:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRAWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(577)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(554)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(557)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKSSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(543)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 731:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSWrm128:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(731)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_114(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(739)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(745)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(743)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 747:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMADDUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(747)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 749:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(749)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 757:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(757)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHMINPOSUWrm128:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(630)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_114(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 623:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKUSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(623)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(634)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(547)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 549:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(549)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 565:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(565)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 564:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(564)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(551)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(561)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 559:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(559)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 749:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR128:v8i16:$src1)
+ // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(749)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(634)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 575:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Emits: (PSLLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(575)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSLLWri, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 587:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Emits: (PSRLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(587)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSRLWri, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 579:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Emits: (PSRAWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(579)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSRAWri, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 625:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
+ // Emits: (PBLENDWrri:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(625)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::PBLENDWrri, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PADDSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(547)) {
+ SDNode *Result = Emit_109(N, X86::PADDSWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 549:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PADDUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(549)) {
+ SDNode *Result = Emit_109(N, X86::PADDUSWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 589:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSUBSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(589)) {
+ SDNode *Result = Emit_109(N, X86::PSUBSWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 591:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSUBUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(591)) {
+ SDNode *Result = Emit_109(N, X86::PSUBUSWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 565:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMULHUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(565)) {
+ SDNode *Result = Emit_109(N, X86::PMULHUWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 564:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMULHWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(564)) {
+ SDNode *Result = Emit_109(N, X86::PMULHWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PAVGWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(551)) {
+ SDNode *Result = Emit_109(N, X86::PAVGWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMINSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(561)) {
+ SDNode *Result = Emit_109(N, X86::PMINSWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 559:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMAXSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(559)) {
+ SDNode *Result = Emit_109(N, X86::PMAXSWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 572:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSLLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(572)) {
+ SDNode *Result = Emit_109(N, X86::PSLLWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 584:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSRLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(584)) {
+ SDNode *Result = Emit_109(N, X86::PSRLWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 577:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSRAWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(577)) {
+ SDNode *Result = Emit_109(N, X86::PSRAWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PCMPEQWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(554)) {
+ SDNode *Result = Emit_109(N, X86::PCMPEQWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PCMPGTWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(557)) {
+ SDNode *Result = Emit_109(N, X86::PCMPGTWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PACKSSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(543)) {
+ SDNode *Result = Emit_109(N, X86::PACKSSDWrr, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 731:iPTR, VR128:v8i16:$src)
+ // Emits: (PABSWrr128:v8i16 VR128:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(731)) {
+ SDNode *Result = Emit_106(N, X86::PABSWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PHADDWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(739)) {
+ SDNode *Result = Emit_109(N, X86::PHADDWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PHSUBWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(745)) {
+ SDNode *Result = Emit_109(N, X86::PHSUBWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PHSUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(743)) {
+ SDNode *Result = Emit_109(N, X86::PHSUBSWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 747:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMADDUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(747)) {
+ SDNode *Result = Emit_109(N, X86::PMADDUBSWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 749:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMULHRSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(749)) {
+ SDNode *Result = Emit_109(N, X86::PMULHRSWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 757:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSIGNWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(757)) {
+ SDNode *Result = Emit_109(N, X86::PSIGNWrr128, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, VR128:v8i16:$src)
+ // Emits: (PHMINPOSUWrr128:v8i16 VR128:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(630)) {
+ SDNode *Result = Emit_106(N, X86::PHMINPOSUWrr128, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 623:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PACKUSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(623)) {
+ SDNode *Result = Emit_109(N, X86::PACKUSDWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMINUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(638)) {
+ SDNode *Result = Emit_109(N, X86::PMINUWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMAXUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(634)) {
+ SDNode *Result = Emit_109(N, X86::PMAXUWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVSXBWrr:v8i16 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(641)) {
+ SDNode *Result = Emit_106(N, X86::PMOVSXBWrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVZXBWrr:v8i16 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(647)) {
+ SDNode *Result = Emit_106(N, X86::PMOVZXBWrr, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 728:iPTR, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSDrm64:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(728)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_114(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 734:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(734)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_115(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 740:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(740)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_115(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 754:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(754)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_115(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 480:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(480)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 472:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(472)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 492:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(492)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 482:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSLLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(482)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRADrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(488)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(467)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 470:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(470)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 480:iPTR, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
+ // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(480)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 472:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(472)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 691:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPS2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(691)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 697:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTPS2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(697)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPD2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(688)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 696:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTTPD2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(696)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 495:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSRLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(495)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSRLDri, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 485:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSLLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(485)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSLLDri, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 490:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSRADri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(490)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSRADri, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 691:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTPS2PIrr:v2i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(691)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 697:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTTPS2PIrr:v2i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(697)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTPD2PIrr:v2i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(688)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 696:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTTPD2PIrr:v2i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(696)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 728:iPTR, VR64:v2i32:$src)
+ // Emits: (PABSDrr64:v2i32 VR64:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(728)) {
+ SDNode *Result = Emit_106(N, X86::PABSDrr64, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 734:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (PHADDDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(734)) {
+ SDNode *Result = Emit_109(N, X86::PHADDDrr64, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 740:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (PHSUBDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(740)) {
+ SDNode *Result = Emit_109(N, X86::PHSUBDrr64, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 754:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (PSIGNDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(754)) {
+ SDNode *Result = Emit_109(N, X86::PSIGNDrr64, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i32 480:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PMULUDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(480)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMULUDQrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 472:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMADDWDrr:v2i32 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(472)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PMADDWDrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 492:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSRLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(492)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSRLDrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 482:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSLLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(482)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSLLDrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSRADrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(488)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSRADrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PCMPEQDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(467)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i32 470:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PCMPGTDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(470)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_130(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N2, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(649)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_127(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(649)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_127(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_127(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_127(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 558:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(558)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 568:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSLLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(568)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 580:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(580)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRADrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(576)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(553)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 556:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(556)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 729:iPTR, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PABSDrm128:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(729)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_114(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 735:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PHADDDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(735)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_115(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDSWrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(737)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 741:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PHSUBDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(741)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_115(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 755:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSIGNDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(755)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_115(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(636)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 637:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(632)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(633)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 558:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(558)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(636)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 637:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(632)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(633)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(649)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 516:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPS2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(516)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 525:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTTPS2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(525)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 514:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPD2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(514)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 524:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTTPD2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(524)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(652)) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (intrinsic_wo_chain:v4i32 652:iPTR, VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 652:iPTR, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
+ // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_130(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 573:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Emits: (PSLLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(573)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSLLDri, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 585:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Emits: (PSRLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(585)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSRLDri, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 578:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Emits: (PSRADri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(578)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSRADri, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 516:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTPS2DQrr:v4i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(516)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 525:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTTPS2DQrr:v4i32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(525)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 514:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTPD2DQrr:v4i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(514)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 524:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTTPD2DQrr:v4i32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(524)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 558:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMADDWDrr:v4i32 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(558)) {
+ SDNode *Result = Emit_109(N, X86::PMADDWDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 568:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PSLLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(568)) {
+ SDNode *Result = Emit_109(N, X86::PSLLDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 580:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PSRLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(580)) {
+ SDNode *Result = Emit_109(N, X86::PSRLDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PSRADrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(576)) {
+ SDNode *Result = Emit_109(N, X86::PSRADrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PCMPEQDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(553)) {
+ SDNode *Result = Emit_109(N, X86::PCMPEQDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 556:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PCMPGTDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(556)) {
+ SDNode *Result = Emit_109(N, X86::PCMPGTDrr, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 729:iPTR, VR128:v4i32:$src)
+ // Emits: (PABSDrr128:v4i32 VR128:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(729)) {
+ SDNode *Result = Emit_106(N, X86::PABSDrr128, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 735:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PHADDDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(735)) {
+ SDNode *Result = Emit_109(N, X86::PHADDDrr128, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PHADDSWrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(737)) {
+ SDNode *Result = Emit_109(N, X86::PHADDSWrr128, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 741:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PHSUBDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(741)) {
+ SDNode *Result = Emit_109(N, X86::PHSUBDrr128, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 755:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PSIGNDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(755)) {
+ SDNode *Result = Emit_109(N, X86::PSIGNDrr128, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMINSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(636)) {
+ SDNode *Result = Emit_109(N, X86::PMINSDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 637:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMINUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(637)) {
+ SDNode *Result = Emit_109(N, X86::PMINUDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMAXSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(632)) {
+ SDNode *Result = Emit_109(N, X86::PMAXSDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMAXUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(633)) {
+ SDNode *Result = Emit_109(N, X86::PMAXUDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 652:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMULLDrr_int:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(652)) {
+ SDNode *Result = Emit_109(N, X86::PMULLDrr_int, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, VR128:v8i16:$src)
+ // Emits: (PMOVSXWDrr:v4i32 VR128:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(643)) {
+ SDNode *Result = Emit_106(N, X86::PMOVSXWDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, VR128:v8i16:$src)
+ // Emits: (PMOVZXWDrr:v4i32 VR128:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(649)) {
+ SDNode *Result = Emit_106(N, X86::PMOVZXWDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVSXBDrr:v4i32 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(639)) {
+ SDNode *Result = Emit_106(N, X86::PMOVSXBDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVZXBDrr:v4i32 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(645)) {
+ SDNode *Result = Emit_106(N, X86::PMOVZXBDrr, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
+ SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_132(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Chain2 = N2.getOperand(0);
+ SDValue N21 = N2.getOperand(1);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
+ SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp5, Chain2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v1i64 493:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(493)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 483:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSLLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(483)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_115(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 732:iPTR, VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>, (imm:i8):$src3)
+ // Emits: (PALIGNR64rm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(732)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop64(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_132(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v1i64 496:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSRLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(496)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSRLQri, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 486:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
+ // Emits: (MMX_PSLLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(486)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::MMX_PSLLQri, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 732:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2, (imm:i8):$src3)
+ // Emits: (PALIGNR64rr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
+ // Pattern complexity = 11 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(732)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_131(N, X86::PALIGNR64rr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v1i64 493:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSRLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(493)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSRLQrr, MVT::v1i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v1i64 483:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSLLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(483)) {
+ SDNode *Result = Emit_109(N, X86::MMX_PSLLQrr, MVT::v1i64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_133(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = Transform_BYTE_imm(Tmp3.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp4);
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(648)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 650:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(650)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getOperand(0);
+ if (N1000.getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
+ SDValue Chain1000 = N1000.getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_127(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(648)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_127(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_127(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 650:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(650)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_127(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
+ // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16_anyext(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_127(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
+ // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16_anyext(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_127(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(566)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(567)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 571:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSLLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(571)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 583:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(583)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 626:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(626)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 651:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(651)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 671:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(671)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 733:iPTR, VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$src3)
+ // Emits: (PALIGNR128rm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(733)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_132(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(566)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(567)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 626:iPTR, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2i64:$src1)
+ // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(626)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 651:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(651)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(648)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 574:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Emits: (PSLLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(574)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSLLQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 586:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Emits: (PSRLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(586)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSRLQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 569:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(569)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_133(N, X86::PSLLDQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 581:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(581)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_133(N, X86::PSRLDQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 570:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(570)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSLLDQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 582:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(582)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::PSRLDQri, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 733:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2, (imm:i8):$src3)
+ // Emits: (PALIGNR128rr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
+ // Pattern complexity = 11 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(733)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_131(N, X86::PALIGNR128rr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMULUDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(566)) {
+ SDNode *Result = Emit_109(N, X86::PMULUDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSADBWrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(567)) {
+ SDNode *Result = Emit_109(N, X86::PSADBWrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 571:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PSLLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(571)) {
+ SDNode *Result = Emit_109(N, X86::PSLLQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 583:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PSRLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(583)) {
+ SDNode *Result = Emit_109(N, X86::PSRLQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2i64 626:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PCMPEQQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(626)) {
+ SDNode *Result = Emit_109(N, X86::PCMPEQQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 651:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PMULDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(651)) {
+ SDNode *Result = Emit_109(N, X86::PMULDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, VR128:v4i32:$src)
+ // Emits: (PMOVSXDQrr:v2i64 VR128:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(642)) {
+ SDNode *Result = Emit_106(N, X86::PMOVSXDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, VR128:v4i32:$src)
+ // Emits: (PMOVZXDQrr:v2i64 VR128:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(648)) {
+ SDNode *Result = Emit_106(N, X86::PMOVZXDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, VR128:v8i16:$src)
+ // Emits: (PMOVSXWQrr:v2i64 VR128:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(644)) {
+ SDNode *Result = Emit_106(N, X86::PMOVSXWQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 650:iPTR, VR128:v8i16:$src)
+ // Emits: (PMOVZXWQrr:v2i64 VR128:v8i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(650)) {
+ SDNode *Result = Emit_106(N, X86::PMOVZXWQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVSXBQrr:v2i64 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(640)) {
+ SDNode *Result = Emit_106(N, X86::PMOVSXBQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, VR128:v16i8:$src)
+ // Emits: (PMOVZXBQrr:v2i64 VR128:v16i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(646)) {
+ SDNode *Result = Emit_106(N, X86::PMOVZXBQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 671:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PCMPGTQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(671)) {
+ SDNode *Result = Emit_109(N, X86::PCMPGTQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4, SDValue &Chain1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp3, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_137(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
+ SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp4, Chain2 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (BLENDPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(614)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_118(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CN1 == INT64_C(618)) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (intrinsic_wo_chain:v4f32 618:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_118(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 618:iPTR, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4f32:$src1, (imm:i32):$src3)
+ // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_125(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 681:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
+ // Emits: (Int_CMPSSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(681)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 680:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Emits: (CMPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(680)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 513:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (Int_CVTDQ2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(513)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_114(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 657:iPTR, (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
+ // Emits: (ROUNDPSm_Int:v4f32 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(657)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_136(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 616:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v4f32)
+ // Emits: (BLENDVPSrm0:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(616)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_120(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 693:iPTR, VR128:v4f32:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (Int_CVTSI2SS64rm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(693)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_loadi64(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPI2PSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(690)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 692:iPTR, VR128:v4f32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (Int_CVTSI2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(692)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_loadi32(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(703)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(705)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPSm_Int:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(715)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RSQRTPSm_Int:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(712)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RCPPSm_Int:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(710)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 515:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPD2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(515)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 520:iPTR, VR128:v4f32:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSD2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(520)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(605)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 607:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(607)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 609:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(609)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 659:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
+ // Emits: (ROUNDSSm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(659)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_137(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 679:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (ADDSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(679)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (MULSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(709)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 719:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (SUBSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(719)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (DIVSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(700)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 704:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (MAXSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(704)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (MINSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(706)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, sse_load_f32:v4f32:$src)
+ // Emits: (SQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(716)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_135(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, sse_load_f32:v4f32:$src)
+ // Emits: (RSQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(713)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_135(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, sse_load_f32:v4f32:$src)
+ // Emits: (RCPSSm_Int:v4f32 sse_load_f32:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(711)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_135(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 681:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Emits: (Int_CMPSSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(681)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_121(N, X86::Int_CMPSSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 680:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Emits: (CMPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(680)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_121(N, X86::CMPPSrri, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 657:iPTR, VR128:v4f32:$src1, (imm:i32):$src2)
+ // Emits: (ROUNDPSr_Int:v4f32 VR128:v4f32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(657)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::ROUNDPSr_Int, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 659:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Emits: (ROUNDSSr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(659)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::ROUNDSSr_Int, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Emits: (BLENDPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(614)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::BLENDPSrri, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 618:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Emits: (DPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(618)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::DPPSrri, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 620:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Emits: (INSERTPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(620)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::INSERTPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 693:iPTR, VR128:v4f32:$src1, GR64:i64:$src2)
+ // Emits: (Int_CVTSI2SS64rr:v4f32 VR128:v4f32:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(693)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, VR64:v2i32:$src2)
+ // Emits: (Int_CVTPI2PSrr:v4f32 VR128:v4f32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(690)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 692:iPTR, VR128:v4f32:$src1, GR32:i32:$src2)
+ // Emits: (Int_CVTSI2SSrr:v4f32 VR128:v4f32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(692)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 679:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (ADDSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(679)) {
+ SDNode *Result = Emit_109(N, X86::ADDSSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MULSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(709)) {
+ SDNode *Result = Emit_109(N, X86::MULSSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 719:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (SUBSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(719)) {
+ SDNode *Result = Emit_109(N, X86::SUBSSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (DIVSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(700)) {
+ SDNode *Result = Emit_109(N, X86::DIVSSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 704:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MAXSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(704)) {
+ SDNode *Result = Emit_109(N, X86::MAXSSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MAXPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(703)) {
+ SDNode *Result = Emit_109(N, X86::MAXPSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MINSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(706)) {
+ SDNode *Result = Emit_109(N, X86::MINSSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MINPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(705)) {
+ SDNode *Result = Emit_109(N, X86::MINPSrr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, VR128:v4f32:$src)
+ // Emits: (SQRTSSr_Int:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(716)) {
+ SDNode *Result = Emit_106(N, X86::SQRTSSr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, VR128:v4f32:$src)
+ // Emits: (SQRTPSr_Int:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(715)) {
+ SDNode *Result = Emit_106(N, X86::SQRTPSr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, VR128:v4f32:$src)
+ // Emits: (RSQRTSSr_Int:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(713)) {
+ SDNode *Result = Emit_106(N, X86::RSQRTSSr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, VR128:v4f32:$src)
+ // Emits: (RSQRTPSr_Int:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(712)) {
+ SDNode *Result = Emit_106(N, X86::RSQRTPSr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, VR128:v4f32:$src)
+ // Emits: (RCPSSr_Int:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(711)) {
+ SDNode *Result = Emit_106(N, X86::RCPSSr_Int, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, VR128:v4f32:$src)
+ // Emits: (RCPPSr_Int:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(710)) {
+ SDNode *Result = Emit_106(N, X86::RCPPSr_Int, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 513:iPTR, VR128:v4i32:$src)
+ // Emits: (Int_CVTDQ2PSrr:v4f32 VR128:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(513)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 515:iPTR, VR128:v2f64:$src)
+ // Emits: (Int_CVTPD2PSrr:v4f32 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(515)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 520:iPTR, VR128:v4f32:$src1, VR128:v2f64:$src2)
+ // Emits: (Int_CVTSD2SSrr:v4f32 VR128:v4f32:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(520)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (ADDSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(605)) {
+ SDNode *Result = Emit_109(N, X86::ADDSUBPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 607:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (HADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(607)) {
+ SDNode *Result = Emit_109(N, X86::HADDPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 609:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (HSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(609)) {
+ SDNode *Result = Emit_109(N, X86::HSUBPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4f32 616:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, XMM0:v4f32)
+ // Emits: (BLENDVPSrr0:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(616)) {
+ SDNode *Result = Emit_119(N, X86::BLENDVPSrr0, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (BLENDPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(613)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_118(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CN1 == INT64_C(617)) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (intrinsic_wo_chain:v2f64 617:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_118(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 617:iPTR, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2f64:$src1, (imm:i32):$src3)
+ // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_125(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 505:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
+ // Emits: (Int_CMPSDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(505)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 512:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (Int_CVTDQ2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(512)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_114(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 504:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Emits: (CMPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(504)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 656:iPTR, (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
+ // Emits: (ROUNDPDm_Int:v2f64 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(656)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_136(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 615:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v2f64)
+ // Emits: (BLENDVPDrm0:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(615)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getOperand(0);
+ if (N20.getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
+ SDValue Chain20 = N20.getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_120(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 522:iPTR, VR128:v2f64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (Int_CVTSI2SD64rm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(522)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_loadi64(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 689:iPTR, (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPI2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(689)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(533)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 536:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(536)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPS2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(517)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 521:iPTR, VR128:v2f64:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (Int_CVTSI2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(521)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_loadi32(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 523:iPTR, VR128:v2f64:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSS2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(523)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 592:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPDm_Int:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(592)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_107(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(604)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 606:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(606)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 608:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(608)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain2 = N2.getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_108(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 658:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
+ // Emits: (ROUNDSDm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(658)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_137(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (ADDSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(502)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 542:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (MULSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(542)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 597:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (SUBSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(597)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 528:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (DIVSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(528)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (MAXSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(534)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 537:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (MINSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(537)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_134(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, sse_load_f64:v2f64:$src)
+ // Emits: (SQRTSDm_Int:v2f64 sse_load_f64:v2f64:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(593)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_135(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 505:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Emits: (Int_CMPSDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(505)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_121(N, X86::Int_CMPSDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 504:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Emits: (CMPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(504)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_121(N, X86::CMPPDrri, MVT::v2f64);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 656:iPTR, VR128:v2f64:$src1, (imm:i32):$src2)
+ // Emits: (ROUNDPDr_Int:v2f64 VR128:v2f64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(656)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_126(N, X86::ROUNDPDr_Int, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 658:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Emits: (ROUNDSDr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(658)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::ROUNDSDr_Int, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Emits: (BLENDPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(613)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::BLENDPDrri, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 617:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Emits: (DPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (CN1 == INT64_C(617)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_117(N, X86::DPPDrri, MVT::v2f64);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 522:iPTR, VR128:v2f64:$src1, GR64:i64:$src2)
+ // Emits: (Int_CVTSI2SD64rr:v2f64 VR128:v2f64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(522)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 689:iPTR, VR64:v2i32:$src)
+ // Emits: (Int_CVTPI2PDrr:v2f64 VR64:v2i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(689)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (ADDSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(502)) {
+ SDNode *Result = Emit_109(N, X86::ADDSDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 542:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MULSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(542)) {
+ SDNode *Result = Emit_109(N, X86::MULSDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 597:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (SUBSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(597)) {
+ SDNode *Result = Emit_109(N, X86::SUBSDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 528:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (DIVSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(528)) {
+ SDNode *Result = Emit_109(N, X86::DIVSDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MAXSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(534)) {
+ SDNode *Result = Emit_109(N, X86::MAXSDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MAXPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(533)) {
+ SDNode *Result = Emit_109(N, X86::MAXPDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 537:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MINSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(537)) {
+ SDNode *Result = Emit_109(N, X86::MINSDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 536:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MINPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(536)) {
+ SDNode *Result = Emit_109(N, X86::MINPDrr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 512:iPTR, VR128:v4i32:$src)
+ // Emits: (Int_CVTDQ2PDrr:v2f64 VR128:v4i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(512)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, VR128:v4f32:$src)
+ // Emits: (Int_CVTPS2PDrr:v2f64 VR128:v4f32:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(517)) {
+ SDNode *Result = Emit_106(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 521:iPTR, VR128:v2f64:$src1, GR32:i32:$src2)
+ // Emits: (Int_CVTSI2SDrr:v2f64 VR128:v2f64:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(521)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 523:iPTR, VR128:v2f64:$src1, VR128:v4f32:$src2)
+ // Emits: (Int_CVTSS2SDrr:v2f64 VR128:v2f64:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(523)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, VR128:v2f64:$src)
+ // Emits: (SQRTSDr_Int:v2f64 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(593)) {
+ SDNode *Result = Emit_106(N, X86::SQRTSDr_Int, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 592:iPTR, VR128:v2f64:$src)
+ // Emits: (SQRTPDr_Int:v2f64 VR128:v2f64:$src)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(592)) {
+ SDNode *Result = Emit_106(N, X86::SQRTPDr_Int, MVT::v2f64);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (ADDSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(604)) {
+ SDNode *Result = Emit_109(N, X86::ADDSUBPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 606:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (HADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(606)) {
+ SDNode *Result = Emit_109(N, X86::HADDPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 608:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (HSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(608)) {
+ SDNode *Result = Emit_109(N, X86::HSUBPDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2f64 615:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, XMM0:v2f64)
+ // Emits: (BLENDVPDrr0:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(615)) {
+ SDNode *Result = Emit_119(N, X86::BLENDVPDrr0, MVT::v2f64);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_138(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+}
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
+
+ // Pattern: (intrinsic_w_chain:v16i8 530:iPTR, addr:iPTR:$src)
+ // Emits: (MOVDQUrm_Int:v16i8 addr:iPTR:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(530)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_138(N, X86::MOVDQUrm_Int, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_w_chain:v16i8 610:iPTR, addr:iPTR:$src)
+ // Emits: (LDDQUrm:v16i8 addr:iPTR:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if ((Subtarget->hasSSE3())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(610)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_138(N, X86::LDDQUrm, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(621)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_138(N, X86::MOVNTDQArm, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(702)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_138(N, X86::MOVUPSrm_Int, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(531)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_138(N, X86::MOVUPDrm_Int, MVT::v2f64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelectIntrinsic(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_139(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>
+ // Emits: (MOV8rm:i8 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_load(N.getNode()) &&
+ Predicate_loadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (MOV8rm:i8 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (MOV8rm:i8 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extload(N.getNode()) &&
+ Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>
+ // Emits: (MOV16rm:i16 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_loadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (MOVSX16rm8:i16 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextload(N.getNode()) &&
+ Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_gsload>>
+ // Emits: (GS_MOV32rm:i32 addr:iPTR:$src)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if (Predicate_gsload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::GS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_fsload>>
+ // Emits: (FS_MOV32rm:i32 addr:iPTR:$src)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if (Predicate_fsload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::FS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>
+ // Emits: (MOV32rm:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_loadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (MOVSX32rm8:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (MOVSX32rm16:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (MOVSX32rm16:i32 addr:iPTR:$dst)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextload(N.getNode()) &&
+ Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (MOVZX32rm16:i32 addr:iPTR:$dst)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (MOVZX32rm16:i32 addr:iPTR:$dst)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extload(N.getNode()) &&
+ Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_140(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ Chain = SDValue(Tmp2.getNode(), 1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
+ MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops1[] = { Tmp0, Tmp2, Tmp3, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, MVT::Other, Ops1, 4);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
+ return ResNode;
+}
+SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+ if (Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_gsload>>
+ // Emits: (MOV64GSrm:i64 addr:iPTR:$src)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if (Predicate_gsload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV64GSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_fsload>>
+ // Emits: (MOV64FSrm:i64 addr:iPTR:$src)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if (Predicate_fsload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV64FSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (MOV64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOV64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ if (Predicate_sextload(N.getNode())) {
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
+ // Emits: (MOVSX64rm8:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (MOVSX64rm16:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
+ // Emits: (MOVSX64rm32:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_zextload(N.getNode())) {
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
+ // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (MOVZX64rm16:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
+ // Emits: (MOVZX64rm32:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
+ // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
+ // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi1(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
+ // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi8(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (MOVZX64rm16:i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
+ // Emits: (MOVSX64rm16:i64 addr:iPTR:$dst)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_sextload(N.getNode()) &&
+ Predicate_sextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
+ // Emits: (MOVZX64rm16:i64 addr:iPTR:$dst)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_zextload(N.getNode()) &&
+ Predicate_zextloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
+ // Emits: (MOVZX64rm16:i64 addr:iPTR:$dst)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extloadi16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
+ // Emits: (SUBREG_TO_REG:i64 0:i64, (MOV32rm:i32 addr:iPTR:$src), 4:i32)
+ // Pattern complexity = 22 cost = 2 size = 3
+ if (Predicate_extloadi32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_140(N, X86::MOV32rm, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
+
+ // Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>
+ // Emits: (LD_Fp32m:f32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode()) &&
+ Predicate_loadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>
+ // Emits: (MOVSSrm:f32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_loadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (FsMOVAPSrm:f32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::FsMOVAPSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
+ // Emits: (LD_Fp64m:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_load(N.getNode()) &&
+ Predicate_loadf64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (LD_Fp32m64:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_extload(N.getNode()) &&
+ Predicate_extloadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::LD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
+ // Emits: (MOVSDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_load(N.getNode()) &&
+ Predicate_loadf64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVSDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_extload(N.getNode()) &&
+ Predicate_extloadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (FsMOVAPDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_load(N.getNode()) &&
+ Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::FsMOVAPDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode())) {
+
+ // Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf80>>
+ // Emits: (LD_Fp80m:f80 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_load(N.getNode()) &&
+ Predicate_loadf80(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ if (Predicate_extload(N.getNode())) {
+
+ // Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>
+ // Emits: (LD_Fp64m80:f80 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_extloadf64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::LD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
+ // Emits: (LD_Fp32m80:f80 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_extloadf32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::LD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (MOVAPSrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVAPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (MOVUPSrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVUPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v1i64(const SDValue &N) {
+ if ((Subtarget->hasMMX())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MMX_MOVQ64rm, MVT::v1i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v2i64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (MOVAPSrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVAPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (MOVUPSrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVUPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v4f32(const SDValue &N) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (MOVAPSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVAPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (MOVUPSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVUPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedload(N.getNode()) &&
+ Predicate_load(N.getNode())) {
+
+ // Pattern: (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
+ // Emits: (MOVAPDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedload(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVAPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
+ // Emits: (MOVUPDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_139(N, X86::MOVUPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_141(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue N4 = N.getOperand(4);
+ SDValue N5 = N.getOperand(5);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (membarrier:isVoid 0:i8, 0:i8, 0:i8, 1:i8, 1:i8)
+ // Emits: (SFENCE:isVoid)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(0)) {
+ SDValue N3 = N.getOperand(3);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(0)) {
+ SDValue N4 = N.getOperand(4);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4);
+ if (Tmp6) {
+ int64_t CN7 = Tmp6->getSExtValue();
+ if (CN7 == INT64_C(1)) {
+ SDValue N5 = N.getOperand(5);
+ ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5);
+ if (Tmp8) {
+ int64_t CN9 = Tmp8->getSExtValue();
+ if (CN9 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_141(N, X86::SFENCE);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (membarrier:isVoid 1:i8, 0:i8, 0:i8, 0:i8, 1:i8)
+ // Emits: (LFENCE:isVoid)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp2) {
+ int64_t CN3 = Tmp2->getSExtValue();
+ if (CN3 == INT64_C(0)) {
+ SDValue N3 = N.getOperand(3);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3);
+ if (Tmp4) {
+ int64_t CN5 = Tmp4->getSExtValue();
+ if (CN5 == INT64_C(0)) {
+ SDValue N4 = N.getOperand(4);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4);
+ if (Tmp6) {
+ int64_t CN7 = Tmp6->getSExtValue();
+ if (CN7 == INT64_C(0)) {
+ SDValue N5 = N.getOperand(5);
+ ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5);
+ if (Tmp8) {
+ int64_t CN9 = Tmp8->getSExtValue();
+ if (CN9 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_141(N, X86::LFENCE);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDValue N4 = N.getOperand(4);
+ if (N4.getOpcode() == ISD::Constant) {
+ SDValue N5 = N.getOperand(5);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N5);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (membarrier:isVoid (imm:i8):$ll, (imm:i8):$ls, (imm:i8):$sl, (imm:i8):$ss, 0:i8)
+ // Emits: (NOOP:isVoid)
+ // Pattern complexity = 20 cost = 1 size = 3
+ if (CN1 == INT64_C(0) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_141(N, X86::NOOP);
+ return Result;
+ }
+
+ // Pattern: (membarrier:isVoid (imm:i8):$ll, (imm:i8):$ls, (imm:i8):$sl, (imm:i8):$ss, 1:i8)
+ // Emits: (MFENCE:isVoid)
+ // Pattern complexity = 20 cost = 1 size = 3
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_141(N, X86::MFENCE);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::AL, N0, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i8, MVT::i32, N1, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_143(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N.getDebugLoc(), X86::AL, N0, InFlag).getNode();
+ Chain1 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i8, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_ISD_MUL_i8(const SDValue &N) {
+
+ // Pattern: (mul:i8 AL:i8, (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (MUL8m:isVoid addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_143(N, X86::MUL8m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i8 AL:i8, GR8:i8:$src)
+ // Emits: (MUL8r:isVoid GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_142(N, X86::MUL8r);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_144(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_ISD_MUL_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_144(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16):$src2)
+ // Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ SDNode *Result = Emit_144(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
+ // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::IMUL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (mul:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (IMUL16rri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::IMUL16rri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (mul:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (IMUL16rri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::IMUL16rri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (mul:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (IMUL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::IMUL16rr, MVT::i16);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_145(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_ISD_MUL_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_145(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$src2)
+ // Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ SDNode *Result = Emit_145(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
+ // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::IMUL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (mul:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (IMUL32rri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::IMUL32rri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (mul:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (IMUL32rri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::IMUL32rri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (mul:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (IMUL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::IMUL32rr, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_146(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_ISD_MUL_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (mul:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_146(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (mul:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_146(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::IMUL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: lea64addr:i64:$src
+ // Emits: (LEA64r:i64 lea64addr:i64:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (mul:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (IMUL64rri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::IMUL64rri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (mul:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (IMUL64rri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::IMUL64rri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (mul:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (IMUL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::IMUL64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PMULLDrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PMULLDrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v16i8:$src1)
+ // Emits: (PMULLDrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PMULLDrm, MVT::v16i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMULLWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PMULLWrr, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (mul:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PMULLWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PMULLWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (mul:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMULLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PMULLWrr, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
+ if ((Subtarget->hasSSE41())) {
+ SDNode *Result = Emit_15(N, X86::PMULLDrr, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_OR_i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
+ // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (OR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR8rr, MVT::i8);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getDebugLoc(), X86::CL, N01, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::CX, N010, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::CL, N011, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getDebugLoc(), X86::CX, N0101, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_152(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, Tmp2);
+}
+SDNode *Select_ISD_OR_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
+ // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
+ // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1101 = N110.getOperand(1);
+ if (N010 == N1101 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_148(N, X86::SHRD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+
+ // Pattern: (or:i16 (shl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
+ // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1101 = N110.getOperand(1);
+ if (N010 == N1101 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_148(N, X86::SHLD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)))
+ // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N010.getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N0101 == N110 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_151(N, X86::SHRD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)))
+ // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N0101 == N110 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_151(N, X86::SHLD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (srl:i16 GR16:i16:$src1, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)))
+ // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_147(N, X86::SHRD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (or:i16 (shl:i16 GR16:i16:$src1, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)))
+ // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_147(N, X86::SHLD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 GR16:i16:$src1, CL:i8:$amt))
+ // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (N01.getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_150(N, X86::SHRD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 GR16:i16:$src1, CL:i8:$amt))
+ // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_150(N, X86::SHLD16rrCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
+ // Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shrd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_149(N, X86::SHRD16rri8, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (shl:i16 GR16:i16:$src1, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
+ // Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shld(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_149(N, X86::SHLD16rri8, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 GR16:i16:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
+ // Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shrd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_152(N, X86::SHRD16rri8, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 GR16:i16:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
+ // Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shld(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_152(N, X86::SHLD16rri8, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (OR16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::OR16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (or:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (OR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::OR16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (OR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR16rr, MVT::i16);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::ECX, N010, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_154(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getDebugLoc(), X86::ECX, N0101, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
+}
+SDNode *Select_ISD_OR_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
+ // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
+ // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1101 = N110.getOperand(1);
+ if (N010 == N1101 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_153(N, X86::SHRD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+
+ // Pattern: (or:i32 (shl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
+ // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1101 = N110.getOperand(1);
+ if (N010 == N1101 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_153(N, X86::SHLD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)))
+ // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N010.getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N0101 == N110 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_154(N, X86::SHRD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)))
+ // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N0101 == N110 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_154(N, X86::SHLD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (srl:i32 GR32:i32:$src1, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)))
+ // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_147(N, X86::SHRD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (or:i32 (shl:i32 GR32:i32:$src1, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)))
+ // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_147(N, X86::SHLD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 GR32:i32:$src1, CL:i8:$amt))
+ // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (N01.getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_150(N, X86::SHRD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 GR32:i32:$src1, CL:i8:$amt))
+ // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_150(N, X86::SHLD32rrCL, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
+ // Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shrd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_149(N, X86::SHRD32rri8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (shl:i32 GR32:i32:$src1, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
+ // Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shld(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_149(N, X86::SHLD32rri8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 GR32:i32:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
+ // Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shrd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_152(N, X86::SHRD32rri8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 GR32:i32:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
+ // Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shld(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_152(N, X86::SHLD32rri8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (OR32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::OR32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (OR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::OR32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (OR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR32rr, MVT::i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N1100 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::RCX, N010, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_156(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N010 = N01.getOperand(0);
+ SDValue N0100 = N010.getOperand(0);
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getDebugLoc(), X86::RCX, N0101, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
+}
+SDNode *Select_ISD_OR_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:i64 (srl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)), (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))))
+ // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N1101 = N110.getOperand(1);
+ if (N010 == N1101 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_155(N, X86::SHRD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+
+ // Pattern: (or:i64 (shl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)), (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))))
+ // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N1101 = N110.getOperand(1);
+ if (N010 == N1101 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_155(N, X86::SHLD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (srl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)))
+ // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N010.getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N0101 == N110 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_156(N, X86::SHRD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (shl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)))
+ // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 23 cost = 1 size = 3
+ if (N01.getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getOperand(0);
+ if (N010.getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N0101 = N010.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getOperand(0);
+ if (N0101 == N110 &&
+ N01.getValueType() == MVT::i8 &&
+ N010.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8 &&
+ N110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_156(N, X86::SHLD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (srl:i64 GR64:i64:$src1, CL:i8:$amt), (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)))
+ // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_147(N, X86::SHRD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+
+ // Pattern: (or:i64 (shl:i64 GR64:i64:$src1, CL:i8:$amt), (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)))
+ // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N01 == N111 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_147(N, X86::SHLD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (srl:i64 GR64:i64:$src1, CL:i8:$amt))
+ // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (N01.getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_150(N, X86::SHRD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (shl:i64 GR64:i64:$src1, CL:i8:$amt))
+ // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N011 == N11 &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_150(N, X86::SHLD64rrCL, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (srl:i64 GR64:i64:$src1, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
+ // Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shrd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_149(N, X86::SHRD64rri8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (shl:i64 GR64:i64:$src1, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
+ // Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shld(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_149(N, X86::SHLD64rri8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 GR64:i64:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
+ // Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shrd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_152(N, X86::SHRD64rri8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 GR64:i64:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
+ // Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 16 cost = 1 size = 3
+ if (Predicate_shld(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ N01.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_152(N, X86::SHLD64rri8, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: lea64addr:i64:$src
+ // Emits: (LEA64r:i64 lea64addr:i64:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (OR64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::OR64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (OR64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::OR64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (OR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_OR_v1i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
+ // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PORrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_56(N, X86::ORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_56(N, X86::ORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
+ // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_61(N, X86::ORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
+ // Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_61(N, X86::ORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (ORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N00.getValueType() == MVT::v2f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_58(N, X86::ORPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (ORPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::ORPSrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (or:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PORrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PORrr, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_157(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+}
+SDNode *Select_ISD_PREFETCH(const SDValue &N) {
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDValue N3 = N.getOperand(3);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 3:i32)
+ // Emits: (PREFETCHT0:isVoid addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (CN1 == INT64_C(3) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_157(N, X86::PREFETCHT0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 2:i32)
+ // Emits: (PREFETCHT1:isVoid addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (CN1 == INT64_C(2) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_157(N, X86::PREFETCHT1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 1:i32)
+ // Emits: (PREFETCHT2:isVoid addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (CN1 == INT64_C(1) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_157(N, X86::PREFETCHT2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 0:i32)
+ // Emits: (PREFETCHNTA:isVoid addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (CN1 == INT64_C(0) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_157(N, X86::PREFETCHNTA, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::CL, N1, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_159(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotl:i8 GR8:i8:$src1, 1:i8)
+ // Emits: (ROL8r1:i8 GR8:i8:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROL8r1, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotl:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ROL8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROL8ri, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (rotl:i8 GR8:i8:$src, CL:i8)
+ // Emits: (ROL8rCL:i8 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROL8rCL, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotl:i16 GR16:i16:$src1, 1:i8)
+ // Emits: (ROL16r1:i16 GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROL16r1, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotl:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Emits: (ROL16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROL16ri, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (rotl:i16 GR16:i16:$src, CL:i8)
+ // Emits: (ROL16rCL:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROL16rCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotl:i32 GR32:i32:$src1, 1:i8)
+ // Emits: (ROL32r1:i32 GR32:i32:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROL32r1, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotl:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Emits: (ROL32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROL32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (rotl:i32 GR32:i32:$src, CL:i8)
+ // Emits: (ROL32rCL:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROL32rCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotl:i64 GR64:i64:$src1, 1:i8)
+ // Emits: (ROL64r1:i64 GR64:i64:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROL64r1, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotl:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Emits: (ROL64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROL64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (rotl:i64 GR64:i64:$src, CL:i8)
+ // Emits: (ROL64rCL:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROL64rCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotr:i8 GR8:i8:$src1, 1:i8)
+ // Emits: (ROR8r1:i8 GR8:i8:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROR8r1, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotr:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ROR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROR8ri, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (rotr:i8 GR8:i8:$src, CL:i8)
+ // Emits: (ROR8rCL:i8 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROR8rCL, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotr:i16 GR16:i16:$src1, 1:i8)
+ // Emits: (ROR16r1:i16 GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROR16r1, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotr:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Emits: (ROR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROR16ri, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (rotr:i16 GR16:i16:$src, CL:i8)
+ // Emits: (ROR16rCL:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROR16rCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotr:i32 GR32:i32:$src1, 1:i8)
+ // Emits: (ROR32r1:i32 GR32:i32:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROR32r1, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotr:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Emits: (ROR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROR32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (rotr:i32 GR32:i32:$src, CL:i8)
+ // Emits: (ROR32rCL:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROR32rCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (rotr:i64 GR64:i64:$src1, 1:i8)
+ // Emits: (ROR64r1:i64 GR64:i64:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::ROR64r1, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (rotr:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Emits: (ROR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::ROR64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (rotr:i64 GR64:i64:$src, CL:i8)
+ // Emits: (ROR64rCL:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::ROR64rCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
+
+ // Pattern: (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (MMX_MOVD64rm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_77(N, X86::MMX_MOVD64rm, MVT::v2i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (scalar_to_vector:v2i32 GR32:i32:$src)
+ // Emits: (MMX_MOVD64rr:v2i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64rr, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
+
+ // Pattern: (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (MOVDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_77(N, X86::MOVDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (scalar_to_vector:v4i32 GR32:i32:$src)
+ // Emits: (MOVDI2PDIrr:v4i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::MOVDI2PDIrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v1i64(const SDValue &N) {
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MMX_MOVD64rrv164, MVT::v1i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_160(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
+}
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
+
+ // Pattern: (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (MOVQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_77(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+
+ // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v8i8:$src))
+ // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v4i16:$src))
+ // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v2i32:$src))
+ // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v1i64:$src))
+ // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (scalar_to_vector:v2i64 GR64:i64:$src)
+ // Emits: (MOV64toPQIrr:v2i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::MOV64toPQIrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
+
+ // Pattern: (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (MOVSS2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_77(N, X86::MOVSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (scalar_to_vector:v4f32 FR32:f32:$src)
+ // Emits: (MOVSS2PSrr:v4f32 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_71(N, X86::MOVSS2PSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
+
+ // Pattern: (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (MOVSD2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_77(N, X86::MOVSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (scalar_to_vector:v2f64 FR64:f64:$src)
+ // Emits: (MOVSD2PDrr:v2f64 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_71(N, X86::MOVSD2PDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_161(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
+}
+DISABLE_INLINE SDNode *Emit_162(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getDebugLoc(), X86::CL, N10, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, InFlag);
+}
+SDNode *Select_ISD_SHL_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHL8rCL:i8 GR8:i8:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHL8rCL, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (shl:i8 GR8:i8:$src1, 1:i8)
+ // Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_161(N, X86::ADD8rr, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (shl:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SHL8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHL8ri, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (shl:i8 GR8:i8:$src, CL:i8)
+ // Emits: (SHL8rCL:i8 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHL8rCL, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHL16rCL:i16 GR16:i16:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHL16rCL, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (shl:i16 GR16:i16:$src1, 1:i8)
+ // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_161(N, X86::ADD16rr, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (shl:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Emits: (SHL16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHL16ri, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (shl:i16 GR16:i16:$src, CL:i8)
+ // Emits: (SHL16rCL:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHL16rCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_i32(const SDValue &N) {
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHL32rCL:i32 GR32:i32:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHL32rCL, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (shl:i32 GR32:i32:$src1, 1:i8)
+ // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_161(N, X86::ADD32rr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (shl:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Emits: (SHL32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHL32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (shl:i32 GR32:i32:$src, CL:i8)
+ // Emits: (SHL32rCL:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHL32rCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SHL_i64(const SDValue &N) {
+
+ // Pattern: lea64addr:i64:$src
+ // Emits: (LEA64r:i64 lea64addr:i64:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (shl:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
+ // Emits: (SHL64rCL:i64 GR64:i64:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(63)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHL64rCL, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (shl:i64 GR64:i64:$src1, 1:i8)
+ // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_161(N, X86::ADD64rr, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (shl:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Emits: (SHL64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHL64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (shl:i64 GR64:i64:$src, CL:i8)
+ // Emits: (SHL64rCL:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHL64rCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SIGN_EXTEND_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVSX16rr8, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SIGN_EXTEND_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sext:i32 GR8:i8:$src)
+ // Emits: (MOVSX32rr8:i32 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVSX32rr8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sext:i32 GR16:i16:$src)
+ // Emits: (MOVSX32rr16:i32 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_71(N, X86::MOVSX32rr16, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sext:i64 GR8:i8:$src)
+ // Emits: (MOVSX64rr8:i64 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVSX64rr8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sext:i64 GR16:i16:$src)
+ // Emits: (MOVSX64rr16:i64 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_71(N, X86::MOVSX64rr16, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sext:i64 GR32:i32:$src)
+ // Emits: (MOVSX64rr32:i64 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::MOVSX64rr32, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp2, Tmp3), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_164(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
+}
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
+
+ // Pattern: (sext_inreg:i16 GR16:i16:$src, i8:Other)
+ // Emits: (MOVSX16rr8:i16 (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32))
+ // Pattern complexity = 3 cost = 2 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sext_inreg:i16 GR16:i16:$src, i8:Other)
+ // Emits: (MOVSX16rr8:i16 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32))
+ // Pattern complexity = 3 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_163(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_165(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_166(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp2, Tmp3), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp4);
+}
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
+
+ // Pattern: (sext_inreg:i32 GR32:i32:$src, i16:Other)
+ // Emits: (MOVSX32rr16:i32 (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
+ // Pattern complexity = 3 cost = 2 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 GR32:i32:$src, i8:Other)
+ // Emits: (MOVSX32rr8:i32 (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32))
+ // Pattern complexity = 3 cost = 2 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sext_inreg:i32 GR32:i32:$src, i8:Other)
+ // Emits: (MOVSX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32))
+ // Pattern complexity = 3 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_166(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_167(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
+}
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sext_inreg:i64 GR64:i64:$src, i32:Other)
+ // Emits: (MOVSX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
+ // Pattern complexity = 3 cost = 2 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i64 GR64:i64:$src, i16:Other)
+ // Emits: (MOVSX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
+ // Pattern complexity = 3 cost = 2 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sext_inreg:i64 GR64:i64:$src, i8:Other)
+ // Emits: (MOVSX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
+ // Pattern complexity = 3 cost = 2 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
+
+ // Pattern: (sint_to_fp:f32 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (CVTSI2SS64rm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_77(N, X86::CVTSI2SS64rm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (sint_to_fp:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (CVTSI2SSrm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_77(N, X86::CVTSI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sint_to_fp:f32 GR64:i64:$src)
+ // Emits: (CVTSI2SS64rr:f32 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::CVTSI2SS64rr, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (sint_to_fp:f32 GR32:i32:$src)
+ // Emits: (CVTSI2SSrr:f32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::CVTSI2SSrr, MVT::f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
+
+ // Pattern: (sint_to_fp:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (CVTSI2SD64rm:f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_77(N, X86::CVTSI2SD64rm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (sint_to_fp:f64 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (CVTSI2SDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_77(N, X86::CVTSI2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sint_to_fp:f64 GR64:i64:$src)
+ // Emits: (CVTSI2SD64rr:f64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_71(N, X86::CVTSI2SD64rr, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (sint_to_fp:f64 GR32:i32:$src)
+ // Emits: (CVTSI2SDrr:f64 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::CVTSI2SDrr, MVT::f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SINT_TO_FP_v4f32(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_71(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SINT_TO_FP_v2f64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_71(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SAR8rCL:i8 GR8:i8:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SAR8rCL, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sra:i8 GR8:i8:$src1, 1:i8)
+ // Emits: (SAR8r1:i8 GR8:i8:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SAR8r1, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sra:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SAR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SAR8ri, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (sra:i8 GR8:i8:$src, CL:i8)
+ // Emits: (SAR8rCL:i8 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SAR8rCL, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SAR16rCL:i16 GR16:i16:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SAR16rCL, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sra:i16 GR16:i16:$src1, 1:i8)
+ // Emits: (SAR16r1:i16 GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SAR16r1, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sra:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Emits: (SAR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SAR16ri, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (sra:i16 GR16:i16:$src, CL:i8)
+ // Emits: (SAR16rCL:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SAR16rCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SAR32rCL:i32 GR32:i32:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SAR32rCL, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sra:i32 GR32:i32:$src1, 1:i8)
+ // Emits: (SAR32r1:i32 GR32:i32:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SAR32r1, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sra:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Emits: (SAR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SAR32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sra:i32 GR32:i32:$src, CL:i8)
+ // Emits: (SAR32rCL:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SAR32rCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRA_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (sra:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
+ // Emits: (SAR64rCL:i64 GR64:i64:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(63)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SAR64rCL, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (sra:i64 GR64:i64:$src1, 1:i8)
+ // Emits: (SAR64r1:i64 GR64:i64:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SAR64r1, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sra:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Emits: (SAR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SAR64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sra:i64 GR64:i64:$src, CL:i8)
+ // Emits: (SAR64rCL:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SAR64rCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHR8rCL:i8 GR8:i8:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHR8rCL, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (srl:i8 GR8:i8:$src1, 1:i8)
+ // Emits: (SHR8r1:i8 GR8:i8:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SHR8r1, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (srl:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SHR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHR8ri, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (srl:i8 GR8:i8:$src, CL:i8)
+ // Emits: (SHR8rCL:i8 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHR8rCL, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_168(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp4, Tmp5), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp6), 0);
+ SDValue Tmp8 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp7, Tmp8);
+}
+SDNode *Select_ISD_SRL_i16(const SDValue &N) {
+
+ // Pattern: (srl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHR16rCL:i16 GR16:i16:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHR16rCL, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>
+ // Emits: (EXTRACT_SUBREG:i16 (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
+ // Pattern complexity = 9 cost = 4 size = 3
+ if ((!Subtarget->is64Bit()) &&
+ Predicate_srl_su(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>
+ // Emits: (EXTRACT_SUBREG:i16 (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
+ // Pattern complexity = 9 cost = 4 size = 3
+ if ((Subtarget->is64Bit()) &&
+ Predicate_srl_su(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i16 GR16:i16:$src1, 1:i8)
+ // Emits: (SHR16r1:i16 GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SHR16r1, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (srl:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Emits: (SHR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHR16ri, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (srl:i16 GR16:i16:$src, CL:i8)
+ // Emits: (SHR16rCL:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHR16rCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHR32rCL:i32 GR32:i32:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(31)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHR32rCL, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (srl:i32 GR32:i32:$src1, 1:i8)
+ // Emits: (SHR32r1:i32 GR32:i32:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SHR32r1, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (srl:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Emits: (SHR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHR32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (srl:i32 GR32:i32:$src, CL:i8)
+ // Emits: (SHR32rCL:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHR32rCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SRL_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (srl:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
+ // Emits: (SHR64rCL:i64 GR64:i64:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0 &&
+ CheckAndMask(N10, Tmp0, INT64_C(63)) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_162(N, X86::SHR64rCL, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (srl:i64 GR64:i64:$src1, 1:i8)
+ // Emits: (SHR64r1:i64 GR64:i64:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1) &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_92(N, X86::SHR64r1, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (srl:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Emits: (SHR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_159(N, X86::SHR64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (srl:i64 GR64:i64:$src, CL:i8)
+ // Emits: (SHR64rCL:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_158(N, X86::SHR64rCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Chain11 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N11.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain11);
+ Chain11 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N11)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, Chain11 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 6);
+ Chain11 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N11.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain11.getNode(), Chain11.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 6);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getDebugLoc(), X86::CL, N11, InFlag).getNode();
+ Chain10 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getDebugLoc(), X86::CL, N12, InFlag).getNode();
+ Chain10 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N12)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Tmp2, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag = N1.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_185(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
+ SDValue InFlag = N1.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i16);
+ SDValue InFlag = N1.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue InFlag = N1.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getDebugLoc(), X86::EFLAGS, N11, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i64);
+ SDValue InFlag = N1.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1000, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N11.getDebugLoc(), X86::CL, N110, InFlag).getNode();
+ Chain10 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N1111 = N111.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N100.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain100);
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N10.getDebugLoc(), X86::CL, N101, InFlag).getNode();
+ Chain100 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain100 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N100.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain100.getNode(), Chain100.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N11100 = N1110.getOperand(0);
+ SDValue N11101 = N1110.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N100.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain100);
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getDebugLoc(), X86::ECX, N1010, InFlag).getNode();
+ Chain100 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain100 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N100.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain100.getNode(), Chain100.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N100.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain100);
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Tmp2, Chain100 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain100 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N100.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain100.getNode(), Chain100.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N11100 = N1110.getOperand(0);
+ SDValue N11101 = N1110.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N100.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain100);
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getDebugLoc(), X86::CX, N1010, InFlag).getNode();
+ Chain100 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain100 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N100.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain100.getNode(), Chain100.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 6);
+ Chain10 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N1, Tmp2), 0);
+ MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
+ MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops1[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp3, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc1, MVT::Other, Ops1, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFF80000000ULL, MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR64_ABCDRegClassID, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
+ MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc2, MVT::Other, Ops2, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
+ MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc2, MVT::Other, Ops2, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
+ MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc2, MVT::Other, Ops2, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N11100 = N1110.getOperand(0);
+ SDValue N11101 = N1110.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N100.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain100);
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getDebugLoc(), X86::RCX, N1010, InFlag).getNode();
+ Chain100 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain100 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N100.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain100.getNode(), Chain100.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N10.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain10);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain10 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N10.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain10.getNode(), Chain10.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N100.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain100);
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N11, Chain100 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ Chain100 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N100.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain100.getNode(), Chain100.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1000, Tmp2, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Chain11 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N11.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain11);
+ Chain11 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N11)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, N10, Chain11 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ Chain11 = SDValue(ResNode, 1);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N11.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 1),
+ SDValue(Chain11.getNode(), Chain11.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Chain11 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N11.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain11);
+ Chain11 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag = N1.getOperand(2);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N11)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, N10, Chain11, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain11 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N11.getNode(), 1),
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain11.getNode(), Chain11.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain110 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N110.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain110);
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N101.getDebugLoc(), X86::CL, N1011, InFlag).getNode();
+ Chain110 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain110 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N110.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain110.getNode(), Chain110.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N10100 = N1010.getOperand(0);
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain110 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N110.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain110);
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getDebugLoc(), X86::ECX, N10101, InFlag).getNode();
+ Chain110 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain110 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N110.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain110.getNode(), Chain110.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain110 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N110.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain110);
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Tmp2, Chain110 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain110 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N110.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain110.getNode(), Chain110.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N10100 = N1010.getOperand(0);
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain110 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N110.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain110);
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getDebugLoc(), X86::CX, N10101, InFlag).getNode();
+ Chain110 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain110 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N110.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain110.getNode(), Chain110.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N10100 = N1010.getOperand(0);
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N110 = N11.getOperand(0);
+ SDValue Chain110 = N110.getOperand(0);
+ SDValue N1101 = N110.getOperand(1);
+ SDValue N111 = N11.getOperand(1);
+ SDValue N1110 = N111.getOperand(0);
+ SDValue N2 = N.getOperand(2);
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N110.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain110);
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getDebugLoc(), X86::RCX, N10101, InFlag).getNode();
+ Chain110 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
+ MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ Chain110 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
+ const SDValue Froms[] = {
+ SDValue(N110.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ SDValue(Chain110.getNode(), Chain110.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_ISD_STORE(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N1110.getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N11101 = N1110.getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_203(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N1110.getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N11101 = N1110.getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_203(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N1110.getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11101 = N1110.getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i16 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N1110.getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11101 = N1110.getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i16 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt)), (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N1110.getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N11101 = N1110.getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i64 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_213(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::SHL) {
+
+ // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt)), (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N1110.getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N11101 = N1110.getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i64 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_213(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_220(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_220(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i16 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_222(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i16 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_222(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i64 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_223(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::SRL) {
+
+ // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getOperand(0);
+ if (N1010.getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N10101 = N1010.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i64 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_223(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1111 = N111.getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1111 = N111.getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1111 = N111.getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1111 = N111.getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt), (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N1111 = N111.getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getOpcode() == ISD::SHL) {
+
+ // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt), (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N1111 = N111.getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_219(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_219(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_219(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_219(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_219(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(64)) {
+ SDValue N1011 = N101.getOperand(1);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_219(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_221(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_221(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_221(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_221(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_221(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getOperand(0);
+ if (N110.getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getOperand(1);
+ if (N111.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_221(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getOperand(0);
+ SDValue N111 = N11.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode())) {
+
+ // Pattern: (st:isVoid (sub:i8 0:i8, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_load(N11.getNode()) &&
+ Predicate_loadi8(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_173(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i16 0:i16, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_173(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i32 0:i32, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_173(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_175(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, -1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_175(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (st:isVoid (sub:i64 0:i64, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode()) &&
+ Predicate_loadi64(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_173(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_175(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, -1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_175(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 128:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, -128:i16)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(128)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_199(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 128:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, -128:i32)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(128)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_200(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 128:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, -128:i64)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (CN1 == INT64_C(128)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_208(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 34359738368:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, -2147483648:i64)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (CN1 == INT64_C(34359738368)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_209(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 2
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_174(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_174(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+
+ // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
+ SDNode *Result = Emit_191(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ SDNode *Result = Emit_191(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_191(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_191(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_174(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR128:v4i32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N1.hasOneUse() &&
+ Predicate_movlp(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_215(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ if (N12.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ if (N12.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ if (N12.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ if (N12.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_185(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_185(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ if (N12.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ if (N12.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v4f32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N1.hasOneUse() &&
+ Predicate_movlp(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_214(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N1.hasOneUse() &&
+ Predicate_movlp(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2f64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_214(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2i64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_214(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N10.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_206(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N10.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_206(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N10.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_206(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N10.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_206(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_182(N, X86::SHLD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_182(N, X86::SHRD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_182(N, X86::SHLD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_182(N, X86::SHRD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_184(N, X86::ADC8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_184(N, X86::ADC16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, X86::ADC32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_184(N, X86::SBB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_184(N, X86::SBB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_184(N, X86::SBB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_184(N, X86::ADC64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_184(N, X86::SBB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_180(N, X86::ROR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_182(N, X86::SHLD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N12 = N1.getOperand(2);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_182(N, X86::SHRD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2) {
+
+ // Pattern: (st:isVoid (and:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_217(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (and:i16 GR16:i16:$src, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_217(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (and:i32 GR32:i32:$src, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_217(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2) {
+
+ // Pattern: (st:isVoid (or:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_217(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (or:i16 GR16:i16:$src, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_217(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (or:i32 GR32:i32:$src, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_217(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2) {
+
+ // Pattern: (st:isVoid (xor:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_217(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (xor:i16 GR16:i16:$src, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_217(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (xor:i32 GR32:i32:$src, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_217(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2) {
+
+ // Pattern: (st:isVoid (add:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_217(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (add:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_217(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (add:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_217(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2) {
+
+ // Pattern: (st:isVoid (adde:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_218(N, X86::ADC8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (adde:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_218(N, X86::ADC16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (adde:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_218(N, X86::ADC32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (add:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_217(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (adde:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_218(N, X86::ADC64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (and:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_217(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_217(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (xor:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode())) {
+ SDValue N111 = N11.getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_217(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_extract:f64 (vector_shuffle:v2f64 (bitconvert:v2f64 VR128:v4f32:$src), (undef:v2f64))<<P:Predicate_unpckh>>, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVHPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 40 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ Predicate_unpckh(N10.getNode())) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::UNDEF) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f64 &&
+ N10.getValueType() == MVT::v2f64 &&
+ N1000.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_195(N, X86::MOVHPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_extract:f64 (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_unpckh>>, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVHPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ Predicate_unpckh(N10.getNode())) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::UNDEF) {
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_197(N, X86::MOVHPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (trunc:i8 (srl:i64 GR64:i64:$src, 8:i8)<<P:Predicate_srl_su>>)<<P:Predicate_trunc_su>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i64 GR64:i64:$src, GR64_ABCD:i64), 2:i32))
+ // Pattern complexity = 35 cost = 3 size = 3
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TRUNCATE &&
+ Predicate_trunc_su(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N10.getNode())) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i8 &&
+ N10.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_210(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::TRUNCATE &&
+ Predicate_trunc_su(N1.getNode())) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N10.getNode())) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i8) {
+
+ // Pattern: (st:isVoid (trunc:i8 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>)<<P:Predicate_trunc_su>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
+ // Pattern complexity = 35 cost = 3 size = 3
+ if (N10.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_211(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (trunc:i8 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)<<P:Predicate_trunc_su>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
+ // Pattern complexity = 35 cost = 3 size = 3
+ if (N10.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_212(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (bitconvert:f32 (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (EXTRACTPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src1, (imm:i32):$src2)
+ // Pattern complexity = 34 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N1000 = N100.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ if (N101.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f32 &&
+ N10.getValueType() == MVT::i32 &&
+ N100.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_216(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_extract:f64 (bitconvert:v2f64 VR128:v4f32:$src), 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f64 &&
+ N10.getValueType() == MVT::v2f64 &&
+ N100.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_194(N, X86::MOVLPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (EXTRACTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 31 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_198(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::SETCC) {
+ SDValue N10 = N1.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (st:isVoid (X86setcc:i8 4:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETEm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 9:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETNEm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETNEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 7:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETLm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETLm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 6:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETGEm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETGEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 8:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETLEm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETLEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 5:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETGm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETGm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 2:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETBm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETBm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 1:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETAEm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETAEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 3:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETBEm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETBEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 0:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETAm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETAm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 15:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETSm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 12:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETNSm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETNSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 14:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETPm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 11:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETNPm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETNPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 13:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETOm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86setcc:i8 10:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SETNOm:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDNode *Result = Emit_188(N, X86::SETNOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_extract:f32 VR128:v4f32:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVPS2SSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f32 &&
+ N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_196(N, X86::MOVPS2SSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid (vector_extract:f64 VR128:v2f64:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (N1.getValueType() == MVT::f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_196(N, X86::MOVLPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (vector_extract:i64 VR128:v2i64:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVPQI2QImr:isVoid addr:iPTR:$dst, VR128:v2i64:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64 &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_196(N, X86::MOVPQI2QImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (vector_extract:f64 VR128:v2f64:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVPD2SDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (N1.getValueType() == MVT::f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_196(N, X86::MOVPD2SDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (vector_extract:i32 VR128:v4i32:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVPDI2DImr:isVoid addr:iPTR:$dst, VR128:v4i32:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_196(N, X86::MOVPDI2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ if (N11.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid (extractelt:i64 VR128:v2i64:$src1, (imm:iPTR):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (PEXTRQmr:isVoid addr:iPTR:$dst, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64 &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_193(N, X86::PEXTRQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (extractelt:i32 VR128:v4i32:$src1, (imm:iPTR):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (PEXTRDmr:isVoid addr:iPTR:$dst, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_193(N, X86::PEXTRDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((TM.getCodeModel() == CodeModel::Small ||TM.getCodeModel() == CodeModel::Kernel) && (TM.getRelocationModel() == Reloc::Static)) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (st:isVoid (X86Wrapper:i64 (tconstpool:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tconstpool:i64):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86Wrapper:i64 (tjumptable:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tjumptable:i64):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetJumpTable) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86Wrapper:i64 (tglobaladdr:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tglobaladdr:i64):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86Wrapper:i64 (texternalsym:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (texternalsym:i64):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86Wrapper:i64 (tblockaddress:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tblockaddress:i64):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == X86ISD::Wrapper) {
+ SDValue N10 = N1.getOperand(0);
+
+ // Pattern: (st:isVoid (X86Wrapper:i32 (tglobaladdr:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (tglobaladdr:i32):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86Wrapper:i32 (texternalsym:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (texternalsym:i32):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86Wrapper:i32 (tblockaddress:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (tblockaddress:i32):$src)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N10.getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (imm:i64)<<P:Predicate_i64immSExt32>>:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_189(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid (imm:i8):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_169(N, X86::MOV8mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (imm:i16):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (imm:i32):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_171(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid (bitconvert:i64 FR64:f64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVSDto64mr:isVoid addr:iPTR:$dst, FR64:f64:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64 &&
+ N10.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_192(N, X86::MOVSDto64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (bitconvert:i32 FR32:f32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVSS2DImr:isVoid addr:iPTR:$dst, FR32:f32:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_192(N, X86::MOVSS2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_truncstore(N.getNode()) &&
+ Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid (imm:i32):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (imm:i64):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid RFP32:f32:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_172(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+
+ // Pattern: (st:isVoid RFP64:f64:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref32>>
+ // Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_truncstore(N.getNode()) &&
+ Predicate_truncstoref32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_172(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid RFP64:f64:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ST_Fp64m:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_172(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+ if (Predicate_truncstore(N.getNode())) {
+
+ // Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref32>>
+ // Emits: (ST_Fp80m32:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_truncstoref32(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_172(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref64>>
+ // Emits: (ST_Fp80m64:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (Predicate_truncstoref64(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_172(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 22 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_172(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GR8:i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_172(N, X86::MOV8mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GR16:i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_172(N, X86::MOV16mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GR32:i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_172(N, X86::MOV32mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GR64:i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOV64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_172(N, X86::MOV64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+
+ // Pattern: (st:isVoid FR32:f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVSSmr:isVoid addr:iPTR:$dst, FR32:f32:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_172(N, X86::MOVSSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
+ // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedstore(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+
+ // Pattern: (st:isVoid FR64:f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVSDmr:isVoid addr:iPTR:$dst, FR64:f64:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_172(N, X86::MOVSDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
+ // Emits: (MOVAPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_alignedstore(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_172(N, X86::MOVAPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVUPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_172(N, X86::MOVUPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid VR64:v1i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
+ N1.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode()) &&
+ Predicate_store(N.getNode())) {
+ if (Predicate_alignedstore(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid VR128:v2i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
+ // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR128:v4i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
+ // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR128:v8i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
+ // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR128:v16i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
+ // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid VR128:v2i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR128:v4i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR128:v8i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR128:v16i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_unindexedstore(N.getNode())) {
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid VR64:v8i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR64:v4i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR64:v2i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR64:v2f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2f32) {
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid VR64:v1i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_truncstore(N.getNode()) &&
+ Predicate_truncstorei16(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (st:isVoid GR32:i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
+ // Pattern complexity = 22 cost = 2 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid GR64:i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
+ // Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
+ // Pattern complexity = 22 cost = 2 size = 3
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_224(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N1);
+}
+SDNode *Select_ISD_SUB_i8(const SDValue &N) {
+
+ // Pattern: (sub:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i8 0:i8, GR8:i8:$src)
+ // Emits: (NEG8r:i8 GR8:i8:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_224(N, X86::NEG8r, MVT::i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (SUB8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_i16(const SDValue &N) {
+
+ // Pattern: (sub:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i16 0:i16, GR16:i16:$src)
+ // Emits: (NEG16r:i16 GR16:i16:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_224(N, X86::NEG16r, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sub:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (SUB16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::SUB16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (sub:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (SUB16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::SUB16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (SUB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_i32(const SDValue &N) {
+
+ // Pattern: (sub:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i32 0:i32, GR32:i32:$src)
+ // Emits: (NEG32r:i32 GR32:i32:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_224(N, X86::NEG32r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sub:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::SUB32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sub:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (SUB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::SUB32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sub:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (SUB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_i64(const SDValue &N) {
+
+ // Pattern: (sub:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: lea64addr:i64:$src
+ // Emits: (LEA64r:i64 lea64addr:i64:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (sub:i64 0:i64, GR64:i64:$src)
+ // Emits: (NEG64r:i64 GR64:i64:$src)
+ // Pattern complexity = 8 cost = 1 size = 2
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_224(N, X86::NEG64r, MVT::i64);
+ return Result;
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sub:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::SUB64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sub:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (SUB64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::SUB64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sub:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (SUB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
+
+ // Pattern: (sub:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PSUBBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PSUBBrr, MVT::v8i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
+
+ // Pattern: (sub:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSUBBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSUBBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PSUBBrr, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
+
+ // Pattern: (sub:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PSUBWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PSUBWrr, MVT::v4i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
+
+ // Pattern: (sub:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSUBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSUBWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PSUBWrr, MVT::v8i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
+
+ // Pattern: (sub:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PSUBDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PSUBDrr, MVT::v2i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
+
+ // Pattern: (sub:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSUBDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PSUBDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PSUBDrr, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v1i64(const SDValue &N) {
+
+ // Pattern: (sub:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSUBQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PSUBQrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUB_v2i64(const SDValue &N) {
+
+ // Pattern: (sub:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PSUBQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PSUBQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (sub:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PSUBQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PSUBQrr, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
+
+ // Pattern: (subc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_21(N, X86::SUB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (subc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_22(N, X86::SUB32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (subc:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (SUB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_22(N, X86::SUB32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (SUB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_20(N, X86::SUB32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
+
+ // Pattern: (subc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_21(N, X86::SUB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (subc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_24(N, X86::SUB64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (subc:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Emits: (SUB64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_24(N, X86::SUB64ri32, MVT::i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (subc:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (SUB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_20(N, X86::SUB64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_SUBE_i8(const SDValue &N) {
+
+ // Pattern: (sube:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::SBB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (sube:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SBB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_27(N, X86::SBB8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (SBB8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::SBB8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_ISD_SUBE_i16(const SDValue &N) {
+
+ // Pattern: (sube:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::SBB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sube:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (SBB16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_29(N, X86::SBB16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (sube:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (SBB16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_29(N, X86::SBB16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (SBB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::SBB16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
+
+ // Pattern: (sube:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::SBB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sube:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (SBB32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_30(N, X86::SBB32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (sube:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (SBB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_30(N, X86::SBB32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (sube:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (SBB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::SBB32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
+
+ // Pattern: (sube:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_26(N, X86::SBB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (sube:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (SBB64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_31(N, X86::SBB64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (sube:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (SBB64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_31(N, X86::SBB64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (sube:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (SBB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_25(N, X86::SBB64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+}
+SDNode *Select_ISD_TRAP(const SDValue &N) {
+ SDNode *Result = Emit_225(N, X86::TRAP);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_227(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp4, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp4, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_230(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8)) {
+
+ // Pattern: (trunc:i8 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR16:i16:$src, GR16_ABCD:i16), 2:i32)
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_228(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (trunc:i8 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR32:i32:$src, GR32_ABCD:i32), 2:i32)
+ // Pattern complexity = 12 cost = 2 size = 0
+ if (N0.getValueType() == MVT::i32 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_229(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (trunc:i8 GR64:i64:$src)
+ // Emits: (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ return Result;
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (trunc:i8 GR32:i32:$src)
+ // Emits: (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (trunc:i8 GR16:i16:$src)
+ // Emits: (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ return Result;
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (trunc:i8 GR32:i32:$src)
+ // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32)
+ // Pattern complexity = 3 cost = 2 size = 0
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_226(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (trunc:i8 GR16:i16:$src)
+ // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32)
+ // Pattern complexity = 3 cost = 2 size = 0
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_227(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_231(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (trunc:i16 GR32:i32:$src)
+ // Emits: (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (trunc:i16 GR64:i64:$src)
+ // Emits: (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_232(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+
+ // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
+ // Emits: (MMX_PUNPCKHBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_mmx_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PUNPCKHBWrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
+ // Emits: (MMX_PUNPCKLBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_mmx_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PUNPCKLBWrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src, (undef:v8i8))<<P:Predicate_mmx_unpckl_undef>>
+ // Emits: (MMX_PUNPCKLBWrr:v8i8 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_mmx_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src, (undef:v8i8))<<P:Predicate_mmx_unpckh_undef>>
+ // Emits: (MMX_PUNPCKHBWrr:v8i8 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_mmx_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+
+ // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)<<P:Predicate_mmx_unpckh>>
+ // Emits: (MMX_PUNPCKHBWrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_mmx_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)<<P:Predicate_mmx_unpckl>>
+ // Emits: (MMX_PUNPCKLBWrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_mmx_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_233(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_palign_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N0, Tmp3);
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKLBWrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKHBWrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckl_undef>>
+ // Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLBWrr, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckh_undef>>
+ // Emits: (PUNPCKHBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHBWrr, MVT::v16i8);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
+ // Emits: (PALIGNR128rr:v16i8 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3()) &&
+ Predicate_palign(N.getNode())) {
+ SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v16i8);
+ return Result;
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKLBWrr, MVT::v16i8);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHBWrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKHBWrr, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_234(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_235(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(N.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+
+ // Pattern: (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (MMX_PSHUFWmi:v4i16 addr:iPTR:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16)):$src2))
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (Predicate_mmx_pshufw(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_235(N, X86::MMX_PSHUFWmi, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
+ // Emits: (MMX_PUNPCKHWDrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_mmx_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PUNPCKHWDrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
+ // Emits: (MMX_PUNPCKLWDrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_mmx_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PUNPCKLWDrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src, (undef:v4i16))<<P:Predicate_mmx_unpckl_undef>>
+ // Emits: (MMX_PUNPCKLWDrr:v4i16 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_mmx_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src, (undef:v4i16))<<P:Predicate_mmx_unpckh_undef>>
+ // Emits: (MMX_PUNPCKHWDrr:v4i16 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_mmx_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (MMX_PSHUFWri:v4i16 VR64:v4i16:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 VR64:v4i16:$src1, (undef:v4i16)):$src2))
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_mmx_pshufw(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_234(N, X86::MMX_PSHUFWri, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)<<P:Predicate_mmx_unpckh>>
+ // Emits: (MMX_PUNPCKHWDrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_mmx_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)<<P:Predicate_mmx_unpckl>>
+ // Emits: (MMX_PUNPCKLWDrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_mmx_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_236(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(N.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_238(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_239(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(N.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
+ // Emits: (PSHUFHWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (Predicate_pshufhw(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_237(N, X86::PSHUFHWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshuflw>><<X:SHUFFLE_get_pshuflw_imm>>:$src2
+ // Emits: (PSHUFLWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshuflw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (Predicate_pshuflw(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_239(N, X86::PSHUFLWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLWDrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKLWDrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHWDrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKHWDrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckl_undef>>
+ // Emits: (PUNPCKLWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLWDrr, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckh_undef>>
+ // Emits: (PUNPCKHWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHWDrr, MVT::v8i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
+ // Emits: (PALIGNR128rr:v8i16 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3()) &&
+ Predicate_palign(N.getNode())) {
+ SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v8i16);
+ return Result;
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
+ // Emits: (PSHUFHWri:v8i16 VR128:v8i16:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16)):$src2))
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_pshufhw(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_236(N, X86::PSHUFHWri, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16))<<P:Predicate_pshuflw>><<X:SHUFFLE_get_pshuflw_imm>>:$src2
+ // Emits: (PSHUFLWri:v8i16 VR128:v8i16:$src1, (SHUFFLE_get_pshuflw_imm:i8 (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16)):$src2))
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_pshuflw(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFLWri, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLWDrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKLWDrr, MVT::v8i16);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHWDrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKHWDrr, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+
+ // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
+ // Emits: (MMX_PUNPCKHDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_mmx_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PUNPCKHDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
+ // Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_mmx_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src, (undef:v2i32))<<P:Predicate_mmx_unpckl_undef>>
+ // Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_mmx_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src, (undef:v2i32))<<P:Predicate_mmx_unpckh_undef>>
+ // Emits: (MMX_PUNPCKHDQrr:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_mmx_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+
+ // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)<<P:Predicate_mmx_unpckh>>
+ // Emits: (MMX_PUNPCKHDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_mmx_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)<<P:Predicate_mmx_unpckl>>
+ // Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_mmx_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_240(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_243(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_244(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE3())) {
+
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movshdup>>
+ // Emits: (MOVSHDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movshdup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_242(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movsldup>>
+ // Emits: (MOVSLDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movsldup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_242(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32)):$src2))
+ // Pattern complexity = 37 cost = 1 size = 3
+ if (Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_241(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_242(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_241(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKLDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKHDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_shufp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_244(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_movhlps_undef>>
+ // Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src1)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if (Predicate_movhlps_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movlhps>>
+ // Emits: (MOVLHPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 24 cost = 1 size = 3
+ if (Predicate_movlhps(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLHPSrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movhlps>>
+ // Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 24 cost = 1 size = 3
+ if (Predicate_movhlps(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVHLPSrr, MVT::v4i32);
+ return Result;
+ }
+ if ((Subtarget->hasSSE3())) {
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_movshdup>>
+ // Emits: (MOVSHDUPrr:v4i32 VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_movshdup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_92(N, X86::MOVSHDUPrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_movsldup>>
+ // Emits: (MOVSLDUPrr:v4i32 VR128:v16i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_movsldup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_92(N, X86::MOVSLDUPrr, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if ((!OptForSize) && (Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckl_undef>>:$src2
+ // Emits: (PSHUFDri:v4i32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckh_undef>>:$src2
+ // Emits: (PSHUFDri:v4i32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movl>>
+ // Emits: (MOVLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 19 cost = 1 size = 3
+ if (Predicate_movl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLPSrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 19 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckl_undef>>
+ // Emits: (PUNPCKLDQrr:v4i32 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLDQrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckh_undef>>
+ // Emits: (PUNPCKHDQrr:v4i32 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHDQrr, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (PSHUFDri:v4i32 VR128:v4i32:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32)):$src2))
+ // Pattern complexity = 12 cost = 1 size = 3
+ if (Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
+ // Emits: (PALIGNR128rr:v4i32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3()) &&
+ Predicate_palign(N.getNode())) {
+ SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v4i32);
+ return Result;
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLDQrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKLDQrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHDQrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKHDQrr, MVT::v4i32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_shufp(N.getNode())) {
+ SDNode *Result = Emit_243(N, X86::SHUFPSrri, MVT::v4i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_245(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100);
+}
+DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_247(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0, Tmp3);
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_movlp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2i64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 34 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_246(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_movddup>>
+ // Emits: (MOVLHPSrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PUNPCKLQDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PUNPCKHQDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_movl>>
+ // Emits: (MOVLPDrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 19 cost = 1 size = 3
+ if (Predicate_movl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_splat_lo>>
+ // Emits: (PUNPCKLQDQrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_splat_lo(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLQDQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHQDQrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHQDQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 (build_vector:v2i64)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v8i8:$src)))<<P:Predicate_movl>>
+ // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
+ // Pattern complexity = 14 cost = 1 size = 3
+ if (Predicate_movl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N0.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getOperand(0);
+ if (N10.getValueType() == MVT::i64 &&
+ N100.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_245(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (undef:v2i64))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_247(N, X86::SHUFPDrri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLQDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKLQDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHQDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::PUNPCKHQDQrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_shufp(N.getNode())) {
+ SDNode *Result = Emit_243(N, X86::SHUFPDrri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue N100 = N10.getOperand(0);
+ SDValue Chain100 = N100.getOperand(0);
+ SDValue N1001 = N100.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N100)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, Chain100 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp3, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_250(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N0, Tmp3);
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE1())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlp>>
+ // Emits: (MOVLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadf64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2f64 &&
+ N100.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_248(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlhps>>
+ // Emits: (MOVHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movlhps(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getOperand(0);
+ if (N100.getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
+ SDValue Chain100 = N100.getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadf64(N100.getNode())) {
+ SDValue N1001 = N100.getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2f64 &&
+ N100.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_248(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPSrm:v4f32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 (bitconvert:v4f32 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4f32))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_242(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKHPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
+ // Emits: (UNPCKLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3())) {
+
+ // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movshdup>>
+ // Emits: (MOVSHDUPrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_movshdup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_246(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movsldup>>
+ // Emits: (MOVSLDUPrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_movsldup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_246(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movddup>>
+ // Emits: (MOVLHPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_movhlps_undef>>
+ // Emits: (MOVHLPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src1)
+ // Pattern complexity = 27 cost = 1 size = 3
+ if (Predicate_movhlps_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1()) &&
+ Predicate_shufp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_249(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlhps>>
+ // Emits: (MOVLHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 24 cost = 1 size = 3
+ if (Predicate_movlhps(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLHPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movhlps>>
+ // Emits: (MOVHLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 24 cost = 1 size = 3
+ if (Predicate_movhlps(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVHLPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+ if ((!OptForSize) && (Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckl_undef>>:$src2
+ // Emits: (PSHUFDri:v4f32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckh_undef>>:$src2
+ // Emits: (PSHUFDri:v4f32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movl>>
+ // Emits: (MOVLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 19 cost = 1 size = 3
+ if ((Subtarget->hasSSE1()) &&
+ Predicate_movl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 19 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_movlp(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v4f32);
+ return Result;
+ }
+ if ((Subtarget->hasSSE1())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckl_undef>>
+ // Emits: (UNPCKLPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckl_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKLPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckh_undef>>
+ // Emits: (UNPCKHPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_unpckh_undef(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKHPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 14 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::UNPCKHPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_unpckl>>
+ // Emits: (UNPCKLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 14 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::UNPCKLPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (PSHUFDri:v4f32 VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 12 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_240(N, X86::PSHUFDri, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
+ // Emits: (PALIGNR128rr:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3()) &&
+ Predicate_palign(N.getNode())) {
+ SDNode *Result = Emit_233(N, X86::PALIGNR128rr, MVT::v4f32);
+ return Result;
+ }
+ if ((Subtarget->hasSSE3())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movshdup>>
+ // Emits: (MOVSHDUPrr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_movshdup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_92(N, X86::MOVSHDUPrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movsldup>>
+ // Emits: (MOVSLDUPrr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_movsldup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_92(N, X86::MOVSLDUPrr, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_247(N, X86::SHUFPSrri, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2):$src3))
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_shufp(N.getNode())) {
+ SDNode *Result = Emit_243(N, X86::SHUFPSrri, MVT::v4f32);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlp>>:$src3
+ // Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDNode *Result = Emit_250(N, X86::SHUFPSrri, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_251(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N000 = N00.getOperand(0);
+ SDValue Chain000 = N000.getOperand(0);
+ SDValue N0001 = N000.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N000)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4, Chain000 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N000.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 49 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadf64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_16(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlhps>>
+ // Emits: (MOVHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 49 cost = 1 size = 3
+ if (Predicate_movlhps(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadf64(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_16(N, X86::MOVHPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrm:v2f64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if (Predicate_movlp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckh(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKHPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
+ // Emits: (UNPCKLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)), (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N00.hasOneUse()) {
+ SDValue N000 = N00.getOperand(0);
+ if (N000.getOpcode() == ISD::LOAD &&
+ N000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N.getNode())) {
+ SDValue Chain000 = N000.getOperand(0);
+ if (Predicate_unindexedload(N000.getNode()) &&
+ Predicate_load(N000.getNode()) &&
+ Predicate_loadi64(N000.getNode())) {
+ SDValue N0001 = N000.getOperand(1);
+ SDValue CPTmpN0001_0;
+ SDValue CPTmpN0001_1;
+ SDValue CPTmpN0001_2;
+ SDValue CPTmpN0001_3;
+ SDValue CPTmpN0001_4;
+ if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64 &&
+ N000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_251(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 34 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_246(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>), (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadf64(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_242(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
+ // Pattern complexity = 26 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_shufp(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_249(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ if (Predicate_movl(N.getNode())) {
+
+ // Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64)<<P:Predicate_immAllZerosV_bc>>, VR128:v2f64:$src)<<P:Predicate_movl>>
+ // Emits: (MOVZPQILo2PQIrr:v2f64 VR128:v16i8:$src)
+ // Pattern complexity = 23 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllZerosV_bc(N0.getNode())) {
+ SDNode *Result = Emit_106(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_movl>>
+ // Emits: (MOVLPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 19 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_splat_lo>>
+ // Emits: (UNPCKLPDrr:v2f64 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ if (Predicate_splat_lo(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKLPDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+ if (Predicate_unpckh(N.getNode())) {
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPDrr:v2f64 VR128:v16i8:$src, VR128:v16i8:$src)
+ // Pattern complexity = 17 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKHPDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 14 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::UNPCKHPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_unpckl>>
+ // Emits: (UNPCKLPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 14 cost = 1 size = 3
+ if (Predicate_unpckl(N.getNode())) {
+ SDNode *Result = Emit_15(N, X86::UNPCKLPDrr, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrr:v2f64 VR128:v2f64:$src)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_92(N, X86::MOVDDUPrr, MVT::v2f64);
+ return Result;
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (undef:v2f64))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPDrri:v2f64 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_pshufd(N.getNode())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_247(N, X86::SHUFPDrri, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2):$src3))
+ // Pattern complexity = 4 cost = 1 size = 3
+ if (Predicate_shufp(N.getNode())) {
+ SDNode *Result = Emit_243(N, X86::SHUFPDrri, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_XOR_i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
+ // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i8 GR8:i8:$src, (imm:i8)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOT8r:i8 GR8:i8:$src)
+ // Pattern complexity = 22 cost = 1 size = 2
+ if (Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_92(N, X86::NOT8r, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (xor:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_3(N, X86::XOR8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (XOR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_ISD_XOR_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
+ // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i16 GR16:i16:$src, (imm:i16)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOT16r:i16 GR16:i16:$src)
+ // Pattern complexity = 22 cost = 1 size = 2
+ if (Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_92(N, X86::NOT16r, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (xor:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (XOR16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::XOR16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (xor:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (XOR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::XOR16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (XOR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_ISD_XOR_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
+ // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i32 GR32:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOT32r:i32 GR32:i32:$src)
+ // Pattern complexity = 22 cost = 1 size = 2
+ if (Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_92(N, X86::NOT32r, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (XOR32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::XOR32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (xor:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (XOR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::XOR32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (xor:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (XOR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_ISD_XOR_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
+ // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (xor:i64 GR64:i64:$src, (imm:i64)<<P:Predicate_immAllOnes>>)
+ // Emits: (NOT64r:i64 GR64:i64:$src)
+ // Pattern complexity = 22 cost = 1 size = 3
+ if (Predicate_immAllOnes(N1.getNode())) {
+ SDNode *Result = Emit_92(N, X86::NOT64r, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (xor:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (XOR64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::XOR64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (xor:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (XOR64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::XOR64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (xor:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (XOR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_ISD_XOR_v1i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
+ // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PXORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDNode *Result = Emit_15(N, X86::MMX_PXORrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_56(N, X86::XORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_56(N, X86::XORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
+ // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_61(N, X86::XORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
+ // Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_61(N, X86::XORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PXORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PXORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (XORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getOperand(0);
+ if (N00.getValueType() == MVT::v2f64 &&
+ N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_58(N, X86::XORPDrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (XORPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::XORPSrr, MVT::v2i64);
+ return Result;
+ }
+
+ // Pattern: (xor:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PXORrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::PXORrr, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ZERO_EXTEND_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (zext:i16 (X86setcc_c:i8 2:i8, EFLAGS:i32))
+ // Emits: (SETB_C16r:i16)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_72(N, X86::SETB_C16r, MVT::i16);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (zext:i16 GR8:i8:$src)
+ // Emits: (MOVZX16rr8:i16 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVZX16rr8, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ZERO_EXTEND_i32(const SDValue &N) {
+
+ // Pattern: (zext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
+ // Pattern complexity = 12 cost = 3 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (zext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
+ // Pattern complexity = 12 cost = 3 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (zext:i32 (X86setcc_c:i8 2:i8, EFLAGS:i32))
+ // Emits: (SETB_C32r:i32)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_72(N, X86::SETB_C32r, MVT::i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (zext:i32 GR8:i8:$src)
+ // Emits: (MOVZX32rr8:i32 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVZX32rr8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (zext:i32 GR16:i16:$src)
+ // Emits: (MOVZX32rr16:i32 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_71(N, X86::MOVZX32rr16, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (zext:i64 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
+ // Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 4:i32)
+ // Pattern complexity = 12 cost = 4 size = 3
+ if (N0.getOpcode() == ISD::SRL &&
+ Predicate_srl_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(8) &&
+ N0.getValueType() == MVT::i16 &&
+ N01.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_75(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (zext:i64 (X86setcc_c:i8 2:i8, EFLAGS:i32))
+ // Emits: (SETB_C64r:i64)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_72(N, X86::SETB_C64r, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (zext:i64 GR32:i32<<P:Predicate_def32>>:$src)
+ // Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
+ // Pattern complexity = 4 cost = 1 size = 0
+ if (Predicate_def32(N0.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_74(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (zext:i64 GR8:i8:$src)
+ // Emits: (MOVZX64rr8:i64 GR8:i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_71(N, X86::MOVZX64rr8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (zext:i64 GR16:i16:$src)
+ // Emits: (MOVZX64rr16:i64 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_71(N, X86::MOVZX64rr16, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (zext:i64 GR32:i32:$src)
+ // Emits: (MOVZX64rr32:i64 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_71(N, X86::MOVZX64rr32, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_ADD_i8(const SDValue &N) {
+
+ // Pattern: (X86add_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86add_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86add_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_ADD_i16(const SDValue &N) {
+
+ // Pattern: (X86add_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86add_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::ADD16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86add_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (ADD16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::ADD16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86add_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_ADD_i32(const SDValue &N) {
+
+ // Pattern: (X86add_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86add_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::ADD32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86add_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86add_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_ADD_i64(const SDValue &N) {
+
+ // Pattern: (X86add_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86add_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::ADD64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86add_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::ADD64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86add_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_AND_i8(const SDValue &N) {
+
+ // Pattern: (X86and_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86and_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86and_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (AND8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_AND_i16(const SDValue &N) {
+
+ // Pattern: (X86and_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86and_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (AND16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::AND16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86and_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (AND16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::AND16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86and_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (AND16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_AND_i32(const SDValue &N) {
+
+ // Pattern: (X86and_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86and_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (AND32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::AND32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86and_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (AND32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::AND32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86and_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (AND32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_AND_i64(const SDValue &N) {
+
+ // Pattern: (X86and_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86and_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (AND64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::AND64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86and_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (AND64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::AND64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86and_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (AND64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::AND64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_252(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain, InFlag);
+}
+SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BasicBlock) {
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 4:i8, EFLAGS:i32)
+ // Emits: (JE:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_252(N, X86::JE);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 9:i8, EFLAGS:i32)
+ // Emits: (JNE:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_252(N, X86::JNE);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 7:i8, EFLAGS:i32)
+ // Emits: (JL:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_252(N, X86::JL);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 8:i8, EFLAGS:i32)
+ // Emits: (JLE:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_252(N, X86::JLE);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 5:i8, EFLAGS:i32)
+ // Emits: (JG:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_252(N, X86::JG);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 6:i8, EFLAGS:i32)
+ // Emits: (JGE:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_252(N, X86::JGE);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 2:i8, EFLAGS:i32)
+ // Emits: (JB:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_252(N, X86::JB);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 3:i8, EFLAGS:i32)
+ // Emits: (JBE:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_252(N, X86::JBE);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 0:i8, EFLAGS:i32)
+ // Emits: (JA:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_252(N, X86::JA);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 1:i8, EFLAGS:i32)
+ // Emits: (JAE:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_252(N, X86::JAE);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 15:i8, EFLAGS:i32)
+ // Emits: (JS:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_252(N, X86::JS);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 12:i8, EFLAGS:i32)
+ // Emits: (JNS:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_252(N, X86::JNS);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 14:i8, EFLAGS:i32)
+ // Emits: (JP:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_252(N, X86::JP);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 11:i8, EFLAGS:i32)
+ // Emits: (JNP:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_252(N, X86::JNP);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 13:i8, EFLAGS:i32)
+ // Emits: (JO:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_252(N, X86::JO);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 10:i8, EFLAGS:i32)
+ // Emits: (JNO:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_252(N, X86::JNO);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_253(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0);
+}
+DISABLE_INLINE SDNode *Emit_254(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
+ return ResNode;
+}
+SDNode *Select_X86ISD_BSF_i16(const SDValue &N) {
+
+ // Pattern: (X86bsf:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (BSF16rm:i16 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_254(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86bsf:i16 GR16:i16:$src)
+ // Emits: (BSF16rr:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_253(N, X86::BSF16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_BSF_i32(const SDValue &N) {
+
+ // Pattern: (X86bsf:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (BSF32rm:i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_254(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86bsf:i32 GR32:i32:$src)
+ // Emits: (BSF32rr:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_253(N, X86::BSF32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_BSF_i64(const SDValue &N) {
+
+ // Pattern: (X86bsf:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (BSF64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_254(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86bsf:i64 GR64:i64:$src)
+ // Emits: (BSF64rr:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_253(N, X86::BSF64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_BSR_i16(const SDValue &N) {
+
+ // Pattern: (X86bsr:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (BSR16rm:i16 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_254(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86bsr:i16 GR16:i16:$src)
+ // Emits: (BSR16rr:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_253(N, X86::BSR16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_BSR_i32(const SDValue &N) {
+
+ // Pattern: (X86bsr:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (BSR32rm:i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_254(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86bsr:i32 GR32:i32:$src)
+ // Emits: (BSR32rr:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_253(N, X86::BSR32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_BSR_i64(const SDValue &N) {
+
+ // Pattern: (X86bsr:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (BSR64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_254(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86bsr:i64 GR64:i64:$src)
+ // Emits: (BSR64rr:i64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_253(N, X86::BSR64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_255(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, N1);
+}
+DISABLE_INLINE SDNode *Emit_256(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_257(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_260(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_261(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_BT(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
+
+ // Pattern: (X86bt:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (BT16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_258(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86bt:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (BT32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_259(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86bt:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (BT64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_261(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86bt:isVoid GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (BT16ri8:isVoid GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_256(N, X86::BT16ri8);
+ return Result;
+ }
+
+ // Pattern: (X86bt:isVoid GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (BT32ri8:isVoid GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_257(N, X86::BT32ri8);
+ return Result;
+ }
+
+ // Pattern: (X86bt:isVoid GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (BT64ri8:isVoid GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_260(N, X86::BT64ri8);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86bt:isVoid GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (BT16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_255(N, X86::BT16rr);
+ return Result;
+ }
+
+ // Pattern: (X86bt:isVoid GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (BT32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_255(N, X86::BT32rr);
+ return Result;
+ }
+
+ // Pattern: (X86bt:isVoid GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (BT64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_255(N, X86::BT64rr);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SmallVector<SDValue, 8> InChains;
+ if (Chain.getNode() != N1.getNode()) {
+ InChains.push_back(Chain);
+ }
+ InChains.push_back(Chain1);
+ Chain1 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(CPTmpN11_0);
+ Ops0.push_back(CPTmpN11_1);
+ Ops0.push_back(CPTmpN11_2);
+ Ops0.push_back(CPTmpN11_3);
+ Ops0.push_back(CPTmpN11_4);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ Ops0.push_back(Chain1);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain1 = SDValue(ResNode, 0);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N1.getNode(), 1),
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ SDValue(ResNode, 0),
+ InFlag,
+ SDValue(Chain1.getNode(), Chain1.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 3);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_264(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(Tmp0);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_CALL(const SDValue &N) {
+
+ // Pattern: (X86call:isVoid (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (CALL32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_263(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86call:isVoid (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (CALL64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((!Subtarget->isTargetWin64())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_263(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86call:isVoid (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (WINCALL64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->isTargetWin64())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_263(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->isTargetWin64())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86call:isVoid (tglobaladdr:i64):$dst)
+ // Emits: (CALL64pcrel32:isVoid (tglobaladdr:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_262(N, X86::CALL64pcrel32, 1);
+ return Result;
+ }
+
+ // Pattern: (X86call:isVoid (texternalsym:i64):$dst)
+ // Emits: (CALL64pcrel32:isVoid (texternalsym:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_262(N, X86::CALL64pcrel32, 1);
+ return Result;
+ }
+ }
+ if ((Subtarget->isTargetWin64())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86call:isVoid (tglobaladdr:i64):$dst)
+ // Emits: (WINCALL64pcrel32:isVoid (tglobaladdr:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_262(N, X86::WINCALL64pcrel32, 1);
+ return Result;
+ }
+
+ // Pattern: (X86call:isVoid (texternalsym:i64):$dst)
+ // Emits: (WINCALL64pcrel32:isVoid (texternalsym:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_262(N, X86::WINCALL64pcrel32, 1);
+ return Result;
+ }
+ }
+ {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86call:isVoid (tglobaladdr:i32):$dst)
+ // Emits: (CALLpcrel32:isVoid (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, X86::CALLpcrel32, 1);
+ return Result;
+ }
+
+ // Pattern: (X86call:isVoid (texternalsym:i32):$dst)
+ // Emits: (CALLpcrel32:isVoid (texternalsym:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, X86::CALLpcrel32, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86call:isVoid (imm:i32):$dst)
+ // Emits: (CALLpcrel32:isVoid (imm:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->IsLegalToCallImmediateAddr(TM))) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_264(N, X86::CALLpcrel32, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86call:isVoid GR32:i32:$dst)
+ // Emits: (CALL32r:isVoid GR32:i32:$dst)
+ // Pattern complexity = 3 cost = 1 size = 3
+ {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_262(N, X86::CALL32r, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86call:isVoid GR64:i64:$dst)
+ // Emits: (CALL64r:isVoid GR64:i64:$dst)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((!Subtarget->isTargetWin64())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_262(N, X86::CALL64r, 1);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86call:isVoid GR64:i64:$dst)
+ // Emits: (WINCALL64r:isVoid GR64:i64:$dst)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->isTargetWin64())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_262(N, X86::WINCALL64r, 1);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ SDValue Ops0[] = { N0, N1, Tmp2, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+}
+SDNode *Select_X86ISD_CMOV_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_GR8, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ Chain1 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_268(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain0, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ Chain0 = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0, InFlag };
+ ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_267(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_267(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_267(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_267(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_267(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_267(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_267(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_267(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_267(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_267(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_267(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_267(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVL16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_268(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVG16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_268(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVLE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_268(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVNP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_268(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVNS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_268(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVNO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_268(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVAE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_268(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVB16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_268(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVNE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_268(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVA16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_268(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVBE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_268(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_268(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVAE16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVA16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_266(N, X86::CMOVL16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_266(N, X86::CMOVGE16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_266(N, X86::CMOVLE16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_266(N, X86::CMOVG16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_266(N, X86::CMOVS16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNS16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_266(N, X86::CMOVO16rr, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNO16rr, MVT::i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_267(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_267(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_267(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_267(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_267(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_267(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_267(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_267(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_267(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_267(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_267(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_267(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVL32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_268(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVG32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_268(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVLE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_268(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVNP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_268(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVNS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_268(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVNO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_268(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVAE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_268(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVB32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_268(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVNE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_268(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVA32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_268(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVBE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_268(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_268(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVAE32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVA32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_266(N, X86::CMOVL32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_266(N, X86::CMOVGE32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_266(N, X86::CMOVLE32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_266(N, X86::CMOVG32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_266(N, X86::CMOVS32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNS32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_266(N, X86::CMOVO32rr, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNO32rr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_267(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_267(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_267(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_267(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_267(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_267(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_267(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_267(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_267(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_267(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_267(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_267(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVAE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_268(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVB64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_268(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVNE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_268(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVA64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_268(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVBE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_268(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_268(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVL64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_268(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVG64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_268(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVLE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_268(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVNP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_268(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVNS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_268(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVNO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_268(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_268(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVAE64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVA64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_266(N, X86::CMOVL64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_266(N, X86::CMOVGE64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_266(N, X86::CMOVLE64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_266(N, X86::CMOVG64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_266(N, X86::CMOVS64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNS64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_266(N, X86::CMOVO64rr, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNO64rr, MVT::i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVNB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNB_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVNBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNBE_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE_Fp32, MVT::f32);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP_Fp32, MVT::f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmov:f32 FR32:f32:$t, FR32:f32:$f, (imm:i8):$cond, EFLAGS:i32)
+ // Emits: (CMOV_FR32:f32 FR32:f32:$t, FR32:f32:$f, (imm:i8):$cond)
+ // Pattern complexity = 6 cost = 11 size = 3
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_FR32, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVNB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNB_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVNBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNBE_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE_Fp64, MVT::f64);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP_Fp64, MVT::f64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmov:f64 FR64:f64:$t, FR64:f64:$f, (imm:i8):$cond, EFLAGS:i32)
+ // Emits: (CMOV_FR64:f64 FR64:f64:$t, FR64:f64:$f, (imm:i8):$cond)
+ // Pattern complexity = 6 cost = 11 size = 3
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_FR64, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVNB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNB_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVNBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNBE_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE_Fp80, MVT::f80);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
+ // Pattern complexity = 8 cost = 1 size = 0
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP_Fp80, MVT::f80);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_v1i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_V1I64, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_v2i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_V2I64, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_v4f32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_V4F32, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMOV_v2f64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_265(N, X86::CMOV_V2F64, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_269(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, N01);
+}
+DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue Chain01 = N01.getOperand(0);
+ SDValue N011 = N01.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N01)->getMemOperand();
+ SDValue Ops0[] = { N00, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4, Chain01 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N01.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, N1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_279(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Chain0 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_283(const SDValue &N, unsigned Opc0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, N0);
+}
+DISABLE_INLINE SDNode *Emit_284(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { N01, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_CMP(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode())) {
+ if (Predicate_load(N00.getNode())) {
+
+ // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), 0:i64)
+ // Emits: (TEST64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if (Predicate_loadi64(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_282(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), 0:i8)
+ // Emits: (TEST8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_loadi8(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_274(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), 0:i16)
+ // Emits: (TEST16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_loadi16(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_275(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), 0:i32)
+ // Emits: (TEST32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_276(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::LOAD &&
+ N01.hasOneUse() &&
+ IsLegalAndProfitableToFold(N01.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain01 = N01.getOperand(0);
+ if (Predicate_unindexedload(N01.getNode())) {
+
+ // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), 0:i8)
+ // Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_load(N01.getNode()) &&
+ Predicate_loadi8(N01.getNode())) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_270(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), 0:i16)
+ // Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_loadi16(N01.getNode())) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_270(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), 0:i32)
+ // Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_loadi32(N01.getNode())) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_270(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), 0:i64)
+ // Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_load(N01.getNode()) &&
+ Predicate_loadi64(N01.getNode())) {
+ SDValue N011 = N01.getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_270(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode())) {
+
+ // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1), 0:i8)
+ // Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_load(N00.getNode()) &&
+ Predicate_loadi8(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_284(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1), 0:i16)
+ // Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_loadi16(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_284(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1), 0:i32)
+ // Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_284(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1), 0:i64)
+ // Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_load(N00.getNode()) &&
+ Predicate_loadi64(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_284(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
+
+ // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (CMP16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_258(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (CMP32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_259(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ if (Predicate_load(N0.getNode())) {
+ if (Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (CMP64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_261(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (CMP64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_261(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2)
+ // Emits: (CMP8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_280(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
+ // Emits: (CMP16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_258(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
+ // Emits: (CMP32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_259(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2)
+ // Emits: (CMP8mr:isVoid addr:iPTR:$src1, GR8:i8:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_277(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2)
+ // Emits: (CMP16mr:isVoid addr:iPTR:$src1, GR16:i16:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_277(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2)
+ // Emits: (CMP32mr:isVoid addr:iPTR:$src1, GR32:i32:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_277(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (X86cmp:isVoid GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (CMP8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_278(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (CMP16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_278(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (CMP32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_278(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2)
+ // Emits: (CMP64mr:isVoid addr:iPTR:$src1, GR64:i64:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_277(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (CMP64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_278(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (UCOMISSrm:isVoid FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_278(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (UCOMISDrm:isVoid FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_278(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::AND) {
+ if (Predicate_and_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+
+ // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (imm:i8):$src2)<<P:Predicate_and_su>>, 0:i8)
+ // Emits: (TEST8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_271(N, X86::TEST8ri);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, (imm:i16):$src2)<<P:Predicate_and_su>>, 0:i16)
+ // Emits: (TEST16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_272(N, X86::TEST16ri);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, (imm:i32):$src2)<<P:Predicate_and_su>>, 0:i32)
+ // Emits: (TEST32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_273(N, X86::TEST32ri);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), 0:i64)
+ // Emits: (TEST64ri32:isVoid GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 15 cost = 1 size = 3
+ {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ if (N01.getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N01.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_281(N, X86::TEST64ri32);
+ return Result;
+ }
+ }
+ }
+ }
+ if (Predicate_and_su(N0.getNode())) {
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+
+ // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, GR8:i8:$src2)<<P:Predicate_and_su>>, 0:i8)
+ // Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 12 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_269(N, X86::TEST8rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, GR16:i16:$src2)<<P:Predicate_and_su>>, 0:i16)
+ // Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 12 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_269(N, X86::TEST16rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, GR32:i32:$src2)<<P:Predicate_and_su>>, 0:i32)
+ // Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 12 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_269(N, X86::TEST32rr);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, GR64:i64:$src2), 0:i64)
+ // Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 11 cost = 1 size = 3
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
+ SDValue N1 = N.getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_269(N, X86::TEST64rr);
+ return Result;
+ }
+ }
+ }
+ SDValue N1 = N.getOperand(1);
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+
+ // Pattern: (X86cmp:isVoid GR64:i64:$src1, 0:i64)
+ // Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_283(N, X86::TEST64rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR8:i8:$src1, 0:i8)
+ // Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_283(N, X86::TEST8rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR16:i16:$src1, 0:i16)
+ // Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_283(N, X86::TEST16rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR32:i32:$src1, 0:i32)
+ // Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_283(N, X86::TEST32rr);
+ return Result;
+ }
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86cmp:isVoid GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (CMP16ri8:isVoid GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_256(N, X86::CMP16ri8);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (CMP32ri8:isVoid GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_257(N, X86::CMP32ri8);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (CMP64ri8:isVoid GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_260(N, X86::CMP64ri8);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (CMP64ri32:isVoid GR64:i64:$src1, (imm:i64):$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_260(N, X86::CMP64ri32);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (CMP8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_279(N, X86::CMP8ri);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (CMP16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_256(N, X86::CMP16ri);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (CMP32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_257(N, X86::CMP32ri);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid RFP32:f32:$lhs, RFP32:f32:$rhs)
+ // Emits: (UCOM_FpIr32:isVoid RFP32:f32:$lhs, RFP32:f32:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_255(N, X86::UCOM_FpIr32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid RFP64:f64:$lhs, RFP64:f64:$rhs)
+ // Emits: (UCOM_FpIr64:isVoid RFP64:f64:$lhs, RFP64:f64:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_255(N, X86::UCOM_FpIr64);
+ return Result;
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86cmp:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
+ // Emits: (UCOM_FpIr80:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if (N0.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_255(N, X86::UCOM_FpIr80);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (CMP8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_255(N, X86::CMP8rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (CMP16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_255(N, X86::CMP16rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (CMP32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_255(N, X86::CMP32rr);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (CMP64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_255(N, X86::CMP64rr);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (UCOMISSrr:isVoid FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_255(N, X86::UCOMISSrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (UCOMISDrr:isVoid FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_255(N, X86::UCOMISDrr);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_285(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_286(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain1 = N1.getOperand(0);
+ SDValue N11 = N1.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp2, Chain1 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_CMPPD_v2i64(const SDValue &N) {
+
+ // Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Emits: (CMPPDrmi:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_286(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i8):$cc)
+ // Emits: (CMPPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_285(N, X86::CMPPDrri, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_CMPPS_v4i32(const SDValue &N) {
+
+ // Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Emits: (CMPPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_286(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i8):$cc)
+ // Emits: (CMPPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_285(N, X86::CMPPSrri, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_COMI(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86comi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_COMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_278(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86comi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_COMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_278(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86comi:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (Int_COMISSrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_255(N, X86::Int_COMISSrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86comi:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (Int_COMISDrr:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_255(N, X86::Int_COMISDrr);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_DEC_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_253(N, X86::DEC8r, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_DEC_i16(const SDValue &N) {
+
+ // Pattern: (X86dec_flag:i16 GR16:i16:$src)
+ // Emits: (DEC16r:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 1
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_253(N, X86::DEC16r, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86dec_flag:i16 GR16:i16:$src)
+ // Emits: (DEC64_16r:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 2
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_253(N, X86::DEC64_16r, MVT::i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
+
+ // Pattern: (X86dec_flag:i32 GR32:i32:$src)
+ // Emits: (DEC32r:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 1
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_253(N, X86::DEC32r, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86dec_flag:i32 GR32:i32:$src)
+ // Emits: (DEC64_32r:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 2
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_253(N, X86::DEC64_32r, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_DEC_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_253(N, X86::DEC64r, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_EH_RETURN(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86ehret:isVoid GR32:i32:$addr)
+ // Emits: (EH_RETURN:isVoid GR32:i32:$addr)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_81(N, X86::EH_RETURN);
+ return Result;
+ }
+
+ // Pattern: (X86ehret:isVoid GR64:i64:$addr)
+ // Emits: (EH_RETURN64:isVoid GR64:i64:$addr)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_81(N, X86::EH_RETURN64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FAND_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86fand:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsANDPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fand:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
+ // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsANDPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fand:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (FsANDPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::FsANDPSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FAND_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86fand:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsANDPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fand:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
+ // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsANDPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fand:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (FsANDPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::FsANDPDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_287(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+}
+SDNode *Select_X86ISD_FILD_f32(const SDValue &N) {
+ if ((!Subtarget->hasSSE1())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86fild:f32 addr:iPTR:$src, i16:Other)
+ // Emits: (ILD_Fp16m32:f32 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86fild:f32 addr:iPTR:$src, i32:Other)
+ // Emits: (ILD_Fp32m32:f32 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86fild:f32 addr:iPTR:$src, i64:Other)
+ // Emits: (ILD_Fp64m32:f32 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FILD_f64(const SDValue &N) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86fild:f64 addr:iPTR:$src, i16:Other)
+ // Emits: (ILD_Fp16m64:f64 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86fild:f64 addr:iPTR:$src, i32:Other)
+ // Emits: (ILD_Fp32m64:f64 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86fild:f64 addr:iPTR:$src, i64:Other)
+ // Emits: (ILD_Fp64m64:f64 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86fild:f80 addr:iPTR:$src, i16:Other)
+ // Emits: (ILD_Fp16m80:f80 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86fild:f80 addr:iPTR:$src, i32:Other)
+ // Emits: (ILD_Fp32m80:f80 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86fild:f80 addr:iPTR:$src, i64:Other)
+ // Emits: (ILD_Fp64m80:f80 addr:iPTR:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
+ SDNode *Result = Emit_287(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_288(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 6);
+ Chain = SDValue(ResNode, 1);
+ SDValue InFlag(ResNode, 2);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 2),
+ SDValue(N.getNode(), 1)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_FILD_FLAG_f64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
+ SDNode *Result = Emit_288(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FLD_f32(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (cast<VTSDNode>(N2)->getVT() == MVT::f32) {
+ SDNode *Result = Emit_287(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FLD_f64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (cast<VTSDNode>(N2)->getVT() == MVT::f64) {
+ SDNode *Result = Emit_287(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FLD_f80(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (cast<VTSDNode>(N2)->getVT() == MVT::f80) {
+ SDNode *Result = Emit_287(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMAX_f32(const SDValue &N) {
+
+ // Pattern: (X86fmax:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MAXSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmax:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (MAXSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MAXSSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMAX_f64(const SDValue &N) {
+
+ // Pattern: (X86fmax:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MAXSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmax:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (MAXSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MAXSDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMAX_v4f32(const SDValue &N) {
+
+ // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MAXPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MAXPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMAX_v2f64(const SDValue &N) {
+
+ // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MAXPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MAXPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMIN_f32(const SDValue &N) {
+
+ // Pattern: (X86fmin:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MINSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmin:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (MINSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MINSSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMIN_f64(const SDValue &N) {
+
+ // Pattern: (X86fmin:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MINSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmin:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (MINSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MINSDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMIN_v4f32(const SDValue &N) {
+
+ // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MINPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::MINPSrr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FMIN_v2f64(const SDValue &N) {
+
+ // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MINPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::MINPDrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_289(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+}
+SDNode *Select_X86ISD_FNSTCW16m(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_289(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FOR_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86for:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86for:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
+ // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86for:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (FsORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::FsORPSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FOR_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86for:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86for:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
+ // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86for:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (FsORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::FsORPDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_290(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+}
+SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
+ if ((Subtarget->hasSSE3())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (X86fp_to_i16mem:isVoid RFP32:f32:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp16m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i16mem:isVoid RFP64:f64:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp16m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i16mem:isVoid RFP80:f80:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp16m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (X86fp_to_i16mem:isVoid RFP32:f32:$src, addr:iPTR:$dst)
+ // Emits: (FP32_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i16mem:isVoid RFP64:f64:$src, addr:iPTR:$dst)
+ // Emits: (FP64_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_290(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i16mem:isVoid RFP80:f80:$src, addr:iPTR:$dst)
+ // Emits: (FP80_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_290(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
+ if ((Subtarget->hasSSE3())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (X86fp_to_i32mem:isVoid RFP32:f32:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp32m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i32mem:isVoid RFP64:f64:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp32m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i32mem:isVoid RFP80:f80:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp32m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (X86fp_to_i32mem:isVoid RFP32:f32:$src, addr:iPTR:$dst)
+ // Emits: (FP32_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i32mem:isVoid RFP64:f64:$src, addr:iPTR:$dst)
+ // Emits: (FP64_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_290(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i32mem:isVoid RFP80:f80:$src, addr:iPTR:$dst)
+ // Emits: (FP80_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_290(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
+ if ((Subtarget->hasSSE3())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (X86fp_to_i64mem:isVoid RFP32:f32:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp64m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i64mem:isVoid RFP64:f64:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp64m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i64mem:isVoid RFP80:f80:$src, addr:iPTR:$op)
+ // Emits: (ISTT_Fp64m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_290(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+ }
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+
+ // Pattern: (X86fp_to_i64mem:isVoid RFP32:f32:$src, addr:iPTR:$dst)
+ // Emits: (FP32_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_290(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i64mem:isVoid RFP64:f64:$src, addr:iPTR:$dst)
+ // Emits: (FP64_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_290(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fp_to_i64mem:isVoid RFP80:f80:$src, addr:iPTR:$dst)
+ // Emits: (FP80_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 11 size = 3
+ if (N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_290(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FRCP_f32(const SDValue &N) {
+
+ // Pattern: (X86frcp:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (RCPSSm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::RCPSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86frcp:f32 FR32:f32:$src)
+ // Emits: (RCPSSr:f32 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::RCPSSr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FRCP_v4f32(const SDValue &N) {
+
+ // Pattern: (X86frcp:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RCPPSm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86frcp:v4f32 VR128:v4f32:$src)
+ // Emits: (RCPPSr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::RCPPSr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FRSQRT_f32(const SDValue &N) {
+
+ // Pattern: (X86frsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (RSQRTSSm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::RSQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86frsqrt:f32 FR32:f32:$src)
+ // Emits: (RSQRTSSr:f32 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::RSQRTSSr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FRSQRT_v4f32(const SDValue &N) {
+
+ // Pattern: (X86frsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RSQRTPSm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86frsqrt:v4f32 VR128:v4f32:$src)
+ // Emits: (RSQRTPSr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_71(N, X86::RSQRTPSr, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_BYTE_imm(Tmp1.getNode());
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+}
+SDNode *Select_X86ISD_FSRL_v2f64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N1.getNode()) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_291(N, X86::PSRLDQri, MVT::v2f64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_292(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag = N.getOperand(4);
+ SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain, InFlag };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+}
+SDNode *Select_X86ISD_FST(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
+ SDValue N3 = N.getOperand(3);
+ if (cast<VTSDNode>(N3)->getVT() == MVT::f32) {
+
+ // Pattern: (X86fst:isVoid RFP32:f32:$src, addr:iPTR:$op, f32:Other)
+ // Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_292(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fst:isVoid RFP64:f64:$src, addr:iPTR:$op, f32:Other)
+ // Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_292(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86fst:isVoid RFP64:f64:$src, addr:iPTR:$op, f64:Other)
+ // Emits: (ST_Fp64m:isVoid addr:iPTR:$op, RFP64:f64:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N3)->getVT() == MVT::f64 &&
+ N1.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_292(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f32:Other)
+ // Emits: (ST_Fp80m32:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N3)->getVT() == MVT::f32 &&
+ N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_292(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f64:Other)
+ // Emits: (ST_Fp80m64:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N3)->getVT() == MVT::f64 &&
+ N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_292(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+
+ // Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f80:Other)
+ // Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
+ // Pattern complexity = 21 cost = 1 size = 0
+ if (cast<VTSDNode>(N3)->getVT() == MVT::f80 &&
+ N1.getValueType() == MVT::f80) {
+ SDNode *Result = Emit_292(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FXOR_f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86fxor:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsXORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fxor:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
+ // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsXORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fxor:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (FsXORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_15(N, X86::FsXORPSrr, MVT::f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_FXOR_f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86fxor:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsXORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fxor:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
+ // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsXORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86fxor:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (FsXORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDNode *Result = Emit_15(N, X86::FsXORPDrr, MVT::f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_INC_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_253(N, X86::INC8r, MVT::i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_INC_i16(const SDValue &N) {
+
+ // Pattern: (X86inc_flag:i16 GR16:i16:$src)
+ // Emits: (INC16r:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 1
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_253(N, X86::INC16r, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86inc_flag:i16 GR16:i16:$src)
+ // Emits: (INC64_16r:i16 GR16:i16:$src)
+ // Pattern complexity = 3 cost = 1 size = 2
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_253(N, X86::INC64_16r, MVT::i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
+
+ // Pattern: (X86inc_flag:i32 GR32:i32:$src)
+ // Emits: (INC32r:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 1
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_253(N, X86::INC32r, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86inc_flag:i32 GR32:i32:$src)
+ // Emits: (INC64_32r:i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 2
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_253(N, X86::INC64_32r, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_INC_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_253(N, X86::INC64r, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_293(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp2, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
+
+ // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>), (imm:iPTR):$src3)
+ // Emits: (INSERTPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 31 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadf32(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_293(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:iPTR):$src3)
+ // Emits: (INSERTPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_97(N, X86::INSERTPSrr, MVT::v4f32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_294(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 7);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_LCMPXCHG8_DAG(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_294(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_295(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SDValue InFlag = N.getOperand(4);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR32:i32:$swap, 4:i8)
+ // Emits: (LCMPXCHG32:isVoid addr:iPTR:$ptr, GR32:i32:$swap)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(4) &&
+ N2.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_295(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR16:i16:$swap, 2:i8)
+ // Emits: (LCMPXCHG16:isVoid addr:iPTR:$ptr, GR16:i16:$swap)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(2) &&
+ N2.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_295(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR8:i8:$swap, 1:i8)
+ // Emits: (LCMPXCHG8:isVoid addr:iPTR:$ptr, GR8:i8:$swap)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(1) &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_295(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR64:i64:$swap, 8:i8)
+ // Emits: (LCMPXCHG64:isVoid addr:iPTR:$ptr, GR64:i64:$swap)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(8) &&
+ N2.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_295(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_MUL_IMM_i32(const SDValue &N) {
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ // Pattern: lea32addr:i32:$src
+ // Emits: (LEA32r:i32 lea32addr:i32:$src)
+ // Pattern complexity = 15 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_MUL_IMM_i64(const SDValue &N) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_OR_i8(const SDValue &N) {
+
+ // Pattern: (X86or_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86or_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86or_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (OR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_OR_i16(const SDValue &N) {
+
+ // Pattern: (X86or_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86or_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (OR16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::OR16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86or_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (OR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::OR16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86or_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (OR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_OR_i32(const SDValue &N) {
+
+ // Pattern: (X86or_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86or_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (OR32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::OR32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86or_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (OR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::OR32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86or_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (OR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_OR_i64(const SDValue &N) {
+
+ // Pattern: (X86or_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86or_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (OR64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::OR64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86or_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (OR64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::OR64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86or_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (OR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::OR64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQB_v8i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqb:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqb:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQB_v16i8(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqb:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v16i8:$src1)
+ // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqb:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPEQBrr, MVT::v16i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQD_v2i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqd:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
+ // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqd:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PCMPEQDrr:v2i32 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQD_v4i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPEQDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqd:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
+ // Emits: (PCMPEQDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqd:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PCMPEQDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPEQDrr, MVT::v4i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQQ_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPEQQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqq:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PCMPEQQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqq:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PCMPEQQrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPEQQrr, MVT::v2i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQW_v4i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqw:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqw:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PCMPEQWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPEQW_v8i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86pcmpeqw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPEQWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqw:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v8i16:$src1)
+ // Emits: (PCMPEQWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpeqw:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PCMPEQWrr:v8i16 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPEQWrr, MVT::v8i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTB_v8i8(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtb:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTB_v16i8(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtb:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPGTBrr, MVT::v16i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTD_v2i32(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtd:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PCMPGTDrr:v2i32 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTD_v4i32(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPGTDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtd:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PCMPGTDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPGTDrr, MVT::v4i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTQ_v2i64(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPGTQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtq:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PCMPGTQrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPGTQrr, MVT::v2i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTW_v4i16(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtw:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PCMPGTWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PCMPGTW_v8i16(const SDValue &N) {
+
+ // Pattern: (X86pcmpgtw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PCMPGTWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pcmpgtw:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PCMPGTWrr:v8i16 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::PCMPGTWrr, MVT::v8i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_PEXTRB_i32(const SDValue &N) {
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_93(N, X86::PEXTRBrr, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_296(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+}
+SDNode *Select_X86ISD_PEXTRW_i32(const SDValue &N) {
+
+ // Pattern: (X86pextrw:i32 VR128:v8i16:$src1, (imm:iPTR):$src2)
+ // Emits: (PEXTRWri:i32 VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_93(N, X86::PEXTRWri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (MMX_X86pextrw:i32 VR64:v4i16:$src1, (imm:iPTR):$src2)
+ // Emits: (MMX_PEXTRWri:i32 VR64:v4i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16 &&
+ N1.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_296(N, X86::MMX_PEXTRWri, MVT::i32);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
+
+ // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:iPTR):$src3)
+ // Emits: (PINSRBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_extload(N1.getNode()) &&
+ Predicate_extloadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRBrr:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_97(N, X86::PINSRBrr, MVT::v16i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N10 = N1.getOperand(0);
+ SDValue Chain10 = N10.getOperand(0);
+ SDValue N101 = N10.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp2, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_PINSRW_v4i16(const SDValue &N) {
+
+ // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, (anyext:i32 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), (imm:iPTR):$src3)
+ // Emits: (MMX_PINSRWrmi:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2, (imm:i16):$src3)
+ // Pattern complexity = 31 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::ANY_EXTEND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i16 &&
+ N2.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_298(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (MMX_PINSRWrri:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:i16):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4i16 &&
+ N1.getValueType() == MVT::i32 &&
+ N2.getValueType() == TLI.getPointerTy()) {
+ SDNode *Result = Emit_297(N, X86::MMX_PINSRWrri, MVT::v4i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_PINSRW_v8i16(const SDValue &N) {
+
+ // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:iPTR):$src3)
+ // Emits: (PINSRWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_extload(N1.getNode()) &&
+ Predicate_extloadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRWrmi, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRWrri:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_97(N, X86::PINSRWrri, MVT::v8i16);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_PSHUFB_v16i8(const SDValue &N) {
+
+ // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$mask)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src, addr:iPTR:$mask)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSSE3())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getOperand(0);
+ if (N10.getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
+ SDValue Chain10 = N10.getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
+ // Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDNode *Result = Emit_15(N, X86::PSHUFBrr128, MVT::v16i8);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_PTEST(const SDValue &N) {
+
+ // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (PTESTrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None &&
+ (Subtarget->hasSSE41())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_278(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (PTESTrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDNode *Result = Emit_255(N, X86::PTESTrr);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain);
+ Chain = SDValue(ResNode, 0);
+ SDValue InFlag(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_RDTSC_DAG(const SDValue &N) {
+ SDNode *Result = Emit_299(N, X86::RDTSC);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_300(const SDValue &N, unsigned Opc0) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue InFlag = N.getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86rep_movs:isVoid i8:Other)
+ // Emits: (REP_MOVSB:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_300(N, X86::REP_MOVSB);
+ return Result;
+ }
+
+ // Pattern: (X86rep_movs:isVoid i16:Other)
+ // Emits: (REP_MOVSW:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_300(N, X86::REP_MOVSW);
+ return Result;
+ }
+
+ // Pattern: (X86rep_movs:isVoid i32:Other)
+ // Emits: (REP_MOVSD:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_300(N, X86::REP_MOVSD);
+ return Result;
+ }
+
+ // Pattern: (X86rep_movs:isVoid i64:Other)
+ // Emits: (REP_MOVSQ:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i64) {
+ SDNode *Result = Emit_300(N, X86::REP_MOVSQ);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86rep_stos:isVoid i8:Other)
+ // Emits: (REP_STOSB:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ SDNode *Result = Emit_300(N, X86::REP_STOSB);
+ return Result;
+ }
+
+ // Pattern: (X86rep_stos:isVoid i16:Other)
+ // Emits: (REP_STOSW:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ SDNode *Result = Emit_300(N, X86::REP_STOSW);
+ return Result;
+ }
+
+ // Pattern: (X86rep_stos:isVoid i32:Other)
+ // Emits: (REP_STOSD:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
+ SDNode *Result = Emit_300(N, X86::REP_STOSD);
+ return Result;
+ }
+
+ // Pattern: (X86rep_stos:isVoid i64:Other)
+ // Emits: (REP_STOSQ:isVoid)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (cast<VTSDNode>(N1)->getVT() == MVT::i64) {
+ SDNode *Result = Emit_300(N, X86::REP_STOSQ);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86retflag:isVoid 0:i16)
+ // Emits: (RET:isVoid)
+ // Pattern complexity = 8 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_301(N, X86::RET, 1);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86retflag:isVoid (timm:i16):$amt)
+ // Emits: (RETI:isVoid (timm:i16):$amt)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_302(N, X86::RETI, 1);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N1, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, InFlag);
+}
+SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86setcc:i8 4:i8, EFLAGS:i32)
+ // Emits: (SETEr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_303(N, X86::SETEr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 9:i8, EFLAGS:i32)
+ // Emits: (SETNEr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_303(N, X86::SETNEr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 7:i8, EFLAGS:i32)
+ // Emits: (SETLr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_303(N, X86::SETLr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 6:i8, EFLAGS:i32)
+ // Emits: (SETGEr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_303(N, X86::SETGEr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 8:i8, EFLAGS:i32)
+ // Emits: (SETLEr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_303(N, X86::SETLEr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 5:i8, EFLAGS:i32)
+ // Emits: (SETGr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_303(N, X86::SETGr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 2:i8, EFLAGS:i32)
+ // Emits: (SETBr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_303(N, X86::SETBr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 1:i8, EFLAGS:i32)
+ // Emits: (SETAEr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_303(N, X86::SETAEr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 3:i8, EFLAGS:i32)
+ // Emits: (SETBEr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_303(N, X86::SETBEr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 0:i8, EFLAGS:i32)
+ // Emits: (SETAr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_303(N, X86::SETAr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 15:i8, EFLAGS:i32)
+ // Emits: (SETSr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_303(N, X86::SETSr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 12:i8, EFLAGS:i32)
+ // Emits: (SETNSr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_303(N, X86::SETNSr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 14:i8, EFLAGS:i32)
+ // Emits: (SETPr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_303(N, X86::SETPr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 11:i8, EFLAGS:i32)
+ // Emits: (SETNPr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_303(N, X86::SETNPr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 13:i8, EFLAGS:i32)
+ // Emits: (SETOr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_303(N, X86::SETOr, MVT::i8);
+ return Result;
+ }
+
+ // Pattern: (X86setcc:i8 10:i8, EFLAGS:i32)
+ // Emits: (SETNOr:i8)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_303(N, X86::SETNOr, MVT::i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SETCC_CARRY_i8(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_303(N, X86::SETB_C8r, MVT::i8);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_304(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue Chain = CurDAG->getEntryNode();
+ SDValue InFlag(0, 0);
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::CL, N2, InFlag).getNode();
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, InFlag);
+}
+SDNode *Select_X86ISD_SHLD_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86shld:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
+ // Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N2.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_285(N, X86::SHLD16rri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86shld:i16 GR16:i16:$src1, GR16:i16:$src2, CL:i8)
+ // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_304(N, X86::SHLD16rrCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SHLD_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86shld:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
+ // Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N2.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_285(N, X86::SHLD32rri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86shld:i32 GR32:i32:$src1, GR32:i32:$src2, CL:i8)
+ // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_304(N, X86::SHLD32rrCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SHLD_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86shld:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
+ // Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N2.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_285(N, X86::SHLD64rri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86shld:i64 GR64:i64:$src1, GR64:i64:$src2, CL:i8)
+ // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_304(N, X86::SHLD64rrCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SHRD_i16(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86shrd:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
+ // Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N2.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_285(N, X86::SHRD16rri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86shrd:i16 GR16:i16:$src1, GR16:i16:$src2, CL:i8)
+ // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_304(N, X86::SHRD16rrCL, MVT::i16);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SHRD_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86shrd:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
+ // Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N2.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_285(N, X86::SHRD32rri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86shrd:i32 GR32:i32:$src1, GR32:i32:$src2, CL:i8)
+ // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_304(N, X86::SHRD32rrCL, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+
+ // Pattern: (X86shrd:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
+ // Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N2.getOpcode() == ISD::Constant &&
+ N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_285(N, X86::SHRD64rri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86shrd:i64 GR64:i64:$src1, GR64:i64:$src2, CL:i8)
+ // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if (N2.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_304(N, X86::SHRD64rrCL, MVT::i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_305(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, N0);
+}
+SDNode *Select_X86ISD_SMUL_i16(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_144(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
+ // Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ SDNode *Result = Emit_144(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86smul_flag:i16 GR16:i16:$src1, 2:i16)
+ // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src1)
+ // Pattern complexity = 10 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_305(N, X86::ADD16rr, MVT::i16);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86smul_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (IMUL16rri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::IMUL16rri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86smul_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (IMUL16rri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::IMUL16rri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86smul_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (IMUL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::IMUL16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_SMUL_i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_145(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
+ // Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ SDNode *Result = Emit_145(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86smul_flag:i32 GR32:i32:$src1, 2:i32)
+ // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src1)
+ // Pattern complexity = 10 cost = 1 size = 3
+ {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_305(N, X86::ADD32rr, MVT::i32);
+ return Result;
+ }
+ }
+ }
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86smul_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (IMUL32rri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::IMUL32rri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86smul_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (IMUL32rri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::IMUL32rri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86smul_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (IMUL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::IMUL32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_146(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_146(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86smul_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (IMUL64rri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::IMUL64rri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86smul_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (IMUL64rri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::IMUL64rri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (IMUL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::IMUL64rr, MVT::i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_SUB_i8(const SDValue &N) {
+
+ // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86sub_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (SUB8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_SUB_i16(const SDValue &N) {
+
+ // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (SUB16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::SUB16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (SUB16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::SUB16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86sub_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (SUB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_SUB_i32(const SDValue &N) {
+
+ // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::SUB32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (SUB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::SUB32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86sub_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (SUB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_SUB_i64(const SDValue &N) {
+
+ // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::SUB64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (SUB64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::SUB64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86sub_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (SUB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::SUB64rr, MVT::i64);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_306(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ Ops0.push_back(N1);
+ Ops0.push_back(Tmp1);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ if (HasInFlag)
+ Ops0.push_back(InFlag);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+
+ // Pattern: (X86tcret:isVoid (tglobaladdr:i64):$dst, (imm:i32):$off)
+ // Emits: (TCRETURNdi64:isVoid (tglobaladdr:i64):$dst, (imm:i32):$off)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86tcret:isVoid (texternalsym:i64):$dst, (imm:i32):$off)
+ // Emits: (TCRETURNdi64:isVoid (texternalsym:i64):$dst, (imm:i32):$off)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86tcret:isVoid (tglobaladdr:i32):$dst, (imm:i32):$off)
+ // Emits: (TCRETURNdi:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86tcret:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
+ // Emits: (TCRETURNdi:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
+ // Pattern complexity = 9 cost = 1 size = 3
+ if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
+ return Result;
+ }
+ }
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86tcret:isVoid GR64:i64:$dst, (imm:i32):$off)
+ // Emits: (TCRETURNri64:isVoid GR64:i64:$dst, (imm:i32):$off)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_306(N, X86::TCRETURNri64, 2);
+ return Result;
+ }
+
+ // Pattern: (X86tcret:isVoid GR32:i32:$dst, (imm:i32):$off)
+ // Emits: (TCRETURNri:isVoid GR32:i32:$dst, (imm:i32):$off)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_306(N, X86::TCRETURNri, 2);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_307(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+ SDValue InFlag(0, 0);
+ if (HasInFlag) {
+ InFlag = N.getOperand(N.getNumOperands()-1);
+ }
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, Chain, InFlag };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
+ Chain = SDValue(ResNode, 0);
+ InFlag = SDValue(ResNode, 1);
+ const SDValue Froms[] = {
+ SDValue(N.getNode(), 1),
+ SDValue(N.getNode(), 0)
+ };
+ const SDValue Tos[] = {
+ InFlag,
+ SDValue(Chain.getNode(), Chain.getResNo())
+ };
+ ReplaceUses(Froms, Tos, 2);
+ return ResNode;
+}
+SDNode *Select_X86ISD_TLSADDR(const SDValue &N) {
+
+ // Pattern: (X86tlsaddr:isVoid tls32addr:i32:$sym)
+ // Emits: (TLS_addr32:isVoid tls32addr:i32:$sym)
+ // Pattern complexity = 18 cost = 1 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_307(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86tlsaddr:isVoid tls64addr:i64:$sym)
+ // Emits: (TLS_addr64:isVoid tls64addr:i64:$sym)
+ // Pattern complexity = 18 cost = 1 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_307(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_UCOMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_278(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86ucomi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_UCOMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_278(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (Int_UCOMISSrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_255(N, X86::Int_UCOMISSrr);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86ucomi:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (Int_UCOMISDrr:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_255(N, X86::Int_UCOMISDrr);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_308(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue N3 = N.getOperand(3);
+ SmallVector<SDValue, 8> Ops0;
+ SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i64);
+ SDValue Tmp2 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i64);
+ Ops0.push_back(N1);
+ Ops0.push_back(Tmp1);
+ Ops0.push_back(Tmp2);
+ for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands(); i != e; ++i) {
+ Ops0.push_back(N.getOperand(i));
+ }
+ Ops0.push_back(Chain);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+}
+SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ if (N2.getOpcode() == ISD::Constant) {
+ SDValue N3 = N.getOperand(3);
+ if (N3.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_308(N, X86::VASTART_SAVE_XMM_REGS, 3);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VSHL_v1i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_93(N, X86::MMX_PSLLQri, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VSHL_v2i64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_291(N, X86::PSLLDQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VSRL_v1i64(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_93(N, X86::MMX_PSRLQri, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VSRL_v2i64(const SDValue &N) {
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_291(N, X86::PSRLDQri, MVT::v2i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_309(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
+ return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+}
+SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
+ SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Chain00 = N00.getOperand(0);
+ SDValue N001 = N00.getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_311(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, Tmp1);
+}
+SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
+ // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 GR32:i32:$src))
+ // Emits: (MMX_MOVZDI2PDIrr:v2i32 GR32:i32:$src)
+ // Pattern complexity = 21 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_160(N, X86::MMX_MOVZDI2PDIrr, MVT::v2i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2i32 VR64:v2i32:$src)
+ // Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, (MMX_V_SET0:v8i8))
+ // Pattern complexity = 18 cost = 2 size = 6
+ SDNode *Result = Emit_311(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
+ return Result;
+}
+
+DISABLE_INLINE SDNode *Emit_312(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0);
+}
+SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
+ // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+
+ // Pattern: (X86vzmovl:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+
+ // Pattern: (X86vzmovl:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 45 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 GR32:i32:$src))
+ // Emits: (MOVZDI2PDIrr:v4i32 GR32:i32:$src)
+ // Pattern complexity = 21 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_160(N, X86::MOVZDI2PDIrr, MVT::v4i32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v4i32 VR128:v4i32:$src)
+ // Emits: (MOVLPSrr:v4i32 (V_SET0:v16i8), VR128:v16i8:$src)
+ // Pattern complexity = 18 cost = 2 size = 6
+ if ((Subtarget->hasSSE1())) {
+ SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))
+ // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadi64(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+
+ // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+
+ // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_310(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 45 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 45 cost = 1 size = 3
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 GR64:i64:$src))
+ // Emits: (MOVZQI2PQIrr:v2i64 GR64:i64:$src)
+ // Pattern complexity = 21 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_160(N, X86::MOVZQI2PQIrr, MVT::v2i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2i64 VR128:v2i64:$src)
+ // Emits: (MOVZPQILo2PQIrr:v2i64 VR128:v2i64:$src)
+ // Pattern complexity = 18 cost = 1 size = 3
+ SDNode *Result = Emit_71(N, X86::MOVZPQILo2PQIrr, MVT::v2i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_313(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N00 = N0.getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N00);
+}
+SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>))
+ // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadf32(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_310(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE1())) {
+
+ // Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 FR32:f32:$src))
+ // Emits: (MOVLSS2PSrr:v4f32 (V_SET0:v16i8), FR32:f32:$src)
+ // Pattern complexity = 21 cost = 2 size = 6
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v4f32 VR128:v4f32:$src)
+ // Emits: (MOVLPSrr:v4f32 (V_SET0:v16i8), VR128:v16i8:$src)
+ // Pattern complexity = 18 cost = 2 size = 6
+ SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
+ if (OptLevel != CodeGenOpt::None) {
+
+ // Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))
+ // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadf64(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86vzmovl:v2f64 (bitconvert:v2f64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
+ SDValue Chain00 = N00.getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 45 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_77(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+
+ // Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 FR64:f64:$src))
+ // Emits: (MOVLSD2PDrr:v2f64 (V_SET0:v16i8), FR64:f64:$src)
+ // Pattern complexity = 21 cost = 2 size = 6
+ {
+ SDValue N0 = N.getOperand(0);
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getOperand(0);
+ if (N00.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86vzmovl:v2f64 VR128:v2f64:$src)
+ // Emits: (MOVZPQILo2PQIrr:v2f64 VR128:v16i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_71(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_Wrapper_i32(const SDValue &N) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86Wrapper:i32 (tconstpool:i32):$dst)
+ // Emits: (MOV32ri:i32 (tconstpool:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i32 (tjumptable:i32):$dst)
+ // Emits: (MOV32ri:i32 (tjumptable:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i32 (tglobaltlsaddr:i32):$dst)
+ // Emits: (MOV32ri:i32 (tglobaltlsaddr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetGlobalTLSAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i32 (tglobaladdr:i32):$dst)
+ // Emits: (MOV32ri:i32 (tglobaladdr:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i32 (texternalsym:i32):$dst)
+ // Emits: (MOV32ri:i32 (texternalsym:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i32 (tblockaddress:i32):$dst)
+ // Emits: (MOV32ri:i32 (tblockaddress:i32):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_Wrapper_i64(const SDValue &N) {
+ if ((TM.getCodeModel() != CodeModel::Small &&TM.getCodeModel() != CodeModel::Kernel)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
+ // Emits: (MOV64ri:i64 (tconstpool:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
+ // Emits: (MOV64ri:i64 (tjumptable:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
+ // Emits: (MOV64ri:i64 (tglobaladdr:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
+ // Emits: (MOV64ri:i64 (texternalsym:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
+ // Emits: (MOV64ri:i64 (tblockaddress:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ return Result;
+ }
+ }
+ if ((TM.getCodeModel() == CodeModel::Small)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
+ // Emits: (MOV64ri64i32:i64 (tconstpool:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
+ // Emits: (MOV64ri64i32:i64 (tjumptable:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
+ // Emits: (MOV64ri64i32:i64 (tglobaladdr:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
+ // Emits: (MOV64ri64i32:i64 (texternalsym:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
+ // Emits: (MOV64ri64i32:i64 (tblockaddress:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ return Result;
+ }
+ }
+ if ((TM.getCodeModel() == CodeModel::Kernel)) {
+ SDValue N0 = N.getOperand(0);
+
+ // Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
+ // Emits: (MOV64ri32:i64 (tconstpool:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
+ // Emits: (MOV64ri32:i64 (tjumptable:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
+ // Emits: (MOV64ri32:i64 (tglobaladdr:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
+ // Emits: (MOV64ri32:i64 (texternalsym:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
+ // Emits: (MOV64ri32:i64 (tblockaddress:i64):$dst)
+ // Pattern complexity = 6 cost = 1 size = 3
+ if (N0.getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ return Result;
+ }
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_WrapperRIP_i64(const SDValue &N) {
+ SDValue CPTmpN_0;
+ SDValue CPTmpN_1;
+ SDValue CPTmpN_2;
+ SDValue CPTmpN_3;
+ if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_X86ISD_XOR_i8(const SDValue &N) {
+
+ // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_3(N, X86::XOR8ri, MVT::i8);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86xor_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Emits: (XOR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR8rr, MVT::i8);
+ return Result;
+}
+
+SDNode *Select_X86ISD_XOR_i16(const SDValue &N) {
+
+ // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (XOR16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::XOR16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Emits: (XOR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::XOR16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86xor_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Emits: (XOR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR16rr, MVT::i16);
+ return Result;
+}
+
+SDNode *Select_X86ISD_XOR_i32(const SDValue &N) {
+
+ // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (XOR32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::XOR32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Emits: (XOR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::XOR32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86xor_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Emits: (XOR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR32rr, MVT::i32);
+ return Result;
+}
+
+SDNode *Select_X86ISD_XOR_i64(const SDValue &N) {
+
+ // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
+ SDValue Chain1 = N1.getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ {
+ SDValue N0 = N.getOperand(0);
+ SDValue N1 = N.getOperand(1);
+ if (N1.getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (XOR64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::XOR64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (XOR64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 7 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::XOR64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (X86xor_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Emits: (XOR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::XOR64rr, MVT::i64);
+ return Result;
+}
+
+// The main instruction selector code.
+SDNode *SelectCode(SDValue N) {
+ MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
+ switch (N.getOpcode()) {
+ default:
+ assert(!N.isMachineOpcode() && "Node already selected!");
+ break;
+ case ISD::EntryToken: // These nodes remain the same.
+ case ISD::BasicBlock:
+ case ISD::Register:
+ case ISD::HANDLENODE:
+ case ISD::TargetConstant:
+ case ISD::TargetConstantFP:
+ case ISD::TargetConstantPool:
+ case ISD::TargetFrameIndex:
+ case ISD::TargetExternalSymbol:
+ case ISD::TargetBlockAddress:
+ case ISD::TargetJumpTable:
+ case ISD::TargetGlobalTLSAddress:
+ case ISD::TargetGlobalAddress:
+ case ISD::TokenFactor:
+ case ISD::CopyFromReg:
+ case ISD::CopyToReg: {
+ return NULL;
+ }
+ case ISD::AssertSext:
+ case ISD::AssertZext: {
+ ReplaceUses(N, N.getOperand(0));
+ return NULL;
+ }
+ case ISD::INLINEASM: return Select_INLINEASM(N);
+ case ISD::EH_LABEL: return Select_EH_LABEL(N);
+ case ISD::UNDEF: return Select_UNDEF(N);
+ case ISD::ADD: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ADD_i8(N);
+ case MVT::i16:
+ return Select_ISD_ADD_i16(N);
+ case MVT::i32:
+ return Select_ISD_ADD_i32(N);
+ case MVT::i64:
+ return Select_ISD_ADD_i64(N);
+ case MVT::v8i8:
+ return Select_ISD_ADD_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_ADD_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_ADD_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_ADD_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_ADD_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_ADD_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_ADD_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_ADD_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ADDC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_ADDC_i32(N);
+ case MVT::i64:
+ return Select_ISD_ADDC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ADDE: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ADDE_i8(N);
+ case MVT::i16:
+ return Select_ISD_ADDE_i16(N);
+ case MVT::i32:
+ return Select_ISD_ADDE_i32(N);
+ case MVT::i64:
+ return Select_ISD_ADDE_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::AND: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_AND_i8(N);
+ case MVT::i16:
+ return Select_ISD_AND_i16(N);
+ case MVT::i32:
+ return Select_ISD_AND_i32(N);
+ case MVT::i64:
+ return Select_ISD_AND_i64(N);
+ case MVT::v1i64:
+ return Select_ISD_AND_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_AND_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ANY_EXTEND: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_ANY_EXTEND_i16(N);
+ case MVT::i32:
+ return Select_ISD_ANY_EXTEND_i32(N);
+ case MVT::i64:
+ return Select_ISD_ANY_EXTEND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_ADD: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ATOMIC_LOAD_ADD_i8(N);
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_ADD_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_ADD_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_ADD_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_AND: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ATOMIC_LOAD_AND_i8(N);
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_AND_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_AND_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_AND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_MAX: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_MAX_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_MAX_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_MAX_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_MIN: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_MIN_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_MIN_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_MIN_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_NAND: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ATOMIC_LOAD_NAND_i8(N);
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_NAND_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_NAND_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_NAND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_OR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ATOMIC_LOAD_OR_i8(N);
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_OR_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_OR_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_OR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_UMAX: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_UMAX_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_UMAX_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_UMAX_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_UMIN: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_UMIN_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_UMIN_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_UMIN_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_LOAD_XOR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ATOMIC_LOAD_XOR_i8(N);
+ case MVT::i16:
+ return Select_ISD_ATOMIC_LOAD_XOR_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_LOAD_XOR_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_LOAD_XOR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ATOMIC_SWAP: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ATOMIC_SWAP_i8(N);
+ case MVT::i16:
+ return Select_ISD_ATOMIC_SWAP_i16(N);
+ case MVT::i32:
+ return Select_ISD_ATOMIC_SWAP_i32(N);
+ case MVT::i64:
+ return Select_ISD_ATOMIC_SWAP_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BIT_CONVERT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_BIT_CONVERT_i32(N);
+ case MVT::i64:
+ return Select_ISD_BIT_CONVERT_i64(N);
+ case MVT::f32:
+ return Select_ISD_BIT_CONVERT_f32(N);
+ case MVT::f64:
+ return Select_ISD_BIT_CONVERT_f64(N);
+ case MVT::v8i8:
+ return Select_ISD_BIT_CONVERT_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_BIT_CONVERT_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_BIT_CONVERT_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_BIT_CONVERT_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_BIT_CONVERT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_BIT_CONVERT_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_BIT_CONVERT_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_BIT_CONVERT_v2i64(N);
+ case MVT::v2f32:
+ return Select_ISD_BIT_CONVERT_v2f32(N);
+ case MVT::v4f32:
+ return Select_ISD_BIT_CONVERT_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_BIT_CONVERT_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BR: {
+ return Select_ISD_BR(N);
+ break;
+ }
+ case ISD::BRIND: {
+ return Select_ISD_BRIND(N);
+ break;
+ }
+ case ISD::BSWAP: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_BSWAP_i32(N);
+ case MVT::i64:
+ return Select_ISD_BSWAP_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::BUILD_VECTOR: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_BUILD_VECTOR_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_BUILD_VECTOR_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_BUILD_VECTOR_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_BUILD_VECTOR_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_BUILD_VECTOR_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_BUILD_VECTOR_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_BUILD_VECTOR_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_BUILD_VECTOR_v2i64(N);
+ case MVT::v4f32:
+ return Select_ISD_BUILD_VECTOR_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_BUILD_VECTOR_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::CALLSEQ_END: {
+ return Select_ISD_CALLSEQ_END(N);
+ break;
+ }
+ case ISD::CALLSEQ_START: {
+ return Select_ISD_CALLSEQ_START(N);
+ break;
+ }
+ case ISD::Constant: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_Constant_i8(N);
+ case MVT::i16:
+ return Select_ISD_Constant_i16(N);
+ case MVT::i32:
+ return Select_ISD_Constant_i32(N);
+ case MVT::i64:
+ return Select_ISD_Constant_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ConstantFP: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_ConstantFP_f32(N);
+ case MVT::f64:
+ return Select_ISD_ConstantFP_f64(N);
+ case MVT::f80:
+ return Select_ISD_ConstantFP_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::EXTRACT_VECTOR_ELT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_EXTRACT_VECTOR_ELT_i32(N);
+ case MVT::i64:
+ return Select_ISD_EXTRACT_VECTOR_ELT_i64(N);
+ case MVT::f32:
+ return Select_ISD_EXTRACT_VECTOR_ELT_f32(N);
+ case MVT::f64:
+ return Select_ISD_EXTRACT_VECTOR_ELT_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FABS: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FABS_f32(N);
+ case MVT::f64:
+ return Select_ISD_FABS_f64(N);
+ case MVT::f80:
+ return Select_ISD_FABS_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FADD: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FADD_f32(N);
+ case MVT::f64:
+ return Select_ISD_FADD_f64(N);
+ case MVT::f80:
+ return Select_ISD_FADD_f80(N);
+ case MVT::v4f32:
+ return Select_ISD_FADD_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_FADD_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FCOS: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FCOS_f32(N);
+ case MVT::f64:
+ return Select_ISD_FCOS_f64(N);
+ case MVT::f80:
+ return Select_ISD_FCOS_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FDIV: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FDIV_f32(N);
+ case MVT::f64:
+ return Select_ISD_FDIV_f64(N);
+ case MVT::f80:
+ return Select_ISD_FDIV_f80(N);
+ case MVT::v4f32:
+ return Select_ISD_FDIV_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_FDIV_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FMUL: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FMUL_f32(N);
+ case MVT::f64:
+ return Select_ISD_FMUL_f64(N);
+ case MVT::f80:
+ return Select_ISD_FMUL_f80(N);
+ case MVT::v4f32:
+ return Select_ISD_FMUL_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_FMUL_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FNEG: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FNEG_f32(N);
+ case MVT::f64:
+ return Select_ISD_FNEG_f64(N);
+ case MVT::f80:
+ return Select_ISD_FNEG_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_EXTEND: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_ISD_FP_EXTEND_f64(N);
+ case MVT::f80:
+ return Select_ISD_FP_EXTEND_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_ROUND: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FP_ROUND_f32(N);
+ case MVT::f64:
+ return Select_ISD_FP_ROUND_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FP_TO_SINT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_FP_TO_SINT_i32(N);
+ case MVT::i64:
+ return Select_ISD_FP_TO_SINT_i64(N);
+ case MVT::v2i32:
+ return Select_ISD_FP_TO_SINT_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_FP_TO_SINT_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSIN: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSIN_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSIN_f64(N);
+ case MVT::f80:
+ return Select_ISD_FSIN_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSQRT: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSQRT_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSQRT_f64(N);
+ case MVT::f80:
+ return Select_ISD_FSQRT_f80(N);
+ case MVT::v4f32:
+ return Select_ISD_FSQRT_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_FSQRT_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FSUB: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_FSUB_f32(N);
+ case MVT::f64:
+ return Select_ISD_FSUB_f64(N);
+ case MVT::f80:
+ return Select_ISD_FSUB_f80(N);
+ case MVT::v4f32:
+ return Select_ISD_FSUB_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_FSUB_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::FrameIndex: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_FrameIndex_i32(N);
+ case MVT::i64:
+ return Select_ISD_FrameIndex_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INSERT_VECTOR_ELT: {
+ switch (NVT) {
+ case MVT::v4i32:
+ return Select_ISD_INSERT_VECTOR_ELT_v4i32(N);
+ case MVT::v2i64:
+ return Select_ISD_INSERT_VECTOR_ELT_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INTRINSIC_VOID: {
+ return Select_ISD_INTRINSIC_VOID(N);
+ break;
+ }
+ case ISD::INTRINSIC_WO_CHAIN: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_i32(N);
+ case MVT::i64:
+ return Select_ISD_INTRINSIC_WO_CHAIN_i64(N);
+ case MVT::v8i8:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v2i64(N);
+ case MVT::v4f32:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_INTRINSIC_WO_CHAIN_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::INTRINSIC_W_CHAIN: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_ISD_INTRINSIC_W_CHAIN_v16i8(N);
+ case MVT::v2i64:
+ return Select_ISD_INTRINSIC_W_CHAIN_v2i64(N);
+ case MVT::v4f32:
+ return Select_ISD_INTRINSIC_W_CHAIN_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_INTRINSIC_W_CHAIN_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::LOAD: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_LOAD_i8(N);
+ case MVT::i16:
+ return Select_ISD_LOAD_i16(N);
+ case MVT::i32:
+ return Select_ISD_LOAD_i32(N);
+ case MVT::i64:
+ return Select_ISD_LOAD_i64(N);
+ case MVT::f32:
+ return Select_ISD_LOAD_f32(N);
+ case MVT::f64:
+ return Select_ISD_LOAD_f64(N);
+ case MVT::f80:
+ return Select_ISD_LOAD_f80(N);
+ case MVT::v4i32:
+ return Select_ISD_LOAD_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_LOAD_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_LOAD_v2i64(N);
+ case MVT::v4f32:
+ return Select_ISD_LOAD_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_LOAD_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::MEMBARRIER: {
+ return Select_ISD_MEMBARRIER(N);
+ break;
+ }
+ case ISD::MUL: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_MUL_i8(N);
+ case MVT::i16:
+ return Select_ISD_MUL_i16(N);
+ case MVT::i32:
+ return Select_ISD_MUL_i32(N);
+ case MVT::i64:
+ return Select_ISD_MUL_i64(N);
+ case MVT::v16i8:
+ return Select_ISD_MUL_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_MUL_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_MUL_v8i16(N);
+ case MVT::v4i32:
+ return Select_ISD_MUL_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::OR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_OR_i8(N);
+ case MVT::i16:
+ return Select_ISD_OR_i16(N);
+ case MVT::i32:
+ return Select_ISD_OR_i32(N);
+ case MVT::i64:
+ return Select_ISD_OR_i64(N);
+ case MVT::v1i64:
+ return Select_ISD_OR_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_OR_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::PREFETCH: {
+ return Select_ISD_PREFETCH(N);
+ break;
+ }
+ case ISD::ROTL: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ROTL_i8(N);
+ case MVT::i16:
+ return Select_ISD_ROTL_i16(N);
+ case MVT::i32:
+ return Select_ISD_ROTL_i32(N);
+ case MVT::i64:
+ return Select_ISD_ROTL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ROTR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_ROTR_i8(N);
+ case MVT::i16:
+ return Select_ISD_ROTR_i16(N);
+ case MVT::i32:
+ return Select_ISD_ROTR_i32(N);
+ case MVT::i64:
+ return Select_ISD_ROTR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SCALAR_TO_VECTOR: {
+ switch (NVT) {
+ case MVT::v2i32:
+ return Select_ISD_SCALAR_TO_VECTOR_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_SCALAR_TO_VECTOR_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_SCALAR_TO_VECTOR_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_SCALAR_TO_VECTOR_v2i64(N);
+ case MVT::v4f32:
+ return Select_ISD_SCALAR_TO_VECTOR_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_SCALAR_TO_VECTOR_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SHL: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_SHL_i8(N);
+ case MVT::i16:
+ return Select_ISD_SHL_i16(N);
+ case MVT::i32:
+ return Select_ISD_SHL_i32(N);
+ case MVT::i64:
+ return Select_ISD_SHL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SIGN_EXTEND: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_SIGN_EXTEND_i16(N);
+ case MVT::i32:
+ return Select_ISD_SIGN_EXTEND_i32(N);
+ case MVT::i64:
+ return Select_ISD_SIGN_EXTEND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SIGN_EXTEND_INREG: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_SIGN_EXTEND_INREG_i16(N);
+ case MVT::i32:
+ return Select_ISD_SIGN_EXTEND_INREG_i32(N);
+ case MVT::i64:
+ return Select_ISD_SIGN_EXTEND_INREG_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SINT_TO_FP: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_ISD_SINT_TO_FP_f32(N);
+ case MVT::f64:
+ return Select_ISD_SINT_TO_FP_f64(N);
+ case MVT::v4f32:
+ return Select_ISD_SINT_TO_FP_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_SINT_TO_FP_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SRA: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_SRA_i8(N);
+ case MVT::i16:
+ return Select_ISD_SRA_i16(N);
+ case MVT::i32:
+ return Select_ISD_SRA_i32(N);
+ case MVT::i64:
+ return Select_ISD_SRA_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SRL: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_SRL_i8(N);
+ case MVT::i16:
+ return Select_ISD_SRL_i16(N);
+ case MVT::i32:
+ return Select_ISD_SRL_i32(N);
+ case MVT::i64:
+ return Select_ISD_SRL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::STORE: {
+ return Select_ISD_STORE(N);
+ break;
+ }
+ case ISD::SUB: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_SUB_i8(N);
+ case MVT::i16:
+ return Select_ISD_SUB_i16(N);
+ case MVT::i32:
+ return Select_ISD_SUB_i32(N);
+ case MVT::i64:
+ return Select_ISD_SUB_i64(N);
+ case MVT::v8i8:
+ return Select_ISD_SUB_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_SUB_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_SUB_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_SUB_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_SUB_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_SUB_v4i32(N);
+ case MVT::v1i64:
+ return Select_ISD_SUB_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_SUB_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SUBC: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ISD_SUBC_i32(N);
+ case MVT::i64:
+ return Select_ISD_SUBC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::SUBE: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_SUBE_i8(N);
+ case MVT::i16:
+ return Select_ISD_SUBE_i16(N);
+ case MVT::i32:
+ return Select_ISD_SUBE_i32(N);
+ case MVT::i64:
+ return Select_ISD_SUBE_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::TRAP: {
+ return Select_ISD_TRAP(N);
+ break;
+ }
+ case ISD::TRUNCATE: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_TRUNCATE_i8(N);
+ case MVT::i16:
+ return Select_ISD_TRUNCATE_i16(N);
+ case MVT::i32:
+ return Select_ISD_TRUNCATE_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::VECTOR_SHUFFLE: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_ISD_VECTOR_SHUFFLE_v8i8(N);
+ case MVT::v16i8:
+ return Select_ISD_VECTOR_SHUFFLE_v16i8(N);
+ case MVT::v4i16:
+ return Select_ISD_VECTOR_SHUFFLE_v4i16(N);
+ case MVT::v8i16:
+ return Select_ISD_VECTOR_SHUFFLE_v8i16(N);
+ case MVT::v2i32:
+ return Select_ISD_VECTOR_SHUFFLE_v2i32(N);
+ case MVT::v4i32:
+ return Select_ISD_VECTOR_SHUFFLE_v4i32(N);
+ case MVT::v2i64:
+ return Select_ISD_VECTOR_SHUFFLE_v2i64(N);
+ case MVT::v4f32:
+ return Select_ISD_VECTOR_SHUFFLE_v4f32(N);
+ case MVT::v2f64:
+ return Select_ISD_VECTOR_SHUFFLE_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::XOR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_ISD_XOR_i8(N);
+ case MVT::i16:
+ return Select_ISD_XOR_i16(N);
+ case MVT::i32:
+ return Select_ISD_XOR_i32(N);
+ case MVT::i64:
+ return Select_ISD_XOR_i64(N);
+ case MVT::v1i64:
+ return Select_ISD_XOR_v1i64(N);
+ case MVT::v2i64:
+ return Select_ISD_XOR_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case ISD::ZERO_EXTEND: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_ISD_ZERO_EXTEND_i16(N);
+ case MVT::i32:
+ return Select_ISD_ZERO_EXTEND_i32(N);
+ case MVT::i64:
+ return Select_ISD_ZERO_EXTEND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::ADD: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_ADD_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_ADD_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_ADD_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_ADD_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::AND: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_AND_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_AND_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_AND_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_AND_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::BRCOND: {
+ return Select_X86ISD_BRCOND(N);
+ break;
+ }
+ case X86ISD::BSF: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_X86ISD_BSF_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_BSF_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_BSF_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::BSR: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_X86ISD_BSR_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_BSR_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_BSR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::BT: {
+ return Select_X86ISD_BT(N);
+ break;
+ }
+ case X86ISD::CALL: {
+ return Select_X86ISD_CALL(N);
+ break;
+ }
+ case X86ISD::CMOV: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_CMOV_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_CMOV_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_CMOV_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_CMOV_i64(N);
+ case MVT::f32:
+ return Select_X86ISD_CMOV_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_CMOV_f64(N);
+ case MVT::f80:
+ return Select_X86ISD_CMOV_f80(N);
+ case MVT::v1i64:
+ return Select_X86ISD_CMOV_v1i64(N);
+ case MVT::v2i64:
+ return Select_X86ISD_CMOV_v2i64(N);
+ case MVT::v4f32:
+ return Select_X86ISD_CMOV_v4f32(N);
+ case MVT::v2f64:
+ return Select_X86ISD_CMOV_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::CMP: {
+ return Select_X86ISD_CMP(N);
+ break;
+ }
+ case X86ISD::CMPPD: {
+ switch (NVT) {
+ case MVT::v2i64:
+ return Select_X86ISD_CMPPD_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::CMPPS: {
+ switch (NVT) {
+ case MVT::v4i32:
+ return Select_X86ISD_CMPPS_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::COMI: {
+ return Select_X86ISD_COMI(N);
+ break;
+ }
+ case X86ISD::DEC: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_DEC_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_DEC_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_DEC_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_DEC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::EH_RETURN: {
+ return Select_X86ISD_EH_RETURN(N);
+ break;
+ }
+ case X86ISD::FAND: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FAND_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FAND_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FILD: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FILD_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FILD_f64(N);
+ case MVT::f80:
+ return Select_X86ISD_FILD_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FILD_FLAG: {
+ switch (NVT) {
+ case MVT::f64:
+ return Select_X86ISD_FILD_FLAG_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FLD: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FLD_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FLD_f64(N);
+ case MVT::f80:
+ return Select_X86ISD_FLD_f80(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FMAX: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FMAX_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FMAX_f64(N);
+ case MVT::v4f32:
+ return Select_X86ISD_FMAX_v4f32(N);
+ case MVT::v2f64:
+ return Select_X86ISD_FMAX_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FMIN: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FMIN_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FMIN_f64(N);
+ case MVT::v4f32:
+ return Select_X86ISD_FMIN_v4f32(N);
+ case MVT::v2f64:
+ return Select_X86ISD_FMIN_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FNSTCW16m: {
+ return Select_X86ISD_FNSTCW16m(N);
+ break;
+ }
+ case X86ISD::FOR: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FOR_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FOR_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FP_TO_INT16_IN_MEM: {
+ return Select_X86ISD_FP_TO_INT16_IN_MEM(N);
+ break;
+ }
+ case X86ISD::FP_TO_INT32_IN_MEM: {
+ return Select_X86ISD_FP_TO_INT32_IN_MEM(N);
+ break;
+ }
+ case X86ISD::FP_TO_INT64_IN_MEM: {
+ return Select_X86ISD_FP_TO_INT64_IN_MEM(N);
+ break;
+ }
+ case X86ISD::FRCP: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FRCP_f32(N);
+ case MVT::v4f32:
+ return Select_X86ISD_FRCP_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FRSQRT: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FRSQRT_f32(N);
+ case MVT::v4f32:
+ return Select_X86ISD_FRSQRT_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FSRL: {
+ switch (NVT) {
+ case MVT::v2f64:
+ return Select_X86ISD_FSRL_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::FST: {
+ return Select_X86ISD_FST(N);
+ break;
+ }
+ case X86ISD::FXOR: {
+ switch (NVT) {
+ case MVT::f32:
+ return Select_X86ISD_FXOR_f32(N);
+ case MVT::f64:
+ return Select_X86ISD_FXOR_f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::INC: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_INC_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_INC_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_INC_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_INC_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::INSERTPS: {
+ switch (NVT) {
+ case MVT::v4f32:
+ return Select_X86ISD_INSERTPS_v4f32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::LCMPXCHG8_DAG: {
+ return Select_X86ISD_LCMPXCHG8_DAG(N);
+ break;
+ }
+ case X86ISD::LCMPXCHG_DAG: {
+ return Select_X86ISD_LCMPXCHG_DAG(N);
+ break;
+ }
+ case X86ISD::MUL_IMM: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_X86ISD_MUL_IMM_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_MUL_IMM_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::OR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_OR_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_OR_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_OR_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_OR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPEQB: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_X86ISD_PCMPEQB_v8i8(N);
+ case MVT::v16i8:
+ return Select_X86ISD_PCMPEQB_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPEQD: {
+ switch (NVT) {
+ case MVT::v2i32:
+ return Select_X86ISD_PCMPEQD_v2i32(N);
+ case MVT::v4i32:
+ return Select_X86ISD_PCMPEQD_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPEQQ: {
+ switch (NVT) {
+ case MVT::v2i64:
+ return Select_X86ISD_PCMPEQQ_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPEQW: {
+ switch (NVT) {
+ case MVT::v4i16:
+ return Select_X86ISD_PCMPEQW_v4i16(N);
+ case MVT::v8i16:
+ return Select_X86ISD_PCMPEQW_v8i16(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPGTB: {
+ switch (NVT) {
+ case MVT::v8i8:
+ return Select_X86ISD_PCMPGTB_v8i8(N);
+ case MVT::v16i8:
+ return Select_X86ISD_PCMPGTB_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPGTD: {
+ switch (NVT) {
+ case MVT::v2i32:
+ return Select_X86ISD_PCMPGTD_v2i32(N);
+ case MVT::v4i32:
+ return Select_X86ISD_PCMPGTD_v4i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPGTQ: {
+ switch (NVT) {
+ case MVT::v2i64:
+ return Select_X86ISD_PCMPGTQ_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PCMPGTW: {
+ switch (NVT) {
+ case MVT::v4i16:
+ return Select_X86ISD_PCMPGTW_v4i16(N);
+ case MVT::v8i16:
+ return Select_X86ISD_PCMPGTW_v8i16(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PEXTRB: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_X86ISD_PEXTRB_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PEXTRW: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_X86ISD_PEXTRW_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PINSRB: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_X86ISD_PINSRB_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PINSRW: {
+ switch (NVT) {
+ case MVT::v4i16:
+ return Select_X86ISD_PINSRW_v4i16(N);
+ case MVT::v8i16:
+ return Select_X86ISD_PINSRW_v8i16(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PSHUFB: {
+ switch (NVT) {
+ case MVT::v16i8:
+ return Select_X86ISD_PSHUFB_v16i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::PTEST: {
+ return Select_X86ISD_PTEST(N);
+ break;
+ }
+ case X86ISD::RDTSC_DAG: {
+ return Select_X86ISD_RDTSC_DAG(N);
+ break;
+ }
+ case X86ISD::REP_MOVS: {
+ return Select_X86ISD_REP_MOVS(N);
+ break;
+ }
+ case X86ISD::REP_STOS: {
+ return Select_X86ISD_REP_STOS(N);
+ break;
+ }
+ case X86ISD::RET_FLAG: {
+ return Select_X86ISD_RET_FLAG(N);
+ break;
+ }
+ case X86ISD::SETCC: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_SETCC_i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::SETCC_CARRY: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_SETCC_CARRY_i8(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::SHLD: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_X86ISD_SHLD_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_SHLD_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_SHLD_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::SHRD: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_X86ISD_SHRD_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_SHRD_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_SHRD_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::SMUL: {
+ switch (NVT) {
+ case MVT::i16:
+ return Select_X86ISD_SMUL_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_SMUL_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_SMUL_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::SUB: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_SUB_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_SUB_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_SUB_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_SUB_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::TC_RETURN: {
+ return Select_X86ISD_TC_RETURN(N);
+ break;
+ }
+ case X86ISD::TLSADDR: {
+ return Select_X86ISD_TLSADDR(N);
+ break;
+ }
+ case X86ISD::UCOMI: {
+ return Select_X86ISD_UCOMI(N);
+ break;
+ }
+ case X86ISD::VASTART_SAVE_XMM_REGS: {
+ return Select_X86ISD_VASTART_SAVE_XMM_REGS(N);
+ break;
+ }
+ case X86ISD::VSHL: {
+ switch (NVT) {
+ case MVT::v1i64:
+ return Select_X86ISD_VSHL_v1i64(N);
+ case MVT::v2i64:
+ return Select_X86ISD_VSHL_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::VSRL: {
+ switch (NVT) {
+ case MVT::v1i64:
+ return Select_X86ISD_VSRL_v1i64(N);
+ case MVT::v2i64:
+ return Select_X86ISD_VSRL_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::VZEXT_LOAD: {
+ switch (NVT) {
+ case MVT::v2i64:
+ return Select_X86ISD_VZEXT_LOAD_v2i64(N);
+ case MVT::v2f64:
+ return Select_X86ISD_VZEXT_LOAD_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::VZEXT_MOVL: {
+ switch (NVT) {
+ case MVT::v2i32:
+ return Select_X86ISD_VZEXT_MOVL_v2i32(N);
+ case MVT::v4i32:
+ return Select_X86ISD_VZEXT_MOVL_v4i32(N);
+ case MVT::v2i64:
+ return Select_X86ISD_VZEXT_MOVL_v2i64(N);
+ case MVT::v4f32:
+ return Select_X86ISD_VZEXT_MOVL_v4f32(N);
+ case MVT::v2f64:
+ return Select_X86ISD_VZEXT_MOVL_v2f64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::Wrapper: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_X86ISD_Wrapper_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_Wrapper_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::WrapperRIP: {
+ switch (NVT) {
+ case MVT::i64:
+ return Select_X86ISD_WrapperRIP_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ case X86ISD::XOR: {
+ switch (NVT) {
+ case MVT::i8:
+ return Select_X86ISD_XOR_i8(N);
+ case MVT::i16:
+ return Select_X86ISD_XOR_i16(N);
+ case MVT::i32:
+ return Select_X86ISD_XOR_i32(N);
+ case MVT::i64:
+ return Select_X86ISD_XOR_i64(N);
+ default:
+ break;
+ }
+ break;
+ }
+ } // end of big switch.
+
+ if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&
+ N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
+ N.getOpcode() != ISD::INTRINSIC_VOID) {
+ CannotYetSelect(N);
+ } else {
+ CannotYetSelectIntrinsic(N);
+ }
+ return NULL;
+}
+
diff --git a/libclamav/c++/X86GenFastISel.inc b/libclamav/c++/X86GenFastISel.inc
new file mode 100644
index 0000000..a4b1dab
--- /dev/null
+++ b/libclamav/c++/X86GenFastISel.inc
@@ -0,0 +1,3501 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// "Fast" Instruction Selector for the X86 target
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+// FastEmit functions for ISD::Constant.
+
+unsigned FastEmit_ISD_Constant_MVT_i8_i(MVT RetVT, uint64_t imm0) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_i(X86::MOV8ri, X86::GR8RegisterClass, imm0);
+}
+
+unsigned FastEmit_ISD_Constant_MVT_i16_i(MVT RetVT, uint64_t imm0) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_i(X86::MOV16ri, X86::GR16RegisterClass, imm0);
+}
+
+unsigned FastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_i(X86::MOV32ri, X86::GR32RegisterClass, imm0);
+}
+
+unsigned FastEmit_ISD_Constant_MVT_i64_i(MVT RetVT, uint64_t imm0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_i(X86::MOV64ri, X86::GR64RegisterClass, imm0);
+}
+
+unsigned FastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_Constant_MVT_i8_i(RetVT, imm0);
+ case MVT::i16: return FastEmit_ISD_Constant_MVT_i16_i(RetVT, imm0);
+ case MVT::i32: return FastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
+ case MVT::i64: return FastEmit_ISD_Constant_MVT_i64_i(RetVT, imm0);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned FastEmit_i(MVT VT, MVT RetVT, ISD::NodeType Opcode, uint64_t imm0) {
+ switch (Opcode) {
+ case ISD::Constant: return FastEmit_ISD_Constant_i(VT, RetVT, imm0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ANY_EXTEND.
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i16_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX16rr8, X86::GR16RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX32rr8, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX64rr8, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i16: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i16_r(Op0);
+ case MVT::i32: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i16_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX32rr16, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i16_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX64rr16, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_ANY_EXTEND_MVT_i16_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_ANY_EXTEND_MVT_i16_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ANY_EXTEND_MVT_i8_r(RetVT, Op0);
+ case MVT::i16: return FastEmit_ISD_ANY_EXTEND_MVT_i16_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::BIT_CONVERT.
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVDI2SSrr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_f64_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOV64toSDrr, X86::FR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v8i8_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64to64rr, X86::VR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v4i16_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64to64rr, X86::VR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v2i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64to64rr, X86::VR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v1i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64to64rr, X86::VR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v2f32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64to64rr, X86::VR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_i64_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::f64: return FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_f64_r(Op0);
+ case MVT::v8i8: return FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v8i8_r(Op0);
+ case MVT::v4i16: return FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v4i16_r(Op0);
+ case MVT::v2i32: return FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v2i32_r(Op0);
+ case MVT::v1i64: return FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v1i64_r(Op0);
+ case MVT::v2f32: return FastEmit_ISD_BIT_CONVERT_MVT_i64_MVT_v2f32_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVSS2DIrr, X86::GR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVSDto64rr, X86::GR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v8i8_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64from64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v8i8_MVT_f64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVQ2FR64rr, X86::FR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v8i8_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i64: return FastEmit_ISD_BIT_CONVERT_MVT_v8i8_MVT_i64_r(Op0);
+ case MVT::f64: return FastEmit_ISD_BIT_CONVERT_MVT_v8i8_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v4i16_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64from64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v4i16_MVT_f64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVQ2FR64rr, X86::FR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v4i16_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i64: return FastEmit_ISD_BIT_CONVERT_MVT_v4i16_MVT_i64_r(Op0);
+ case MVT::f64: return FastEmit_ISD_BIT_CONVERT_MVT_v4i16_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v2i32_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64from64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v2i32_MVT_f64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVQ2FR64rr, X86::FR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v2i32_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i64: return FastEmit_ISD_BIT_CONVERT_MVT_v2i32_MVT_i64_r(Op0);
+ case MVT::f64: return FastEmit_ISD_BIT_CONVERT_MVT_v2i32_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v1i64_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVD64from64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v1i64_MVT_f64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MMX_MOVQ2FR64rr, X86::FR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v1i64_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i64: return FastEmit_ISD_BIT_CONVERT_MVT_v1i64_MVT_i64_r(Op0);
+ case MVT::f64: return FastEmit_ISD_BIT_CONVERT_MVT_v1i64_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_MVT_v2f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::MMX_MOVD64from64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BIT_CONVERT_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_BIT_CONVERT_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_ISD_BIT_CONVERT_MVT_i64_r(RetVT, Op0);
+ case MVT::f32: return FastEmit_ISD_BIT_CONVERT_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_BIT_CONVERT_MVT_f64_r(RetVT, Op0);
+ case MVT::v8i8: return FastEmit_ISD_BIT_CONVERT_MVT_v8i8_r(RetVT, Op0);
+ case MVT::v4i16: return FastEmit_ISD_BIT_CONVERT_MVT_v4i16_r(RetVT, Op0);
+ case MVT::v2i32: return FastEmit_ISD_BIT_CONVERT_MVT_v2i32_r(RetVT, Op0);
+ case MVT::v1i64: return FastEmit_ISD_BIT_CONVERT_MVT_v1i64_r(RetVT, Op0);
+ case MVT::v2f32: return FastEmit_ISD_BIT_CONVERT_MVT_v2f32_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::BRIND.
+
+unsigned FastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_r(X86::JMP32r, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_r(X86::JMP64r, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::BSWAP.
+
+unsigned FastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_r(X86::BSWAP32r, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::BSWAP64r, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FABS.
+
+unsigned FastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::ABS_Fp32, X86::RFP32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::ABS_Fp64, X86::RFP64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FABS_MVT_f80_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_r(X86::ABS_Fp80, X86::RFP80RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
+ case MVT::f80: return FastEmit_ISD_FABS_MVT_f80_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FCOS.
+
+unsigned FastEmit_ISD_FCOS_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::COS_Fp32, X86::RFP32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FCOS_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::COS_Fp64, X86::RFP64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FCOS_MVT_f80_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_r(X86::COS_Fp80, X86::RFP80RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_FCOS_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FCOS_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FCOS_MVT_f64_r(RetVT, Op0);
+ case MVT::f80: return FastEmit_ISD_FCOS_MVT_f80_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FNEG.
+
+unsigned FastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::CHS_Fp32, X86::RFP32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CHS_Fp64, X86::RFP64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FNEG_MVT_f80_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_r(X86::CHS_Fp80, X86::RFP80RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
+ case MVT::f80: return FastEmit_ISD_FNEG_MVT_f80_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_EXTEND.
+
+unsigned FastEmit_ISD_FP_EXTEND_MVT_f32_MVT_f64_r(unsigned Op0) {
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::MOV_Fp3264, X86::RFP64RegisterClass, Op0);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CVTSS2SDrr, X86::FR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_EXTEND_MVT_f32_MVT_f80_r(unsigned Op0) {
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::MOV_Fp3280, X86::RFP80RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::f64: return FastEmit_ISD_FP_EXTEND_MVT_f32_MVT_f64_r(Op0);
+ case MVT::f80: return FastEmit_ISD_FP_EXTEND_MVT_f32_MVT_f80_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOV_Fp6480, X86::RFP80RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_ROUND.
+
+unsigned FastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::MOV_Fp6432, X86::RFP32RegisterClass, Op0);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CVTSD2SSrr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_ROUND_MVT_f80_MVT_f32_r(unsigned Op0) {
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::MOV_Fp8032, X86::RFP32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_ROUND_MVT_f80_MVT_f64_r(unsigned Op0) {
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOV_Fp8064, X86::RFP64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_ROUND_MVT_f80_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FP_ROUND_MVT_f80_MVT_f32_r(Op0);
+ case MVT::f64: return FastEmit_ISD_FP_ROUND_MVT_f80_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f64: return FastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
+ case MVT::f80: return FastEmit_ISD_FP_ROUND_MVT_f80_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_TO_SINT.
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) {
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::CVTTSS2SIrr, X86::GR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) {
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::CVTTSS2SI64rr, X86::GR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CVTTSD2SIrr, X86::GR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CVTTSD2SI64rr, X86::GR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::Int_CVTTPS2DQrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2i32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::Int_CVTTPD2PIrr, X86::VR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0);
+ case MVT::v4f32: return FastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
+ case MVT::v2f64: return FastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FSIN.
+
+unsigned FastEmit_ISD_FSIN_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::SIN_Fp32, X86::RFP32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSIN_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::SIN_Fp64, X86::RFP64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSIN_MVT_f80_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_r(X86::SIN_Fp80, X86::RFP80RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_FSIN_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FSIN_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FSIN_MVT_f64_r(RetVT, Op0);
+ case MVT::f80: return FastEmit_ISD_FSIN_MVT_f80_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FSQRT.
+
+unsigned FastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::SQRT_Fp32, X86::RFP32RegisterClass, Op0);
+ }
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::SQRTSSr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::SQRT_Fp64, X86::RFP64RegisterClass, Op0);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::SQRTSDr, X86::FR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSQRT_MVT_f80_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_r(X86::SQRT_Fp80, X86::RFP80RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::SQRTPSr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::SQRTPDr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
+ case MVT::f80: return FastEmit_ISD_FSQRT_MVT_f80_r(RetVT, Op0);
+ case MVT::v4f32: return FastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
+ case MVT::v2f64: return FastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SCALAR_TO_VECTOR.
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v2i32_r(unsigned Op0) {
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_r(X86::MMX_MOVD64rr, X86::VR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVDI2PDIrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::v2i32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v2i32_r(Op0);
+ case MVT::v4i32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_MVT_v4i32_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_MVT_v1i64_r(unsigned Op0) {
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_r(X86::MMX_MOVD64rrv164, X86::VR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_MVT_v2i64_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOV64toPQIrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::v1i64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_MVT_v1i64_r(Op0);
+ case MVT::v2i64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_MVT_v2i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::MOVSS2PSrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVSD2PDrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
+ case MVT::f32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
+ case MVT::f64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SIGN_EXTEND.
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i16_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVSX16rr8, X86::GR16RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVSX32rr8, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVSX64rr8, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i16: return FastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i16_r(Op0);
+ case MVT::i32: return FastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVSX32rr16, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVSX64rr16, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::MOVSX64rr32, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SIGN_EXTEND_MVT_i8_r(RetVT, Op0);
+ case MVT::i16: return FastEmit_ISD_SIGN_EXTEND_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SINT_TO_FP.
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) {
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::CVTSI2SSrr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CVTSI2SDrr, X86::FR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
+ case MVT::f64: return FastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) {
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::CVTSI2SS64rr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) {
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::CVTSI2SD64rr, X86::FR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0);
+ case MVT::f64: return FastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::Int_CVTPI2PDrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::Int_CVTDQ2PSrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
+ case MVT::v2i32: return FastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0);
+ case MVT::v4i32: return FastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::TRUNCATE.
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i16_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ if ((Subtarget->is64Bit())) {
+ return FastEmitInst_extractsubreg(RetVT, Op0, 1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i32_MVT_i8_r(unsigned Op0) {
+ if ((Subtarget->is64Bit())) {
+ return FastEmitInst_extractsubreg(MVT::i8, Op0, 1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i32_MVT_i16_r(unsigned Op0) {
+ return FastEmitInst_extractsubreg(MVT::i16, Op0, 3);
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_TRUNCATE_MVT_i32_MVT_i8_r(Op0);
+ case MVT::i16: return FastEmit_ISD_TRUNCATE_MVT_i32_MVT_i16_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i64_MVT_i8_r(unsigned Op0) {
+ return FastEmitInst_extractsubreg(MVT::i8, Op0, 1);
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i64_MVT_i16_r(unsigned Op0) {
+ return FastEmitInst_extractsubreg(MVT::i16, Op0, 3);
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i64_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_extractsubreg(MVT::i32, Op0, 4);
+}
+
+unsigned FastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_TRUNCATE_MVT_i64_MVT_i8_r(Op0);
+ case MVT::i16: return FastEmit_ISD_TRUNCATE_MVT_i64_MVT_i16_r(Op0);
+ case MVT::i32: return FastEmit_ISD_TRUNCATE_MVT_i64_MVT_i32_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_ISD_TRUNCATE_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ZERO_EXTEND.
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i8_MVT_i16_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX16rr8, X86::GR16RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i8_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX32rr8, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i8_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX64rr8, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i16: return FastEmit_ISD_ZERO_EXTEND_MVT_i8_MVT_i16_r(Op0);
+ case MVT::i32: return FastEmit_ISD_ZERO_EXTEND_MVT_i8_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_ZERO_EXTEND_MVT_i8_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i16_MVT_i32_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX32rr16, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i16_MVT_i64_r(unsigned Op0) {
+ return FastEmitInst_r(X86::MOVZX64rr16, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_ZERO_EXTEND_MVT_i16_MVT_i32_r(Op0);
+ case MVT::i64: return FastEmit_ISD_ZERO_EXTEND_MVT_i16_MVT_i64_r(Op0);
+ default: return 0;
+}
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::MOVZX64rr32, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ZERO_EXTEND_MVT_i8_r(RetVT, Op0);
+ case MVT::i16: return FastEmit_ISD_ZERO_EXTEND_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_ISD_ZERO_EXTEND_MVT_i32_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::BSF.
+
+unsigned FastEmit_X86ISD_BSF_MVT_i16_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_r(X86::BSF16rr, X86::GR16RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_BSF_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_r(X86::BSF32rr, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_BSF_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::BSF64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_BSF_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_X86ISD_BSF_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_X86ISD_BSF_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_X86ISD_BSF_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::BSR.
+
+unsigned FastEmit_X86ISD_BSR_MVT_i16_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_r(X86::BSR16rr, X86::GR16RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_BSR_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_r(X86::BSR32rr, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_BSR_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::BSR64rr, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_BSR_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_X86ISD_BSR_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_X86ISD_BSR_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_X86ISD_BSR_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::CALL.
+
+unsigned FastEmit_X86ISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_r(X86::CALL32r, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((!Subtarget->isTargetWin64())) {
+ return FastEmitInst_r(X86::CALL64r, X86::GR64RegisterClass, Op0);
+ }
+ if ((Subtarget->isTargetWin64())) {
+ return FastEmitInst_r(X86::WINCALL64r, X86::GR64RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_X86ISD_CALL_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_X86ISD_CALL_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::DEC.
+
+unsigned FastEmit_X86ISD_DEC_MVT_i8_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_r(X86::DEC8r, X86::GR8RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_DEC_MVT_i16_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ if ((!Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::DEC16r, X86::GR16RegisterClass, Op0);
+ }
+ if ((Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::DEC64_16r, X86::GR16RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_DEC_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((!Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::DEC32r, X86::GR32RegisterClass, Op0);
+ }
+ if ((Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::DEC64_32r, X86::GR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_DEC_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::DEC64r, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_DEC_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_DEC_MVT_i8_r(RetVT, Op0);
+ case MVT::i16: return FastEmit_X86ISD_DEC_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_X86ISD_DEC_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_X86ISD_DEC_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::EH_RETURN.
+
+unsigned FastEmit_X86ISD_EH_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_r(X86::EH_RETURN, X86::GR32RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_EH_RETURN_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_r(X86::EH_RETURN64, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_EH_RETURN_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_X86ISD_EH_RETURN_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_X86ISD_EH_RETURN_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FRCP.
+
+unsigned FastEmit_X86ISD_FRCP_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::RCPSSr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FRCP_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::RCPPSr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FRCP_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FRCP_MVT_f32_r(RetVT, Op0);
+ case MVT::v4f32: return FastEmit_X86ISD_FRCP_MVT_v4f32_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FRSQRT.
+
+unsigned FastEmit_X86ISD_FRSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::RSQRTSSr, X86::FR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FRSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_r(X86::RSQRTPSr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FRSQRT_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FRSQRT_MVT_f32_r(RetVT, Op0);
+ case MVT::v4f32: return FastEmit_X86ISD_FRSQRT_MVT_v4f32_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::INC.
+
+unsigned FastEmit_X86ISD_INC_MVT_i8_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_r(X86::INC8r, X86::GR8RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_INC_MVT_i16_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ if ((!Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::INC16r, X86::GR16RegisterClass, Op0);
+ }
+ if ((Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::INC64_16r, X86::GR16RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_INC_MVT_i32_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((!Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::INC32r, X86::GR32RegisterClass, Op0);
+ }
+ if ((Subtarget->is64Bit())) {
+ return FastEmitInst_r(X86::INC64_32r, X86::GR32RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_INC_MVT_i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_r(X86::INC64r, X86::GR64RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_INC_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_INC_MVT_i8_r(RetVT, Op0);
+ case MVT::i16: return FastEmit_X86ISD_INC_MVT_i16_r(RetVT, Op0);
+ case MVT::i32: return FastEmit_X86ISD_INC_MVT_i32_r(RetVT, Op0);
+ case MVT::i64: return FastEmit_X86ISD_INC_MVT_i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::VZEXT_MOVL.
+
+unsigned FastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVZPQILo2PQIrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_r(X86::MOVZPQILo2PQIrr, X86::VR128RegisterClass, Op0);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_VZEXT_MOVL_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::v2i64: return FastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(RetVT, Op0);
+ case MVT::v2f64: return FastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned FastEmit_r(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0) {
+ switch (Opcode) {
+ case ISD::ANY_EXTEND: return FastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
+ case ISD::BIT_CONVERT: return FastEmit_ISD_BIT_CONVERT_r(VT, RetVT, Op0);
+ case ISD::BRIND: return FastEmit_ISD_BRIND_r(VT, RetVT, Op0);
+ case ISD::BSWAP: return FastEmit_ISD_BSWAP_r(VT, RetVT, Op0);
+ case ISD::FABS: return FastEmit_ISD_FABS_r(VT, RetVT, Op0);
+ case ISD::FCOS: return FastEmit_ISD_FCOS_r(VT, RetVT, Op0);
+ case ISD::FNEG: return FastEmit_ISD_FNEG_r(VT, RetVT, Op0);
+ case ISD::FP_EXTEND: return FastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
+ case ISD::FP_ROUND: return FastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
+ case ISD::FP_TO_SINT: return FastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
+ case ISD::FSIN: return FastEmit_ISD_FSIN_r(VT, RetVT, Op0);
+ case ISD::FSQRT: return FastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
+ case ISD::SCALAR_TO_VECTOR: return FastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0);
+ case ISD::SIGN_EXTEND: return FastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
+ case ISD::SINT_TO_FP: return FastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
+ case ISD::TRUNCATE: return FastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0);
+ case ISD::ZERO_EXTEND: return FastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0);
+ case X86ISD::BSF: return FastEmit_X86ISD_BSF_r(VT, RetVT, Op0);
+ case X86ISD::BSR: return FastEmit_X86ISD_BSR_r(VT, RetVT, Op0);
+ case X86ISD::CALL: return FastEmit_X86ISD_CALL_r(VT, RetVT, Op0);
+ case X86ISD::DEC: return FastEmit_X86ISD_DEC_r(VT, RetVT, Op0);
+ case X86ISD::EH_RETURN: return FastEmit_X86ISD_EH_RETURN_r(VT, RetVT, Op0);
+ case X86ISD::FRCP: return FastEmit_X86ISD_FRCP_r(VT, RetVT, Op0);
+ case X86ISD::FRSQRT: return FastEmit_X86ISD_FRSQRT_r(VT, RetVT, Op0);
+ case X86ISD::INC: return FastEmit_X86ISD_INC_r(VT, RetVT, Op0);
+ case X86ISD::VZEXT_MOVL: return FastEmit_X86ISD_VZEXT_MOVL_r(VT, RetVT, Op0);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADD.
+
+unsigned FastEmit_ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::ADD8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::ADD16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::ADD32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ADD_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_ADD_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_ADD_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADDC.
+
+unsigned FastEmit_ISD_ADDC_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::ADD32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADDC_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_ADDC_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADDE.
+
+unsigned FastEmit_ISD_ADDE_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::ADC8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADDE_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::ADC16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADDE_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::ADC32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ADDE_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ADDE_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_ADDE_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_ADDE_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::AND.
+
+unsigned FastEmit_ISD_AND_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::AND8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_AND_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::AND16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_AND_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::AND32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_AND_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_AND_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_AND_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_AND_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::MUL.
+
+unsigned FastEmit_ISD_MUL_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::IMUL16rri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_MUL_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::IMUL32rri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_MUL_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_ISD_MUL_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_MUL_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::OR.
+
+unsigned FastEmit_ISD_OR_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::OR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_OR_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::OR16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_OR_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::OR32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_OR_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_OR_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_OR_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_OR_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ROTL.
+
+unsigned FastEmit_ISD_ROTL_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::ROL8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ROTL_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ROTL_MVT_i8_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ROTR.
+
+unsigned FastEmit_ISD_ROTR_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::ROR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_ROTR_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ROTR_MVT_i8_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SHL.
+
+unsigned FastEmit_ISD_SHL_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::SHL8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SHL_MVT_i8_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRA.
+
+unsigned FastEmit_ISD_SRA_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::SAR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SRA_MVT_i8_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRL.
+
+unsigned FastEmit_ISD_SRL_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::SHR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SRL_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SRL_MVT_i8_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUB.
+
+unsigned FastEmit_ISD_SUB_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::SUB8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUB_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::SUB16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUB_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::SUB32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUB_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SUB_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_SUB_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_SUB_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUBC.
+
+unsigned FastEmit_ISD_SUBC_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::SUB32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUBC_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_ri(X86::SUB64ri32, X86::GR64RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUBC_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_SUBC_MVT_i32_ri(RetVT, Op0, imm1);
+ case MVT::i64: return FastEmit_ISD_SUBC_MVT_i64_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUBE.
+
+unsigned FastEmit_ISD_SUBE_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::SBB8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUBE_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::SBB16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUBE_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::SBB32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_SUBE_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SUBE_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_SUBE_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_SUBE_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::XOR.
+
+unsigned FastEmit_ISD_XOR_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::XOR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_XOR_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::XOR16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_XOR_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::XOR32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_ISD_XOR_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_XOR_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_ISD_XOR_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_ISD_XOR_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::ADD.
+
+unsigned FastEmit_X86ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::ADD8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::ADD16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::ADD32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_ADD_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_X86ISD_ADD_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_ADD_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::AND.
+
+unsigned FastEmit_X86ISD_AND_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::AND8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_AND_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::AND16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_AND_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::AND32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_AND_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_AND_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_X86ISD_AND_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_AND_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::CMP.
+
+unsigned FastEmit_X86ISD_CMP_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_ri(X86::CMP8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_ri(X86::CMP16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_ri(X86::CMP32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_CMP_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_CMP_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_X86ISD_CMP_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_CMP_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::OR.
+
+unsigned FastEmit_X86ISD_OR_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::OR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_OR_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::OR16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_OR_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::OR32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_OR_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_OR_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_X86ISD_OR_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_OR_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::SMUL.
+
+unsigned FastEmit_X86ISD_SMUL_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::IMUL16rri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_SMUL_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::IMUL32rri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_SMUL_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_X86ISD_SMUL_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_SMUL_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::SUB.
+
+unsigned FastEmit_X86ISD_SUB_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::SUB8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_SUB_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::SUB16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_SUB_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::SUB32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_SUB_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_SUB_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_X86ISD_SUB_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_SUB_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::TC_RETURN.
+
+unsigned FastEmit_X86ISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_ri(X86::TCRETURNri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_X86ISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::XOR.
+
+unsigned FastEmit_X86ISD_XOR_MVT_i8_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_ri(X86::XOR8ri, X86::GR8RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_XOR_MVT_i16_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_ri(X86::XOR16ri, X86::GR16RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_XOR_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_ri(X86::XOR32ri, X86::GR32RegisterClass, Op0, imm1);
+}
+
+unsigned FastEmit_X86ISD_XOR_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_XOR_MVT_i8_ri(RetVT, Op0, imm1);
+ case MVT::i16: return FastEmit_X86ISD_XOR_MVT_i16_ri(RetVT, Op0, imm1);
+ case MVT::i32: return FastEmit_X86ISD_XOR_MVT_i32_ri(RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned FastEmit_ri(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::ADD: return FastEmit_ISD_ADD_ri(VT, RetVT, Op0, imm1);
+ case ISD::ADDC: return FastEmit_ISD_ADDC_ri(VT, RetVT, Op0, imm1);
+ case ISD::ADDE: return FastEmit_ISD_ADDE_ri(VT, RetVT, Op0, imm1);
+ case ISD::AND: return FastEmit_ISD_AND_ri(VT, RetVT, Op0, imm1);
+ case ISD::MUL: return FastEmit_ISD_MUL_ri(VT, RetVT, Op0, imm1);
+ case ISD::OR: return FastEmit_ISD_OR_ri(VT, RetVT, Op0, imm1);
+ case ISD::ROTL: return FastEmit_ISD_ROTL_ri(VT, RetVT, Op0, imm1);
+ case ISD::ROTR: return FastEmit_ISD_ROTR_ri(VT, RetVT, Op0, imm1);
+ case ISD::SHL: return FastEmit_ISD_SHL_ri(VT, RetVT, Op0, imm1);
+ case ISD::SRA: return FastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1);
+ case ISD::SRL: return FastEmit_ISD_SRL_ri(VT, RetVT, Op0, imm1);
+ case ISD::SUB: return FastEmit_ISD_SUB_ri(VT, RetVT, Op0, imm1);
+ case ISD::SUBC: return FastEmit_ISD_SUBC_ri(VT, RetVT, Op0, imm1);
+ case ISD::SUBE: return FastEmit_ISD_SUBE_ri(VT, RetVT, Op0, imm1);
+ case ISD::XOR: return FastEmit_ISD_XOR_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::ADD: return FastEmit_X86ISD_ADD_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::AND: return FastEmit_X86ISD_AND_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::CMP: return FastEmit_X86ISD_CMP_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::OR: return FastEmit_X86ISD_OR_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::SMUL: return FastEmit_X86ISD_SMUL_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::SUB: return FastEmit_X86ISD_SUB_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::TC_RETURN: return FastEmit_X86ISD_TC_RETURN_ri(VT, RetVT, Op0, imm1);
+ case X86ISD::XOR: return FastEmit_X86ISD_XOR_ri(VT, RetVT, Op0, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADD.
+
+unsigned FastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::ADD8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::ADD16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::ADD32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::ADD64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i8)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PADDBrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PADDBrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i16)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PADDWrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PADDWrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i32)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PADDDrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PADDDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v1i64)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PADDQrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PADDQrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ADD_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_ADD_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::v8i8: return FastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op1);
+ case MVT::v16i8: return FastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
+ case MVT::v4i16: return FastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op1);
+ case MVT::v8i16: return FastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
+ case MVT::v2i32: return FastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op1);
+ case MVT::v4i32: return FastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
+ case MVT::v1i64: return FastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op1);
+ case MVT::v2i64: return FastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADDC.
+
+unsigned FastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::ADD32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::ADD64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADDE.
+
+unsigned FastEmit_ISD_ADDE_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::ADC8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADDE_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::ADC16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::ADC32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::ADC64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_ADDE_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_ADDE_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::AND.
+
+unsigned FastEmit_ISD_AND_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::AND8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_AND_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::AND16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::AND32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::AND64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_AND_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v1i64)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PANDrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::ANDPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PANDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_AND_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_AND_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::v1i64: return FastEmit_ISD_AND_MVT_v1i64_rr(RetVT, Op0, Op1);
+ case MVT::v2i64: return FastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FADD.
+
+unsigned FastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::ADD_Fp32, X86::RFP32RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::ADDSSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::ADD_Fp64, X86::RFP64RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::ADDSDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FADD_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_rr(X86::ADD_Fp80, X86::RFP80RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::ADDPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::ADDPDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::f80: return FastEmit_ISD_FADD_MVT_f80_rr(RetVT, Op0, Op1);
+ case MVT::v4f32: return FastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FDIV.
+
+unsigned FastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::DIV_Fp32, X86::RFP32RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::DIVSSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::DIV_Fp64, X86::RFP64RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::DIVSDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FDIV_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_rr(X86::DIV_Fp80, X86::RFP80RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::DIVPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::DIVPDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::f80: return FastEmit_ISD_FDIV_MVT_f80_rr(RetVT, Op0, Op1);
+ case MVT::v4f32: return FastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FMUL.
+
+unsigned FastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MUL_Fp32, X86::RFP32RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MULSSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MUL_Fp64, X86::RFP64RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MULSDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FMUL_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_rr(X86::MUL_Fp80, X86::RFP80RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MULPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MULPDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::f80: return FastEmit_ISD_FMUL_MVT_f80_rr(RetVT, Op0, Op1);
+ case MVT::v4f32: return FastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FSUB.
+
+unsigned FastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::SUB_Fp32, X86::RFP32RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::SUBSSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::SUB_Fp64, X86::RFP64RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::SUBSDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSUB_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f80)
+ return 0;
+ return FastEmitInst_rr(X86::SUB_Fp80, X86::RFP80RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::SUBPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::SUBPDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::f80: return FastEmit_ISD_FSUB_MVT_f80_rr(RetVT, Op0, Op1);
+ case MVT::v4f32: return FastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::MUL.
+
+unsigned FastEmit_ISD_MUL_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ TII.copyRegToReg(*MBB, MBB->end(), X86::AL, Op0, TM.getRegisterInfo()->getPhysicalRegisterRegClass(X86::AL), MRI.getRegClass(Op0));
+ return FastEmitInst_r(X86::MUL8r, X86::GR8RegisterClass, Op1);
+}
+
+unsigned FastEmit_ISD_MUL_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::IMUL16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::IMUL32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::IMUL64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i16)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PMULLWrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PMULLWrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasSSE41())) {
+ return FastEmitInst_rr(X86::PMULLDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_MUL_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_MUL_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::v4i16: return FastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op1);
+ case MVT::v8i16: return FastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
+ case MVT::v4i32: return FastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::OR.
+
+unsigned FastEmit_ISD_OR_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::OR8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_OR_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::OR16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::OR32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::OR64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_OR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v1i64)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PORrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::ORPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PORrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_OR_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_OR_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::v1i64: return FastEmit_ISD_OR_MVT_v1i64_rr(RetVT, Op0, Op1);
+ case MVT::v2i64: return FastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUB.
+
+unsigned FastEmit_ISD_SUB_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::SUB8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUB_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::SUB16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::SUB32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::SUB64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i8)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PSUBBrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PSUBBrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i16)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PSUBWrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PSUBWrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i32)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PSUBDrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PSUBDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v1i64)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PSUBQrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PSUBQrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SUB_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_SUB_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::v8i8: return FastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op1);
+ case MVT::v16i8: return FastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
+ case MVT::v4i16: return FastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op1);
+ case MVT::v8i16: return FastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
+ case MVT::v2i32: return FastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op1);
+ case MVT::v4i32: return FastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
+ case MVT::v1i64: return FastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op1);
+ case MVT::v2i64: return FastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUBC.
+
+unsigned FastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::SUB32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::SUB64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return FastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUBE.
+
+unsigned FastEmit_ISD_SUBE_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::SBB8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUBE_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::SBB16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUBE_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::SBB32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUBE_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::SBB64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_SUBE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_SUBE_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_SUBE_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_SUBE_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_SUBE_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::XOR.
+
+unsigned FastEmit_ISD_XOR_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::XOR8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_XOR_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::XOR16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::XOR32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::XOR64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_ISD_XOR_MVT_v1i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v1i64)
+ return 0;
+ if ((Subtarget->hasMMX())) {
+ return FastEmitInst_rr(X86::MMX_PXORrr, X86::VR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::XORPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::PXORrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_ISD_XOR_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_ISD_XOR_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::v1i64: return FastEmit_ISD_XOR_MVT_v1i64_rr(RetVT, Op0, Op1);
+ case MVT::v2i64: return FastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::ADD.
+
+unsigned FastEmit_X86ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::ADD8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::ADD16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::ADD32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::ADD64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_ADD_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_X86ISD_ADD_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::AND.
+
+unsigned FastEmit_X86ISD_AND_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::AND8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_AND_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::AND16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::AND32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::AND64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_AND_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_X86ISD_AND_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::BT.
+
+unsigned FastEmit_X86ISD_BT_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::BT16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_BT_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::BT32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_BT_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::BT64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_BT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_X86ISD_BT_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_BT_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_BT_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::CMP.
+
+unsigned FastEmit_X86ISD_CMP_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::CMP8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::CMP16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::CMP32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::CMP64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((!Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::UCOM_FpIr32, X86::RFP32RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::UCOMISSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((!Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::UCOM_FpIr64, X86::RFP64RegisterClass, Op0, Op1);
+ }
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::UCOMISDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_CMP_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return FastEmitInst_rr(X86::UCOM_FpIr80, X86::RFP80RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_CMP_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_X86ISD_CMP_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_CMP_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_CMP_MVT_i64_rr(RetVT, Op0, Op1);
+ case MVT::f32: return FastEmit_X86ISD_CMP_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_X86ISD_CMP_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::f80: return FastEmit_X86ISD_CMP_MVT_f80_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::COMI.
+
+unsigned FastEmit_X86ISD_COMI_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::Int_COMISSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_COMI_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::Int_COMISDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_COMI_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return FastEmit_X86ISD_COMI_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_X86ISD_COMI_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FAND.
+
+unsigned FastEmit_X86ISD_FAND_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::FsANDPSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FAND_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::FsANDPDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FAND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FAND_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_X86ISD_FAND_MVT_f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FMAX.
+
+unsigned FastEmit_X86ISD_FMAX_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MAXSSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMAX_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MAXSDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMAX_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MAXPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMAX_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MAXPDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FMAX_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_X86ISD_FMAX_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::v4f32: return FastEmit_X86ISD_FMAX_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_X86ISD_FMAX_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FMIN.
+
+unsigned FastEmit_X86ISD_FMIN_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MINSSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMIN_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MINSDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMIN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::MINPSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMIN_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::MINPDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FMIN_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_X86ISD_FMIN_MVT_f64_rr(RetVT, Op0, Op1);
+ case MVT::v4f32: return FastEmit_X86ISD_FMIN_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_X86ISD_FMIN_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FOR.
+
+unsigned FastEmit_X86ISD_FOR_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::FsORPSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FOR_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::FsORPDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FOR_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_X86ISD_FOR_MVT_f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::FXOR.
+
+unsigned FastEmit_X86ISD_FXOR_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::FsXORPSrr, X86::FR32RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FXOR_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::FsXORPDrr, X86::FR64RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_FXOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return FastEmit_X86ISD_FXOR_MVT_f32_rr(RetVT, Op0, Op1);
+ case MVT::f64: return FastEmit_X86ISD_FXOR_MVT_f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::OR.
+
+unsigned FastEmit_X86ISD_OR_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::OR8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_OR_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::OR16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::OR32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::OR64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_OR_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_X86ISD_OR_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPEQB.
+
+unsigned FastEmit_X86ISD_PCMPEQB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i8)
+ return 0;
+ return FastEmitInst_rr(X86::MMX_PCMPEQBrr, X86::VR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPEQBrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v8i8: return FastEmit_X86ISD_PCMPEQB_MVT_v8i8_rr(RetVT, Op0, Op1);
+ case MVT::v16i8: return FastEmit_X86ISD_PCMPEQB_MVT_v16i8_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPEQD.
+
+unsigned FastEmit_X86ISD_PCMPEQD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i32)
+ return 0;
+ return FastEmitInst_rr(X86::MMX_PCMPEQDrr, X86::VR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPEQDrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v2i32: return FastEmit_X86ISD_PCMPEQD_MVT_v2i32_rr(RetVT, Op0, Op1);
+ case MVT::v4i32: return FastEmit_X86ISD_PCMPEQD_MVT_v4i32_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPEQQ.
+
+unsigned FastEmit_X86ISD_PCMPEQQ_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPEQQrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQQ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v2i64: return FastEmit_X86ISD_PCMPEQQ_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPEQW.
+
+unsigned FastEmit_X86ISD_PCMPEQW_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i16)
+ return 0;
+ return FastEmitInst_rr(X86::MMX_PCMPEQWrr, X86::VR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQW_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPEQWrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPEQW_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i16: return FastEmit_X86ISD_PCMPEQW_MVT_v4i16_rr(RetVT, Op0, Op1);
+ case MVT::v8i16: return FastEmit_X86ISD_PCMPEQW_MVT_v8i16_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPGTB.
+
+unsigned FastEmit_X86ISD_PCMPGTB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i8)
+ return 0;
+ return FastEmitInst_rr(X86::MMX_PCMPGTBrr, X86::VR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPGTBrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v8i8: return FastEmit_X86ISD_PCMPGTB_MVT_v8i8_rr(RetVT, Op0, Op1);
+ case MVT::v16i8: return FastEmit_X86ISD_PCMPGTB_MVT_v16i8_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPGTD.
+
+unsigned FastEmit_X86ISD_PCMPGTD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i32)
+ return 0;
+ return FastEmitInst_rr(X86::MMX_PCMPGTDrr, X86::VR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPGTDrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v2i32: return FastEmit_X86ISD_PCMPGTD_MVT_v2i32_rr(RetVT, Op0, Op1);
+ case MVT::v4i32: return FastEmit_X86ISD_PCMPGTD_MVT_v4i32_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPGTQ.
+
+unsigned FastEmit_X86ISD_PCMPGTQ_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPGTQrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTQ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v2i64: return FastEmit_X86ISD_PCMPGTQ_MVT_v2i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PCMPGTW.
+
+unsigned FastEmit_X86ISD_PCMPGTW_MVT_v4i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v4i16)
+ return 0;
+ return FastEmitInst_rr(X86::MMX_PCMPGTWrr, X86::VR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTW_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ return FastEmitInst_rr(X86::PCMPGTWrr, X86::VR128RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_PCMPGTW_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i16: return FastEmit_X86ISD_PCMPGTW_MVT_v4i16_rr(RetVT, Op0, Op1);
+ case MVT::v8i16: return FastEmit_X86ISD_PCMPGTW_MVT_v8i16_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PSHUFB.
+
+unsigned FastEmit_X86ISD_PSHUFB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasSSSE3())) {
+ return FastEmitInst_rr(X86::PSHUFBrr128, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_PSHUFB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return FastEmit_X86ISD_PSHUFB_MVT_v16i8_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::PTEST.
+
+unsigned FastEmit_X86ISD_PTEST_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasSSE41())) {
+ return FastEmitInst_rr(X86::PTESTrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_PTEST_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return FastEmit_X86ISD_PTEST_MVT_v4f32_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::SMUL.
+
+unsigned FastEmit_X86ISD_SMUL_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::IMUL16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SMUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::IMUL32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SMUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::IMUL64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i16: return FastEmit_X86ISD_SMUL_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_SMUL_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_SMUL_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::SUB.
+
+unsigned FastEmit_X86ISD_SUB_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::SUB8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SUB_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::SUB16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::SUB32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::SUB64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_SUB_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_X86ISD_SUB_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::UCOMI.
+
+unsigned FastEmit_X86ISD_UCOMI_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasSSE1())) {
+ return FastEmitInst_rr(X86::Int_UCOMISSrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_UCOMI_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasSSE2())) {
+ return FastEmitInst_rr(X86::Int_UCOMISDrr, X86::VR128RegisterClass, Op0, Op1);
+ }
+ return 0;
+}
+
+unsigned FastEmit_X86ISD_UCOMI_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return FastEmit_X86ISD_UCOMI_MVT_v4f32_rr(RetVT, Op0, Op1);
+ case MVT::v2f64: return FastEmit_X86ISD_UCOMI_MVT_v2f64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for X86ISD::XOR.
+
+unsigned FastEmit_X86ISD_XOR_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i8)
+ return 0;
+ return FastEmitInst_rr(X86::XOR8rr, X86::GR8RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_XOR_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i16)
+ return 0;
+ return FastEmitInst_rr(X86::XOR16rr, X86::GR16RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return FastEmitInst_rr(X86::XOR32rr, X86::GR32RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ return FastEmitInst_rr(X86::XOR64rr, X86::GR64RegisterClass, Op0, Op1);
+}
+
+unsigned FastEmit_X86ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
+ switch (VT.SimpleTy) {
+ case MVT::i8: return FastEmit_X86ISD_XOR_MVT_i8_rr(RetVT, Op0, Op1);
+ case MVT::i16: return FastEmit_X86ISD_XOR_MVT_i16_rr(RetVT, Op0, Op1);
+ case MVT::i32: return FastEmit_X86ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
+ case MVT::i64: return FastEmit_X86ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned FastEmit_rr(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0, unsigned Op1) {
+ switch (Opcode) {
+ case ISD::ADD: return FastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
+ case ISD::ADDC: return FastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
+ case ISD::ADDE: return FastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
+ case ISD::AND: return FastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
+ case ISD::FADD: return FastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
+ case ISD::FDIV: return FastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
+ case ISD::FMUL: return FastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
+ case ISD::FSUB: return FastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
+ case ISD::MUL: return FastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
+ case ISD::OR: return FastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
+ case ISD::SUB: return FastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
+ case ISD::SUBC: return FastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
+ case ISD::SUBE: return FastEmit_ISD_SUBE_rr(VT, RetVT, Op0, Op1);
+ case ISD::XOR: return FastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::ADD: return FastEmit_X86ISD_ADD_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::AND: return FastEmit_X86ISD_AND_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::BT: return FastEmit_X86ISD_BT_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::CMP: return FastEmit_X86ISD_CMP_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::COMI: return FastEmit_X86ISD_COMI_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::FAND: return FastEmit_X86ISD_FAND_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::FMAX: return FastEmit_X86ISD_FMAX_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::FMIN: return FastEmit_X86ISD_FMIN_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::FOR: return FastEmit_X86ISD_FOR_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::FXOR: return FastEmit_X86ISD_FXOR_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::OR: return FastEmit_X86ISD_OR_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPEQB: return FastEmit_X86ISD_PCMPEQB_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPEQD: return FastEmit_X86ISD_PCMPEQD_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPEQQ: return FastEmit_X86ISD_PCMPEQQ_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPEQW: return FastEmit_X86ISD_PCMPEQW_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPGTB: return FastEmit_X86ISD_PCMPGTB_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPGTD: return FastEmit_X86ISD_PCMPGTD_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPGTQ: return FastEmit_X86ISD_PCMPGTQ_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PCMPGTW: return FastEmit_X86ISD_PCMPGTW_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PSHUFB: return FastEmit_X86ISD_PSHUFB_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::PTEST: return FastEmit_X86ISD_PTEST_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::SMUL: return FastEmit_X86ISD_SMUL_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::SUB: return FastEmit_X86ISD_SUB_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::UCOMI: return FastEmit_X86ISD_UCOMI_rr(VT, RetVT, Op0, Op1);
+ case X86ISD::XOR: return FastEmit_X86ISD_XOR_rr(VT, RetVT, Op0, Op1);
+ default: return 0;
+ }
+}
+
diff --git a/libclamav/c++/X86GenInstrInfo.inc b/libclamav/c++/X86GenInstrInfo.inc
new file mode 100644
index 0000000..ee4f15c
--- /dev/null
+++ b/libclamav/c++/X86GenInstrInfo.inc
@@ -0,0 +1,2517 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Instruction Descriptors
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+static const unsigned ImplicitList1[] = { X86::EFLAGS, 0 };
+static const TargetRegisterClass* Barriers1[] = { &X86::CCRRegClass, NULL };
+static const unsigned ImplicitList2[] = { X86::ESP, 0 };
+static const unsigned ImplicitList3[] = { X86::ESP, X86::EFLAGS, 0 };
+static const unsigned ImplicitList4[] = { X86::RSP, 0 };
+static const unsigned ImplicitList5[] = { X86::RSP, X86::EFLAGS, 0 };
+static const unsigned ImplicitList6[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 };
+static const TargetRegisterClass* Barriers2[] = { &X86::CCRRegClass, &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, NULL };
+static const unsigned ImplicitList7[] = { X86::EFLAGS, X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 };
+static const unsigned ImplicitList8[] = { X86::XMM0, 0 };
+static const TargetRegisterClass* Barriers3[] = { &X86::CCRRegClass, &X86::FR32RegClass, &X86::FR64RegClass, &X86::GR32_ADRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR128RegClass, &X86::VR64RegClass, NULL };
+static const unsigned ImplicitList9[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 };
+static const TargetRegisterClass* Barriers4[] = { &X86::CCRRegClass, &X86::FR32RegClass, &X86::FR64RegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR128RegClass, &X86::VR64RegClass, NULL };
+static const unsigned ImplicitList10[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 };
+static const unsigned ImplicitList11[] = { X86::AL, 0 };
+static const unsigned ImplicitList12[] = { X86::AX, 0 };
+static const unsigned ImplicitList13[] = { X86::EAX, 0 };
+static const TargetRegisterClass* Barriers5[] = { &X86::GR32_ADRegClass, NULL };
+static const unsigned ImplicitList14[] = { X86::EAX, X86::EDX, 0 };
+static const unsigned ImplicitList15[] = { X86::RAX, 0 };
+static const unsigned ImplicitList16[] = { X86::RAX, X86::RDX, 0 };
+static const unsigned ImplicitList17[] = { X86::AX, X86::DX, 0 };
+static const unsigned ImplicitList18[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
+static const TargetRegisterClass* Barriers6[] = { &X86::CCRRegClass, &X86::GR32_ADRegClass, NULL };
+static const unsigned ImplicitList19[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList20[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList21[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
+static const TargetRegisterClass* Barriers7[] = { &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, NULL };
+static const unsigned ImplicitList22[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 };
+static const unsigned ImplicitList23[] = { X86::ST0, 0 };
+static const unsigned ImplicitList24[] = { X86::ST1, 0 };
+static const unsigned ImplicitList25[] = { X86::DX, 0 };
+static const unsigned ImplicitList26[] = { X86::AH, 0 };
+static const unsigned ImplicitList27[] = { X86::AX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList28[] = { X86::EAX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList29[] = { X86::RAX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList30[] = { X86::AL, X86::EFLAGS, 0 };
+static const unsigned ImplicitList31[] = { X86::EBP, X86::ESP, 0 };
+static const unsigned ImplicitList32[] = { X86::RBP, X86::RSP, 0 };
+static const unsigned ImplicitList33[] = { X86::EDI, 0 };
+static const unsigned ImplicitList34[] = { X86::RDI, 0 };
+static const unsigned ImplicitList35[] = { X86::DX, X86::AX, 0 };
+static const unsigned ImplicitList36[] = { X86::DX, X86::EAX, 0 };
+static const unsigned ImplicitList37[] = { X86::DX, X86::AL, 0 };
+static const unsigned ImplicitList38[] = { X86::ECX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList39[] = { X86::XMM0, X86::EFLAGS, 0 };
+static const unsigned ImplicitList40[] = { X86::CL, 0 };
+static const unsigned ImplicitList41[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
+static const unsigned ImplicitList42[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
+static const unsigned ImplicitList43[] = { X86::AL, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList44[] = { X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList45[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList46[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
+static const unsigned ImplicitList47[] = { X86::RCX, X86::RDI, 0 };
+static const unsigned ImplicitList48[] = { X86::AX, X86::ECX, X86::EDI, 0 };
+static const TargetRegisterClass* Barriers8[] = { &X86::CCRRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR64RegClass, NULL };
+static const unsigned ImplicitList49[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 };
+
+static const TargetOperandInfo OperandInfo2[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo3[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo4[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo5[] = { { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo6[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo7[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo8[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo9[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo10[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo11[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo12[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo13[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo14[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo15[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo16[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo17[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo18[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo19[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo21[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo22[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo23[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo24[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo25[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo26[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo27[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo28[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo29[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo30[] = { { X86::RSTRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo31[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo32[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo33[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo34[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo35[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo36[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo37[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo38[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo39[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo40[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo41[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo42[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo43[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo44[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo45[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo46[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo52[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo53[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo54[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo65[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { X86::FR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo80[] = { { X86::FR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo81[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo82[] = { { X86::FR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo83[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { X86::FR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo88[] = { { X86::GR64RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo89[] = { { X86::GR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo91[] = { { X86::GR8RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, };
+static const TargetOperandInfo OperandInfo92[] = { { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo93[] = { { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo94[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo95[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo96[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo97[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo98[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo99[] = { { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo100[] = { { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo101[] = { { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo102[] = { { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo103[] = { { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo104[] = { { X86::FR64RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo105[] = { { X86::FR32RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo106[] = { { X86::RFP32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo107[] = { { X86::RFP64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo108[] = { { X86::RFP80RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo109[] = { { X86::GR16RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo110[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo111[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo112[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo113[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo114[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo115[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo116[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo117[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo118[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo119[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo120[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo121[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo122[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo123[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo124[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo125[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo126[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo127[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo128[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo129[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo130[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo131[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo132[] = { { X86::VR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo133[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo134[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo135[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo136[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo137[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo138[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo139[] = { { X86::GR32RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo140[] = { { X86::VR64RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo141[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo142[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo143[] = { { X86::VR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo144[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo145[] = { { X86::GR16RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo146[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo147[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo148[] = { { X86::GR64RegClassID, 0, 0 }, { X86::SEGMENT_REGRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo149[] = { { X86::SEGMENT_REGRegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo150[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo152[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR64_NOREXRegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo153[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo154[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo155[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo156[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo157[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo158[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo159[] = { { X86::FR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo160[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo161[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo162[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo163[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo164[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo165[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo166[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo167[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo168[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo169[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo170[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo171[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo172[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo173[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo174[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo175[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo176[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo177[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo178[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo179[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo180[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo181[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo182[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo183[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo184[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo185[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo186[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo187[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo188[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo189[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo190[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo191[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo192[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo193[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo194[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo195[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo196[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo197[] = { { X86::VR128RegClassID, 0, 0 }, };
+
+static const TargetInstrDesc X86Insts[] = {
+ { 0, 0, 0, 0, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
+ { 1, 0, 0, 0, "INLINEASM", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM
+ { 2, 1, 0, 0, "DBG_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #2 = DBG_LABEL
+ { 3, 1, 0, 0, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #3 = EH_LABEL
+ { 4, 1, 0, 0, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #4 = GC_LABEL
+ { 5, 0, 0, 0, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
+ { 6, 3, 1, 0, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo75 }, // Inst #6 = EXTRACT_SUBREG
+ { 7, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo115 }, // Inst #7 = INSERT_SUBREG
+ { 8, 1, 1, 0, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF
+ { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo193 }, // Inst #9 = SUBREG_TO_REG
+ { 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo75 }, // Inst #10 = COPY_TO_REGCLASS
+ { 11, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #11 = ABS_F
+ { 12, 2, 1, 0, "ABS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ABS_Fp32
+ { 13, 2, 1, 0, "ABS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ABS_Fp64
+ { 14, 2, 1, 0, "ABS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #14 = ABS_Fp80
+ { 15, 1, 0, 0, "ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #15 = ADC16i16
+ { 16, 6, 0, 0, "ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #16 = ADC16mi
+ { 17, 6, 0, 0, "ADC16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #17 = ADC16mi8
+ { 18, 6, 0, 0, "ADC16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #18 = ADC16mr
+ { 19, 3, 1, 0, "ADC16ri", 0, 0|18|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #19 = ADC16ri
+ { 20, 3, 1, 0, "ADC16ri8", 0, 0|18|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri8
+ { 21, 7, 1, 0, "ADC16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #21 = ADC16rm
+ { 22, 3, 1, 0, "ADC16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #22 = ADC16rr
+ { 23, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #23 = ADC32i32
+ { 24, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #24 = ADC32mi
+ { 25, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #25 = ADC32mi8
+ { 26, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #26 = ADC32mr
+ { 27, 3, 1, 0, "ADC32ri", 0, 0|18|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #27 = ADC32ri
+ { 28, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #28 = ADC32ri8
+ { 29, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #29 = ADC32rm
+ { 30, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #30 = ADC32rr
+ { 31, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #31 = ADC64i32
+ { 32, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #32 = ADC64mi32
+ { 33, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #33 = ADC64mi8
+ { 34, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #34 = ADC64mr
+ { 35, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #35 = ADC64ri32
+ { 36, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #36 = ADC64ri8
+ { 37, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #37 = ADC64rm
+ { 38, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #38 = ADC64rr
+ { 39, 1, 0, 0, "ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(20<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #39 = ADC8i8
+ { 40, 6, 0, 0, "ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #40 = ADC8mi
+ { 41, 6, 0, 0, "ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #41 = ADC8mr
+ { 42, 3, 1, 0, "ADC8ri", 0, 0|18|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #42 = ADC8ri
+ { 43, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #43 = ADC8rm
+ { 44, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #44 = ADC8rr
+ { 45, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #45 = ADD16i16
+ { 46, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #46 = ADD16mi
+ { 47, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #47 = ADD16mi8
+ { 48, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #48 = ADD16mr
+ { 49, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #49 = ADD16mrmrr
+ { 50, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #50 = ADD16ri
+ { 51, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #51 = ADD16ri8
+ { 52, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #52 = ADD16rm
+ { 53, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #53 = ADD16rr
+ { 54, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #54 = ADD32i32
+ { 55, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #55 = ADD32mi
+ { 56, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #56 = ADD32mi8
+ { 57, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #57 = ADD32mr
+ { 58, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #58 = ADD32mrmrr
+ { 59, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #59 = ADD32ri
+ { 60, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #60 = ADD32ri8
+ { 61, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #61 = ADD32rm
+ { 62, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #62 = ADD32rr
+ { 63, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #63 = ADD64i32
+ { 64, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #64 = ADD64mi32
+ { 65, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #65 = ADD64mi8
+ { 66, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #66 = ADD64mr
+ { 67, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #67 = ADD64mrmrr
+ { 68, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #68 = ADD64ri32
+ { 69, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #69 = ADD64ri8
+ { 70, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #70 = ADD64rm
+ { 71, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #71 = ADD64rr
+ { 72, 1, 0, 0, "ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(4<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #72 = ADD8i8
+ { 73, 6, 0, 0, "ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #73 = ADD8mi
+ { 74, 6, 0, 0, "ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4, NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #74 = ADD8mr
+ { 75, 3, 1, 0, "ADD8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #75 = ADD8mrmrr
+ { 76, 3, 1, 0, "ADD8ri", 0, 0|16|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #76 = ADD8ri
+ { 77, 7, 1, 0, "ADD8rm", 0|(1<<TID::MayLoad), 0|6|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #77 = ADD8rm
+ { 78, 3, 1, 0, "ADD8rr", 0|(1<<TID::Commutable), 0|3, NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #78 = ADD8rr
+ { 79, 7, 1, 0, "ADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #79 = ADDPDrm
+ { 80, 3, 1, 0, "ADDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #80 = ADDPDrr
+ { 81, 7, 1, 0, "ADDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #81 = ADDPSrm
+ { 82, 3, 1, 0, "ADDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #82 = ADDPSrr
+ { 83, 7, 1, 0, "ADDSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #83 = ADDSDrm
+ { 84, 7, 1, 0, "ADDSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #84 = ADDSDrm_Int
+ { 85, 3, 1, 0, "ADDSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #85 = ADDSDrr
+ { 86, 3, 1, 0, "ADDSDrr_Int", 0, 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #86 = ADDSDrr_Int
+ { 87, 7, 1, 0, "ADDSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #87 = ADDSSrm
+ { 88, 7, 1, 0, "ADDSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #88 = ADDSSrm_Int
+ { 89, 3, 1, 0, "ADDSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #89 = ADDSSrr
+ { 90, 3, 1, 0, "ADDSSrr_Int", 0, 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #90 = ADDSSrr_Int
+ { 91, 7, 1, 0, "ADDSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #91 = ADDSUBPDrm
+ { 92, 3, 1, 0, "ADDSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #92 = ADDSUBPDrr
+ { 93, 7, 1, 0, "ADDSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #93 = ADDSUBPSrm
+ { 94, 3, 1, 0, "ADDSUBPSrr", 0, 0|5|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #94 = ADDSUBPSrr
+ { 95, 5, 0, 0, "ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #95 = ADD_F32m
+ { 96, 5, 0, 0, "ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #96 = ADD_F64m
+ { 97, 5, 0, 0, "ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #97 = ADD_FI16m
+ { 98, 5, 0, 0, "ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #98 = ADD_FI32m
+ { 99, 1, 0, 0, "ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #99 = ADD_FPrST0
+ { 100, 1, 0, 0, "ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #100 = ADD_FST0r
+ { 101, 3, 1, 0, "ADD_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #101 = ADD_Fp32
+ { 102, 7, 1, 0, "ADD_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #102 = ADD_Fp32m
+ { 103, 3, 1, 0, "ADD_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #103 = ADD_Fp64
+ { 104, 7, 1, 0, "ADD_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #104 = ADD_Fp64m
+ { 105, 7, 1, 0, "ADD_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #105 = ADD_Fp64m32
+ { 106, 3, 1, 0, "ADD_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #106 = ADD_Fp80
+ { 107, 7, 1, 0, "ADD_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #107 = ADD_Fp80m32
+ { 108, 7, 1, 0, "ADD_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #108 = ADD_Fp80m64
+ { 109, 7, 1, 0, "ADD_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #109 = ADD_FpI16m32
+ { 110, 7, 1, 0, "ADD_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #110 = ADD_FpI16m64
+ { 111, 7, 1, 0, "ADD_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #111 = ADD_FpI16m80
+ { 112, 7, 1, 0, "ADD_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #112 = ADD_FpI32m32
+ { 113, 7, 1, 0, "ADD_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #113 = ADD_FpI32m64
+ { 114, 7, 1, 0, "ADD_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #114 = ADD_FpI32m80
+ { 115, 1, 0, 0, "ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #115 = ADD_FrST0
+ { 116, 1, 0, 0, "ADJCALLSTACKDOWN32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo5 }, // Inst #116 = ADJCALLSTACKDOWN32
+ { 117, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #117 = ADJCALLSTACKDOWN64
+ { 118, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo37 }, // Inst #118 = ADJCALLSTACKUP32
+ { 119, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo37 }, // Inst #119 = ADJCALLSTACKUP64
+ { 120, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #120 = AND16i16
+ { 121, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #121 = AND16mi
+ { 122, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #122 = AND16mi8
+ { 123, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #123 = AND16mr
+ { 124, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #124 = AND16ri
+ { 125, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #125 = AND16ri8
+ { 126, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #126 = AND16rm
+ { 127, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #127 = AND16rr
+ { 128, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #128 = AND32i32
+ { 129, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #129 = AND32mi
+ { 130, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #130 = AND32mi8
+ { 131, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #131 = AND32mr
+ { 132, 3, 1, 0, "AND32ri", 0, 0|20|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #132 = AND32ri
+ { 133, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #133 = AND32ri8
+ { 134, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #134 = AND32rm
+ { 135, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #135 = AND32rr
+ { 136, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #136 = AND64i32
+ { 137, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #137 = AND64mi32
+ { 138, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #138 = AND64mi8
+ { 139, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #139 = AND64mr
+ { 140, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #140 = AND64ri32
+ { 141, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #141 = AND64ri8
+ { 142, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #142 = AND64rm
+ { 143, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #143 = AND64rr
+ { 144, 1, 0, 0, "AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(36<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #144 = AND8i8
+ { 145, 6, 0, 0, "AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #145 = AND8mi
+ { 146, 6, 0, 0, "AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #146 = AND8mr
+ { 147, 3, 1, 0, "AND8ri", 0, 0|20|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #147 = AND8ri
+ { 148, 7, 1, 0, "AND8rm", 0|(1<<TID::MayLoad), 0|6|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #148 = AND8rm
+ { 149, 3, 1, 0, "AND8rr", 0|(1<<TID::Commutable), 0|3|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #149 = AND8rr
+ { 150, 7, 1, 0, "ANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #150 = ANDNPDrm
+ { 151, 3, 1, 0, "ANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #151 = ANDNPDrr
+ { 152, 7, 1, 0, "ANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #152 = ANDNPSrm
+ { 153, 3, 1, 0, "ANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #153 = ANDNPSrr
+ { 154, 7, 1, 0, "ANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #154 = ANDPDrm
+ { 155, 3, 1, 0, "ANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #155 = ANDPDrr
+ { 156, 7, 1, 0, "ANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #156 = ANDPSrm
+ { 157, 3, 1, 0, "ANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #157 = ANDPSrr
+ { 158, 9, 2, 0, "ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #158 = ATOMADD6432
+ { 159, 7, 1, 0, "ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #159 = ATOMAND16
+ { 160, 7, 1, 0, "ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #160 = ATOMAND32
+ { 161, 7, 1, 0, "ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #161 = ATOMAND64
+ { 162, 9, 2, 0, "ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #162 = ATOMAND6432
+ { 163, 7, 1, 0, "ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #163 = ATOMAND8
+ { 164, 7, 1, 0, "ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #164 = ATOMMAX16
+ { 165, 7, 1, 0, "ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #165 = ATOMMAX32
+ { 166, 7, 1, 0, "ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #166 = ATOMMAX64
+ { 167, 7, 1, 0, "ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #167 = ATOMMIN16
+ { 168, 7, 1, 0, "ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #168 = ATOMMIN32
+ { 169, 7, 1, 0, "ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #169 = ATOMMIN64
+ { 170, 7, 1, 0, "ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #170 = ATOMNAND16
+ { 171, 7, 1, 0, "ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #171 = ATOMNAND32
+ { 172, 7, 1, 0, "ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #172 = ATOMNAND64
+ { 173, 9, 2, 0, "ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #173 = ATOMNAND6432
+ { 174, 7, 1, 0, "ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #174 = ATOMNAND8
+ { 175, 7, 1, 0, "ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #175 = ATOMOR16
+ { 176, 7, 1, 0, "ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #176 = ATOMOR32
+ { 177, 7, 1, 0, "ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #177 = ATOMOR64
+ { 178, 9, 2, 0, "ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #178 = ATOMOR6432
+ { 179, 7, 1, 0, "ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #179 = ATOMOR8
+ { 180, 9, 2, 0, "ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #180 = ATOMSUB6432
+ { 181, 9, 2, 0, "ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #181 = ATOMSWAP6432
+ { 182, 7, 1, 0, "ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #182 = ATOMUMAX16
+ { 183, 7, 1, 0, "ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #183 = ATOMUMAX32
+ { 184, 7, 1, 0, "ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #184 = ATOMUMAX64
+ { 185, 7, 1, 0, "ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #185 = ATOMUMIN16
+ { 186, 7, 1, 0, "ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #186 = ATOMUMIN32
+ { 187, 7, 1, 0, "ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #187 = ATOMUMIN64
+ { 188, 7, 1, 0, "ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #188 = ATOMXOR16
+ { 189, 7, 1, 0, "ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #189 = ATOMXOR32
+ { 190, 7, 1, 0, "ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #190 = ATOMXOR64
+ { 191, 9, 2, 0, "ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo38 }, // Inst #191 = ATOMXOR6432
+ { 192, 7, 1, 0, "ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #192 = ATOMXOR8
+ { 193, 8, 1, 0, "BLENDPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #193 = BLENDPDrmi
+ { 194, 4, 1, 0, "BLENDPDrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #194 = BLENDPDrri
+ { 195, 8, 1, 0, "BLENDPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #195 = BLENDPSrmi
+ { 196, 4, 1, 0, "BLENDPSrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #196 = BLENDPSrri
+ { 197, 7, 1, 0, "BLENDVPDrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo23 }, // Inst #197 = BLENDVPDrm0
+ { 198, 3, 1, 0, "BLENDVPDrr0", 0, 0|5|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #198 = BLENDVPDrr0
+ { 199, 7, 1, 0, "BLENDVPSrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo23 }, // Inst #199 = BLENDVPSrm0
+ { 200, 3, 1, 0, "BLENDVPSrr0", 0, 0|5|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #200 = BLENDVPSrr0
+ { 201, 6, 1, 0, "BSF16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #201 = BSF16rm
+ { 202, 2, 1, 0, "BSF16rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #202 = BSF16rr
+ { 203, 6, 1, 0, "BSF32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #203 = BSF32rm
+ { 204, 2, 1, 0, "BSF32rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #204 = BSF32rr
+ { 205, 6, 1, 0, "BSF64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #205 = BSF64rm
+ { 206, 2, 1, 0, "BSF64rr", 0, 0|5|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #206 = BSF64rr
+ { 207, 6, 1, 0, "BSR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #207 = BSR16rm
+ { 208, 2, 1, 0, "BSR16rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #208 = BSR16rr
+ { 209, 6, 1, 0, "BSR32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #209 = BSR32rm
+ { 210, 2, 1, 0, "BSR32rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #210 = BSR32rr
+ { 211, 6, 1, 0, "BSR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #211 = BSR64rm
+ { 212, 2, 1, 0, "BSR64rr", 0, 0|5|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #212 = BSR64rr
+ { 213, 2, 1, 0, "BSWAP32r", 0, 0|2|(1<<8)|(200<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #213 = BSWAP32r
+ { 214, 2, 1, 0, "BSWAP64r", 0, 0|2|(1<<8)|(1<<12)|(200<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #214 = BSWAP64r
+ { 215, 6, 0, 0, "BT16mi8", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #215 = BT16mi8
+ { 216, 2, 0, 0, "BT16ri8", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #216 = BT16ri8
+ { 217, 2, 0, 0, "BT16rr", 0, 0|3|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #217 = BT16rr
+ { 218, 6, 0, 0, "BT32mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #218 = BT32mi8
+ { 219, 2, 0, 0, "BT32ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #219 = BT32ri8
+ { 220, 2, 0, 0, "BT32rr", 0, 0|3|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #220 = BT32rr
+ { 221, 6, 0, 0, "BT64mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #221 = BT64mi8
+ { 222, 2, 0, 0, "BT64ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #222 = BT64ri8
+ { 223, 2, 0, 0, "BT64rr", 0, 0|3|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #223 = BT64rr
+ { 224, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo29 }, // Inst #224 = CALL32m
+ { 225, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo56 }, // Inst #225 = CALL32r
+ { 226, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo29 }, // Inst #226 = CALL64m
+ { 227, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #227 = CALL64pcrel32
+ { 228, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo57 }, // Inst #228 = CALL64r
+ { 229, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #229 = CALLpcrel32
+ { 230, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #230 = CBW
+ { 231, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #231 = CDQ
+ { 232, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #232 = CDQE
+ { 233, 0, 0, 0, "CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(224<<24), NULL, NULL, NULL, 0 }, // Inst #233 = CHS_F
+ { 234, 2, 1, 0, "CHS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #234 = CHS_Fp32
+ { 235, 2, 1, 0, "CHS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #235 = CHS_Fp64
+ { 236, 2, 1, 0, "CHS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #236 = CHS_Fp80
+ { 237, 5, 0, 0, "CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #237 = CLFLUSH
+ { 238, 7, 1, 0, "CMOVA16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #238 = CMOVA16rm
+ { 239, 3, 1, 0, "CMOVA16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #239 = CMOVA16rr
+ { 240, 7, 1, 0, "CMOVA32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #240 = CMOVA32rm
+ { 241, 3, 1, 0, "CMOVA32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #241 = CMOVA32rr
+ { 242, 7, 1, 0, "CMOVA64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #242 = CMOVA64rm
+ { 243, 3, 1, 0, "CMOVA64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #243 = CMOVA64rr
+ { 244, 7, 1, 0, "CMOVAE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #244 = CMOVAE16rm
+ { 245, 3, 1, 0, "CMOVAE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #245 = CMOVAE16rr
+ { 246, 7, 1, 0, "CMOVAE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #246 = CMOVAE32rm
+ { 247, 3, 1, 0, "CMOVAE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #247 = CMOVAE32rr
+ { 248, 7, 1, 0, "CMOVAE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #248 = CMOVAE64rm
+ { 249, 3, 1, 0, "CMOVAE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #249 = CMOVAE64rr
+ { 250, 7, 1, 0, "CMOVB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #250 = CMOVB16rm
+ { 251, 3, 1, 0, "CMOVB16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #251 = CMOVB16rr
+ { 252, 7, 1, 0, "CMOVB32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #252 = CMOVB32rm
+ { 253, 3, 1, 0, "CMOVB32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #253 = CMOVB32rr
+ { 254, 7, 1, 0, "CMOVB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #254 = CMOVB64rm
+ { 255, 3, 1, 0, "CMOVB64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #255 = CMOVB64rr
+ { 256, 7, 1, 0, "CMOVBE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #256 = CMOVBE16rm
+ { 257, 3, 1, 0, "CMOVBE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #257 = CMOVBE16rr
+ { 258, 7, 1, 0, "CMOVBE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #258 = CMOVBE32rm
+ { 259, 3, 1, 0, "CMOVBE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #259 = CMOVBE32rr
+ { 260, 7, 1, 0, "CMOVBE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #260 = CMOVBE64rm
+ { 261, 3, 1, 0, "CMOVBE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #261 = CMOVBE64rr
+ { 262, 1, 1, 0, "CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(208<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #262 = CMOVBE_F
+ { 263, 3, 1, 0, "CMOVBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #263 = CMOVBE_Fp32
+ { 264, 3, 1, 0, "CMOVBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #264 = CMOVBE_Fp64
+ { 265, 3, 1, 0, "CMOVBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #265 = CMOVBE_Fp80
+ { 266, 1, 1, 0, "CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #266 = CMOVB_F
+ { 267, 3, 1, 0, "CMOVB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #267 = CMOVB_Fp32
+ { 268, 3, 1, 0, "CMOVB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #268 = CMOVB_Fp64
+ { 269, 3, 1, 0, "CMOVB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #269 = CMOVB_Fp80
+ { 270, 7, 1, 0, "CMOVE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #270 = CMOVE16rm
+ { 271, 3, 1, 0, "CMOVE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #271 = CMOVE16rr
+ { 272, 7, 1, 0, "CMOVE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #272 = CMOVE32rm
+ { 273, 3, 1, 0, "CMOVE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #273 = CMOVE32rr
+ { 274, 7, 1, 0, "CMOVE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #274 = CMOVE64rm
+ { 275, 3, 1, 0, "CMOVE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #275 = CMOVE64rr
+ { 276, 1, 1, 0, "CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #276 = CMOVE_F
+ { 277, 3, 1, 0, "CMOVE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #277 = CMOVE_Fp32
+ { 278, 3, 1, 0, "CMOVE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #278 = CMOVE_Fp64
+ { 279, 3, 1, 0, "CMOVE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #279 = CMOVE_Fp80
+ { 280, 7, 1, 0, "CMOVG16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #280 = CMOVG16rm
+ { 281, 3, 1, 0, "CMOVG16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #281 = CMOVG16rr
+ { 282, 7, 1, 0, "CMOVG32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #282 = CMOVG32rm
+ { 283, 3, 1, 0, "CMOVG32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #283 = CMOVG32rr
+ { 284, 7, 1, 0, "CMOVG64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #284 = CMOVG64rm
+ { 285, 3, 1, 0, "CMOVG64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #285 = CMOVG64rr
+ { 286, 7, 1, 0, "CMOVGE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #286 = CMOVGE16rm
+ { 287, 3, 1, 0, "CMOVGE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #287 = CMOVGE16rr
+ { 288, 7, 1, 0, "CMOVGE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #288 = CMOVGE32rm
+ { 289, 3, 1, 0, "CMOVGE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #289 = CMOVGE32rr
+ { 290, 7, 1, 0, "CMOVGE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #290 = CMOVGE64rm
+ { 291, 3, 1, 0, "CMOVGE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #291 = CMOVGE64rr
+ { 292, 7, 1, 0, "CMOVL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #292 = CMOVL16rm
+ { 293, 3, 1, 0, "CMOVL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #293 = CMOVL16rr
+ { 294, 7, 1, 0, "CMOVL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #294 = CMOVL32rm
+ { 295, 3, 1, 0, "CMOVL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #295 = CMOVL32rr
+ { 296, 7, 1, 0, "CMOVL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #296 = CMOVL64rm
+ { 297, 3, 1, 0, "CMOVL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #297 = CMOVL64rr
+ { 298, 7, 1, 0, "CMOVLE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #298 = CMOVLE16rm
+ { 299, 3, 1, 0, "CMOVLE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #299 = CMOVLE16rr
+ { 300, 7, 1, 0, "CMOVLE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #300 = CMOVLE32rm
+ { 301, 3, 1, 0, "CMOVLE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #301 = CMOVLE32rr
+ { 302, 7, 1, 0, "CMOVLE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #302 = CMOVLE64rm
+ { 303, 3, 1, 0, "CMOVLE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #303 = CMOVLE64rr
+ { 304, 1, 1, 0, "CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(208<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #304 = CMOVNBE_F
+ { 305, 3, 1, 0, "CMOVNBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #305 = CMOVNBE_Fp32
+ { 306, 3, 1, 0, "CMOVNBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #306 = CMOVNBE_Fp64
+ { 307, 3, 1, 0, "CMOVNBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #307 = CMOVNBE_Fp80
+ { 308, 1, 1, 0, "CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #308 = CMOVNB_F
+ { 309, 3, 1, 0, "CMOVNB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #309 = CMOVNB_Fp32
+ { 310, 3, 1, 0, "CMOVNB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #310 = CMOVNB_Fp64
+ { 311, 3, 1, 0, "CMOVNB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #311 = CMOVNB_Fp80
+ { 312, 7, 1, 0, "CMOVNE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #312 = CMOVNE16rm
+ { 313, 3, 1, 0, "CMOVNE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #313 = CMOVNE16rr
+ { 314, 7, 1, 0, "CMOVNE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #314 = CMOVNE32rm
+ { 315, 3, 1, 0, "CMOVNE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #315 = CMOVNE32rr
+ { 316, 7, 1, 0, "CMOVNE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #316 = CMOVNE64rm
+ { 317, 3, 1, 0, "CMOVNE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #317 = CMOVNE64rr
+ { 318, 1, 1, 0, "CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #318 = CMOVNE_F
+ { 319, 3, 1, 0, "CMOVNE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #319 = CMOVNE_Fp32
+ { 320, 3, 1, 0, "CMOVNE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #320 = CMOVNE_Fp64
+ { 321, 3, 1, 0, "CMOVNE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #321 = CMOVNE_Fp80
+ { 322, 7, 1, 0, "CMOVNO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #322 = CMOVNO16rm
+ { 323, 3, 1, 0, "CMOVNO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #323 = CMOVNO16rr
+ { 324, 7, 1, 0, "CMOVNO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #324 = CMOVNO32rm
+ { 325, 3, 1, 0, "CMOVNO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #325 = CMOVNO32rr
+ { 326, 7, 1, 0, "CMOVNO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #326 = CMOVNO64rm
+ { 327, 3, 1, 0, "CMOVNO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #327 = CMOVNO64rr
+ { 328, 7, 1, 0, "CMOVNP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #328 = CMOVNP16rm
+ { 329, 3, 1, 0, "CMOVNP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #329 = CMOVNP16rr
+ { 330, 7, 1, 0, "CMOVNP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #330 = CMOVNP32rm
+ { 331, 3, 1, 0, "CMOVNP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #331 = CMOVNP32rr
+ { 332, 7, 1, 0, "CMOVNP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #332 = CMOVNP64rm
+ { 333, 3, 1, 0, "CMOVNP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #333 = CMOVNP64rr
+ { 334, 1, 1, 0, "CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #334 = CMOVNP_F
+ { 335, 3, 1, 0, "CMOVNP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #335 = CMOVNP_Fp32
+ { 336, 3, 1, 0, "CMOVNP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #336 = CMOVNP_Fp64
+ { 337, 3, 1, 0, "CMOVNP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #337 = CMOVNP_Fp80
+ { 338, 7, 1, 0, "CMOVNS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #338 = CMOVNS16rm
+ { 339, 3, 1, 0, "CMOVNS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #339 = CMOVNS16rr
+ { 340, 7, 1, 0, "CMOVNS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #340 = CMOVNS32rm
+ { 341, 3, 1, 0, "CMOVNS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #341 = CMOVNS32rr
+ { 342, 7, 1, 0, "CMOVNS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #342 = CMOVNS64rm
+ { 343, 3, 1, 0, "CMOVNS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #343 = CMOVNS64rr
+ { 344, 7, 1, 0, "CMOVO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #344 = CMOVO16rm
+ { 345, 3, 1, 0, "CMOVO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #345 = CMOVO16rr
+ { 346, 7, 1, 0, "CMOVO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #346 = CMOVO32rm
+ { 347, 3, 1, 0, "CMOVO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #347 = CMOVO32rr
+ { 348, 7, 1, 0, "CMOVO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #348 = CMOVO64rm
+ { 349, 3, 1, 0, "CMOVO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #349 = CMOVO64rr
+ { 350, 7, 1, 0, "CMOVP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #350 = CMOVP16rm
+ { 351, 3, 1, 0, "CMOVP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #351 = CMOVP16rr
+ { 352, 7, 1, 0, "CMOVP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #352 = CMOVP32rm
+ { 353, 3, 1, 0, "CMOVP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #353 = CMOVP32rr
+ { 354, 7, 1, 0, "CMOVP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #354 = CMOVP64rm
+ { 355, 3, 1, 0, "CMOVP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #355 = CMOVP64rr
+ { 356, 1, 1, 0, "CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #356 = CMOVP_F
+ { 357, 3, 1, 0, "CMOVP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo58 }, // Inst #357 = CMOVP_Fp32
+ { 358, 3, 1, 0, "CMOVP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #358 = CMOVP_Fp64
+ { 359, 3, 1, 0, "CMOVP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #359 = CMOVP_Fp80
+ { 360, 7, 1, 0, "CMOVS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #360 = CMOVS16rm
+ { 361, 3, 1, 0, "CMOVS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #361 = CMOVS16rr
+ { 362, 7, 1, 0, "CMOVS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #362 = CMOVS32rm
+ { 363, 3, 1, 0, "CMOVS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #363 = CMOVS32rr
+ { 364, 7, 1, 0, "CMOVS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #364 = CMOVS64rm
+ { 365, 3, 1, 0, "CMOVS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #365 = CMOVS64rr
+ { 366, 4, 1, 0, "CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #366 = CMOV_FR32
+ { 367, 4, 1, 0, "CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo62 }, // Inst #367 = CMOV_FR64
+ { 368, 4, 1, 0, "CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, ImplicitList1, Barriers1, OperandInfo63 }, // Inst #368 = CMOV_GR8
+ { 369, 4, 1, 0, "CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo64 }, // Inst #369 = CMOV_V1I64
+ { 370, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #370 = CMOV_V2F64
+ { 371, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #371 = CMOV_V2I64
+ { 372, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #372 = CMOV_V4F32
+ { 373, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #373 = CMP16i16
+ { 374, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #374 = CMP16mi
+ { 375, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #375 = CMP16mi8
+ { 376, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #376 = CMP16mr
+ { 377, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #377 = CMP16mrmrr
+ { 378, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #378 = CMP16ri
+ { 379, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #379 = CMP16ri8
+ { 380, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #380 = CMP16rm
+ { 381, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #381 = CMP16rr
+ { 382, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #382 = CMP32i32
+ { 383, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #383 = CMP32mi
+ { 384, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #384 = CMP32mi8
+ { 385, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #385 = CMP32mr
+ { 386, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #386 = CMP32mrmrr
+ { 387, 2, 0, 0, "CMP32ri", 0, 0|23|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #387 = CMP32ri
+ { 388, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #388 = CMP32ri8
+ { 389, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #389 = CMP32rm
+ { 390, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #390 = CMP32rr
+ { 391, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #391 = CMP64i32
+ { 392, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #392 = CMP64mi32
+ { 393, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #393 = CMP64mi8
+ { 394, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #394 = CMP64mr
+ { 395, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #395 = CMP64mrmrr
+ { 396, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #396 = CMP64ri32
+ { 397, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #397 = CMP64ri8
+ { 398, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #398 = CMP64rm
+ { 399, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #399 = CMP64rr
+ { 400, 1, 0, 0, "CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(60<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #400 = CMP8i8
+ { 401, 6, 0, 0, "CMP8mi", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #401 = CMP8mi
+ { 402, 6, 0, 0, "CMP8mr", 0|(1<<TID::MayLoad), 0|4|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #402 = CMP8mr
+ { 403, 2, 0, 0, "CMP8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #403 = CMP8mrmrr
+ { 404, 2, 0, 0, "CMP8ri", 0, 0|23|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #404 = CMP8ri
+ { 405, 6, 0, 0, "CMP8rm", 0|(1<<TID::MayLoad), 0|6|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #405 = CMP8rm
+ { 406, 2, 0, 0, "CMP8rr", 0, 0|3|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #406 = CMP8rr
+ { 407, 8, 1, 0, "CMPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #407 = CMPPDrmi
+ { 408, 4, 1, 0, "CMPPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #408 = CMPPDrri
+ { 409, 8, 1, 0, "CMPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #409 = CMPPSrmi
+ { 410, 4, 1, 0, "CMPPSrri", 0, 0|5|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #410 = CMPPSrri
+ { 411, 0, 0, 0, "CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #411 = CMPS16
+ { 412, 0, 0, 0, "CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(167<<24), NULL, NULL, NULL, 0 }, // Inst #412 = CMPS32
+ { 413, 0, 0, 0, "CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #413 = CMPS64
+ { 414, 0, 0, 0, "CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(166<<24), NULL, NULL, NULL, 0 }, // Inst #414 = CMPS8
+ { 415, 8, 1, 0, "CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #415 = CMPSDrm
+ { 416, 4, 1, 0, "CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo70 }, // Inst #416 = CMPSDrr
+ { 417, 8, 1, 0, "CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo71 }, // Inst #417 = CMPSSrm
+ { 418, 4, 1, 0, "CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo72 }, // Inst #418 = CMPSSrr
+ { 419, 6, 0, 0, "COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #419 = COMISDrm
+ { 420, 2, 0, 0, "COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #420 = COMISDrr
+ { 421, 0, 0, 0, "COS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(255<<24), NULL, NULL, NULL, 0 }, // Inst #421 = COS_F
+ { 422, 2, 1, 0, "COS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #422 = COS_Fp32
+ { 423, 2, 1, 0, "COS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #423 = COS_Fp64
+ { 424, 2, 1, 0, "COS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #424 = COS_Fp80
+ { 425, 0, 0, 0, "CQO", 0, 0|1|(1<<12)|(153<<24), ImplicitList15, ImplicitList16, NULL, 0 }, // Inst #425 = CQO
+ { 426, 7, 1, 0, "CRC32m16", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #426 = CRC32m16
+ { 427, 7, 1, 0, "CRC32m32", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #427 = CRC32m32
+ { 428, 7, 1, 0, "CRC32m8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #428 = CRC32m8
+ { 429, 3, 1, 0, "CRC32r16", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo76 }, // Inst #429 = CRC32r16
+ { 430, 3, 1, 0, "CRC32r32", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #430 = CRC32r32
+ { 431, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo77 }, // Inst #431 = CRC32r8
+ { 432, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #432 = CRC64m64
+ { 433, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #433 = CRC64r64
+ { 434, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #434 = CVTDQ2PDrm
+ { 435, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #435 = CVTDQ2PDrr
+ { 436, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #436 = CVTDQ2PSrm
+ { 437, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #437 = CVTDQ2PSrr
+ { 438, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #438 = CVTPD2DQrm
+ { 439, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #439 = CVTPD2DQrr
+ { 440, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #440 = CVTPS2DQrm
+ { 441, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #441 = CVTPS2DQrr
+ { 442, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #442 = CVTSD2SSrm
+ { 443, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #443 = CVTSD2SSrr
+ { 444, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #444 = CVTSI2SD64rm
+ { 445, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #445 = CVTSI2SD64rr
+ { 446, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #446 = CVTSI2SDrm
+ { 447, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #447 = CVTSI2SDrr
+ { 448, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #448 = CVTSI2SS64rm
+ { 449, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #449 = CVTSI2SS64rr
+ { 450, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #450 = CVTSI2SSrm
+ { 451, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #451 = CVTSI2SSrr
+ { 452, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #452 = CVTSS2SDrm
+ { 453, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = CVTSS2SDrr
+ { 454, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #454 = CVTTSD2SI64rm
+ { 455, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #455 = CVTTSD2SI64rr
+ { 456, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #456 = CVTTSD2SIrm
+ { 457, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #457 = CVTTSD2SIrr
+ { 458, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #458 = CVTTSS2SI64rm
+ { 459, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #459 = CVTTSS2SI64rr
+ { 460, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #460 = CVTTSS2SIrm
+ { 461, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #461 = CVTTSS2SIrr
+ { 462, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList17, NULL, 0 }, // Inst #462 = CWD
+ { 463, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #463 = CWDE
+ { 464, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #464 = DEC16m
+ { 465, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #465 = DEC16r
+ { 466, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #466 = DEC32m
+ { 467, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #467 = DEC32r
+ { 468, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #468 = DEC64_16m
+ { 469, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #469 = DEC64_16r
+ { 470, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #470 = DEC64_32m
+ { 471, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #471 = DEC64_32r
+ { 472, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #472 = DEC64m
+ { 473, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #473 = DEC64r
+ { 474, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #474 = DEC8m
+ { 475, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #475 = DEC8r
+ { 476, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #476 = DIV16m
+ { 477, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #477 = DIV16r
+ { 478, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #478 = DIV32m
+ { 479, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #479 = DIV32r
+ { 480, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #480 = DIV64m
+ { 481, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #481 = DIV64r
+ { 482, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #482 = DIV8m
+ { 483, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #483 = DIV8r
+ { 484, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #484 = DIVPDrm
+ { 485, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #485 = DIVPDrr
+ { 486, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #486 = DIVPSrm
+ { 487, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #487 = DIVPSrr
+ { 488, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #488 = DIVR_F32m
+ { 489, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #489 = DIVR_F64m
+ { 490, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #490 = DIVR_FI16m
+ { 491, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #491 = DIVR_FI32m
+ { 492, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #492 = DIVR_FPrST0
+ { 493, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #493 = DIVR_FST0r
+ { 494, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #494 = DIVR_Fp32m
+ { 495, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #495 = DIVR_Fp64m
+ { 496, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #496 = DIVR_Fp64m32
+ { 497, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #497 = DIVR_Fp80m32
+ { 498, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #498 = DIVR_Fp80m64
+ { 499, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #499 = DIVR_FpI16m32
+ { 500, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #500 = DIVR_FpI16m64
+ { 501, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #501 = DIVR_FpI16m80
+ { 502, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #502 = DIVR_FpI32m32
+ { 503, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #503 = DIVR_FpI32m64
+ { 504, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #504 = DIVR_FpI32m80
+ { 505, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #505 = DIVR_FrST0
+ { 506, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #506 = DIVSDrm
+ { 507, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #507 = DIVSDrm_Int
+ { 508, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #508 = DIVSDrr
+ { 509, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #509 = DIVSDrr_Int
+ { 510, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #510 = DIVSSrm
+ { 511, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #511 = DIVSSrm_Int
+ { 512, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #512 = DIVSSrr
+ { 513, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #513 = DIVSSrr_Int
+ { 514, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #514 = DIV_F32m
+ { 515, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #515 = DIV_F64m
+ { 516, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #516 = DIV_FI16m
+ { 517, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #517 = DIV_FI32m
+ { 518, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #518 = DIV_FPrST0
+ { 519, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #519 = DIV_FST0r
+ { 520, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #520 = DIV_Fp32
+ { 521, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #521 = DIV_Fp32m
+ { 522, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #522 = DIV_Fp64
+ { 523, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #523 = DIV_Fp64m
+ { 524, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #524 = DIV_Fp64m32
+ { 525, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #525 = DIV_Fp80
+ { 526, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #526 = DIV_Fp80m32
+ { 527, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #527 = DIV_Fp80m64
+ { 528, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #528 = DIV_FpI16m32
+ { 529, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #529 = DIV_FpI16m64
+ { 530, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #530 = DIV_FpI16m80
+ { 531, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #531 = DIV_FpI32m32
+ { 532, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #532 = DIV_FpI32m64
+ { 533, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #533 = DIV_FpI32m80
+ { 534, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #534 = DIV_FrST0
+ { 535, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #535 = DPPDrmi
+ { 536, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #536 = DPPDrri
+ { 537, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #537 = DPPSrmi
+ { 538, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #538 = DPPSrri
+ { 539, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #539 = EH_RETURN
+ { 540, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #540 = EH_RETURN64
+ { 541, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo37 }, // Inst #541 = ENTER
+ { 542, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #542 = EXTRACTPSmr
+ { 543, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #543 = EXTRACTPSrr
+ { 544, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo37 }, // Inst #544 = FARCALL16i
+ { 545, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo29 }, // Inst #545 = FARCALL16m
+ { 546, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo37 }, // Inst #546 = FARCALL32i
+ { 547, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo29 }, // Inst #547 = FARCALL32m
+ { 548, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo29 }, // Inst #548 = FARCALL64
+ { 549, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo37 }, // Inst #549 = FARJMP16i
+ { 550, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #550 = FARJMP16m
+ { 551, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo37 }, // Inst #551 = FARJMP32i
+ { 552, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #552 = FARJMP32m
+ { 553, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #553 = FARJMP64
+ { 554, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #554 = FBLDm
+ { 555, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #555 = FBSTPm
+ { 556, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #556 = FCOM32m
+ { 557, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #557 = FCOM64m
+ { 558, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #558 = FCOMP32m
+ { 559, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #559 = FCOMP64m
+ { 560, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #560 = FICOM16m
+ { 561, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #561 = FICOM32m
+ { 562, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #562 = FICOMP16m
+ { 563, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #563 = FICOMP32m
+ { 564, 5, 1, 0, "FISTTP32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #564 = FISTTP32m
+ { 565, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #565 = FLDCW16m
+ { 566, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #566 = FLDENVm
+ { 567, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #567 = FNSTCW16m
+ { 568, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #568 = FNSTSW8r
+ { 569, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo96 }, // Inst #569 = FP32_TO_INT16_IN_MEM
+ { 570, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo96 }, // Inst #570 = FP32_TO_INT32_IN_MEM
+ { 571, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo96 }, // Inst #571 = FP32_TO_INT64_IN_MEM
+ { 572, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #572 = FP64_TO_INT16_IN_MEM
+ { 573, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #573 = FP64_TO_INT32_IN_MEM
+ { 574, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #574 = FP64_TO_INT64_IN_MEM
+ { 575, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #575 = FP80_TO_INT16_IN_MEM
+ { 576, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #576 = FP80_TO_INT32_IN_MEM
+ { 577, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #577 = FP80_TO_INT64_IN_MEM
+ { 578, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList22, Barriers7, 0 }, // Inst #578 = FP_REG_KILL
+ { 579, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #579 = FRSTORm
+ { 580, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #580 = FSAVEm
+ { 581, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #581 = FSTENVm
+ { 582, 5, 1, 0, "FSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #582 = FSTSWm
+ { 583, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #583 = FS_MOV32rm
+ { 584, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #584 = FpGET_ST0_32
+ { 585, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #585 = FpGET_ST0_64
+ { 586, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #586 = FpGET_ST0_80
+ { 587, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #587 = FpGET_ST1_32
+ { 588, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #588 = FpGET_ST1_64
+ { 589, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #589 = FpGET_ST1_80
+ { 590, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo99 }, // Inst #590 = FpSET_ST0_32
+ { 591, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo100 }, // Inst #591 = FpSET_ST0_64
+ { 592, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo101 }, // Inst #592 = FpSET_ST0_80
+ { 593, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo99 }, // Inst #593 = FpSET_ST1_32
+ { 594, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #594 = FpSET_ST1_64
+ { 595, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #595 = FpSET_ST1_80
+ { 596, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #596 = FsANDNPDrm
+ { 597, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #597 = FsANDNPDrr
+ { 598, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #598 = FsANDNPSrm
+ { 599, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #599 = FsANDNPSrr
+ { 600, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #600 = FsANDPDrm
+ { 601, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #601 = FsANDPDrr
+ { 602, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #602 = FsANDPSrm
+ { 603, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #603 = FsANDPSrr
+ { 604, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo102 }, // Inst #604 = FsFLD0SD
+ { 605, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #605 = FsFLD0SS
+ { 606, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #606 = FsMOVAPDrm
+ { 607, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #607 = FsMOVAPDrr
+ { 608, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #608 = FsMOVAPSrm
+ { 609, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #609 = FsMOVAPSrr
+ { 610, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #610 = FsORPDrm
+ { 611, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #611 = FsORPDrr
+ { 612, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #612 = FsORPSrm
+ { 613, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #613 = FsORPSrr
+ { 614, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #614 = FsXORPDrm
+ { 615, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #615 = FsXORPDrr
+ { 616, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #616 = FsXORPSrm
+ { 617, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #617 = FsXORPSrr
+ { 618, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #618 = GS_MOV32rm
+ { 619, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #619 = HADDPDrm
+ { 620, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #620 = HADDPDrr
+ { 621, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #621 = HADDPSrm
+ { 622, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #622 = HADDPSrr
+ { 623, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #623 = HSUBPDrm
+ { 624, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #624 = HSUBPDrr
+ { 625, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #625 = HSUBPSrm
+ { 626, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #626 = HSUBPSrr
+ { 627, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #627 = IDIV16m
+ { 628, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #628 = IDIV16r
+ { 629, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #629 = IDIV32m
+ { 630, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #630 = IDIV32r
+ { 631, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #631 = IDIV64m
+ { 632, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #632 = IDIV64r
+ { 633, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #633 = IDIV8m
+ { 634, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #634 = IDIV8r
+ { 635, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #635 = ILD_F16m
+ { 636, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #636 = ILD_F32m
+ { 637, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #637 = ILD_F64m
+ { 638, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #638 = ILD_Fp16m32
+ { 639, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #639 = ILD_Fp16m64
+ { 640, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #640 = ILD_Fp16m80
+ { 641, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #641 = ILD_Fp32m32
+ { 642, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #642 = ILD_Fp32m64
+ { 643, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #643 = ILD_Fp32m80
+ { 644, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #644 = ILD_Fp64m32
+ { 645, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #645 = ILD_Fp64m64
+ { 646, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #646 = ILD_Fp64m80
+ { 647, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #647 = IMUL16m
+ { 648, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #648 = IMUL16r
+ { 649, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #649 = IMUL16rm
+ { 650, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo109 }, // Inst #650 = IMUL16rmi
+ { 651, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo109 }, // Inst #651 = IMUL16rmi8
+ { 652, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #652 = IMUL16rr
+ { 653, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #653 = IMUL16rri
+ { 654, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #654 = IMUL16rri8
+ { 655, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList14, Barriers5, OperandInfo29 }, // Inst #655 = IMUL32m
+ { 656, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #656 = IMUL32r
+ { 657, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #657 = IMUL32rm
+ { 658, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #658 = IMUL32rmi
+ { 659, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #659 = IMUL32rmi8
+ { 660, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #660 = IMUL32rr
+ { 661, 3, 1, 0, "IMUL32rri", 0, 0|5|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #661 = IMUL32rri
+ { 662, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #662 = IMUL32rri8
+ { 663, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #663 = IMUL64m
+ { 664, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #664 = IMUL64r
+ { 665, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #665 = IMUL64rm
+ { 666, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #666 = IMUL64rmi32
+ { 667, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #667 = IMUL64rmi8
+ { 668, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #668 = IMUL64rr
+ { 669, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #669 = IMUL64rri32
+ { 670, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #670 = IMUL64rri8
+ { 671, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #671 = IMUL8m
+ { 672, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #672 = IMUL8r
+ { 673, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #673 = IN16ri
+ { 674, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList25, ImplicitList12, NULL, 0 }, // Inst #674 = IN16rr
+ { 675, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #675 = IN32ri
+ { 676, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList25, ImplicitList13, NULL, 0 }, // Inst #676 = IN32rr
+ { 677, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #677 = IN8ri
+ { 678, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList25, ImplicitList11, NULL, 0 }, // Inst #678 = IN8rr
+ { 679, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #679 = INC16m
+ { 680, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #680 = INC16r
+ { 681, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #681 = INC32m
+ { 682, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #682 = INC32r
+ { 683, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #683 = INC64_16m
+ { 684, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #684 = INC64_16r
+ { 685, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #685 = INC64_32m
+ { 686, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #686 = INC64_32r
+ { 687, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #687 = INC64m
+ { 688, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #688 = INC64r
+ { 689, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #689 = INC8m
+ { 690, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #690 = INC8r
+ { 691, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #691 = INSERTPSrm
+ { 692, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #692 = INSERTPSrr
+ { 693, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #693 = INT
+ { 694, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #694 = INT3
+ { 695, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #695 = ISTT_FP16m
+ { 696, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #696 = ISTT_FP32m
+ { 697, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #697 = ISTT_FP64m
+ { 698, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #698 = ISTT_Fp16m32
+ { 699, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #699 = ISTT_Fp16m64
+ { 700, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #700 = ISTT_Fp16m80
+ { 701, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #701 = ISTT_Fp32m32
+ { 702, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #702 = ISTT_Fp32m64
+ { 703, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #703 = ISTT_Fp32m80
+ { 704, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #704 = ISTT_Fp64m32
+ { 705, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #705 = ISTT_Fp64m64
+ { 706, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #706 = ISTT_Fp64m80
+ { 707, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #707 = IST_F16m
+ { 708, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #708 = IST_F32m
+ { 709, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #709 = IST_FP16m
+ { 710, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #710 = IST_FP32m
+ { 711, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #711 = IST_FP64m
+ { 712, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #712 = IST_Fp16m32
+ { 713, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #713 = IST_Fp16m64
+ { 714, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #714 = IST_Fp16m80
+ { 715, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #715 = IST_Fp32m32
+ { 716, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #716 = IST_Fp32m64
+ { 717, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #717 = IST_Fp32m80
+ { 718, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #718 = IST_Fp64m32
+ { 719, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #719 = IST_Fp64m64
+ { 720, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #720 = IST_Fp64m80
+ { 721, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #721 = Int_CMPSDrm
+ { 722, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #722 = Int_CMPSDrr
+ { 723, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #723 = Int_CMPSSrm
+ { 724, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #724 = Int_CMPSSrr
+ { 725, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #725 = Int_COMISDrm
+ { 726, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #726 = Int_COMISDrr
+ { 727, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #727 = Int_COMISSrm
+ { 728, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #728 = Int_COMISSrr
+ { 729, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #729 = Int_CVTDQ2PDrm
+ { 730, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #730 = Int_CVTDQ2PDrr
+ { 731, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #731 = Int_CVTDQ2PSrm
+ { 732, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #732 = Int_CVTDQ2PSrr
+ { 733, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #733 = Int_CVTPD2DQrm
+ { 734, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #734 = Int_CVTPD2DQrr
+ { 735, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #735 = Int_CVTPD2PIrm
+ { 736, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #736 = Int_CVTPD2PIrr
+ { 737, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #737 = Int_CVTPD2PSrm
+ { 738, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #738 = Int_CVTPD2PSrr
+ { 739, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #739 = Int_CVTPI2PDrm
+ { 740, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #740 = Int_CVTPI2PDrr
+ { 741, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #741 = Int_CVTPI2PSrm
+ { 742, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #742 = Int_CVTPI2PSrr
+ { 743, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #743 = Int_CVTPS2DQrm
+ { 744, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #744 = Int_CVTPS2DQrr
+ { 745, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #745 = Int_CVTPS2PDrm
+ { 746, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #746 = Int_CVTPS2PDrr
+ { 747, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #747 = Int_CVTPS2PIrm
+ { 748, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #748 = Int_CVTPS2PIrr
+ { 749, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #749 = Int_CVTSD2SI64rm
+ { 750, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #750 = Int_CVTSD2SI64rr
+ { 751, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #751 = Int_CVTSD2SIrm
+ { 752, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #752 = Int_CVTSD2SIrr
+ { 753, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #753 = Int_CVTSD2SSrm
+ { 754, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #754 = Int_CVTSD2SSrr
+ { 755, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #755 = Int_CVTSI2SD64rm
+ { 756, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #756 = Int_CVTSI2SD64rr
+ { 757, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #757 = Int_CVTSI2SDrm
+ { 758, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #758 = Int_CVTSI2SDrr
+ { 759, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #759 = Int_CVTSI2SS64rm
+ { 760, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #760 = Int_CVTSI2SS64rr
+ { 761, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #761 = Int_CVTSI2SSrm
+ { 762, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #762 = Int_CVTSI2SSrr
+ { 763, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #763 = Int_CVTSS2SDrm
+ { 764, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #764 = Int_CVTSS2SDrr
+ { 765, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #765 = Int_CVTSS2SI64rm
+ { 766, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #766 = Int_CVTSS2SI64rr
+ { 767, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #767 = Int_CVTSS2SIrm
+ { 768, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #768 = Int_CVTSS2SIrr
+ { 769, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #769 = Int_CVTTPD2DQrm
+ { 770, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #770 = Int_CVTTPD2DQrr
+ { 771, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #771 = Int_CVTTPD2PIrm
+ { 772, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #772 = Int_CVTTPD2PIrr
+ { 773, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #773 = Int_CVTTPS2DQrm
+ { 774, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #774 = Int_CVTTPS2DQrr
+ { 775, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #775 = Int_CVTTPS2PIrm
+ { 776, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #776 = Int_CVTTPS2PIrr
+ { 777, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #777 = Int_CVTTSD2SI64rm
+ { 778, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #778 = Int_CVTTSD2SI64rr
+ { 779, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #779 = Int_CVTTSD2SIrm
+ { 780, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #780 = Int_CVTTSD2SIrr
+ { 781, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #781 = Int_CVTTSS2SI64rm
+ { 782, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #782 = Int_CVTTSS2SI64rr
+ { 783, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #783 = Int_CVTTSS2SIrm
+ { 784, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #784 = Int_CVTTSS2SIrr
+ { 785, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #785 = Int_UCOMISDrm
+ { 786, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #786 = Int_UCOMISDrr
+ { 787, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #787 = Int_UCOMISSrm
+ { 788, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #788 = Int_UCOMISSrr
+ { 789, 1, 0, 0, "JA", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #789 = JA
+ { 790, 1, 0, 0, "JA8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #790 = JA8
+ { 791, 1, 0, 0, "JAE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #791 = JAE
+ { 792, 1, 0, 0, "JAE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #792 = JAE8
+ { 793, 1, 0, 0, "JB", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #793 = JB
+ { 794, 1, 0, 0, "JB8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #794 = JB8
+ { 795, 1, 0, 0, "JBE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #795 = JBE
+ { 796, 1, 0, 0, "JBE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #796 = JBE8
+ { 797, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(227<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #797 = JCXZ8
+ { 798, 1, 0, 0, "JE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #798 = JE
+ { 799, 1, 0, 0, "JE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #799 = JE8
+ { 800, 1, 0, 0, "JG", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #800 = JG
+ { 801, 1, 0, 0, "JG8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #801 = JG8
+ { 802, 1, 0, 0, "JGE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #802 = JGE
+ { 803, 1, 0, 0, "JGE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #803 = JGE8
+ { 804, 1, 0, 0, "JL", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #804 = JL
+ { 805, 1, 0, 0, "JL8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #805 = JL8
+ { 806, 1, 0, 0, "JLE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #806 = JLE
+ { 807, 1, 0, 0, "JLE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #807 = JLE8
+ { 808, 1, 0, 0, "JMP", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #808 = JMP
+ { 809, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #809 = JMP32m
+ { 810, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #810 = JMP32r
+ { 811, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #811 = JMP64m
+ { 812, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #812 = JMP64r
+ { 813, 1, 0, 0, "JMP8", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #813 = JMP8
+ { 814, 1, 0, 0, "JNE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #814 = JNE
+ { 815, 1, 0, 0, "JNE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #815 = JNE8
+ { 816, 1, 0, 0, "JNO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #816 = JNO
+ { 817, 1, 0, 0, "JNO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #817 = JNO8
+ { 818, 1, 0, 0, "JNP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #818 = JNP
+ { 819, 1, 0, 0, "JNP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #819 = JNP8
+ { 820, 1, 0, 0, "JNS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #820 = JNS
+ { 821, 1, 0, 0, "JNS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #821 = JNS8
+ { 822, 1, 0, 0, "JO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #822 = JO
+ { 823, 1, 0, 0, "JO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #823 = JO8
+ { 824, 1, 0, 0, "JP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #824 = JP
+ { 825, 1, 0, 0, "JP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #825 = JP8
+ { 826, 1, 0, 0, "JS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #826 = JS
+ { 827, 1, 0, 0, "JS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #827 = JS8
+ { 828, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList26, NULL, 0 }, // Inst #828 = LAHF
+ { 829, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #829 = LAR16rm
+ { 830, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #830 = LAR16rr
+ { 831, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #831 = LAR32rm
+ { 832, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #832 = LAR32rr
+ { 833, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #833 = LAR64rm
+ { 834, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #834 = LAR64rr
+ { 835, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList27, Barriers1, OperandInfo7 }, // Inst #835 = LCMPXCHG16
+ { 836, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList28, Barriers1, OperandInfo11 }, // Inst #836 = LCMPXCHG32
+ { 837, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList29, Barriers1, OperandInfo15 }, // Inst #837 = LCMPXCHG64
+ { 838, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList30, Barriers1, OperandInfo19 }, // Inst #838 = LCMPXCHG8
+ { 839, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #839 = LCMPXCHG8B
+ { 840, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #840 = LDDQUrm
+ { 841, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #841 = LDMXCSR
+ { 842, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #842 = LD_F0
+ { 843, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #843 = LD_F1
+ { 844, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #844 = LD_F32m
+ { 845, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #845 = LD_F64m
+ { 846, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #846 = LD_F80m
+ { 847, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #847 = LD_Fp032
+ { 848, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #848 = LD_Fp064
+ { 849, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #849 = LD_Fp080
+ { 850, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #850 = LD_Fp132
+ { 851, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #851 = LD_Fp164
+ { 852, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #852 = LD_Fp180
+ { 853, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo106 }, // Inst #853 = LD_Fp32m
+ { 854, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #854 = LD_Fp32m64
+ { 855, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #855 = LD_Fp32m80
+ { 856, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #856 = LD_Fp64m
+ { 857, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #857 = LD_Fp64m80
+ { 858, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #858 = LD_Fp80m
+ { 859, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #859 = LD_Frr
+ { 860, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #860 = LEA16r
+ { 861, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #861 = LEA32r
+ { 862, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #862 = LEA64_32r
+ { 863, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #863 = LEA64r
+ { 864, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList31, ImplicitList31, NULL, 0 }, // Inst #864 = LEAVE
+ { 865, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList32, ImplicitList32, NULL, 0 }, // Inst #865 = LEAVE64
+ { 866, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #866 = LFENCE
+ { 867, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #867 = LOCK_ADD16mi
+ { 868, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #868 = LOCK_ADD16mi8
+ { 869, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #869 = LOCK_ADD16mr
+ { 870, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #870 = LOCK_ADD32mi
+ { 871, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #871 = LOCK_ADD32mi8
+ { 872, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #872 = LOCK_ADD32mr
+ { 873, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #873 = LOCK_ADD64mi32
+ { 874, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #874 = LOCK_ADD64mi8
+ { 875, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #875 = LOCK_ADD64mr
+ { 876, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #876 = LOCK_ADD8mi
+ { 877, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #877 = LOCK_ADD8mr
+ { 878, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #878 = LOCK_DEC16m
+ { 879, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #879 = LOCK_DEC32m
+ { 880, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #880 = LOCK_DEC64m
+ { 881, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #881 = LOCK_DEC8m
+ { 882, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #882 = LOCK_INC16m
+ { 883, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #883 = LOCK_INC32m
+ { 884, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #884 = LOCK_INC64m
+ { 885, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #885 = LOCK_INC8m
+ { 886, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #886 = LOCK_SUB16mi
+ { 887, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #887 = LOCK_SUB16mi8
+ { 888, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #888 = LOCK_SUB16mr
+ { 889, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #889 = LOCK_SUB32mi
+ { 890, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #890 = LOCK_SUB32mi8
+ { 891, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #891 = LOCK_SUB32mr
+ { 892, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #892 = LOCK_SUB64mi32
+ { 893, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #893 = LOCK_SUB64mi8
+ { 894, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #894 = LOCK_SUB64mr
+ { 895, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #895 = LOCK_SUB8mi
+ { 896, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #896 = LOCK_SUB8mr
+ { 897, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #897 = LODSB
+ { 898, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #898 = LODSD
+ { 899, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #899 = LODSQ
+ { 900, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #900 = LODSW
+ { 901, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #901 = LOOP
+ { 902, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #902 = LOOPE
+ { 903, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #903 = LOOPNE
+ { 904, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #904 = LRET
+ { 905, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #905 = LRETI
+ { 906, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo39 }, // Inst #906 = LXADD16
+ { 907, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #907 = LXADD32
+ { 908, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #908 = LXADD64
+ { 909, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #909 = LXADD8
+ { 910, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo74 }, // Inst #910 = MASKMOVDQU
+ { 911, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo74 }, // Inst #911 = MASKMOVDQU64
+ { 912, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #912 = MAXPDrm
+ { 913, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #913 = MAXPDrm_Int
+ { 914, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #914 = MAXPDrr
+ { 915, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #915 = MAXPDrr_Int
+ { 916, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #916 = MAXPSrm
+ { 917, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #917 = MAXPSrm_Int
+ { 918, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #918 = MAXPSrr
+ { 919, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #919 = MAXPSrr_Int
+ { 920, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #920 = MAXSDrm
+ { 921, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #921 = MAXSDrm_Int
+ { 922, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #922 = MAXSDrr
+ { 923, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #923 = MAXSDrr_Int
+ { 924, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #924 = MAXSSrm
+ { 925, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #925 = MAXSSrm_Int
+ { 926, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #926 = MAXSSrr
+ { 927, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #927 = MAXSSrr_Int
+ { 928, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #928 = MFENCE
+ { 929, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #929 = MINPDrm
+ { 930, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #930 = MINPDrm_Int
+ { 931, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #931 = MINPDrr
+ { 932, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #932 = MINPDrr_Int
+ { 933, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #933 = MINPSrm
+ { 934, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #934 = MINPSrm_Int
+ { 935, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #935 = MINPSrr
+ { 936, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #936 = MINPSrr_Int
+ { 937, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #937 = MINSDrm
+ { 938, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #938 = MINSDrm_Int
+ { 939, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #939 = MINSDrr
+ { 940, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #940 = MINSDrr_Int
+ { 941, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #941 = MINSSrm
+ { 942, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #942 = MINSSrm_Int
+ { 943, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #943 = MINSSrr
+ { 944, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #944 = MINSSrr_Int
+ { 945, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #945 = MMX_CVTPD2PIrm
+ { 946, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #946 = MMX_CVTPD2PIrr
+ { 947, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #947 = MMX_CVTPI2PDrm
+ { 948, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #948 = MMX_CVTPI2PDrr
+ { 949, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #949 = MMX_CVTPI2PSrm
+ { 950, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #950 = MMX_CVTPI2PSrr
+ { 951, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #951 = MMX_CVTPS2PIrm
+ { 952, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #952 = MMX_CVTPS2PIrr
+ { 953, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #953 = MMX_CVTTPD2PIrm
+ { 954, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #954 = MMX_CVTTPD2PIrr
+ { 955, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #955 = MMX_CVTTPS2PIrm
+ { 956, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #956 = MMX_CVTTPS2PIrr
+ { 957, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #957 = MMX_EMMS
+ { 958, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #958 = MMX_FEMMS
+ { 959, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo128 }, // Inst #959 = MMX_MASKMOVQ
+ { 960, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo128 }, // Inst #960 = MMX_MASKMOVQ64
+ { 961, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #961 = MMX_MOVD64from64rr
+ { 962, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #962 = MMX_MOVD64mr
+ { 963, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #963 = MMX_MOVD64rm
+ { 964, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #964 = MMX_MOVD64rr
+ { 965, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #965 = MMX_MOVD64rrv164
+ { 966, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #966 = MMX_MOVD64to64rr
+ { 967, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #967 = MMX_MOVDQ2Qrr
+ { 968, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #968 = MMX_MOVNTQmr
+ { 969, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #969 = MMX_MOVQ2DQrr
+ { 970, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #970 = MMX_MOVQ2FR64rr
+ { 971, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #971 = MMX_MOVQ64mr
+ { 972, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #972 = MMX_MOVQ64rm
+ { 973, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #973 = MMX_MOVQ64rr
+ { 974, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #974 = MMX_MOVZDI2PDIrm
+ { 975, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #975 = MMX_MOVZDI2PDIrr
+ { 976, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #976 = MMX_PACKSSDWrm
+ { 977, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #977 = MMX_PACKSSDWrr
+ { 978, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #978 = MMX_PACKSSWBrm
+ { 979, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #979 = MMX_PACKSSWBrr
+ { 980, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #980 = MMX_PACKUSWBrm
+ { 981, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #981 = MMX_PACKUSWBrr
+ { 982, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #982 = MMX_PADDBrm
+ { 983, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #983 = MMX_PADDBrr
+ { 984, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #984 = MMX_PADDDrm
+ { 985, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #985 = MMX_PADDDrr
+ { 986, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #986 = MMX_PADDQrm
+ { 987, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #987 = MMX_PADDQrr
+ { 988, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #988 = MMX_PADDSBrm
+ { 989, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #989 = MMX_PADDSBrr
+ { 990, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #990 = MMX_PADDSWrm
+ { 991, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #991 = MMX_PADDSWrr
+ { 992, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #992 = MMX_PADDUSBrm
+ { 993, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #993 = MMX_PADDUSBrr
+ { 994, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #994 = MMX_PADDUSWrm
+ { 995, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #995 = MMX_PADDUSWrr
+ { 996, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #996 = MMX_PADDWrm
+ { 997, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #997 = MMX_PADDWrr
+ { 998, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #998 = MMX_PANDNrm
+ { 999, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #999 = MMX_PANDNrr
+ { 1000, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1000 = MMX_PANDrm
+ { 1001, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1001 = MMX_PANDrr
+ { 1002, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1002 = MMX_PAVGBrm
+ { 1003, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1003 = MMX_PAVGBrr
+ { 1004, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1004 = MMX_PAVGWrm
+ { 1005, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1005 = MMX_PAVGWrr
+ { 1006, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1006 = MMX_PCMPEQBrm
+ { 1007, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1007 = MMX_PCMPEQBrr
+ { 1008, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1008 = MMX_PCMPEQDrm
+ { 1009, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1009 = MMX_PCMPEQDrr
+ { 1010, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1010 = MMX_PCMPEQWrm
+ { 1011, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1011 = MMX_PCMPEQWrr
+ { 1012, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1012 = MMX_PCMPGTBrm
+ { 1013, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1013 = MMX_PCMPGTBrr
+ { 1014, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1014 = MMX_PCMPGTDrm
+ { 1015, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1015 = MMX_PCMPGTDrr
+ { 1016, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1016 = MMX_PCMPGTWrm
+ { 1017, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1017 = MMX_PCMPGTWrr
+ { 1018, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1018 = MMX_PEXTRWri
+ { 1019, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1019 = MMX_PINSRWrmi
+ { 1020, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1020 = MMX_PINSRWrri
+ { 1021, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1021 = MMX_PMADDWDrm
+ { 1022, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1022 = MMX_PMADDWDrr
+ { 1023, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1023 = MMX_PMAXSWrm
+ { 1024, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1024 = MMX_PMAXSWrr
+ { 1025, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1025 = MMX_PMAXUBrm
+ { 1026, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1026 = MMX_PMAXUBrr
+ { 1027, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1027 = MMX_PMINSWrm
+ { 1028, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1028 = MMX_PMINSWrr
+ { 1029, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1029 = MMX_PMINUBrm
+ { 1030, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1030 = MMX_PMINUBrr
+ { 1031, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1031 = MMX_PMOVMSKBrr
+ { 1032, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1032 = MMX_PMULHUWrm
+ { 1033, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1033 = MMX_PMULHUWrr
+ { 1034, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1034 = MMX_PMULHWrm
+ { 1035, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1035 = MMX_PMULHWrr
+ { 1036, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1036 = MMX_PMULLWrm
+ { 1037, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1037 = MMX_PMULLWrr
+ { 1038, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1038 = MMX_PMULUDQrm
+ { 1039, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1039 = MMX_PMULUDQrr
+ { 1040, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1040 = MMX_PORrm
+ { 1041, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1041 = MMX_PORrr
+ { 1042, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1042 = MMX_PSADBWrm
+ { 1043, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1043 = MMX_PSADBWrr
+ { 1044, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1044 = MMX_PSHUFWmi
+ { 1045, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1045 = MMX_PSHUFWri
+ { 1046, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1046 = MMX_PSLLDri
+ { 1047, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1047 = MMX_PSLLDrm
+ { 1048, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1048 = MMX_PSLLDrr
+ { 1049, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1049 = MMX_PSLLQri
+ { 1050, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1050 = MMX_PSLLQrm
+ { 1051, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1051 = MMX_PSLLQrr
+ { 1052, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1052 = MMX_PSLLWri
+ { 1053, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1053 = MMX_PSLLWrm
+ { 1054, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1054 = MMX_PSLLWrr
+ { 1055, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1055 = MMX_PSRADri
+ { 1056, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1056 = MMX_PSRADrm
+ { 1057, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1057 = MMX_PSRADrr
+ { 1058, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1058 = MMX_PSRAWri
+ { 1059, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1059 = MMX_PSRAWrm
+ { 1060, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1060 = MMX_PSRAWrr
+ { 1061, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1061 = MMX_PSRLDri
+ { 1062, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1062 = MMX_PSRLDrm
+ { 1063, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1063 = MMX_PSRLDrr
+ { 1064, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1064 = MMX_PSRLQri
+ { 1065, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1065 = MMX_PSRLQrm
+ { 1066, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1066 = MMX_PSRLQrr
+ { 1067, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1067 = MMX_PSRLWri
+ { 1068, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1068 = MMX_PSRLWrm
+ { 1069, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1069 = MMX_PSRLWrr
+ { 1070, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1070 = MMX_PSUBBrm
+ { 1071, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1071 = MMX_PSUBBrr
+ { 1072, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1072 = MMX_PSUBDrm
+ { 1073, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1073 = MMX_PSUBDrr
+ { 1074, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1074 = MMX_PSUBQrm
+ { 1075, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1075 = MMX_PSUBQrr
+ { 1076, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1076 = MMX_PSUBSBrm
+ { 1077, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1077 = MMX_PSUBSBrr
+ { 1078, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1078 = MMX_PSUBSWrm
+ { 1079, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1079 = MMX_PSUBSWrr
+ { 1080, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1080 = MMX_PSUBUSBrm
+ { 1081, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1081 = MMX_PSUBUSBrr
+ { 1082, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1082 = MMX_PSUBUSWrm
+ { 1083, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1083 = MMX_PSUBUSWrr
+ { 1084, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1084 = MMX_PSUBWrm
+ { 1085, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1085 = MMX_PSUBWrr
+ { 1086, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1086 = MMX_PUNPCKHBWrm
+ { 1087, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1087 = MMX_PUNPCKHBWrr
+ { 1088, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1088 = MMX_PUNPCKHDQrm
+ { 1089, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1089 = MMX_PUNPCKHDQrr
+ { 1090, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1090 = MMX_PUNPCKHWDrm
+ { 1091, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1091 = MMX_PUNPCKHWDrr
+ { 1092, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1092 = MMX_PUNPCKLBWrm
+ { 1093, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1093 = MMX_PUNPCKLBWrr
+ { 1094, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1094 = MMX_PUNPCKLDQrm
+ { 1095, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1095 = MMX_PUNPCKLDQrr
+ { 1096, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1096 = MMX_PUNPCKLWDrm
+ { 1097, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1097 = MMX_PUNPCKLWDrr
+ { 1098, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1098 = MMX_PXORrm
+ { 1099, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1099 = MMX_PXORrr
+ { 1100, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1100 = MMX_V_SET0
+ { 1101, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1101 = MMX_V_SETALLONES
+ { 1102, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1102 = MONITOR
+ { 1103, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1103 = MOV16ao16
+ { 1104, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1104 = MOV16mi
+ { 1105, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1105 = MOV16mr
+ { 1106, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1106 = MOV16ms
+ { 1107, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1107 = MOV16o16a
+ { 1108, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1108 = MOV16r0
+ { 1109, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(2<<13)|(184<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1109 = MOV16ri
+ { 1110, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1110 = MOV16rm
+ { 1111, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1111 = MOV16rr
+ { 1112, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1112 = MOV16rs
+ { 1113, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1113 = MOV16sm
+ { 1114, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1114 = MOV16sr
+ { 1115, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1115 = MOV32ao32
+ { 1116, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1116 = MOV32mi
+ { 1117, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1117 = MOV32mr
+ { 1118, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1118 = MOV32o32a
+ { 1119, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #1119 = MOV32r0
+ { 1120, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1120 = MOV32ri
+ { 1121, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1121 = MOV32rm
+ { 1122, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1122 = MOV32rr
+ { 1123, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1123 = MOV64FSrm
+ { 1124, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1124 = MOV64GSrm
+ { 1125, 1, 1, 0, "MOV64ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1125 = MOV64ao32
+ { 1126, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1126 = MOV64ao8
+ { 1127, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1127 = MOV64mi32
+ { 1128, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1128 = MOV64mr
+ { 1129, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1129 = MOV64ms
+ { 1130, 1, 0, 0, "MOV64o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1130 = MOV64o32a
+ { 1131, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1131 = MOV64o8a
+ { 1132, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1132 = MOV64ri
+ { 1133, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1133 = MOV64ri32
+ { 1134, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1134 = MOV64ri64i32
+ { 1135, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1135 = MOV64rm
+ { 1136, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1136 = MOV64rr
+ { 1137, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1137 = MOV64rs
+ { 1138, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1138 = MOV64sm
+ { 1139, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1139 = MOV64sr
+ { 1140, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1140 = MOV64toPQIrr
+ { 1141, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1141 = MOV64toSDrm
+ { 1142, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #1142 = MOV64toSDrr
+ { 1143, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1143 = MOV8ao8
+ { 1144, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1144 = MOV8mi
+ { 1145, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo19 }, // Inst #1145 = MOV8mr
+ { 1146, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1146 = MOV8mr_NOREX
+ { 1147, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1147 = MOV8o8a
+ { 1148, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1148 = MOV8r0
+ { 1149, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1149 = MOV8ri
+ { 1150, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1150 = MOV8rm
+ { 1151, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1151 = MOV8rm_NOREX
+ { 1152, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo66 }, // Inst #1152 = MOV8rr
+ { 1153, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1153 = MOV8rr_NOREX
+ { 1154, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1154 = MOVAPDmr
+ { 1155, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1155 = MOVAPDrm
+ { 1156, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1156 = MOVAPDrr
+ { 1157, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1157 = MOVAPSmr
+ { 1158, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1158 = MOVAPSrm
+ { 1159, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1159 = MOVAPSrr
+ { 1160, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1160 = MOVDDUPrm
+ { 1161, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1161 = MOVDDUPrr
+ { 1162, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1162 = MOVDI2PDIrm
+ { 1163, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1163 = MOVDI2PDIrr
+ { 1164, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1164 = MOVDI2SSrm
+ { 1165, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #1165 = MOVDI2SSrr
+ { 1166, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1166 = MOVDQAmr
+ { 1167, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1167 = MOVDQArm
+ { 1168, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1168 = MOVDQArr
+ { 1169, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1169 = MOVDQUmr
+ { 1170, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1170 = MOVDQUmr_Int
+ { 1171, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1171 = MOVDQUrm
+ { 1172, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1172 = MOVDQUrm_Int
+ { 1173, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1173 = MOVHLPSrr
+ { 1174, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1174 = MOVHPDmr
+ { 1175, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1175 = MOVHPDrm
+ { 1176, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1176 = MOVHPSmr
+ { 1177, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1177 = MOVHPSrm
+ { 1178, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1178 = MOVLHPSrr
+ { 1179, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1179 = MOVLPDmr
+ { 1180, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1180 = MOVLPDrm
+ { 1181, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1181 = MOVLPDrr
+ { 1182, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1182 = MOVLPSmr
+ { 1183, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1183 = MOVLPSrm
+ { 1184, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1184 = MOVLPSrr
+ { 1185, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1185 = MOVLQ128mr
+ { 1186, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1186 = MOVLSD2PDrr
+ { 1187, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1187 = MOVLSS2PSrr
+ { 1188, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1188 = MOVMSKPDrr
+ { 1189, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1189 = MOVMSKPSrr
+ { 1190, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1190 = MOVNTDQArm
+ { 1191, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1191 = MOVNTDQmr
+ { 1192, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1192 = MOVNTImr
+ { 1193, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1193 = MOVNTPDmr
+ { 1194, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1194 = MOVNTPSmr
+ { 1195, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(3<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo54 }, // Inst #1195 = MOVPC32r
+ { 1196, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1196 = MOVPD2SDmr
+ { 1197, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1197 = MOVPD2SDrr
+ { 1198, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1198 = MOVPDI2DImr
+ { 1199, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1199 = MOVPDI2DIrr
+ { 1200, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1200 = MOVPQI2QImr
+ { 1201, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #1201 = MOVPQIto64rr
+ { 1202, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1202 = MOVPS2SSmr
+ { 1203, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1203 = MOVPS2SSrr
+ { 1204, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1204 = MOVQI2PQIrm
+ { 1205, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1205 = MOVSD2PDrm
+ { 1206, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1206 = MOVSD2PDrr
+ { 1207, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1207 = MOVSDmr
+ { 1208, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1208 = MOVSDrm
+ { 1209, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #1209 = MOVSDrr
+ { 1210, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1210 = MOVSDto64mr
+ { 1211, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1211 = MOVSDto64rr
+ { 1212, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1212 = MOVSHDUPrm
+ { 1213, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1213 = MOVSHDUPrr
+ { 1214, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1214 = MOVSLDUPrm
+ { 1215, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1215 = MOVSLDUPrr
+ { 1216, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1216 = MOVSS2DImr
+ { 1217, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1217 = MOVSS2DIrr
+ { 1218, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1218 = MOVSS2PSrm
+ { 1219, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1219 = MOVSS2PSrr
+ { 1220, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1220 = MOVSSmr
+ { 1221, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1221 = MOVSSrm
+ { 1222, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1222 = MOVSSrr
+ { 1223, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1223 = MOVSX16rm8
+ { 1224, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1224 = MOVSX16rr8
+ { 1225, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1225 = MOVSX32rm16
+ { 1226, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1226 = MOVSX32rm8
+ { 1227, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1227 = MOVSX32rr16
+ { 1228, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1228 = MOVSX32rr8
+ { 1229, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1229 = MOVSX64rm16
+ { 1230, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1230 = MOVSX64rm32
+ { 1231, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1231 = MOVSX64rm8
+ { 1232, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1232 = MOVSX64rr16
+ { 1233, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #1233 = MOVSX64rr32
+ { 1234, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1234 = MOVSX64rr8
+ { 1235, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1235 = MOVUPDmr
+ { 1236, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1236 = MOVUPDmr_Int
+ { 1237, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1237 = MOVUPDrm
+ { 1238, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1238 = MOVUPDrm_Int
+ { 1239, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1239 = MOVUPDrr
+ { 1240, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1240 = MOVUPSmr
+ { 1241, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1241 = MOVUPSmr_Int
+ { 1242, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1242 = MOVUPSrm
+ { 1243, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1243 = MOVUPSrm_Int
+ { 1244, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1244 = MOVUPSrr
+ { 1245, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1245 = MOVZDI2PDIrm
+ { 1246, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1246 = MOVZDI2PDIrr
+ { 1247, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1247 = MOVZPQILo2PQIrm
+ { 1248, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1248 = MOVZPQILo2PQIrr
+ { 1249, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1249 = MOVZQI2PQIrm
+ { 1250, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1250 = MOVZQI2PQIrr
+ { 1251, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1251 = MOVZSD2PDrm
+ { 1252, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1252 = MOVZSS2PSrm
+ { 1253, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1253 = MOVZX16rm8
+ { 1254, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1254 = MOVZX16rr8
+ { 1255, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1255 = MOVZX32_NOREXrm8
+ { 1256, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1256 = MOVZX32_NOREXrr8
+ { 1257, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1257 = MOVZX32rm16
+ { 1258, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1258 = MOVZX32rm8
+ { 1259, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1259 = MOVZX32rr16
+ { 1260, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1260 = MOVZX32rr8
+ { 1261, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1261 = MOVZX64rm16
+ { 1262, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1262 = MOVZX64rm32
+ { 1263, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1263 = MOVZX64rm8
+ { 1264, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1264 = MOVZX64rr16
+ { 1265, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #1265 = MOVZX64rr32
+ { 1266, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1266 = MOVZX64rr8
+ { 1267, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1267 = MOV_Fp3232
+ { 1268, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo171 }, // Inst #1268 = MOV_Fp3264
+ { 1269, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo172 }, // Inst #1269 = MOV_Fp3280
+ { 1270, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo173 }, // Inst #1270 = MOV_Fp6432
+ { 1271, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1271 = MOV_Fp6464
+ { 1272, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo174 }, // Inst #1272 = MOV_Fp6480
+ { 1273, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo175 }, // Inst #1273 = MOV_Fp8032
+ { 1274, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo176 }, // Inst #1274 = MOV_Fp8064
+ { 1275, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1275 = MOV_Fp8080
+ { 1276, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1276 = MPSADBWrmi
+ { 1277, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1277 = MPSADBWrri
+ { 1278, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo29 }, // Inst #1278 = MUL16m
+ { 1279, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo92 }, // Inst #1279 = MUL16r
+ { 1280, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo29 }, // Inst #1280 = MUL32m
+ { 1281, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo56 }, // Inst #1281 = MUL32r
+ { 1282, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo29 }, // Inst #1282 = MUL64m
+ { 1283, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo57 }, // Inst #1283 = MUL64r
+ { 1284, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo29 }, // Inst #1284 = MUL8m
+ { 1285, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1285 = MUL8r
+ { 1286, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1286 = MULPDrm
+ { 1287, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1287 = MULPDrr
+ { 1288, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1288 = MULPSrm
+ { 1289, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1289 = MULPSrr
+ { 1290, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1290 = MULSDrm
+ { 1291, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1291 = MULSDrm_Int
+ { 1292, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1292 = MULSDrr
+ { 1293, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1293 = MULSDrr_Int
+ { 1294, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1294 = MULSSrm
+ { 1295, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1295 = MULSSrm_Int
+ { 1296, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1296 = MULSSrr
+ { 1297, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1297 = MULSSrr_Int
+ { 1298, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1298 = MUL_F32m
+ { 1299, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1299 = MUL_F64m
+ { 1300, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1300 = MUL_FI16m
+ { 1301, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1301 = MUL_FI32m
+ { 1302, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1302 = MUL_FPrST0
+ { 1303, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1303 = MUL_FST0r
+ { 1304, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #1304 = MUL_Fp32
+ { 1305, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1305 = MUL_Fp32m
+ { 1306, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1306 = MUL_Fp64
+ { 1307, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1307 = MUL_Fp64m
+ { 1308, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1308 = MUL_Fp64m32
+ { 1309, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1309 = MUL_Fp80
+ { 1310, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1310 = MUL_Fp80m32
+ { 1311, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1311 = MUL_Fp80m64
+ { 1312, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1312 = MUL_FpI16m32
+ { 1313, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1313 = MUL_FpI16m64
+ { 1314, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1314 = MUL_FpI16m80
+ { 1315, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1315 = MUL_FpI32m32
+ { 1316, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1316 = MUL_FpI32m64
+ { 1317, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1317 = MUL_FpI32m80
+ { 1318, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1318 = MUL_FrST0
+ { 1319, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1319 = MWAIT
+ { 1320, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1320 = NEG16m
+ { 1321, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1321 = NEG16r
+ { 1322, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1322 = NEG32m
+ { 1323, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1323 = NEG32r
+ { 1324, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1324 = NEG64m
+ { 1325, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1325 = NEG64r
+ { 1326, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1326 = NEG8m
+ { 1327, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1327 = NEG8r
+ { 1328, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1328 = NOOP
+ { 1329, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1329 = NOOPL
+ { 1330, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1330 = NOT16m
+ { 1331, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #1331 = NOT16r
+ { 1332, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1332 = NOT32m
+ { 1333, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1333 = NOT32r
+ { 1334, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1334 = NOT64m
+ { 1335, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1335 = NOT64r
+ { 1336, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1336 = NOT8m
+ { 1337, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1337 = NOT8r
+ { 1338, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1338 = OR16i16
+ { 1339, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1339 = OR16mi
+ { 1340, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1340 = OR16mi8
+ { 1341, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1341 = OR16mr
+ { 1342, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1342 = OR16ri
+ { 1343, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1343 = OR16ri8
+ { 1344, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1344 = OR16rm
+ { 1345, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1345 = OR16rr
+ { 1346, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1346 = OR32i32
+ { 1347, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1347 = OR32mi
+ { 1348, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1348 = OR32mi8
+ { 1349, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1349 = OR32mr
+ { 1350, 3, 1, 0, "OR32ri", 0, 0|17|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1350 = OR32ri
+ { 1351, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1351 = OR32ri8
+ { 1352, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1352 = OR32rm
+ { 1353, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1353 = OR32rr
+ { 1354, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1354 = OR64i32
+ { 1355, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1355 = OR64mi32
+ { 1356, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1356 = OR64mi8
+ { 1357, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1357 = OR64mr
+ { 1358, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1358 = OR64ri32
+ { 1359, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1359 = OR64ri8
+ { 1360, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1360 = OR64rm
+ { 1361, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1361 = OR64rr
+ { 1362, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1362 = OR8i8
+ { 1363, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1363 = OR8mi
+ { 1364, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #1364 = OR8mr
+ { 1365, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1365 = OR8ri
+ { 1366, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1366 = OR8rm
+ { 1367, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1367 = OR8rr
+ { 1368, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1368 = ORPDrm
+ { 1369, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1369 = ORPDrr
+ { 1370, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1370 = ORPSrm
+ { 1371, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1371 = ORPSrr
+ { 1372, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1372 = OUT16ir
+ { 1373, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList35, NULL, NULL, 0 }, // Inst #1373 = OUT16rr
+ { 1374, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1374 = OUT32ir
+ { 1375, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList36, NULL, NULL, 0 }, // Inst #1375 = OUT32rr
+ { 1376, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1376 = OUT8ir
+ { 1377, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList37, NULL, NULL, 0 }, // Inst #1377 = OUT8rr
+ { 1378, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1378 = PABSBrm128
+ { 1379, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #1379 = PABSBrm64
+ { 1380, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1380 = PABSBrr128
+ { 1381, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #1381 = PABSBrr64
+ { 1382, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1382 = PABSDrm128
+ { 1383, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #1383 = PABSDrm64
+ { 1384, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1384 = PABSDrr128
+ { 1385, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #1385 = PABSDrr64
+ { 1386, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1386 = PABSWrm128
+ { 1387, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo116 }, // Inst #1387 = PABSWrm64
+ { 1388, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1388 = PABSWrr128
+ { 1389, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #1389 = PABSWrr64
+ { 1390, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1390 = PACKSSDWrm
+ { 1391, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1391 = PACKSSDWrr
+ { 1392, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1392 = PACKSSWBrm
+ { 1393, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1393 = PACKSSWBrr
+ { 1394, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1394 = PACKUSDWrm
+ { 1395, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1395 = PACKUSDWrr
+ { 1396, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1396 = PACKUSWBrm
+ { 1397, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1397 = PACKUSWBrr
+ { 1398, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1398 = PADDBrm
+ { 1399, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1399 = PADDBrr
+ { 1400, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1400 = PADDDrm
+ { 1401, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1401 = PADDDrr
+ { 1402, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1402 = PADDQrm
+ { 1403, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1403 = PADDQrr
+ { 1404, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1404 = PADDSBrm
+ { 1405, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1405 = PADDSBrr
+ { 1406, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1406 = PADDSWrm
+ { 1407, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1407 = PADDSWrr
+ { 1408, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1408 = PADDUSBrm
+ { 1409, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1409 = PADDUSBrr
+ { 1410, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1410 = PADDUSWrm
+ { 1411, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1411 = PADDUSWrr
+ { 1412, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1412 = PADDWrm
+ { 1413, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1413 = PADDWrr
+ { 1414, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1414 = PALIGNR128rm
+ { 1415, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1415 = PALIGNR128rr
+ { 1416, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1416 = PALIGNR64rm
+ { 1417, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1417 = PALIGNR64rr
+ { 1418, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1418 = PANDNrm
+ { 1419, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1419 = PANDNrr
+ { 1420, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1420 = PANDrm
+ { 1421, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1421 = PANDrr
+ { 1422, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1422 = PAVGBrm
+ { 1423, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1423 = PAVGBrr
+ { 1424, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1424 = PAVGWrm
+ { 1425, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1425 = PAVGWrr
+ { 1426, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo23 }, // Inst #1426 = PBLENDVBrm0
+ { 1427, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1427 = PBLENDVBrr0
+ { 1428, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1428 = PBLENDWrmi
+ { 1429, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1429 = PBLENDWrri
+ { 1430, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1430 = PCMPEQBrm
+ { 1431, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1431 = PCMPEQBrr
+ { 1432, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1432 = PCMPEQDrm
+ { 1433, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1433 = PCMPEQDrr
+ { 1434, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1434 = PCMPEQQrm
+ { 1435, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1435 = PCMPEQQrr
+ { 1436, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1436 = PCMPEQWrm
+ { 1437, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1437 = PCMPEQWrr
+ { 1438, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1438 = PCMPESTRIArm
+ { 1439, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1439 = PCMPESTRIArr
+ { 1440, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1440 = PCMPESTRICrm
+ { 1441, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1441 = PCMPESTRICrr
+ { 1442, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1442 = PCMPESTRIOrm
+ { 1443, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1443 = PCMPESTRIOrr
+ { 1444, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1444 = PCMPESTRISrm
+ { 1445, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1445 = PCMPESTRISrr
+ { 1446, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1446 = PCMPESTRIZrm
+ { 1447, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1447 = PCMPESTRIZrr
+ { 1448, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1448 = PCMPESTRIrm
+ { 1449, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1449 = PCMPESTRIrr
+ { 1450, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo180 }, // Inst #1450 = PCMPESTRM128MEM
+ { 1451, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo65 }, // Inst #1451 = PCMPESTRM128REG
+ { 1452, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo178 }, // Inst #1452 = PCMPESTRM128rm
+ { 1453, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo179 }, // Inst #1453 = PCMPESTRM128rr
+ { 1454, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1454 = PCMPGTBrm
+ { 1455, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1455 = PCMPGTBrr
+ { 1456, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1456 = PCMPGTDrm
+ { 1457, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1457 = PCMPGTDrr
+ { 1458, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1458 = PCMPGTQrm
+ { 1459, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = PCMPGTQrr
+ { 1460, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1460 = PCMPGTWrm
+ { 1461, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1461 = PCMPGTWrr
+ { 1462, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1462 = PCMPISTRIArm
+ { 1463, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1463 = PCMPISTRIArr
+ { 1464, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1464 = PCMPISTRICrm
+ { 1465, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1465 = PCMPISTRICrr
+ { 1466, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1466 = PCMPISTRIOrm
+ { 1467, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1467 = PCMPISTRIOrr
+ { 1468, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1468 = PCMPISTRISrm
+ { 1469, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1469 = PCMPISTRISrr
+ { 1470, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1470 = PCMPISTRIZrm
+ { 1471, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1471 = PCMPISTRIZrr
+ { 1472, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo178 }, // Inst #1472 = PCMPISTRIrm
+ { 1473, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo179 }, // Inst #1473 = PCMPISTRIrr
+ { 1474, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo180 }, // Inst #1474 = PCMPISTRM128MEM
+ { 1475, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo65 }, // Inst #1475 = PCMPISTRM128REG
+ { 1476, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo178 }, // Inst #1476 = PCMPISTRM128rm
+ { 1477, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo179 }, // Inst #1477 = PCMPISTRM128rr
+ { 1478, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1478 = PEXTRBmr
+ { 1479, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1479 = PEXTRBrr
+ { 1480, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1480 = PEXTRDmr
+ { 1481, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1481 = PEXTRDrr
+ { 1482, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1482 = PEXTRQmr
+ { 1483, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo181 }, // Inst #1483 = PEXTRQrr
+ { 1484, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo94 }, // Inst #1484 = PEXTRWmr
+ { 1485, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1485 = PEXTRWri
+ { 1486, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1486 = PHADDDrm128
+ { 1487, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1487 = PHADDDrm64
+ { 1488, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1488 = PHADDDrr128
+ { 1489, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1489 = PHADDDrr64
+ { 1490, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1490 = PHADDSWrm128
+ { 1491, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1491 = PHADDSWrm64
+ { 1492, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1492 = PHADDSWrr128
+ { 1493, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1493 = PHADDSWrr64
+ { 1494, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1494 = PHADDWrm128
+ { 1495, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1495 = PHADDWrm64
+ { 1496, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1496 = PHADDWrr128
+ { 1497, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1497 = PHADDWrr64
+ { 1498, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1498 = PHMINPOSUWrm128
+ { 1499, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1499 = PHMINPOSUWrr128
+ { 1500, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1500 = PHSUBDrm128
+ { 1501, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1501 = PHSUBDrm64
+ { 1502, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1502 = PHSUBDrr128
+ { 1503, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1503 = PHSUBDrr64
+ { 1504, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1504 = PHSUBSWrm128
+ { 1505, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1505 = PHSUBSWrm64
+ { 1506, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1506 = PHSUBSWrr128
+ { 1507, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1507 = PHSUBSWrr64
+ { 1508, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1508 = PHSUBWrm128
+ { 1509, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1509 = PHSUBWrm64
+ { 1510, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1510 = PHSUBWrr128
+ { 1511, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1511 = PHSUBWrr64
+ { 1512, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1512 = PINSRBrm
+ { 1513, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1513 = PINSRBrr
+ { 1514, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1514 = PINSRDrm
+ { 1515, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1515 = PINSRDrr
+ { 1516, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1516 = PINSRQrm
+ { 1517, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1517 = PINSRQrr
+ { 1518, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1518 = PINSRWrmi
+ { 1519, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1519 = PINSRWrri
+ { 1520, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1520 = PMADDUBSWrm128
+ { 1521, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1521 = PMADDUBSWrm64
+ { 1522, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1522 = PMADDUBSWrr128
+ { 1523, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1523 = PMADDUBSWrr64
+ { 1524, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1524 = PMADDWDrm
+ { 1525, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1525 = PMADDWDrr
+ { 1526, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1526 = PMAXSBrm
+ { 1527, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1527 = PMAXSBrr
+ { 1528, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1528 = PMAXSDrm
+ { 1529, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1529 = PMAXSDrr
+ { 1530, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1530 = PMAXSWrm
+ { 1531, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1531 = PMAXSWrr
+ { 1532, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1532 = PMAXUBrm
+ { 1533, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1533 = PMAXUBrr
+ { 1534, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1534 = PMAXUDrm
+ { 1535, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1535 = PMAXUDrr
+ { 1536, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1536 = PMAXUWrm
+ { 1537, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1537 = PMAXUWrr
+ { 1538, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1538 = PMINSBrm
+ { 1539, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1539 = PMINSBrr
+ { 1540, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1540 = PMINSDrm
+ { 1541, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1541 = PMINSDrr
+ { 1542, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1542 = PMINSWrm
+ { 1543, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1543 = PMINSWrr
+ { 1544, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1544 = PMINUBrm
+ { 1545, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1545 = PMINUBrr
+ { 1546, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1546 = PMINUDrm
+ { 1547, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1547 = PMINUDrr
+ { 1548, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1548 = PMINUWrm
+ { 1549, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1549 = PMINUWrr
+ { 1550, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1550 = PMOVMSKBrr
+ { 1551, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1551 = PMOVSXBDrm
+ { 1552, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1552 = PMOVSXBDrr
+ { 1553, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1553 = PMOVSXBQrm
+ { 1554, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1554 = PMOVSXBQrr
+ { 1555, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1555 = PMOVSXBWrm
+ { 1556, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1556 = PMOVSXBWrr
+ { 1557, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1557 = PMOVSXDQrm
+ { 1558, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1558 = PMOVSXDQrr
+ { 1559, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1559 = PMOVSXWDrm
+ { 1560, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1560 = PMOVSXWDrr
+ { 1561, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1561 = PMOVSXWQrm
+ { 1562, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1562 = PMOVSXWQrr
+ { 1563, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1563 = PMOVZXBDrm
+ { 1564, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1564 = PMOVZXBDrr
+ { 1565, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1565 = PMOVZXBQrm
+ { 1566, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1566 = PMOVZXBQrr
+ { 1567, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1567 = PMOVZXBWrm
+ { 1568, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1568 = PMOVZXBWrr
+ { 1569, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1569 = PMOVZXDQrm
+ { 1570, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1570 = PMOVZXDQrr
+ { 1571, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1571 = PMOVZXWDrm
+ { 1572, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1572 = PMOVZXWDrr
+ { 1573, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1573 = PMOVZXWQrm
+ { 1574, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1574 = PMOVZXWQrr
+ { 1575, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1575 = PMULDQrm
+ { 1576, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1576 = PMULDQrr
+ { 1577, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1577 = PMULHRSWrm128
+ { 1578, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1578 = PMULHRSWrm64
+ { 1579, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PMULHRSWrr128
+ { 1580, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1580 = PMULHRSWrr64
+ { 1581, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1581 = PMULHUWrm
+ { 1582, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1582 = PMULHUWrr
+ { 1583, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1583 = PMULHWrm
+ { 1584, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1584 = PMULHWrr
+ { 1585, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1585 = PMULLDrm
+ { 1586, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1586 = PMULLDrm_int
+ { 1587, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PMULLDrr
+ { 1588, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1588 = PMULLDrr_int
+ { 1589, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1589 = PMULLWrm
+ { 1590, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1590 = PMULLWrr
+ { 1591, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1591 = PMULUDQrm
+ { 1592, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1592 = PMULUDQrr
+ { 1593, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1593 = POP16r
+ { 1594, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1594 = POP16rmm
+ { 1595, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1595 = POP16rmr
+ { 1596, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1596 = POP32r
+ { 1597, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1597 = POP32rmm
+ { 1598, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1598 = POP32rmr
+ { 1599, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1599 = POP64r
+ { 1600, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo29 }, // Inst #1600 = POP64rmm
+ { 1601, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1601 = POP64rmr
+ { 1602, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1602 = POPFD
+ { 1603, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1603 = POPFQ
+ { 1604, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1604 = PORrm
+ { 1605, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1605 = PORrr
+ { 1606, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1606 = PREFETCHNTA
+ { 1607, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1607 = PREFETCHT0
+ { 1608, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1608 = PREFETCHT1
+ { 1609, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1609 = PREFETCHT2
+ { 1610, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1610 = PSADBWrm
+ { 1611, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PSADBWrr
+ { 1612, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo23 }, // Inst #1612 = PSHUFBrm128
+ { 1613, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo134 }, // Inst #1613 = PSHUFBrm64
+ { 1614, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1614 = PSHUFBrr128
+ { 1615, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo135 }, // Inst #1615 = PSHUFBrr64
+ { 1616, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1616 = PSHUFDmi
+ { 1617, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1617 = PSHUFDri
+ { 1618, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1618 = PSHUFHWmi
+ { 1619, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1619 = PSHUFHWri
+ { 1620, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1620 = PSHUFLWmi
+ { 1621, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1621 = PSHUFLWri
+ { 1622, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1622 = PSIGNBrm128
+ { 1623, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1623 = PSIGNBrm64
+ { 1624, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1624 = PSIGNBrr128
+ { 1625, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1625 = PSIGNBrr64
+ { 1626, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1626 = PSIGNDrm128
+ { 1627, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1627 = PSIGNDrm64
+ { 1628, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1628 = PSIGNDrr128
+ { 1629, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1629 = PSIGNDrr64
+ { 1630, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1630 = PSIGNWrm128
+ { 1631, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1631 = PSIGNWrm64
+ { 1632, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1632 = PSIGNWrr128
+ { 1633, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1633 = PSIGNWrr64
+ { 1634, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1634 = PSLLDQri
+ { 1635, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1635 = PSLLDri
+ { 1636, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1636 = PSLLDrm
+ { 1637, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1637 = PSLLDrr
+ { 1638, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1638 = PSLLQri
+ { 1639, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1639 = PSLLQrm
+ { 1640, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1640 = PSLLQrr
+ { 1641, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1641 = PSLLWri
+ { 1642, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1642 = PSLLWrm
+ { 1643, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1643 = PSLLWrr
+ { 1644, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1644 = PSRADri
+ { 1645, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1645 = PSRADrm
+ { 1646, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1646 = PSRADrr
+ { 1647, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1647 = PSRAWri
+ { 1648, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1648 = PSRAWrm
+ { 1649, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1649 = PSRAWrr
+ { 1650, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1650 = PSRLDQri
+ { 1651, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1651 = PSRLDri
+ { 1652, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1652 = PSRLDrm
+ { 1653, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1653 = PSRLDrr
+ { 1654, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1654 = PSRLQri
+ { 1655, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1655 = PSRLQrm
+ { 1656, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1656 = PSRLQrr
+ { 1657, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1657 = PSRLWri
+ { 1658, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1658 = PSRLWrm
+ { 1659, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1659 = PSRLWrr
+ { 1660, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1660 = PSUBBrm
+ { 1661, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1661 = PSUBBrr
+ { 1662, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1662 = PSUBDrm
+ { 1663, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1663 = PSUBDrr
+ { 1664, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1664 = PSUBQrm
+ { 1665, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1665 = PSUBQrr
+ { 1666, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1666 = PSUBSBrm
+ { 1667, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1667 = PSUBSBrr
+ { 1668, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1668 = PSUBSWrm
+ { 1669, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1669 = PSUBSWrr
+ { 1670, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1670 = PSUBUSBrm
+ { 1671, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1671 = PSUBUSBrr
+ { 1672, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1672 = PSUBUSWrm
+ { 1673, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PSUBUSWrr
+ { 1674, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1674 = PSUBWrm
+ { 1675, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1675 = PSUBWrr
+ { 1676, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo73 }, // Inst #1676 = PTESTrm
+ { 1677, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1677 = PTESTrr
+ { 1678, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1678 = PUNPCKHBWrm
+ { 1679, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1679 = PUNPCKHBWrr
+ { 1680, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1680 = PUNPCKHDQrm
+ { 1681, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1681 = PUNPCKHDQrr
+ { 1682, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1682 = PUNPCKHQDQrm
+ { 1683, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1683 = PUNPCKHQDQrr
+ { 1684, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1684 = PUNPCKHWDrm
+ { 1685, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1685 = PUNPCKHWDrr
+ { 1686, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1686 = PUNPCKLBWrm
+ { 1687, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PUNPCKLBWrr
+ { 1688, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1688 = PUNPCKLDQrm
+ { 1689, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1689 = PUNPCKLDQrr
+ { 1690, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1690 = PUNPCKLQDQrm
+ { 1691, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1691 = PUNPCKLQDQrr
+ { 1692, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1692 = PUNPCKLWDrm
+ { 1693, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1693 = PUNPCKLWDrr
+ { 1694, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1694 = PUSH16r
+ { 1695, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1695 = PUSH16rmm
+ { 1696, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo92 }, // Inst #1696 = PUSH16rmr
+ { 1697, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1697 = PUSH32i16
+ { 1698, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1698 = PUSH32i32
+ { 1699, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1699 = PUSH32i8
+ { 1700, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1700 = PUSH32r
+ { 1701, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo29 }, // Inst #1701 = PUSH32rmm
+ { 1702, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo56 }, // Inst #1702 = PUSH32rmr
+ { 1703, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1703 = PUSH64i16
+ { 1704, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1704 = PUSH64i32
+ { 1705, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1705 = PUSH64i8
+ { 1706, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1706 = PUSH64r
+ { 1707, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo29 }, // Inst #1707 = PUSH64rmm
+ { 1708, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo57 }, // Inst #1708 = PUSH64rmr
+ { 1709, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1709 = PUSHFD
+ { 1710, 0, 0, 0, "PUSHFQ", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1710 = PUSHFQ
+ { 1711, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #1711 = PXORrm
+ { 1712, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1712 = PXORrr
+ { 1713, 10, 1, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1713 = RCL16m1
+ { 1714, 10, 1, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1714 = RCL16mCL
+ { 1715, 11, 1, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1715 = RCL16mi
+ { 1716, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1716 = RCL16r1
+ { 1717, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1717 = RCL16rCL
+ { 1718, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1718 = RCL16ri
+ { 1719, 10, 1, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1719 = RCL32m1
+ { 1720, 10, 1, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1720 = RCL32mCL
+ { 1721, 11, 1, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1721 = RCL32mi
+ { 1722, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1722 = RCL32r1
+ { 1723, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1723 = RCL32rCL
+ { 1724, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1724 = RCL32ri
+ { 1725, 10, 1, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1725 = RCL64m1
+ { 1726, 10, 1, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1726 = RCL64mCL
+ { 1727, 11, 1, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1727 = RCL64mi
+ { 1728, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1728 = RCL64r1
+ { 1729, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1729 = RCL64rCL
+ { 1730, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1730 = RCL64ri
+ { 1731, 10, 1, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1731 = RCL8m1
+ { 1732, 10, 1, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1732 = RCL8mCL
+ { 1733, 11, 1, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1733 = RCL8mi
+ { 1734, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1734 = RCL8r1
+ { 1735, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1735 = RCL8rCL
+ { 1736, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1736 = RCL8ri
+ { 1737, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1737 = RCPPSm
+ { 1738, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1738 = RCPPSm_Int
+ { 1739, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1739 = RCPPSr
+ { 1740, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = RCPPSr_Int
+ { 1741, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1741 = RCPSSm
+ { 1742, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1742 = RCPSSm_Int
+ { 1743, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1743 = RCPSSr
+ { 1744, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = RCPSSr_Int
+ { 1745, 10, 1, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1745 = RCR16m1
+ { 1746, 10, 1, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1746 = RCR16mCL
+ { 1747, 11, 1, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1747 = RCR16mi
+ { 1748, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1748 = RCR16r1
+ { 1749, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1749 = RCR16rCL
+ { 1750, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1750 = RCR16ri
+ { 1751, 10, 1, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1751 = RCR32m1
+ { 1752, 10, 1, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1752 = RCR32mCL
+ { 1753, 11, 1, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1753 = RCR32mi
+ { 1754, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1754 = RCR32r1
+ { 1755, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1755 = RCR32rCL
+ { 1756, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1756 = RCR32ri
+ { 1757, 10, 1, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1757 = RCR64m1
+ { 1758, 10, 1, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1758 = RCR64mCL
+ { 1759, 11, 1, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1759 = RCR64mi
+ { 1760, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1760 = RCR64r1
+ { 1761, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1761 = RCR64rCL
+ { 1762, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1762 = RCR64ri
+ { 1763, 10, 1, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1763 = RCR8m1
+ { 1764, 10, 1, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1764 = RCR8mCL
+ { 1765, 11, 1, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo186 }, // Inst #1765 = RCR8mi
+ { 1766, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1766 = RCR8r1
+ { 1767, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1767 = RCR8rCL
+ { 1768, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1768 = RCR8ri
+ { 1769, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList16, NULL, 0 }, // Inst #1769 = RDTSC
+ { 1770, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1770 = REP_MOVSB
+ { 1771, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1771 = REP_MOVSD
+ { 1772, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1772 = REP_MOVSQ
+ { 1773, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1773 = REP_MOVSW
+ { 1774, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList43, ImplicitList44, NULL, 0 }, // Inst #1774 = REP_STOSB
+ { 1775, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList45, ImplicitList44, NULL, 0 }, // Inst #1775 = REP_STOSD
+ { 1776, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList46, ImplicitList47, NULL, 0 }, // Inst #1776 = REP_STOSQ
+ { 1777, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList48, ImplicitList44, NULL, 0 }, // Inst #1777 = REP_STOSW
+ { 1778, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1778 = RET
+ { 1779, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(2<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1779 = RETI
+ { 1780, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1780 = ROL16m1
+ { 1781, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1781 = ROL16mCL
+ { 1782, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1782 = ROL16mi
+ { 1783, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1783 = ROL16r1
+ { 1784, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1784 = ROL16rCL
+ { 1785, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1785 = ROL16ri
+ { 1786, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1786 = ROL32m1
+ { 1787, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1787 = ROL32mCL
+ { 1788, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1788 = ROL32mi
+ { 1789, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1789 = ROL32r1
+ { 1790, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1790 = ROL32rCL
+ { 1791, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1791 = ROL32ri
+ { 1792, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1792 = ROL64m1
+ { 1793, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1793 = ROL64mCL
+ { 1794, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1794 = ROL64mi
+ { 1795, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1795 = ROL64r1
+ { 1796, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1796 = ROL64rCL
+ { 1797, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1797 = ROL64ri
+ { 1798, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1798 = ROL8m1
+ { 1799, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1799 = ROL8mCL
+ { 1800, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1800 = ROL8mi
+ { 1801, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1801 = ROL8r1
+ { 1802, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1802 = ROL8rCL
+ { 1803, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1803 = ROL8ri
+ { 1804, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1804 = ROR16m1
+ { 1805, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1805 = ROR16mCL
+ { 1806, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1806 = ROR16mi
+ { 1807, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1807 = ROR16r1
+ { 1808, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1808 = ROR16rCL
+ { 1809, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1809 = ROR16ri
+ { 1810, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1810 = ROR32m1
+ { 1811, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1811 = ROR32mCL
+ { 1812, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1812 = ROR32mi
+ { 1813, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1813 = ROR32r1
+ { 1814, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1814 = ROR32rCL
+ { 1815, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1815 = ROR32ri
+ { 1816, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1816 = ROR64m1
+ { 1817, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1817 = ROR64mCL
+ { 1818, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1818 = ROR64mi
+ { 1819, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1819 = ROR64r1
+ { 1820, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1820 = ROR64rCL
+ { 1821, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1821 = ROR64ri
+ { 1822, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1822 = ROR8m1
+ { 1823, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1823 = ROR8mCL
+ { 1824, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1824 = ROR8mi
+ { 1825, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1825 = ROR8r1
+ { 1826, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1826 = ROR8rCL
+ { 1827, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1827 = ROR8ri
+ { 1828, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1828 = ROUNDPDm_Int
+ { 1829, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1829 = ROUNDPDr_Int
+ { 1830, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1830 = ROUNDPSm_Int
+ { 1831, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1831 = ROUNDPSr_Int
+ { 1832, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1832 = ROUNDSDm_Int
+ { 1833, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1833 = ROUNDSDr_Int
+ { 1834, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #1834 = ROUNDSSm_Int
+ { 1835, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1835 = ROUNDSSr_Int
+ { 1836, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1836 = RSQRTPSm
+ { 1837, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1837 = RSQRTPSm_Int
+ { 1838, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1838 = RSQRTPSr
+ { 1839, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1839 = RSQRTPSr_Int
+ { 1840, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #1840 = RSQRTSSm
+ { 1841, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #1841 = RSQRTSSm_Int
+ { 1842, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1842 = RSQRTSSr
+ { 1843, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1843 = RSQRTSSr_Int
+ { 1844, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList26, ImplicitList1, Barriers1, 0 }, // Inst #1844 = SAHF
+ { 1845, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1845 = SAR16m1
+ { 1846, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1846 = SAR16mCL
+ { 1847, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1847 = SAR16mi
+ { 1848, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1848 = SAR16r1
+ { 1849, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1849 = SAR16rCL
+ { 1850, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1850 = SAR16ri
+ { 1851, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1851 = SAR32m1
+ { 1852, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1852 = SAR32mCL
+ { 1853, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1853 = SAR32mi
+ { 1854, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1854 = SAR32r1
+ { 1855, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1855 = SAR32rCL
+ { 1856, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1856 = SAR32ri
+ { 1857, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1857 = SAR64m1
+ { 1858, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1858 = SAR64mCL
+ { 1859, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1859 = SAR64mi
+ { 1860, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1860 = SAR64r1
+ { 1861, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1861 = SAR64rCL
+ { 1862, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1862 = SAR64ri
+ { 1863, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1863 = SAR8m1
+ { 1864, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1864 = SAR8mCL
+ { 1865, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1865 = SAR8mi
+ { 1866, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1866 = SAR8r1
+ { 1867, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1867 = SAR8rCL
+ { 1868, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1868 = SAR8ri
+ { 1869, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1869 = SBB16i16
+ { 1870, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1870 = SBB16mi
+ { 1871, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1871 = SBB16mi8
+ { 1872, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1872 = SBB16mr
+ { 1873, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1873 = SBB16ri
+ { 1874, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1874 = SBB16ri8
+ { 1875, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1875 = SBB16rm
+ { 1876, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1876 = SBB16rr
+ { 1877, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1877 = SBB32i32
+ { 1878, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1878 = SBB32mi
+ { 1879, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1879 = SBB32mi8
+ { 1880, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1880 = SBB32mr
+ { 1881, 3, 1, 0, "SBB32ri", 0, 0|19|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1881 = SBB32ri
+ { 1882, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1882 = SBB32ri8
+ { 1883, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1883 = SBB32rm
+ { 1884, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1884 = SBB32rr
+ { 1885, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1885 = SBB64i32
+ { 1886, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1886 = SBB64mi32
+ { 1887, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1887 = SBB64mi8
+ { 1888, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1888 = SBB64mr
+ { 1889, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1889 = SBB64ri32
+ { 1890, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1890 = SBB64ri8
+ { 1891, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1891 = SBB64rm
+ { 1892, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1892 = SBB64rr
+ { 1893, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1893 = SBB8i8
+ { 1894, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1894 = SBB8mi
+ { 1895, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #1895 = SBB8mr
+ { 1896, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1896 = SBB8ri
+ { 1897, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1897 = SBB8rm
+ { 1898, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1898 = SBB8rr
+ { 1899, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #1899 = SCAS16
+ { 1900, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #1900 = SCAS32
+ { 1901, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #1901 = SCAS64
+ { 1902, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1902 = SCAS8
+ { 1903, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1903 = SETAEm
+ { 1904, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1904 = SETAEr
+ { 1905, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1905 = SETAm
+ { 1906, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1906 = SETAr
+ { 1907, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1907 = SETBEm
+ { 1908, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1908 = SETBEr
+ { 1909, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1909 = SETB_C16r
+ { 1910, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #1910 = SETB_C32r
+ { 1911, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1911 = SETB_C64r
+ { 1912, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1912 = SETB_C8r
+ { 1913, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1913 = SETBm
+ { 1914, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1914 = SETBr
+ { 1915, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1915 = SETEm
+ { 1916, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1916 = SETEr
+ { 1917, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1917 = SETGEm
+ { 1918, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1918 = SETGEr
+ { 1919, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1919 = SETGm
+ { 1920, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1920 = SETGr
+ { 1921, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1921 = SETLEm
+ { 1922, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1922 = SETLEr
+ { 1923, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1923 = SETLm
+ { 1924, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1924 = SETLr
+ { 1925, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1925 = SETNEm
+ { 1926, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1926 = SETNEr
+ { 1927, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1927 = SETNOm
+ { 1928, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1928 = SETNOr
+ { 1929, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1929 = SETNPm
+ { 1930, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1930 = SETNPr
+ { 1931, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1931 = SETNSm
+ { 1932, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1932 = SETNSr
+ { 1933, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1933 = SETOm
+ { 1934, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1934 = SETOr
+ { 1935, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1935 = SETPm
+ { 1936, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1936 = SETPr
+ { 1937, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo29 }, // Inst #1937 = SETSm
+ { 1938, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo93 }, // Inst #1938 = SETSr
+ { 1939, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1939 = SFENCE
+ { 1940, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1940 = SHL16m1
+ { 1941, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1941 = SHL16mCL
+ { 1942, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1942 = SHL16mi
+ { 1943, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1943 = SHL16r1
+ { 1944, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1944 = SHL16rCL
+ { 1945, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1945 = SHL16ri
+ { 1946, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1946 = SHL32m1
+ { 1947, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1947 = SHL32mCL
+ { 1948, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1948 = SHL32mi
+ { 1949, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1949 = SHL32r1
+ { 1950, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1950 = SHL32rCL
+ { 1951, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1951 = SHL32ri
+ { 1952, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1952 = SHL64m1
+ { 1953, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1953 = SHL64mCL
+ { 1954, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1954 = SHL64mi
+ { 1955, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1955 = SHL64r1
+ { 1956, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1956 = SHL64rCL
+ { 1957, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1957 = SHL64ri
+ { 1958, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1958 = SHL8m1
+ { 1959, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1959 = SHL8mCL
+ { 1960, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1960 = SHL8mi
+ { 1961, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1961 = SHL8r1
+ { 1962, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1962 = SHL8rCL
+ { 1963, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1963 = SHL8ri
+ { 1964, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1964 = SHLD16mrCL
+ { 1965, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo187 }, // Inst #1965 = SHLD16mri8
+ { 1966, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1966 = SHLD16rrCL
+ { 1967, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo188 }, // Inst #1967 = SHLD16rri8
+ { 1968, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1968 = SHLD32mrCL
+ { 1969, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1969 = SHLD32mri8
+ { 1970, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1970 = SHLD32rrCL
+ { 1971, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #1971 = SHLD32rri8
+ { 1972, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1972 = SHLD64mrCL
+ { 1973, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #1973 = SHLD64mri8
+ { 1974, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1974 = SHLD64rrCL
+ { 1975, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #1975 = SHLD64rri8
+ { 1976, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1976 = SHR16m1
+ { 1977, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1977 = SHR16mCL
+ { 1978, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1978 = SHR16mi
+ { 1979, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1979 = SHR16r1
+ { 1980, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo90 }, // Inst #1980 = SHR16rCL
+ { 1981, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1981 = SHR16ri
+ { 1982, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1982 = SHR32m1
+ { 1983, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1983 = SHR32mCL
+ { 1984, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1984 = SHR32mi
+ { 1985, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1985 = SHR32r1
+ { 1986, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #1986 = SHR32rCL
+ { 1987, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1987 = SHR32ri
+ { 1988, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1988 = SHR64m1
+ { 1989, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1989 = SHR64mCL
+ { 1990, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1990 = SHR64mi
+ { 1991, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1991 = SHR64r1
+ { 1992, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1992 = SHR64rCL
+ { 1993, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1993 = SHR64ri
+ { 1994, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1994 = SHR8m1
+ { 1995, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo29 }, // Inst #1995 = SHR8mCL
+ { 1996, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1996 = SHR8mi
+ { 1997, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1997 = SHR8r1
+ { 1998, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1998 = SHR8rCL
+ { 1999, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1999 = SHR8ri
+ { 2000, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2000 = SHRD16mrCL
+ { 2001, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo187 }, // Inst #2001 = SHRD16mri8
+ { 2002, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2002 = SHRD16rrCL
+ { 2003, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo188 }, // Inst #2003 = SHRD16rri8
+ { 2004, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2004 = SHRD32mrCL
+ { 2005, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #2005 = SHRD32mri8
+ { 2006, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2006 = SHRD32rrCL
+ { 2007, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2007 = SHRD32rri8
+ { 2008, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2008 = SHRD64mrCL
+ { 2009, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2009 = SHRD64mri8
+ { 2010, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2010 = SHRD64rrCL
+ { 2011, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2011 = SHRD64rri8
+ { 2012, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #2012 = SHUFPDrmi
+ { 2013, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2013 = SHUFPDrri
+ { 2014, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo43 }, // Inst #2014 = SHUFPSrmi
+ { 2015, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2015 = SHUFPSrri
+ { 2016, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2016 = SIN_F
+ { 2017, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2017 = SIN_Fp32
+ { 2018, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2018 = SIN_Fp64
+ { 2019, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2019 = SIN_Fp80
+ { 2020, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2020 = SQRTPDm
+ { 2021, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2021 = SQRTPDm_Int
+ { 2022, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2022 = SQRTPDr
+ { 2023, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2023 = SQRTPDr_Int
+ { 2024, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2024 = SQRTPSm
+ { 2025, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2025 = SQRTPSm_Int
+ { 2026, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2026 = SQRTPSr
+ { 2027, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2027 = SQRTPSr_Int
+ { 2028, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2028 = SQRTSDm
+ { 2029, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2029 = SQRTSDm_Int
+ { 2030, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #2030 = SQRTSDr
+ { 2031, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2031 = SQRTSDr_Int
+ { 2032, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #2032 = SQRTSSm
+ { 2033, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #2033 = SQRTSSm_Int
+ { 2034, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2034 = SQRTSSr
+ { 2035, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2035 = SQRTSSr_Int
+ { 2036, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2036 = SQRT_F
+ { 2037, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2037 = SQRT_Fp32
+ { 2038, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2038 = SQRT_Fp64
+ { 2039, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2039 = SQRT_Fp80
+ { 2040, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2040 = STMXCSR
+ { 2041, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2041 = ST_F32m
+ { 2042, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2042 = ST_F64m
+ { 2043, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2043 = ST_FP32m
+ { 2044, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2044 = ST_FP64m
+ { 2045, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2045 = ST_FP80m
+ { 2046, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2046 = ST_FPrr
+ { 2047, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #2047 = ST_Fp32m
+ { 2048, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2048 = ST_Fp64m
+ { 2049, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2049 = ST_Fp64m32
+ { 2050, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2050 = ST_Fp80m32
+ { 2051, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2051 = ST_Fp80m64
+ { 2052, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo96 }, // Inst #2052 = ST_FpP32m
+ { 2053, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2053 = ST_FpP64m
+ { 2054, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2054 = ST_FpP64m32
+ { 2055, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2055 = ST_FpP80m
+ { 2056, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2056 = ST_FpP80m32
+ { 2057, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2057 = ST_FpP80m64
+ { 2058, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2058 = ST_Frr
+ { 2059, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2059 = SUB16i16
+ { 2060, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2060 = SUB16mi
+ { 2061, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2061 = SUB16mi8
+ { 2062, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2062 = SUB16mr
+ { 2063, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2063 = SUB16ri
+ { 2064, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2064 = SUB16ri8
+ { 2065, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2065 = SUB16rm
+ { 2066, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2066 = SUB16rr
+ { 2067, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2067 = SUB32i32
+ { 2068, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2068 = SUB32mi
+ { 2069, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2069 = SUB32mi8
+ { 2070, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2070 = SUB32mr
+ { 2071, 3, 1, 0, "SUB32ri", 0, 0|21|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2071 = SUB32ri
+ { 2072, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2072 = SUB32ri8
+ { 2073, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2073 = SUB32rm
+ { 2074, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2074 = SUB32rr
+ { 2075, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2075 = SUB64i32
+ { 2076, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2076 = SUB64mi32
+ { 2077, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2077 = SUB64mi8
+ { 2078, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2078 = SUB64mr
+ { 2079, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2079 = SUB64ri32
+ { 2080, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2080 = SUB64ri8
+ { 2081, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2081 = SUB64rm
+ { 2082, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2082 = SUB64rr
+ { 2083, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2083 = SUB8i8
+ { 2084, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2084 = SUB8mi
+ { 2085, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #2085 = SUB8mr
+ { 2086, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2086 = SUB8ri
+ { 2087, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2087 = SUB8rm
+ { 2088, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2088 = SUB8rr
+ { 2089, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2089 = SUBPDrm
+ { 2090, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2090 = SUBPDrr
+ { 2091, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2091 = SUBPSrm
+ { 2092, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2092 = SUBPSrr
+ { 2093, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2093 = SUBR_F32m
+ { 2094, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2094 = SUBR_F64m
+ { 2095, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2095 = SUBR_FI16m
+ { 2096, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2096 = SUBR_FI32m
+ { 2097, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2097 = SUBR_FPrST0
+ { 2098, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2098 = SUBR_FST0r
+ { 2099, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2099 = SUBR_Fp32m
+ { 2100, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2100 = SUBR_Fp64m
+ { 2101, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2101 = SUBR_Fp64m32
+ { 2102, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2102 = SUBR_Fp80m32
+ { 2103, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2103 = SUBR_Fp80m64
+ { 2104, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2104 = SUBR_FpI16m32
+ { 2105, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2105 = SUBR_FpI16m64
+ { 2106, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2106 = SUBR_FpI16m80
+ { 2107, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2107 = SUBR_FpI32m32
+ { 2108, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2108 = SUBR_FpI32m64
+ { 2109, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2109 = SUBR_FpI32m80
+ { 2110, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2110 = SUBR_FrST0
+ { 2111, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2111 = SUBSDrm
+ { 2112, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2112 = SUBSDrm_Int
+ { 2113, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2113 = SUBSDrr
+ { 2114, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2114 = SUBSDrr_Int
+ { 2115, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2115 = SUBSSrm
+ { 2116, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2116 = SUBSSrm_Int
+ { 2117, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2117 = SUBSSrr
+ { 2118, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2118 = SUBSSrr_Int
+ { 2119, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2119 = SUB_F32m
+ { 2120, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2120 = SUB_F64m
+ { 2121, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2121 = SUB_FI16m
+ { 2122, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2122 = SUB_FI32m
+ { 2123, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2123 = SUB_FPrST0
+ { 2124, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2124 = SUB_FST0r
+ { 2125, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo31 }, // Inst #2125 = SUB_Fp32
+ { 2126, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2126 = SUB_Fp32m
+ { 2127, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2127 = SUB_Fp64
+ { 2128, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2128 = SUB_Fp64m
+ { 2129, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2129 = SUB_Fp64m32
+ { 2130, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2130 = SUB_Fp80
+ { 2131, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2131 = SUB_Fp80m32
+ { 2132, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2132 = SUB_Fp80m64
+ { 2133, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2133 = SUB_FpI16m32
+ { 2134, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2134 = SUB_FpI16m64
+ { 2135, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2135 = SUB_FpI16m80
+ { 2136, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2136 = SUB_FpI32m32
+ { 2137, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2137 = SUB_FpI32m64
+ { 2138, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2138 = SUB_FpI32m80
+ { 2139, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2139 = SUB_FrST0
+ { 2140, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2140 = SYSCALL
+ { 2141, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2141 = SYSENTER
+ { 2142, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2142 = SYSEXIT
+ { 2143, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2143 = SYSEXIT64
+ { 2144, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2144 = SYSRET
+ { 2145, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2145 = TAILJMPd
+ { 2146, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2146 = TAILJMPm
+ { 2147, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #2147 = TAILJMPr
+ { 2148, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2148 = TAILJMPr64
+ { 2149, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo37 }, // Inst #2149 = TCRETURNdi
+ { 2150, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo37 }, // Inst #2150 = TCRETURNdi64
+ { 2151, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo54 }, // Inst #2151 = TCRETURNri
+ { 2152, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2152 = TCRETURNri64
+ { 2153, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2153 = TEST16i16
+ { 2154, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2154 = TEST16mi
+ { 2155, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2155 = TEST16ri
+ { 2156, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo45 }, // Inst #2156 = TEST16rm
+ { 2157, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2157 = TEST16rr
+ { 2158, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2158 = TEST32i32
+ { 2159, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2159 = TEST32mi
+ { 2160, 2, 0, 0, "TEST32ri", 0, 0|16|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2160 = TEST32ri
+ { 2161, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2161 = TEST32rm
+ { 2162, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2162 = TEST32rr
+ { 2163, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2163 = TEST64i32
+ { 2164, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2164 = TEST64mi32
+ { 2165, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2165 = TEST64ri32
+ { 2166, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2166 = TEST64rm
+ { 2167, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2167 = TEST64rr
+ { 2168, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2168 = TEST8i8
+ { 2169, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2169 = TEST8mi
+ { 2170, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2170 = TEST8ri
+ { 2171, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2171 = TEST8rm
+ { 2172, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #2172 = TEST8rr
+ { 2173, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo194 }, // Inst #2173 = TLS_addr32
+ { 2174, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo195 }, // Inst #2174 = TLS_addr64
+ { 2175, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2175 = TRAP
+ { 2176, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2176 = TST_F
+ { 2177, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2177 = TST_Fp32
+ { 2178, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2178 = TST_Fp64
+ { 2179, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2179 = TST_Fp80
+ { 2180, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2180 = UCOMISDrm
+ { 2181, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo104 }, // Inst #2181 = UCOMISDrr
+ { 2182, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #2182 = UCOMISSrm
+ { 2183, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2183 = UCOMISSrr
+ { 2184, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2184 = UCOM_FIPr
+ { 2185, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2185 = UCOM_FIr
+ { 2186, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList23, ImplicitList1, Barriers1, 0 }, // Inst #2186 = UCOM_FPPr
+ { 2187, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = UCOM_FPr
+ { 2188, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2188 = UCOM_FpIr32
+ { 2189, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2189 = UCOM_FpIr64
+ { 2190, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2190 = UCOM_FpIr80
+ { 2191, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2191 = UCOM_Fpr32
+ { 2192, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2192 = UCOM_Fpr64
+ { 2193, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2193 = UCOM_Fpr80
+ { 2194, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2194 = UCOM_Fr
+ { 2195, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2195 = UNPCKHPDrm
+ { 2196, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2196 = UNPCKHPDrr
+ { 2197, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2197 = UNPCKHPSrm
+ { 2198, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2198 = UNPCKHPSrr
+ { 2199, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2199 = UNPCKLPDrm
+ { 2200, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2200 = UNPCKLPDrr
+ { 2201, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2201 = UNPCKLPSrm
+ { 2202, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2202 = UNPCKLPSrr
+ { 2203, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo196 }, // Inst #2203 = VASTART_SAVE_XMM_REGS
+ { 2204, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo197 }, // Inst #2204 = V_SET0
+ { 2205, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo197 }, // Inst #2205 = V_SETALLONES
+ { 2206, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2206 = WAIT
+ { 2207, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo29 }, // Inst #2207 = WINCALL64m
+ { 2208, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo5 }, // Inst #2208 = WINCALL64pcrel32
+ { 2209, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo57 }, // Inst #2209 = WINCALL64r
+ { 2210, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo39 }, // Inst #2210 = XCHG16rm
+ { 2211, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo40 }, // Inst #2211 = XCHG32rm
+ { 2212, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo41 }, // Inst #2212 = XCHG64rm
+ { 2213, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo42 }, // Inst #2213 = XCHG8rm
+ { 2214, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2214 = XCH_F
+ { 2215, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2215 = XOR16i16
+ { 2216, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2216 = XOR16mi
+ { 2217, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2217 = XOR16mi8
+ { 2218, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2218 = XOR16mr
+ { 2219, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2219 = XOR16ri
+ { 2220, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2220 = XOR16ri8
+ { 2221, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2221 = XOR16rm
+ { 2222, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2222 = XOR16rr
+ { 2223, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2223 = XOR32i32
+ { 2224, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2224 = XOR32mi
+ { 2225, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2225 = XOR32mi8
+ { 2226, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2226 = XOR32mr
+ { 2227, 3, 1, 0, "XOR32ri", 0, 0|22|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2227 = XOR32ri
+ { 2228, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2228 = XOR32ri8
+ { 2229, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2229 = XOR32rm
+ { 2230, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2230 = XOR32rr
+ { 2231, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2231 = XOR64i32
+ { 2232, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2232 = XOR64mi32
+ { 2233, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2233 = XOR64mi8
+ { 2234, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2234 = XOR64mr
+ { 2235, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2235 = XOR64ri32
+ { 2236, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2236 = XOR64ri8
+ { 2237, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2237 = XOR64rm
+ { 2238, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2238 = XOR64rr
+ { 2239, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2239 = XOR8i8
+ { 2240, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2240 = XOR8mi
+ { 2241, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #2241 = XOR8mr
+ { 2242, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2242 = XOR8ri
+ { 2243, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2243 = XOR8rm
+ { 2244, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2244 = XOR8rr
+ { 2245, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2245 = XORPDrm
+ { 2246, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2246 = XORPDrr
+ { 2247, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2247 = XORPSrm
+ { 2248, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2248 = XORPSrr
+};
+} // End llvm namespace
diff --git a/libclamav/c++/X86GenInstrNames.inc b/libclamav/c++/X86GenInstrNames.inc
new file mode 100644
index 0000000..a65c3c4
--- /dev/null
+++ b/libclamav/c++/X86GenInstrNames.inc
@@ -0,0 +1,2265 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Instruction Enum Values
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace X86 {
+ enum {
+ PHI = 0,
+ INLINEASM = 1,
+ DBG_LABEL = 2,
+ EH_LABEL = 3,
+ GC_LABEL = 4,
+ KILL = 5,
+ EXTRACT_SUBREG = 6,
+ INSERT_SUBREG = 7,
+ IMPLICIT_DEF = 8,
+ SUBREG_TO_REG = 9,
+ COPY_TO_REGCLASS = 10,
+ ABS_F = 11,
+ ABS_Fp32 = 12,
+ ABS_Fp64 = 13,
+ ABS_Fp80 = 14,
+ ADC16i16 = 15,
+ ADC16mi = 16,
+ ADC16mi8 = 17,
+ ADC16mr = 18,
+ ADC16ri = 19,
+ ADC16ri8 = 20,
+ ADC16rm = 21,
+ ADC16rr = 22,
+ ADC32i32 = 23,
+ ADC32mi = 24,
+ ADC32mi8 = 25,
+ ADC32mr = 26,
+ ADC32ri = 27,
+ ADC32ri8 = 28,
+ ADC32rm = 29,
+ ADC32rr = 30,
+ ADC64i32 = 31,
+ ADC64mi32 = 32,
+ ADC64mi8 = 33,
+ ADC64mr = 34,
+ ADC64ri32 = 35,
+ ADC64ri8 = 36,
+ ADC64rm = 37,
+ ADC64rr = 38,
+ ADC8i8 = 39,
+ ADC8mi = 40,
+ ADC8mr = 41,
+ ADC8ri = 42,
+ ADC8rm = 43,
+ ADC8rr = 44,
+ ADD16i16 = 45,
+ ADD16mi = 46,
+ ADD16mi8 = 47,
+ ADD16mr = 48,
+ ADD16mrmrr = 49,
+ ADD16ri = 50,
+ ADD16ri8 = 51,
+ ADD16rm = 52,
+ ADD16rr = 53,
+ ADD32i32 = 54,
+ ADD32mi = 55,
+ ADD32mi8 = 56,
+ ADD32mr = 57,
+ ADD32mrmrr = 58,
+ ADD32ri = 59,
+ ADD32ri8 = 60,
+ ADD32rm = 61,
+ ADD32rr = 62,
+ ADD64i32 = 63,
+ ADD64mi32 = 64,
+ ADD64mi8 = 65,
+ ADD64mr = 66,
+ ADD64mrmrr = 67,
+ ADD64ri32 = 68,
+ ADD64ri8 = 69,
+ ADD64rm = 70,
+ ADD64rr = 71,
+ ADD8i8 = 72,
+ ADD8mi = 73,
+ ADD8mr = 74,
+ ADD8mrmrr = 75,
+ ADD8ri = 76,
+ ADD8rm = 77,
+ ADD8rr = 78,
+ ADDPDrm = 79,
+ ADDPDrr = 80,
+ ADDPSrm = 81,
+ ADDPSrr = 82,
+ ADDSDrm = 83,
+ ADDSDrm_Int = 84,
+ ADDSDrr = 85,
+ ADDSDrr_Int = 86,
+ ADDSSrm = 87,
+ ADDSSrm_Int = 88,
+ ADDSSrr = 89,
+ ADDSSrr_Int = 90,
+ ADDSUBPDrm = 91,
+ ADDSUBPDrr = 92,
+ ADDSUBPSrm = 93,
+ ADDSUBPSrr = 94,
+ ADD_F32m = 95,
+ ADD_F64m = 96,
+ ADD_FI16m = 97,
+ ADD_FI32m = 98,
+ ADD_FPrST0 = 99,
+ ADD_FST0r = 100,
+ ADD_Fp32 = 101,
+ ADD_Fp32m = 102,
+ ADD_Fp64 = 103,
+ ADD_Fp64m = 104,
+ ADD_Fp64m32 = 105,
+ ADD_Fp80 = 106,
+ ADD_Fp80m32 = 107,
+ ADD_Fp80m64 = 108,
+ ADD_FpI16m32 = 109,
+ ADD_FpI16m64 = 110,
+ ADD_FpI16m80 = 111,
+ ADD_FpI32m32 = 112,
+ ADD_FpI32m64 = 113,
+ ADD_FpI32m80 = 114,
+ ADD_FrST0 = 115,
+ ADJCALLSTACKDOWN32 = 116,
+ ADJCALLSTACKDOWN64 = 117,
+ ADJCALLSTACKUP32 = 118,
+ ADJCALLSTACKUP64 = 119,
+ AND16i16 = 120,
+ AND16mi = 121,
+ AND16mi8 = 122,
+ AND16mr = 123,
+ AND16ri = 124,
+ AND16ri8 = 125,
+ AND16rm = 126,
+ AND16rr = 127,
+ AND32i32 = 128,
+ AND32mi = 129,
+ AND32mi8 = 130,
+ AND32mr = 131,
+ AND32ri = 132,
+ AND32ri8 = 133,
+ AND32rm = 134,
+ AND32rr = 135,
+ AND64i32 = 136,
+ AND64mi32 = 137,
+ AND64mi8 = 138,
+ AND64mr = 139,
+ AND64ri32 = 140,
+ AND64ri8 = 141,
+ AND64rm = 142,
+ AND64rr = 143,
+ AND8i8 = 144,
+ AND8mi = 145,
+ AND8mr = 146,
+ AND8ri = 147,
+ AND8rm = 148,
+ AND8rr = 149,
+ ANDNPDrm = 150,
+ ANDNPDrr = 151,
+ ANDNPSrm = 152,
+ ANDNPSrr = 153,
+ ANDPDrm = 154,
+ ANDPDrr = 155,
+ ANDPSrm = 156,
+ ANDPSrr = 157,
+ ATOMADD6432 = 158,
+ ATOMAND16 = 159,
+ ATOMAND32 = 160,
+ ATOMAND64 = 161,
+ ATOMAND6432 = 162,
+ ATOMAND8 = 163,
+ ATOMMAX16 = 164,
+ ATOMMAX32 = 165,
+ ATOMMAX64 = 166,
+ ATOMMIN16 = 167,
+ ATOMMIN32 = 168,
+ ATOMMIN64 = 169,
+ ATOMNAND16 = 170,
+ ATOMNAND32 = 171,
+ ATOMNAND64 = 172,
+ ATOMNAND6432 = 173,
+ ATOMNAND8 = 174,
+ ATOMOR16 = 175,
+ ATOMOR32 = 176,
+ ATOMOR64 = 177,
+ ATOMOR6432 = 178,
+ ATOMOR8 = 179,
+ ATOMSUB6432 = 180,
+ ATOMSWAP6432 = 181,
+ ATOMUMAX16 = 182,
+ ATOMUMAX32 = 183,
+ ATOMUMAX64 = 184,
+ ATOMUMIN16 = 185,
+ ATOMUMIN32 = 186,
+ ATOMUMIN64 = 187,
+ ATOMXOR16 = 188,
+ ATOMXOR32 = 189,
+ ATOMXOR64 = 190,
+ ATOMXOR6432 = 191,
+ ATOMXOR8 = 192,
+ BLENDPDrmi = 193,
+ BLENDPDrri = 194,
+ BLENDPSrmi = 195,
+ BLENDPSrri = 196,
+ BLENDVPDrm0 = 197,
+ BLENDVPDrr0 = 198,
+ BLENDVPSrm0 = 199,
+ BLENDVPSrr0 = 200,
+ BSF16rm = 201,
+ BSF16rr = 202,
+ BSF32rm = 203,
+ BSF32rr = 204,
+ BSF64rm = 205,
+ BSF64rr = 206,
+ BSR16rm = 207,
+ BSR16rr = 208,
+ BSR32rm = 209,
+ BSR32rr = 210,
+ BSR64rm = 211,
+ BSR64rr = 212,
+ BSWAP32r = 213,
+ BSWAP64r = 214,
+ BT16mi8 = 215,
+ BT16ri8 = 216,
+ BT16rr = 217,
+ BT32mi8 = 218,
+ BT32ri8 = 219,
+ BT32rr = 220,
+ BT64mi8 = 221,
+ BT64ri8 = 222,
+ BT64rr = 223,
+ CALL32m = 224,
+ CALL32r = 225,
+ CALL64m = 226,
+ CALL64pcrel32 = 227,
+ CALL64r = 228,
+ CALLpcrel32 = 229,
+ CBW = 230,
+ CDQ = 231,
+ CDQE = 232,
+ CHS_F = 233,
+ CHS_Fp32 = 234,
+ CHS_Fp64 = 235,
+ CHS_Fp80 = 236,
+ CLFLUSH = 237,
+ CMOVA16rm = 238,
+ CMOVA16rr = 239,
+ CMOVA32rm = 240,
+ CMOVA32rr = 241,
+ CMOVA64rm = 242,
+ CMOVA64rr = 243,
+ CMOVAE16rm = 244,
+ CMOVAE16rr = 245,
+ CMOVAE32rm = 246,
+ CMOVAE32rr = 247,
+ CMOVAE64rm = 248,
+ CMOVAE64rr = 249,
+ CMOVB16rm = 250,
+ CMOVB16rr = 251,
+ CMOVB32rm = 252,
+ CMOVB32rr = 253,
+ CMOVB64rm = 254,
+ CMOVB64rr = 255,
+ CMOVBE16rm = 256,
+ CMOVBE16rr = 257,
+ CMOVBE32rm = 258,
+ CMOVBE32rr = 259,
+ CMOVBE64rm = 260,
+ CMOVBE64rr = 261,
+ CMOVBE_F = 262,
+ CMOVBE_Fp32 = 263,
+ CMOVBE_Fp64 = 264,
+ CMOVBE_Fp80 = 265,
+ CMOVB_F = 266,
+ CMOVB_Fp32 = 267,
+ CMOVB_Fp64 = 268,
+ CMOVB_Fp80 = 269,
+ CMOVE16rm = 270,
+ CMOVE16rr = 271,
+ CMOVE32rm = 272,
+ CMOVE32rr = 273,
+ CMOVE64rm = 274,
+ CMOVE64rr = 275,
+ CMOVE_F = 276,
+ CMOVE_Fp32 = 277,
+ CMOVE_Fp64 = 278,
+ CMOVE_Fp80 = 279,
+ CMOVG16rm = 280,
+ CMOVG16rr = 281,
+ CMOVG32rm = 282,
+ CMOVG32rr = 283,
+ CMOVG64rm = 284,
+ CMOVG64rr = 285,
+ CMOVGE16rm = 286,
+ CMOVGE16rr = 287,
+ CMOVGE32rm = 288,
+ CMOVGE32rr = 289,
+ CMOVGE64rm = 290,
+ CMOVGE64rr = 291,
+ CMOVL16rm = 292,
+ CMOVL16rr = 293,
+ CMOVL32rm = 294,
+ CMOVL32rr = 295,
+ CMOVL64rm = 296,
+ CMOVL64rr = 297,
+ CMOVLE16rm = 298,
+ CMOVLE16rr = 299,
+ CMOVLE32rm = 300,
+ CMOVLE32rr = 301,
+ CMOVLE64rm = 302,
+ CMOVLE64rr = 303,
+ CMOVNBE_F = 304,
+ CMOVNBE_Fp32 = 305,
+ CMOVNBE_Fp64 = 306,
+ CMOVNBE_Fp80 = 307,
+ CMOVNB_F = 308,
+ CMOVNB_Fp32 = 309,
+ CMOVNB_Fp64 = 310,
+ CMOVNB_Fp80 = 311,
+ CMOVNE16rm = 312,
+ CMOVNE16rr = 313,
+ CMOVNE32rm = 314,
+ CMOVNE32rr = 315,
+ CMOVNE64rm = 316,
+ CMOVNE64rr = 317,
+ CMOVNE_F = 318,
+ CMOVNE_Fp32 = 319,
+ CMOVNE_Fp64 = 320,
+ CMOVNE_Fp80 = 321,
+ CMOVNO16rm = 322,
+ CMOVNO16rr = 323,
+ CMOVNO32rm = 324,
+ CMOVNO32rr = 325,
+ CMOVNO64rm = 326,
+ CMOVNO64rr = 327,
+ CMOVNP16rm = 328,
+ CMOVNP16rr = 329,
+ CMOVNP32rm = 330,
+ CMOVNP32rr = 331,
+ CMOVNP64rm = 332,
+ CMOVNP64rr = 333,
+ CMOVNP_F = 334,
+ CMOVNP_Fp32 = 335,
+ CMOVNP_Fp64 = 336,
+ CMOVNP_Fp80 = 337,
+ CMOVNS16rm = 338,
+ CMOVNS16rr = 339,
+ CMOVNS32rm = 340,
+ CMOVNS32rr = 341,
+ CMOVNS64rm = 342,
+ CMOVNS64rr = 343,
+ CMOVO16rm = 344,
+ CMOVO16rr = 345,
+ CMOVO32rm = 346,
+ CMOVO32rr = 347,
+ CMOVO64rm = 348,
+ CMOVO64rr = 349,
+ CMOVP16rm = 350,
+ CMOVP16rr = 351,
+ CMOVP32rm = 352,
+ CMOVP32rr = 353,
+ CMOVP64rm = 354,
+ CMOVP64rr = 355,
+ CMOVP_F = 356,
+ CMOVP_Fp32 = 357,
+ CMOVP_Fp64 = 358,
+ CMOVP_Fp80 = 359,
+ CMOVS16rm = 360,
+ CMOVS16rr = 361,
+ CMOVS32rm = 362,
+ CMOVS32rr = 363,
+ CMOVS64rm = 364,
+ CMOVS64rr = 365,
+ CMOV_FR32 = 366,
+ CMOV_FR64 = 367,
+ CMOV_GR8 = 368,
+ CMOV_V1I64 = 369,
+ CMOV_V2F64 = 370,
+ CMOV_V2I64 = 371,
+ CMOV_V4F32 = 372,
+ CMP16i16 = 373,
+ CMP16mi = 374,
+ CMP16mi8 = 375,
+ CMP16mr = 376,
+ CMP16mrmrr = 377,
+ CMP16ri = 378,
+ CMP16ri8 = 379,
+ CMP16rm = 380,
+ CMP16rr = 381,
+ CMP32i32 = 382,
+ CMP32mi = 383,
+ CMP32mi8 = 384,
+ CMP32mr = 385,
+ CMP32mrmrr = 386,
+ CMP32ri = 387,
+ CMP32ri8 = 388,
+ CMP32rm = 389,
+ CMP32rr = 390,
+ CMP64i32 = 391,
+ CMP64mi32 = 392,
+ CMP64mi8 = 393,
+ CMP64mr = 394,
+ CMP64mrmrr = 395,
+ CMP64ri32 = 396,
+ CMP64ri8 = 397,
+ CMP64rm = 398,
+ CMP64rr = 399,
+ CMP8i8 = 400,
+ CMP8mi = 401,
+ CMP8mr = 402,
+ CMP8mrmrr = 403,
+ CMP8ri = 404,
+ CMP8rm = 405,
+ CMP8rr = 406,
+ CMPPDrmi = 407,
+ CMPPDrri = 408,
+ CMPPSrmi = 409,
+ CMPPSrri = 410,
+ CMPS16 = 411,
+ CMPS32 = 412,
+ CMPS64 = 413,
+ CMPS8 = 414,
+ CMPSDrm = 415,
+ CMPSDrr = 416,
+ CMPSSrm = 417,
+ CMPSSrr = 418,
+ COMISDrm = 419,
+ COMISDrr = 420,
+ COS_F = 421,
+ COS_Fp32 = 422,
+ COS_Fp64 = 423,
+ COS_Fp80 = 424,
+ CQO = 425,
+ CRC32m16 = 426,
+ CRC32m32 = 427,
+ CRC32m8 = 428,
+ CRC32r16 = 429,
+ CRC32r32 = 430,
+ CRC32r8 = 431,
+ CRC64m64 = 432,
+ CRC64r64 = 433,
+ CVTDQ2PDrm = 434,
+ CVTDQ2PDrr = 435,
+ CVTDQ2PSrm = 436,
+ CVTDQ2PSrr = 437,
+ CVTPD2DQrm = 438,
+ CVTPD2DQrr = 439,
+ CVTPS2DQrm = 440,
+ CVTPS2DQrr = 441,
+ CVTSD2SSrm = 442,
+ CVTSD2SSrr = 443,
+ CVTSI2SD64rm = 444,
+ CVTSI2SD64rr = 445,
+ CVTSI2SDrm = 446,
+ CVTSI2SDrr = 447,
+ CVTSI2SS64rm = 448,
+ CVTSI2SS64rr = 449,
+ CVTSI2SSrm = 450,
+ CVTSI2SSrr = 451,
+ CVTSS2SDrm = 452,
+ CVTSS2SDrr = 453,
+ CVTTSD2SI64rm = 454,
+ CVTTSD2SI64rr = 455,
+ CVTTSD2SIrm = 456,
+ CVTTSD2SIrr = 457,
+ CVTTSS2SI64rm = 458,
+ CVTTSS2SI64rr = 459,
+ CVTTSS2SIrm = 460,
+ CVTTSS2SIrr = 461,
+ CWD = 462,
+ CWDE = 463,
+ DEC16m = 464,
+ DEC16r = 465,
+ DEC32m = 466,
+ DEC32r = 467,
+ DEC64_16m = 468,
+ DEC64_16r = 469,
+ DEC64_32m = 470,
+ DEC64_32r = 471,
+ DEC64m = 472,
+ DEC64r = 473,
+ DEC8m = 474,
+ DEC8r = 475,
+ DIV16m = 476,
+ DIV16r = 477,
+ DIV32m = 478,
+ DIV32r = 479,
+ DIV64m = 480,
+ DIV64r = 481,
+ DIV8m = 482,
+ DIV8r = 483,
+ DIVPDrm = 484,
+ DIVPDrr = 485,
+ DIVPSrm = 486,
+ DIVPSrr = 487,
+ DIVR_F32m = 488,
+ DIVR_F64m = 489,
+ DIVR_FI16m = 490,
+ DIVR_FI32m = 491,
+ DIVR_FPrST0 = 492,
+ DIVR_FST0r = 493,
+ DIVR_Fp32m = 494,
+ DIVR_Fp64m = 495,
+ DIVR_Fp64m32 = 496,
+ DIVR_Fp80m32 = 497,
+ DIVR_Fp80m64 = 498,
+ DIVR_FpI16m32 = 499,
+ DIVR_FpI16m64 = 500,
+ DIVR_FpI16m80 = 501,
+ DIVR_FpI32m32 = 502,
+ DIVR_FpI32m64 = 503,
+ DIVR_FpI32m80 = 504,
+ DIVR_FrST0 = 505,
+ DIVSDrm = 506,
+ DIVSDrm_Int = 507,
+ DIVSDrr = 508,
+ DIVSDrr_Int = 509,
+ DIVSSrm = 510,
+ DIVSSrm_Int = 511,
+ DIVSSrr = 512,
+ DIVSSrr_Int = 513,
+ DIV_F32m = 514,
+ DIV_F64m = 515,
+ DIV_FI16m = 516,
+ DIV_FI32m = 517,
+ DIV_FPrST0 = 518,
+ DIV_FST0r = 519,
+ DIV_Fp32 = 520,
+ DIV_Fp32m = 521,
+ DIV_Fp64 = 522,
+ DIV_Fp64m = 523,
+ DIV_Fp64m32 = 524,
+ DIV_Fp80 = 525,
+ DIV_Fp80m32 = 526,
+ DIV_Fp80m64 = 527,
+ DIV_FpI16m32 = 528,
+ DIV_FpI16m64 = 529,
+ DIV_FpI16m80 = 530,
+ DIV_FpI32m32 = 531,
+ DIV_FpI32m64 = 532,
+ DIV_FpI32m80 = 533,
+ DIV_FrST0 = 534,
+ DPPDrmi = 535,
+ DPPDrri = 536,
+ DPPSrmi = 537,
+ DPPSrri = 538,
+ EH_RETURN = 539,
+ EH_RETURN64 = 540,
+ ENTER = 541,
+ EXTRACTPSmr = 542,
+ EXTRACTPSrr = 543,
+ FARCALL16i = 544,
+ FARCALL16m = 545,
+ FARCALL32i = 546,
+ FARCALL32m = 547,
+ FARCALL64 = 548,
+ FARJMP16i = 549,
+ FARJMP16m = 550,
+ FARJMP32i = 551,
+ FARJMP32m = 552,
+ FARJMP64 = 553,
+ FBLDm = 554,
+ FBSTPm = 555,
+ FCOM32m = 556,
+ FCOM64m = 557,
+ FCOMP32m = 558,
+ FCOMP64m = 559,
+ FICOM16m = 560,
+ FICOM32m = 561,
+ FICOMP16m = 562,
+ FICOMP32m = 563,
+ FISTTP32m = 564,
+ FLDCW16m = 565,
+ FLDENVm = 566,
+ FNSTCW16m = 567,
+ FNSTSW8r = 568,
+ FP32_TO_INT16_IN_MEM = 569,
+ FP32_TO_INT32_IN_MEM = 570,
+ FP32_TO_INT64_IN_MEM = 571,
+ FP64_TO_INT16_IN_MEM = 572,
+ FP64_TO_INT32_IN_MEM = 573,
+ FP64_TO_INT64_IN_MEM = 574,
+ FP80_TO_INT16_IN_MEM = 575,
+ FP80_TO_INT32_IN_MEM = 576,
+ FP80_TO_INT64_IN_MEM = 577,
+ FP_REG_KILL = 578,
+ FRSTORm = 579,
+ FSAVEm = 580,
+ FSTENVm = 581,
+ FSTSWm = 582,
+ FS_MOV32rm = 583,
+ FpGET_ST0_32 = 584,
+ FpGET_ST0_64 = 585,
+ FpGET_ST0_80 = 586,
+ FpGET_ST1_32 = 587,
+ FpGET_ST1_64 = 588,
+ FpGET_ST1_80 = 589,
+ FpSET_ST0_32 = 590,
+ FpSET_ST0_64 = 591,
+ FpSET_ST0_80 = 592,
+ FpSET_ST1_32 = 593,
+ FpSET_ST1_64 = 594,
+ FpSET_ST1_80 = 595,
+ FsANDNPDrm = 596,
+ FsANDNPDrr = 597,
+ FsANDNPSrm = 598,
+ FsANDNPSrr = 599,
+ FsANDPDrm = 600,
+ FsANDPDrr = 601,
+ FsANDPSrm = 602,
+ FsANDPSrr = 603,
+ FsFLD0SD = 604,
+ FsFLD0SS = 605,
+ FsMOVAPDrm = 606,
+ FsMOVAPDrr = 607,
+ FsMOVAPSrm = 608,
+ FsMOVAPSrr = 609,
+ FsORPDrm = 610,
+ FsORPDrr = 611,
+ FsORPSrm = 612,
+ FsORPSrr = 613,
+ FsXORPDrm = 614,
+ FsXORPDrr = 615,
+ FsXORPSrm = 616,
+ FsXORPSrr = 617,
+ GS_MOV32rm = 618,
+ HADDPDrm = 619,
+ HADDPDrr = 620,
+ HADDPSrm = 621,
+ HADDPSrr = 622,
+ HSUBPDrm = 623,
+ HSUBPDrr = 624,
+ HSUBPSrm = 625,
+ HSUBPSrr = 626,
+ IDIV16m = 627,
+ IDIV16r = 628,
+ IDIV32m = 629,
+ IDIV32r = 630,
+ IDIV64m = 631,
+ IDIV64r = 632,
+ IDIV8m = 633,
+ IDIV8r = 634,
+ ILD_F16m = 635,
+ ILD_F32m = 636,
+ ILD_F64m = 637,
+ ILD_Fp16m32 = 638,
+ ILD_Fp16m64 = 639,
+ ILD_Fp16m80 = 640,
+ ILD_Fp32m32 = 641,
+ ILD_Fp32m64 = 642,
+ ILD_Fp32m80 = 643,
+ ILD_Fp64m32 = 644,
+ ILD_Fp64m64 = 645,
+ ILD_Fp64m80 = 646,
+ IMUL16m = 647,
+ IMUL16r = 648,
+ IMUL16rm = 649,
+ IMUL16rmi = 650,
+ IMUL16rmi8 = 651,
+ IMUL16rr = 652,
+ IMUL16rri = 653,
+ IMUL16rri8 = 654,
+ IMUL32m = 655,
+ IMUL32r = 656,
+ IMUL32rm = 657,
+ IMUL32rmi = 658,
+ IMUL32rmi8 = 659,
+ IMUL32rr = 660,
+ IMUL32rri = 661,
+ IMUL32rri8 = 662,
+ IMUL64m = 663,
+ IMUL64r = 664,
+ IMUL64rm = 665,
+ IMUL64rmi32 = 666,
+ IMUL64rmi8 = 667,
+ IMUL64rr = 668,
+ IMUL64rri32 = 669,
+ IMUL64rri8 = 670,
+ IMUL8m = 671,
+ IMUL8r = 672,
+ IN16ri = 673,
+ IN16rr = 674,
+ IN32ri = 675,
+ IN32rr = 676,
+ IN8ri = 677,
+ IN8rr = 678,
+ INC16m = 679,
+ INC16r = 680,
+ INC32m = 681,
+ INC32r = 682,
+ INC64_16m = 683,
+ INC64_16r = 684,
+ INC64_32m = 685,
+ INC64_32r = 686,
+ INC64m = 687,
+ INC64r = 688,
+ INC8m = 689,
+ INC8r = 690,
+ INSERTPSrm = 691,
+ INSERTPSrr = 692,
+ INT = 693,
+ INT3 = 694,
+ ISTT_FP16m = 695,
+ ISTT_FP32m = 696,
+ ISTT_FP64m = 697,
+ ISTT_Fp16m32 = 698,
+ ISTT_Fp16m64 = 699,
+ ISTT_Fp16m80 = 700,
+ ISTT_Fp32m32 = 701,
+ ISTT_Fp32m64 = 702,
+ ISTT_Fp32m80 = 703,
+ ISTT_Fp64m32 = 704,
+ ISTT_Fp64m64 = 705,
+ ISTT_Fp64m80 = 706,
+ IST_F16m = 707,
+ IST_F32m = 708,
+ IST_FP16m = 709,
+ IST_FP32m = 710,
+ IST_FP64m = 711,
+ IST_Fp16m32 = 712,
+ IST_Fp16m64 = 713,
+ IST_Fp16m80 = 714,
+ IST_Fp32m32 = 715,
+ IST_Fp32m64 = 716,
+ IST_Fp32m80 = 717,
+ IST_Fp64m32 = 718,
+ IST_Fp64m64 = 719,
+ IST_Fp64m80 = 720,
+ Int_CMPSDrm = 721,
+ Int_CMPSDrr = 722,
+ Int_CMPSSrm = 723,
+ Int_CMPSSrr = 724,
+ Int_COMISDrm = 725,
+ Int_COMISDrr = 726,
+ Int_COMISSrm = 727,
+ Int_COMISSrr = 728,
+ Int_CVTDQ2PDrm = 729,
+ Int_CVTDQ2PDrr = 730,
+ Int_CVTDQ2PSrm = 731,
+ Int_CVTDQ2PSrr = 732,
+ Int_CVTPD2DQrm = 733,
+ Int_CVTPD2DQrr = 734,
+ Int_CVTPD2PIrm = 735,
+ Int_CVTPD2PIrr = 736,
+ Int_CVTPD2PSrm = 737,
+ Int_CVTPD2PSrr = 738,
+ Int_CVTPI2PDrm = 739,
+ Int_CVTPI2PDrr = 740,
+ Int_CVTPI2PSrm = 741,
+ Int_CVTPI2PSrr = 742,
+ Int_CVTPS2DQrm = 743,
+ Int_CVTPS2DQrr = 744,
+ Int_CVTPS2PDrm = 745,
+ Int_CVTPS2PDrr = 746,
+ Int_CVTPS2PIrm = 747,
+ Int_CVTPS2PIrr = 748,
+ Int_CVTSD2SI64rm = 749,
+ Int_CVTSD2SI64rr = 750,
+ Int_CVTSD2SIrm = 751,
+ Int_CVTSD2SIrr = 752,
+ Int_CVTSD2SSrm = 753,
+ Int_CVTSD2SSrr = 754,
+ Int_CVTSI2SD64rm = 755,
+ Int_CVTSI2SD64rr = 756,
+ Int_CVTSI2SDrm = 757,
+ Int_CVTSI2SDrr = 758,
+ Int_CVTSI2SS64rm = 759,
+ Int_CVTSI2SS64rr = 760,
+ Int_CVTSI2SSrm = 761,
+ Int_CVTSI2SSrr = 762,
+ Int_CVTSS2SDrm = 763,
+ Int_CVTSS2SDrr = 764,
+ Int_CVTSS2SI64rm = 765,
+ Int_CVTSS2SI64rr = 766,
+ Int_CVTSS2SIrm = 767,
+ Int_CVTSS2SIrr = 768,
+ Int_CVTTPD2DQrm = 769,
+ Int_CVTTPD2DQrr = 770,
+ Int_CVTTPD2PIrm = 771,
+ Int_CVTTPD2PIrr = 772,
+ Int_CVTTPS2DQrm = 773,
+ Int_CVTTPS2DQrr = 774,
+ Int_CVTTPS2PIrm = 775,
+ Int_CVTTPS2PIrr = 776,
+ Int_CVTTSD2SI64rm = 777,
+ Int_CVTTSD2SI64rr = 778,
+ Int_CVTTSD2SIrm = 779,
+ Int_CVTTSD2SIrr = 780,
+ Int_CVTTSS2SI64rm = 781,
+ Int_CVTTSS2SI64rr = 782,
+ Int_CVTTSS2SIrm = 783,
+ Int_CVTTSS2SIrr = 784,
+ Int_UCOMISDrm = 785,
+ Int_UCOMISDrr = 786,
+ Int_UCOMISSrm = 787,
+ Int_UCOMISSrr = 788,
+ JA = 789,
+ JA8 = 790,
+ JAE = 791,
+ JAE8 = 792,
+ JB = 793,
+ JB8 = 794,
+ JBE = 795,
+ JBE8 = 796,
+ JCXZ8 = 797,
+ JE = 798,
+ JE8 = 799,
+ JG = 800,
+ JG8 = 801,
+ JGE = 802,
+ JGE8 = 803,
+ JL = 804,
+ JL8 = 805,
+ JLE = 806,
+ JLE8 = 807,
+ JMP = 808,
+ JMP32m = 809,
+ JMP32r = 810,
+ JMP64m = 811,
+ JMP64r = 812,
+ JMP8 = 813,
+ JNE = 814,
+ JNE8 = 815,
+ JNO = 816,
+ JNO8 = 817,
+ JNP = 818,
+ JNP8 = 819,
+ JNS = 820,
+ JNS8 = 821,
+ JO = 822,
+ JO8 = 823,
+ JP = 824,
+ JP8 = 825,
+ JS = 826,
+ JS8 = 827,
+ LAHF = 828,
+ LAR16rm = 829,
+ LAR16rr = 830,
+ LAR32rm = 831,
+ LAR32rr = 832,
+ LAR64rm = 833,
+ LAR64rr = 834,
+ LCMPXCHG16 = 835,
+ LCMPXCHG32 = 836,
+ LCMPXCHG64 = 837,
+ LCMPXCHG8 = 838,
+ LCMPXCHG8B = 839,
+ LDDQUrm = 840,
+ LDMXCSR = 841,
+ LD_F0 = 842,
+ LD_F1 = 843,
+ LD_F32m = 844,
+ LD_F64m = 845,
+ LD_F80m = 846,
+ LD_Fp032 = 847,
+ LD_Fp064 = 848,
+ LD_Fp080 = 849,
+ LD_Fp132 = 850,
+ LD_Fp164 = 851,
+ LD_Fp180 = 852,
+ LD_Fp32m = 853,
+ LD_Fp32m64 = 854,
+ LD_Fp32m80 = 855,
+ LD_Fp64m = 856,
+ LD_Fp64m80 = 857,
+ LD_Fp80m = 858,
+ LD_Frr = 859,
+ LEA16r = 860,
+ LEA32r = 861,
+ LEA64_32r = 862,
+ LEA64r = 863,
+ LEAVE = 864,
+ LEAVE64 = 865,
+ LFENCE = 866,
+ LOCK_ADD16mi = 867,
+ LOCK_ADD16mi8 = 868,
+ LOCK_ADD16mr = 869,
+ LOCK_ADD32mi = 870,
+ LOCK_ADD32mi8 = 871,
+ LOCK_ADD32mr = 872,
+ LOCK_ADD64mi32 = 873,
+ LOCK_ADD64mi8 = 874,
+ LOCK_ADD64mr = 875,
+ LOCK_ADD8mi = 876,
+ LOCK_ADD8mr = 877,
+ LOCK_DEC16m = 878,
+ LOCK_DEC32m = 879,
+ LOCK_DEC64m = 880,
+ LOCK_DEC8m = 881,
+ LOCK_INC16m = 882,
+ LOCK_INC32m = 883,
+ LOCK_INC64m = 884,
+ LOCK_INC8m = 885,
+ LOCK_SUB16mi = 886,
+ LOCK_SUB16mi8 = 887,
+ LOCK_SUB16mr = 888,
+ LOCK_SUB32mi = 889,
+ LOCK_SUB32mi8 = 890,
+ LOCK_SUB32mr = 891,
+ LOCK_SUB64mi32 = 892,
+ LOCK_SUB64mi8 = 893,
+ LOCK_SUB64mr = 894,
+ LOCK_SUB8mi = 895,
+ LOCK_SUB8mr = 896,
+ LODSB = 897,
+ LODSD = 898,
+ LODSQ = 899,
+ LODSW = 900,
+ LOOP = 901,
+ LOOPE = 902,
+ LOOPNE = 903,
+ LRET = 904,
+ LRETI = 905,
+ LXADD16 = 906,
+ LXADD32 = 907,
+ LXADD64 = 908,
+ LXADD8 = 909,
+ MASKMOVDQU = 910,
+ MASKMOVDQU64 = 911,
+ MAXPDrm = 912,
+ MAXPDrm_Int = 913,
+ MAXPDrr = 914,
+ MAXPDrr_Int = 915,
+ MAXPSrm = 916,
+ MAXPSrm_Int = 917,
+ MAXPSrr = 918,
+ MAXPSrr_Int = 919,
+ MAXSDrm = 920,
+ MAXSDrm_Int = 921,
+ MAXSDrr = 922,
+ MAXSDrr_Int = 923,
+ MAXSSrm = 924,
+ MAXSSrm_Int = 925,
+ MAXSSrr = 926,
+ MAXSSrr_Int = 927,
+ MFENCE = 928,
+ MINPDrm = 929,
+ MINPDrm_Int = 930,
+ MINPDrr = 931,
+ MINPDrr_Int = 932,
+ MINPSrm = 933,
+ MINPSrm_Int = 934,
+ MINPSrr = 935,
+ MINPSrr_Int = 936,
+ MINSDrm = 937,
+ MINSDrm_Int = 938,
+ MINSDrr = 939,
+ MINSDrr_Int = 940,
+ MINSSrm = 941,
+ MINSSrm_Int = 942,
+ MINSSrr = 943,
+ MINSSrr_Int = 944,
+ MMX_CVTPD2PIrm = 945,
+ MMX_CVTPD2PIrr = 946,
+ MMX_CVTPI2PDrm = 947,
+ MMX_CVTPI2PDrr = 948,
+ MMX_CVTPI2PSrm = 949,
+ MMX_CVTPI2PSrr = 950,
+ MMX_CVTPS2PIrm = 951,
+ MMX_CVTPS2PIrr = 952,
+ MMX_CVTTPD2PIrm = 953,
+ MMX_CVTTPD2PIrr = 954,
+ MMX_CVTTPS2PIrm = 955,
+ MMX_CVTTPS2PIrr = 956,
+ MMX_EMMS = 957,
+ MMX_FEMMS = 958,
+ MMX_MASKMOVQ = 959,
+ MMX_MASKMOVQ64 = 960,
+ MMX_MOVD64from64rr = 961,
+ MMX_MOVD64mr = 962,
+ MMX_MOVD64rm = 963,
+ MMX_MOVD64rr = 964,
+ MMX_MOVD64rrv164 = 965,
+ MMX_MOVD64to64rr = 966,
+ MMX_MOVDQ2Qrr = 967,
+ MMX_MOVNTQmr = 968,
+ MMX_MOVQ2DQrr = 969,
+ MMX_MOVQ2FR64rr = 970,
+ MMX_MOVQ64mr = 971,
+ MMX_MOVQ64rm = 972,
+ MMX_MOVQ64rr = 973,
+ MMX_MOVZDI2PDIrm = 974,
+ MMX_MOVZDI2PDIrr = 975,
+ MMX_PACKSSDWrm = 976,
+ MMX_PACKSSDWrr = 977,
+ MMX_PACKSSWBrm = 978,
+ MMX_PACKSSWBrr = 979,
+ MMX_PACKUSWBrm = 980,
+ MMX_PACKUSWBrr = 981,
+ MMX_PADDBrm = 982,
+ MMX_PADDBrr = 983,
+ MMX_PADDDrm = 984,
+ MMX_PADDDrr = 985,
+ MMX_PADDQrm = 986,
+ MMX_PADDQrr = 987,
+ MMX_PADDSBrm = 988,
+ MMX_PADDSBrr = 989,
+ MMX_PADDSWrm = 990,
+ MMX_PADDSWrr = 991,
+ MMX_PADDUSBrm = 992,
+ MMX_PADDUSBrr = 993,
+ MMX_PADDUSWrm = 994,
+ MMX_PADDUSWrr = 995,
+ MMX_PADDWrm = 996,
+ MMX_PADDWrr = 997,
+ MMX_PANDNrm = 998,
+ MMX_PANDNrr = 999,
+ MMX_PANDrm = 1000,
+ MMX_PANDrr = 1001,
+ MMX_PAVGBrm = 1002,
+ MMX_PAVGBrr = 1003,
+ MMX_PAVGWrm = 1004,
+ MMX_PAVGWrr = 1005,
+ MMX_PCMPEQBrm = 1006,
+ MMX_PCMPEQBrr = 1007,
+ MMX_PCMPEQDrm = 1008,
+ MMX_PCMPEQDrr = 1009,
+ MMX_PCMPEQWrm = 1010,
+ MMX_PCMPEQWrr = 1011,
+ MMX_PCMPGTBrm = 1012,
+ MMX_PCMPGTBrr = 1013,
+ MMX_PCMPGTDrm = 1014,
+ MMX_PCMPGTDrr = 1015,
+ MMX_PCMPGTWrm = 1016,
+ MMX_PCMPGTWrr = 1017,
+ MMX_PEXTRWri = 1018,
+ MMX_PINSRWrmi = 1019,
+ MMX_PINSRWrri = 1020,
+ MMX_PMADDWDrm = 1021,
+ MMX_PMADDWDrr = 1022,
+ MMX_PMAXSWrm = 1023,
+ MMX_PMAXSWrr = 1024,
+ MMX_PMAXUBrm = 1025,
+ MMX_PMAXUBrr = 1026,
+ MMX_PMINSWrm = 1027,
+ MMX_PMINSWrr = 1028,
+ MMX_PMINUBrm = 1029,
+ MMX_PMINUBrr = 1030,
+ MMX_PMOVMSKBrr = 1031,
+ MMX_PMULHUWrm = 1032,
+ MMX_PMULHUWrr = 1033,
+ MMX_PMULHWrm = 1034,
+ MMX_PMULHWrr = 1035,
+ MMX_PMULLWrm = 1036,
+ MMX_PMULLWrr = 1037,
+ MMX_PMULUDQrm = 1038,
+ MMX_PMULUDQrr = 1039,
+ MMX_PORrm = 1040,
+ MMX_PORrr = 1041,
+ MMX_PSADBWrm = 1042,
+ MMX_PSADBWrr = 1043,
+ MMX_PSHUFWmi = 1044,
+ MMX_PSHUFWri = 1045,
+ MMX_PSLLDri = 1046,
+ MMX_PSLLDrm = 1047,
+ MMX_PSLLDrr = 1048,
+ MMX_PSLLQri = 1049,
+ MMX_PSLLQrm = 1050,
+ MMX_PSLLQrr = 1051,
+ MMX_PSLLWri = 1052,
+ MMX_PSLLWrm = 1053,
+ MMX_PSLLWrr = 1054,
+ MMX_PSRADri = 1055,
+ MMX_PSRADrm = 1056,
+ MMX_PSRADrr = 1057,
+ MMX_PSRAWri = 1058,
+ MMX_PSRAWrm = 1059,
+ MMX_PSRAWrr = 1060,
+ MMX_PSRLDri = 1061,
+ MMX_PSRLDrm = 1062,
+ MMX_PSRLDrr = 1063,
+ MMX_PSRLQri = 1064,
+ MMX_PSRLQrm = 1065,
+ MMX_PSRLQrr = 1066,
+ MMX_PSRLWri = 1067,
+ MMX_PSRLWrm = 1068,
+ MMX_PSRLWrr = 1069,
+ MMX_PSUBBrm = 1070,
+ MMX_PSUBBrr = 1071,
+ MMX_PSUBDrm = 1072,
+ MMX_PSUBDrr = 1073,
+ MMX_PSUBQrm = 1074,
+ MMX_PSUBQrr = 1075,
+ MMX_PSUBSBrm = 1076,
+ MMX_PSUBSBrr = 1077,
+ MMX_PSUBSWrm = 1078,
+ MMX_PSUBSWrr = 1079,
+ MMX_PSUBUSBrm = 1080,
+ MMX_PSUBUSBrr = 1081,
+ MMX_PSUBUSWrm = 1082,
+ MMX_PSUBUSWrr = 1083,
+ MMX_PSUBWrm = 1084,
+ MMX_PSUBWrr = 1085,
+ MMX_PUNPCKHBWrm = 1086,
+ MMX_PUNPCKHBWrr = 1087,
+ MMX_PUNPCKHDQrm = 1088,
+ MMX_PUNPCKHDQrr = 1089,
+ MMX_PUNPCKHWDrm = 1090,
+ MMX_PUNPCKHWDrr = 1091,
+ MMX_PUNPCKLBWrm = 1092,
+ MMX_PUNPCKLBWrr = 1093,
+ MMX_PUNPCKLDQrm = 1094,
+ MMX_PUNPCKLDQrr = 1095,
+ MMX_PUNPCKLWDrm = 1096,
+ MMX_PUNPCKLWDrr = 1097,
+ MMX_PXORrm = 1098,
+ MMX_PXORrr = 1099,
+ MMX_V_SET0 = 1100,
+ MMX_V_SETALLONES = 1101,
+ MONITOR = 1102,
+ MOV16ao16 = 1103,
+ MOV16mi = 1104,
+ MOV16mr = 1105,
+ MOV16ms = 1106,
+ MOV16o16a = 1107,
+ MOV16r0 = 1108,
+ MOV16ri = 1109,
+ MOV16rm = 1110,
+ MOV16rr = 1111,
+ MOV16rs = 1112,
+ MOV16sm = 1113,
+ MOV16sr = 1114,
+ MOV32ao32 = 1115,
+ MOV32mi = 1116,
+ MOV32mr = 1117,
+ MOV32o32a = 1118,
+ MOV32r0 = 1119,
+ MOV32ri = 1120,
+ MOV32rm = 1121,
+ MOV32rr = 1122,
+ MOV64FSrm = 1123,
+ MOV64GSrm = 1124,
+ MOV64ao32 = 1125,
+ MOV64ao8 = 1126,
+ MOV64mi32 = 1127,
+ MOV64mr = 1128,
+ MOV64ms = 1129,
+ MOV64o32a = 1130,
+ MOV64o8a = 1131,
+ MOV64ri = 1132,
+ MOV64ri32 = 1133,
+ MOV64ri64i32 = 1134,
+ MOV64rm = 1135,
+ MOV64rr = 1136,
+ MOV64rs = 1137,
+ MOV64sm = 1138,
+ MOV64sr = 1139,
+ MOV64toPQIrr = 1140,
+ MOV64toSDrm = 1141,
+ MOV64toSDrr = 1142,
+ MOV8ao8 = 1143,
+ MOV8mi = 1144,
+ MOV8mr = 1145,
+ MOV8mr_NOREX = 1146,
+ MOV8o8a = 1147,
+ MOV8r0 = 1148,
+ MOV8ri = 1149,
+ MOV8rm = 1150,
+ MOV8rm_NOREX = 1151,
+ MOV8rr = 1152,
+ MOV8rr_NOREX = 1153,
+ MOVAPDmr = 1154,
+ MOVAPDrm = 1155,
+ MOVAPDrr = 1156,
+ MOVAPSmr = 1157,
+ MOVAPSrm = 1158,
+ MOVAPSrr = 1159,
+ MOVDDUPrm = 1160,
+ MOVDDUPrr = 1161,
+ MOVDI2PDIrm = 1162,
+ MOVDI2PDIrr = 1163,
+ MOVDI2SSrm = 1164,
+ MOVDI2SSrr = 1165,
+ MOVDQAmr = 1166,
+ MOVDQArm = 1167,
+ MOVDQArr = 1168,
+ MOVDQUmr = 1169,
+ MOVDQUmr_Int = 1170,
+ MOVDQUrm = 1171,
+ MOVDQUrm_Int = 1172,
+ MOVHLPSrr = 1173,
+ MOVHPDmr = 1174,
+ MOVHPDrm = 1175,
+ MOVHPSmr = 1176,
+ MOVHPSrm = 1177,
+ MOVLHPSrr = 1178,
+ MOVLPDmr = 1179,
+ MOVLPDrm = 1180,
+ MOVLPDrr = 1181,
+ MOVLPSmr = 1182,
+ MOVLPSrm = 1183,
+ MOVLPSrr = 1184,
+ MOVLQ128mr = 1185,
+ MOVLSD2PDrr = 1186,
+ MOVLSS2PSrr = 1187,
+ MOVMSKPDrr = 1188,
+ MOVMSKPSrr = 1189,
+ MOVNTDQArm = 1190,
+ MOVNTDQmr = 1191,
+ MOVNTImr = 1192,
+ MOVNTPDmr = 1193,
+ MOVNTPSmr = 1194,
+ MOVPC32r = 1195,
+ MOVPD2SDmr = 1196,
+ MOVPD2SDrr = 1197,
+ MOVPDI2DImr = 1198,
+ MOVPDI2DIrr = 1199,
+ MOVPQI2QImr = 1200,
+ MOVPQIto64rr = 1201,
+ MOVPS2SSmr = 1202,
+ MOVPS2SSrr = 1203,
+ MOVQI2PQIrm = 1204,
+ MOVSD2PDrm = 1205,
+ MOVSD2PDrr = 1206,
+ MOVSDmr = 1207,
+ MOVSDrm = 1208,
+ MOVSDrr = 1209,
+ MOVSDto64mr = 1210,
+ MOVSDto64rr = 1211,
+ MOVSHDUPrm = 1212,
+ MOVSHDUPrr = 1213,
+ MOVSLDUPrm = 1214,
+ MOVSLDUPrr = 1215,
+ MOVSS2DImr = 1216,
+ MOVSS2DIrr = 1217,
+ MOVSS2PSrm = 1218,
+ MOVSS2PSrr = 1219,
+ MOVSSmr = 1220,
+ MOVSSrm = 1221,
+ MOVSSrr = 1222,
+ MOVSX16rm8 = 1223,
+ MOVSX16rr8 = 1224,
+ MOVSX32rm16 = 1225,
+ MOVSX32rm8 = 1226,
+ MOVSX32rr16 = 1227,
+ MOVSX32rr8 = 1228,
+ MOVSX64rm16 = 1229,
+ MOVSX64rm32 = 1230,
+ MOVSX64rm8 = 1231,
+ MOVSX64rr16 = 1232,
+ MOVSX64rr32 = 1233,
+ MOVSX64rr8 = 1234,
+ MOVUPDmr = 1235,
+ MOVUPDmr_Int = 1236,
+ MOVUPDrm = 1237,
+ MOVUPDrm_Int = 1238,
+ MOVUPDrr = 1239,
+ MOVUPSmr = 1240,
+ MOVUPSmr_Int = 1241,
+ MOVUPSrm = 1242,
+ MOVUPSrm_Int = 1243,
+ MOVUPSrr = 1244,
+ MOVZDI2PDIrm = 1245,
+ MOVZDI2PDIrr = 1246,
+ MOVZPQILo2PQIrm = 1247,
+ MOVZPQILo2PQIrr = 1248,
+ MOVZQI2PQIrm = 1249,
+ MOVZQI2PQIrr = 1250,
+ MOVZSD2PDrm = 1251,
+ MOVZSS2PSrm = 1252,
+ MOVZX16rm8 = 1253,
+ MOVZX16rr8 = 1254,
+ MOVZX32_NOREXrm8 = 1255,
+ MOVZX32_NOREXrr8 = 1256,
+ MOVZX32rm16 = 1257,
+ MOVZX32rm8 = 1258,
+ MOVZX32rr16 = 1259,
+ MOVZX32rr8 = 1260,
+ MOVZX64rm16 = 1261,
+ MOVZX64rm32 = 1262,
+ MOVZX64rm8 = 1263,
+ MOVZX64rr16 = 1264,
+ MOVZX64rr32 = 1265,
+ MOVZX64rr8 = 1266,
+ MOV_Fp3232 = 1267,
+ MOV_Fp3264 = 1268,
+ MOV_Fp3280 = 1269,
+ MOV_Fp6432 = 1270,
+ MOV_Fp6464 = 1271,
+ MOV_Fp6480 = 1272,
+ MOV_Fp8032 = 1273,
+ MOV_Fp8064 = 1274,
+ MOV_Fp8080 = 1275,
+ MPSADBWrmi = 1276,
+ MPSADBWrri = 1277,
+ MUL16m = 1278,
+ MUL16r = 1279,
+ MUL32m = 1280,
+ MUL32r = 1281,
+ MUL64m = 1282,
+ MUL64r = 1283,
+ MUL8m = 1284,
+ MUL8r = 1285,
+ MULPDrm = 1286,
+ MULPDrr = 1287,
+ MULPSrm = 1288,
+ MULPSrr = 1289,
+ MULSDrm = 1290,
+ MULSDrm_Int = 1291,
+ MULSDrr = 1292,
+ MULSDrr_Int = 1293,
+ MULSSrm = 1294,
+ MULSSrm_Int = 1295,
+ MULSSrr = 1296,
+ MULSSrr_Int = 1297,
+ MUL_F32m = 1298,
+ MUL_F64m = 1299,
+ MUL_FI16m = 1300,
+ MUL_FI32m = 1301,
+ MUL_FPrST0 = 1302,
+ MUL_FST0r = 1303,
+ MUL_Fp32 = 1304,
+ MUL_Fp32m = 1305,
+ MUL_Fp64 = 1306,
+ MUL_Fp64m = 1307,
+ MUL_Fp64m32 = 1308,
+ MUL_Fp80 = 1309,
+ MUL_Fp80m32 = 1310,
+ MUL_Fp80m64 = 1311,
+ MUL_FpI16m32 = 1312,
+ MUL_FpI16m64 = 1313,
+ MUL_FpI16m80 = 1314,
+ MUL_FpI32m32 = 1315,
+ MUL_FpI32m64 = 1316,
+ MUL_FpI32m80 = 1317,
+ MUL_FrST0 = 1318,
+ MWAIT = 1319,
+ NEG16m = 1320,
+ NEG16r = 1321,
+ NEG32m = 1322,
+ NEG32r = 1323,
+ NEG64m = 1324,
+ NEG64r = 1325,
+ NEG8m = 1326,
+ NEG8r = 1327,
+ NOOP = 1328,
+ NOOPL = 1329,
+ NOT16m = 1330,
+ NOT16r = 1331,
+ NOT32m = 1332,
+ NOT32r = 1333,
+ NOT64m = 1334,
+ NOT64r = 1335,
+ NOT8m = 1336,
+ NOT8r = 1337,
+ OR16i16 = 1338,
+ OR16mi = 1339,
+ OR16mi8 = 1340,
+ OR16mr = 1341,
+ OR16ri = 1342,
+ OR16ri8 = 1343,
+ OR16rm = 1344,
+ OR16rr = 1345,
+ OR32i32 = 1346,
+ OR32mi = 1347,
+ OR32mi8 = 1348,
+ OR32mr = 1349,
+ OR32ri = 1350,
+ OR32ri8 = 1351,
+ OR32rm = 1352,
+ OR32rr = 1353,
+ OR64i32 = 1354,
+ OR64mi32 = 1355,
+ OR64mi8 = 1356,
+ OR64mr = 1357,
+ OR64ri32 = 1358,
+ OR64ri8 = 1359,
+ OR64rm = 1360,
+ OR64rr = 1361,
+ OR8i8 = 1362,
+ OR8mi = 1363,
+ OR8mr = 1364,
+ OR8ri = 1365,
+ OR8rm = 1366,
+ OR8rr = 1367,
+ ORPDrm = 1368,
+ ORPDrr = 1369,
+ ORPSrm = 1370,
+ ORPSrr = 1371,
+ OUT16ir = 1372,
+ OUT16rr = 1373,
+ OUT32ir = 1374,
+ OUT32rr = 1375,
+ OUT8ir = 1376,
+ OUT8rr = 1377,
+ PABSBrm128 = 1378,
+ PABSBrm64 = 1379,
+ PABSBrr128 = 1380,
+ PABSBrr64 = 1381,
+ PABSDrm128 = 1382,
+ PABSDrm64 = 1383,
+ PABSDrr128 = 1384,
+ PABSDrr64 = 1385,
+ PABSWrm128 = 1386,
+ PABSWrm64 = 1387,
+ PABSWrr128 = 1388,
+ PABSWrr64 = 1389,
+ PACKSSDWrm = 1390,
+ PACKSSDWrr = 1391,
+ PACKSSWBrm = 1392,
+ PACKSSWBrr = 1393,
+ PACKUSDWrm = 1394,
+ PACKUSDWrr = 1395,
+ PACKUSWBrm = 1396,
+ PACKUSWBrr = 1397,
+ PADDBrm = 1398,
+ PADDBrr = 1399,
+ PADDDrm = 1400,
+ PADDDrr = 1401,
+ PADDQrm = 1402,
+ PADDQrr = 1403,
+ PADDSBrm = 1404,
+ PADDSBrr = 1405,
+ PADDSWrm = 1406,
+ PADDSWrr = 1407,
+ PADDUSBrm = 1408,
+ PADDUSBrr = 1409,
+ PADDUSWrm = 1410,
+ PADDUSWrr = 1411,
+ PADDWrm = 1412,
+ PADDWrr = 1413,
+ PALIGNR128rm = 1414,
+ PALIGNR128rr = 1415,
+ PALIGNR64rm = 1416,
+ PALIGNR64rr = 1417,
+ PANDNrm = 1418,
+ PANDNrr = 1419,
+ PANDrm = 1420,
+ PANDrr = 1421,
+ PAVGBrm = 1422,
+ PAVGBrr = 1423,
+ PAVGWrm = 1424,
+ PAVGWrr = 1425,
+ PBLENDVBrm0 = 1426,
+ PBLENDVBrr0 = 1427,
+ PBLENDWrmi = 1428,
+ PBLENDWrri = 1429,
+ PCMPEQBrm = 1430,
+ PCMPEQBrr = 1431,
+ PCMPEQDrm = 1432,
+ PCMPEQDrr = 1433,
+ PCMPEQQrm = 1434,
+ PCMPEQQrr = 1435,
+ PCMPEQWrm = 1436,
+ PCMPEQWrr = 1437,
+ PCMPESTRIArm = 1438,
+ PCMPESTRIArr = 1439,
+ PCMPESTRICrm = 1440,
+ PCMPESTRICrr = 1441,
+ PCMPESTRIOrm = 1442,
+ PCMPESTRIOrr = 1443,
+ PCMPESTRISrm = 1444,
+ PCMPESTRISrr = 1445,
+ PCMPESTRIZrm = 1446,
+ PCMPESTRIZrr = 1447,
+ PCMPESTRIrm = 1448,
+ PCMPESTRIrr = 1449,
+ PCMPESTRM128MEM = 1450,
+ PCMPESTRM128REG = 1451,
+ PCMPESTRM128rm = 1452,
+ PCMPESTRM128rr = 1453,
+ PCMPGTBrm = 1454,
+ PCMPGTBrr = 1455,
+ PCMPGTDrm = 1456,
+ PCMPGTDrr = 1457,
+ PCMPGTQrm = 1458,
+ PCMPGTQrr = 1459,
+ PCMPGTWrm = 1460,
+ PCMPGTWrr = 1461,
+ PCMPISTRIArm = 1462,
+ PCMPISTRIArr = 1463,
+ PCMPISTRICrm = 1464,
+ PCMPISTRICrr = 1465,
+ PCMPISTRIOrm = 1466,
+ PCMPISTRIOrr = 1467,
+ PCMPISTRISrm = 1468,
+ PCMPISTRISrr = 1469,
+ PCMPISTRIZrm = 1470,
+ PCMPISTRIZrr = 1471,
+ PCMPISTRIrm = 1472,
+ PCMPISTRIrr = 1473,
+ PCMPISTRM128MEM = 1474,
+ PCMPISTRM128REG = 1475,
+ PCMPISTRM128rm = 1476,
+ PCMPISTRM128rr = 1477,
+ PEXTRBmr = 1478,
+ PEXTRBrr = 1479,
+ PEXTRDmr = 1480,
+ PEXTRDrr = 1481,
+ PEXTRQmr = 1482,
+ PEXTRQrr = 1483,
+ PEXTRWmr = 1484,
+ PEXTRWri = 1485,
+ PHADDDrm128 = 1486,
+ PHADDDrm64 = 1487,
+ PHADDDrr128 = 1488,
+ PHADDDrr64 = 1489,
+ PHADDSWrm128 = 1490,
+ PHADDSWrm64 = 1491,
+ PHADDSWrr128 = 1492,
+ PHADDSWrr64 = 1493,
+ PHADDWrm128 = 1494,
+ PHADDWrm64 = 1495,
+ PHADDWrr128 = 1496,
+ PHADDWrr64 = 1497,
+ PHMINPOSUWrm128 = 1498,
+ PHMINPOSUWrr128 = 1499,
+ PHSUBDrm128 = 1500,
+ PHSUBDrm64 = 1501,
+ PHSUBDrr128 = 1502,
+ PHSUBDrr64 = 1503,
+ PHSUBSWrm128 = 1504,
+ PHSUBSWrm64 = 1505,
+ PHSUBSWrr128 = 1506,
+ PHSUBSWrr64 = 1507,
+ PHSUBWrm128 = 1508,
+ PHSUBWrm64 = 1509,
+ PHSUBWrr128 = 1510,
+ PHSUBWrr64 = 1511,
+ PINSRBrm = 1512,
+ PINSRBrr = 1513,
+ PINSRDrm = 1514,
+ PINSRDrr = 1515,
+ PINSRQrm = 1516,
+ PINSRQrr = 1517,
+ PINSRWrmi = 1518,
+ PINSRWrri = 1519,
+ PMADDUBSWrm128 = 1520,
+ PMADDUBSWrm64 = 1521,
+ PMADDUBSWrr128 = 1522,
+ PMADDUBSWrr64 = 1523,
+ PMADDWDrm = 1524,
+ PMADDWDrr = 1525,
+ PMAXSBrm = 1526,
+ PMAXSBrr = 1527,
+ PMAXSDrm = 1528,
+ PMAXSDrr = 1529,
+ PMAXSWrm = 1530,
+ PMAXSWrr = 1531,
+ PMAXUBrm = 1532,
+ PMAXUBrr = 1533,
+ PMAXUDrm = 1534,
+ PMAXUDrr = 1535,
+ PMAXUWrm = 1536,
+ PMAXUWrr = 1537,
+ PMINSBrm = 1538,
+ PMINSBrr = 1539,
+ PMINSDrm = 1540,
+ PMINSDrr = 1541,
+ PMINSWrm = 1542,
+ PMINSWrr = 1543,
+ PMINUBrm = 1544,
+ PMINUBrr = 1545,
+ PMINUDrm = 1546,
+ PMINUDrr = 1547,
+ PMINUWrm = 1548,
+ PMINUWrr = 1549,
+ PMOVMSKBrr = 1550,
+ PMOVSXBDrm = 1551,
+ PMOVSXBDrr = 1552,
+ PMOVSXBQrm = 1553,
+ PMOVSXBQrr = 1554,
+ PMOVSXBWrm = 1555,
+ PMOVSXBWrr = 1556,
+ PMOVSXDQrm = 1557,
+ PMOVSXDQrr = 1558,
+ PMOVSXWDrm = 1559,
+ PMOVSXWDrr = 1560,
+ PMOVSXWQrm = 1561,
+ PMOVSXWQrr = 1562,
+ PMOVZXBDrm = 1563,
+ PMOVZXBDrr = 1564,
+ PMOVZXBQrm = 1565,
+ PMOVZXBQrr = 1566,
+ PMOVZXBWrm = 1567,
+ PMOVZXBWrr = 1568,
+ PMOVZXDQrm = 1569,
+ PMOVZXDQrr = 1570,
+ PMOVZXWDrm = 1571,
+ PMOVZXWDrr = 1572,
+ PMOVZXWQrm = 1573,
+ PMOVZXWQrr = 1574,
+ PMULDQrm = 1575,
+ PMULDQrr = 1576,
+ PMULHRSWrm128 = 1577,
+ PMULHRSWrm64 = 1578,
+ PMULHRSWrr128 = 1579,
+ PMULHRSWrr64 = 1580,
+ PMULHUWrm = 1581,
+ PMULHUWrr = 1582,
+ PMULHWrm = 1583,
+ PMULHWrr = 1584,
+ PMULLDrm = 1585,
+ PMULLDrm_int = 1586,
+ PMULLDrr = 1587,
+ PMULLDrr_int = 1588,
+ PMULLWrm = 1589,
+ PMULLWrr = 1590,
+ PMULUDQrm = 1591,
+ PMULUDQrr = 1592,
+ POP16r = 1593,
+ POP16rmm = 1594,
+ POP16rmr = 1595,
+ POP32r = 1596,
+ POP32rmm = 1597,
+ POP32rmr = 1598,
+ POP64r = 1599,
+ POP64rmm = 1600,
+ POP64rmr = 1601,
+ POPFD = 1602,
+ POPFQ = 1603,
+ PORrm = 1604,
+ PORrr = 1605,
+ PREFETCHNTA = 1606,
+ PREFETCHT0 = 1607,
+ PREFETCHT1 = 1608,
+ PREFETCHT2 = 1609,
+ PSADBWrm = 1610,
+ PSADBWrr = 1611,
+ PSHUFBrm128 = 1612,
+ PSHUFBrm64 = 1613,
+ PSHUFBrr128 = 1614,
+ PSHUFBrr64 = 1615,
+ PSHUFDmi = 1616,
+ PSHUFDri = 1617,
+ PSHUFHWmi = 1618,
+ PSHUFHWri = 1619,
+ PSHUFLWmi = 1620,
+ PSHUFLWri = 1621,
+ PSIGNBrm128 = 1622,
+ PSIGNBrm64 = 1623,
+ PSIGNBrr128 = 1624,
+ PSIGNBrr64 = 1625,
+ PSIGNDrm128 = 1626,
+ PSIGNDrm64 = 1627,
+ PSIGNDrr128 = 1628,
+ PSIGNDrr64 = 1629,
+ PSIGNWrm128 = 1630,
+ PSIGNWrm64 = 1631,
+ PSIGNWrr128 = 1632,
+ PSIGNWrr64 = 1633,
+ PSLLDQri = 1634,
+ PSLLDri = 1635,
+ PSLLDrm = 1636,
+ PSLLDrr = 1637,
+ PSLLQri = 1638,
+ PSLLQrm = 1639,
+ PSLLQrr = 1640,
+ PSLLWri = 1641,
+ PSLLWrm = 1642,
+ PSLLWrr = 1643,
+ PSRADri = 1644,
+ PSRADrm = 1645,
+ PSRADrr = 1646,
+ PSRAWri = 1647,
+ PSRAWrm = 1648,
+ PSRAWrr = 1649,
+ PSRLDQri = 1650,
+ PSRLDri = 1651,
+ PSRLDrm = 1652,
+ PSRLDrr = 1653,
+ PSRLQri = 1654,
+ PSRLQrm = 1655,
+ PSRLQrr = 1656,
+ PSRLWri = 1657,
+ PSRLWrm = 1658,
+ PSRLWrr = 1659,
+ PSUBBrm = 1660,
+ PSUBBrr = 1661,
+ PSUBDrm = 1662,
+ PSUBDrr = 1663,
+ PSUBQrm = 1664,
+ PSUBQrr = 1665,
+ PSUBSBrm = 1666,
+ PSUBSBrr = 1667,
+ PSUBSWrm = 1668,
+ PSUBSWrr = 1669,
+ PSUBUSBrm = 1670,
+ PSUBUSBrr = 1671,
+ PSUBUSWrm = 1672,
+ PSUBUSWrr = 1673,
+ PSUBWrm = 1674,
+ PSUBWrr = 1675,
+ PTESTrm = 1676,
+ PTESTrr = 1677,
+ PUNPCKHBWrm = 1678,
+ PUNPCKHBWrr = 1679,
+ PUNPCKHDQrm = 1680,
+ PUNPCKHDQrr = 1681,
+ PUNPCKHQDQrm = 1682,
+ PUNPCKHQDQrr = 1683,
+ PUNPCKHWDrm = 1684,
+ PUNPCKHWDrr = 1685,
+ PUNPCKLBWrm = 1686,
+ PUNPCKLBWrr = 1687,
+ PUNPCKLDQrm = 1688,
+ PUNPCKLDQrr = 1689,
+ PUNPCKLQDQrm = 1690,
+ PUNPCKLQDQrr = 1691,
+ PUNPCKLWDrm = 1692,
+ PUNPCKLWDrr = 1693,
+ PUSH16r = 1694,
+ PUSH16rmm = 1695,
+ PUSH16rmr = 1696,
+ PUSH32i16 = 1697,
+ PUSH32i32 = 1698,
+ PUSH32i8 = 1699,
+ PUSH32r = 1700,
+ PUSH32rmm = 1701,
+ PUSH32rmr = 1702,
+ PUSH64i16 = 1703,
+ PUSH64i32 = 1704,
+ PUSH64i8 = 1705,
+ PUSH64r = 1706,
+ PUSH64rmm = 1707,
+ PUSH64rmr = 1708,
+ PUSHFD = 1709,
+ PUSHFQ = 1710,
+ PXORrm = 1711,
+ PXORrr = 1712,
+ RCL16m1 = 1713,
+ RCL16mCL = 1714,
+ RCL16mi = 1715,
+ RCL16r1 = 1716,
+ RCL16rCL = 1717,
+ RCL16ri = 1718,
+ RCL32m1 = 1719,
+ RCL32mCL = 1720,
+ RCL32mi = 1721,
+ RCL32r1 = 1722,
+ RCL32rCL = 1723,
+ RCL32ri = 1724,
+ RCL64m1 = 1725,
+ RCL64mCL = 1726,
+ RCL64mi = 1727,
+ RCL64r1 = 1728,
+ RCL64rCL = 1729,
+ RCL64ri = 1730,
+ RCL8m1 = 1731,
+ RCL8mCL = 1732,
+ RCL8mi = 1733,
+ RCL8r1 = 1734,
+ RCL8rCL = 1735,
+ RCL8ri = 1736,
+ RCPPSm = 1737,
+ RCPPSm_Int = 1738,
+ RCPPSr = 1739,
+ RCPPSr_Int = 1740,
+ RCPSSm = 1741,
+ RCPSSm_Int = 1742,
+ RCPSSr = 1743,
+ RCPSSr_Int = 1744,
+ RCR16m1 = 1745,
+ RCR16mCL = 1746,
+ RCR16mi = 1747,
+ RCR16r1 = 1748,
+ RCR16rCL = 1749,
+ RCR16ri = 1750,
+ RCR32m1 = 1751,
+ RCR32mCL = 1752,
+ RCR32mi = 1753,
+ RCR32r1 = 1754,
+ RCR32rCL = 1755,
+ RCR32ri = 1756,
+ RCR64m1 = 1757,
+ RCR64mCL = 1758,
+ RCR64mi = 1759,
+ RCR64r1 = 1760,
+ RCR64rCL = 1761,
+ RCR64ri = 1762,
+ RCR8m1 = 1763,
+ RCR8mCL = 1764,
+ RCR8mi = 1765,
+ RCR8r1 = 1766,
+ RCR8rCL = 1767,
+ RCR8ri = 1768,
+ RDTSC = 1769,
+ REP_MOVSB = 1770,
+ REP_MOVSD = 1771,
+ REP_MOVSQ = 1772,
+ REP_MOVSW = 1773,
+ REP_STOSB = 1774,
+ REP_STOSD = 1775,
+ REP_STOSQ = 1776,
+ REP_STOSW = 1777,
+ RET = 1778,
+ RETI = 1779,
+ ROL16m1 = 1780,
+ ROL16mCL = 1781,
+ ROL16mi = 1782,
+ ROL16r1 = 1783,
+ ROL16rCL = 1784,
+ ROL16ri = 1785,
+ ROL32m1 = 1786,
+ ROL32mCL = 1787,
+ ROL32mi = 1788,
+ ROL32r1 = 1789,
+ ROL32rCL = 1790,
+ ROL32ri = 1791,
+ ROL64m1 = 1792,
+ ROL64mCL = 1793,
+ ROL64mi = 1794,
+ ROL64r1 = 1795,
+ ROL64rCL = 1796,
+ ROL64ri = 1797,
+ ROL8m1 = 1798,
+ ROL8mCL = 1799,
+ ROL8mi = 1800,
+ ROL8r1 = 1801,
+ ROL8rCL = 1802,
+ ROL8ri = 1803,
+ ROR16m1 = 1804,
+ ROR16mCL = 1805,
+ ROR16mi = 1806,
+ ROR16r1 = 1807,
+ ROR16rCL = 1808,
+ ROR16ri = 1809,
+ ROR32m1 = 1810,
+ ROR32mCL = 1811,
+ ROR32mi = 1812,
+ ROR32r1 = 1813,
+ ROR32rCL = 1814,
+ ROR32ri = 1815,
+ ROR64m1 = 1816,
+ ROR64mCL = 1817,
+ ROR64mi = 1818,
+ ROR64r1 = 1819,
+ ROR64rCL = 1820,
+ ROR64ri = 1821,
+ ROR8m1 = 1822,
+ ROR8mCL = 1823,
+ ROR8mi = 1824,
+ ROR8r1 = 1825,
+ ROR8rCL = 1826,
+ ROR8ri = 1827,
+ ROUNDPDm_Int = 1828,
+ ROUNDPDr_Int = 1829,
+ ROUNDPSm_Int = 1830,
+ ROUNDPSr_Int = 1831,
+ ROUNDSDm_Int = 1832,
+ ROUNDSDr_Int = 1833,
+ ROUNDSSm_Int = 1834,
+ ROUNDSSr_Int = 1835,
+ RSQRTPSm = 1836,
+ RSQRTPSm_Int = 1837,
+ RSQRTPSr = 1838,
+ RSQRTPSr_Int = 1839,
+ RSQRTSSm = 1840,
+ RSQRTSSm_Int = 1841,
+ RSQRTSSr = 1842,
+ RSQRTSSr_Int = 1843,
+ SAHF = 1844,
+ SAR16m1 = 1845,
+ SAR16mCL = 1846,
+ SAR16mi = 1847,
+ SAR16r1 = 1848,
+ SAR16rCL = 1849,
+ SAR16ri = 1850,
+ SAR32m1 = 1851,
+ SAR32mCL = 1852,
+ SAR32mi = 1853,
+ SAR32r1 = 1854,
+ SAR32rCL = 1855,
+ SAR32ri = 1856,
+ SAR64m1 = 1857,
+ SAR64mCL = 1858,
+ SAR64mi = 1859,
+ SAR64r1 = 1860,
+ SAR64rCL = 1861,
+ SAR64ri = 1862,
+ SAR8m1 = 1863,
+ SAR8mCL = 1864,
+ SAR8mi = 1865,
+ SAR8r1 = 1866,
+ SAR8rCL = 1867,
+ SAR8ri = 1868,
+ SBB16i16 = 1869,
+ SBB16mi = 1870,
+ SBB16mi8 = 1871,
+ SBB16mr = 1872,
+ SBB16ri = 1873,
+ SBB16ri8 = 1874,
+ SBB16rm = 1875,
+ SBB16rr = 1876,
+ SBB32i32 = 1877,
+ SBB32mi = 1878,
+ SBB32mi8 = 1879,
+ SBB32mr = 1880,
+ SBB32ri = 1881,
+ SBB32ri8 = 1882,
+ SBB32rm = 1883,
+ SBB32rr = 1884,
+ SBB64i32 = 1885,
+ SBB64mi32 = 1886,
+ SBB64mi8 = 1887,
+ SBB64mr = 1888,
+ SBB64ri32 = 1889,
+ SBB64ri8 = 1890,
+ SBB64rm = 1891,
+ SBB64rr = 1892,
+ SBB8i8 = 1893,
+ SBB8mi = 1894,
+ SBB8mr = 1895,
+ SBB8ri = 1896,
+ SBB8rm = 1897,
+ SBB8rr = 1898,
+ SCAS16 = 1899,
+ SCAS32 = 1900,
+ SCAS64 = 1901,
+ SCAS8 = 1902,
+ SETAEm = 1903,
+ SETAEr = 1904,
+ SETAm = 1905,
+ SETAr = 1906,
+ SETBEm = 1907,
+ SETBEr = 1908,
+ SETB_C16r = 1909,
+ SETB_C32r = 1910,
+ SETB_C64r = 1911,
+ SETB_C8r = 1912,
+ SETBm = 1913,
+ SETBr = 1914,
+ SETEm = 1915,
+ SETEr = 1916,
+ SETGEm = 1917,
+ SETGEr = 1918,
+ SETGm = 1919,
+ SETGr = 1920,
+ SETLEm = 1921,
+ SETLEr = 1922,
+ SETLm = 1923,
+ SETLr = 1924,
+ SETNEm = 1925,
+ SETNEr = 1926,
+ SETNOm = 1927,
+ SETNOr = 1928,
+ SETNPm = 1929,
+ SETNPr = 1930,
+ SETNSm = 1931,
+ SETNSr = 1932,
+ SETOm = 1933,
+ SETOr = 1934,
+ SETPm = 1935,
+ SETPr = 1936,
+ SETSm = 1937,
+ SETSr = 1938,
+ SFENCE = 1939,
+ SHL16m1 = 1940,
+ SHL16mCL = 1941,
+ SHL16mi = 1942,
+ SHL16r1 = 1943,
+ SHL16rCL = 1944,
+ SHL16ri = 1945,
+ SHL32m1 = 1946,
+ SHL32mCL = 1947,
+ SHL32mi = 1948,
+ SHL32r1 = 1949,
+ SHL32rCL = 1950,
+ SHL32ri = 1951,
+ SHL64m1 = 1952,
+ SHL64mCL = 1953,
+ SHL64mi = 1954,
+ SHL64r1 = 1955,
+ SHL64rCL = 1956,
+ SHL64ri = 1957,
+ SHL8m1 = 1958,
+ SHL8mCL = 1959,
+ SHL8mi = 1960,
+ SHL8r1 = 1961,
+ SHL8rCL = 1962,
+ SHL8ri = 1963,
+ SHLD16mrCL = 1964,
+ SHLD16mri8 = 1965,
+ SHLD16rrCL = 1966,
+ SHLD16rri8 = 1967,
+ SHLD32mrCL = 1968,
+ SHLD32mri8 = 1969,
+ SHLD32rrCL = 1970,
+ SHLD32rri8 = 1971,
+ SHLD64mrCL = 1972,
+ SHLD64mri8 = 1973,
+ SHLD64rrCL = 1974,
+ SHLD64rri8 = 1975,
+ SHR16m1 = 1976,
+ SHR16mCL = 1977,
+ SHR16mi = 1978,
+ SHR16r1 = 1979,
+ SHR16rCL = 1980,
+ SHR16ri = 1981,
+ SHR32m1 = 1982,
+ SHR32mCL = 1983,
+ SHR32mi = 1984,
+ SHR32r1 = 1985,
+ SHR32rCL = 1986,
+ SHR32ri = 1987,
+ SHR64m1 = 1988,
+ SHR64mCL = 1989,
+ SHR64mi = 1990,
+ SHR64r1 = 1991,
+ SHR64rCL = 1992,
+ SHR64ri = 1993,
+ SHR8m1 = 1994,
+ SHR8mCL = 1995,
+ SHR8mi = 1996,
+ SHR8r1 = 1997,
+ SHR8rCL = 1998,
+ SHR8ri = 1999,
+ SHRD16mrCL = 2000,
+ SHRD16mri8 = 2001,
+ SHRD16rrCL = 2002,
+ SHRD16rri8 = 2003,
+ SHRD32mrCL = 2004,
+ SHRD32mri8 = 2005,
+ SHRD32rrCL = 2006,
+ SHRD32rri8 = 2007,
+ SHRD64mrCL = 2008,
+ SHRD64mri8 = 2009,
+ SHRD64rrCL = 2010,
+ SHRD64rri8 = 2011,
+ SHUFPDrmi = 2012,
+ SHUFPDrri = 2013,
+ SHUFPSrmi = 2014,
+ SHUFPSrri = 2015,
+ SIN_F = 2016,
+ SIN_Fp32 = 2017,
+ SIN_Fp64 = 2018,
+ SIN_Fp80 = 2019,
+ SQRTPDm = 2020,
+ SQRTPDm_Int = 2021,
+ SQRTPDr = 2022,
+ SQRTPDr_Int = 2023,
+ SQRTPSm = 2024,
+ SQRTPSm_Int = 2025,
+ SQRTPSr = 2026,
+ SQRTPSr_Int = 2027,
+ SQRTSDm = 2028,
+ SQRTSDm_Int = 2029,
+ SQRTSDr = 2030,
+ SQRTSDr_Int = 2031,
+ SQRTSSm = 2032,
+ SQRTSSm_Int = 2033,
+ SQRTSSr = 2034,
+ SQRTSSr_Int = 2035,
+ SQRT_F = 2036,
+ SQRT_Fp32 = 2037,
+ SQRT_Fp64 = 2038,
+ SQRT_Fp80 = 2039,
+ STMXCSR = 2040,
+ ST_F32m = 2041,
+ ST_F64m = 2042,
+ ST_FP32m = 2043,
+ ST_FP64m = 2044,
+ ST_FP80m = 2045,
+ ST_FPrr = 2046,
+ ST_Fp32m = 2047,
+ ST_Fp64m = 2048,
+ ST_Fp64m32 = 2049,
+ ST_Fp80m32 = 2050,
+ ST_Fp80m64 = 2051,
+ ST_FpP32m = 2052,
+ ST_FpP64m = 2053,
+ ST_FpP64m32 = 2054,
+ ST_FpP80m = 2055,
+ ST_FpP80m32 = 2056,
+ ST_FpP80m64 = 2057,
+ ST_Frr = 2058,
+ SUB16i16 = 2059,
+ SUB16mi = 2060,
+ SUB16mi8 = 2061,
+ SUB16mr = 2062,
+ SUB16ri = 2063,
+ SUB16ri8 = 2064,
+ SUB16rm = 2065,
+ SUB16rr = 2066,
+ SUB32i32 = 2067,
+ SUB32mi = 2068,
+ SUB32mi8 = 2069,
+ SUB32mr = 2070,
+ SUB32ri = 2071,
+ SUB32ri8 = 2072,
+ SUB32rm = 2073,
+ SUB32rr = 2074,
+ SUB64i32 = 2075,
+ SUB64mi32 = 2076,
+ SUB64mi8 = 2077,
+ SUB64mr = 2078,
+ SUB64ri32 = 2079,
+ SUB64ri8 = 2080,
+ SUB64rm = 2081,
+ SUB64rr = 2082,
+ SUB8i8 = 2083,
+ SUB8mi = 2084,
+ SUB8mr = 2085,
+ SUB8ri = 2086,
+ SUB8rm = 2087,
+ SUB8rr = 2088,
+ SUBPDrm = 2089,
+ SUBPDrr = 2090,
+ SUBPSrm = 2091,
+ SUBPSrr = 2092,
+ SUBR_F32m = 2093,
+ SUBR_F64m = 2094,
+ SUBR_FI16m = 2095,
+ SUBR_FI32m = 2096,
+ SUBR_FPrST0 = 2097,
+ SUBR_FST0r = 2098,
+ SUBR_Fp32m = 2099,
+ SUBR_Fp64m = 2100,
+ SUBR_Fp64m32 = 2101,
+ SUBR_Fp80m32 = 2102,
+ SUBR_Fp80m64 = 2103,
+ SUBR_FpI16m32 = 2104,
+ SUBR_FpI16m64 = 2105,
+ SUBR_FpI16m80 = 2106,
+ SUBR_FpI32m32 = 2107,
+ SUBR_FpI32m64 = 2108,
+ SUBR_FpI32m80 = 2109,
+ SUBR_FrST0 = 2110,
+ SUBSDrm = 2111,
+ SUBSDrm_Int = 2112,
+ SUBSDrr = 2113,
+ SUBSDrr_Int = 2114,
+ SUBSSrm = 2115,
+ SUBSSrm_Int = 2116,
+ SUBSSrr = 2117,
+ SUBSSrr_Int = 2118,
+ SUB_F32m = 2119,
+ SUB_F64m = 2120,
+ SUB_FI16m = 2121,
+ SUB_FI32m = 2122,
+ SUB_FPrST0 = 2123,
+ SUB_FST0r = 2124,
+ SUB_Fp32 = 2125,
+ SUB_Fp32m = 2126,
+ SUB_Fp64 = 2127,
+ SUB_Fp64m = 2128,
+ SUB_Fp64m32 = 2129,
+ SUB_Fp80 = 2130,
+ SUB_Fp80m32 = 2131,
+ SUB_Fp80m64 = 2132,
+ SUB_FpI16m32 = 2133,
+ SUB_FpI16m64 = 2134,
+ SUB_FpI16m80 = 2135,
+ SUB_FpI32m32 = 2136,
+ SUB_FpI32m64 = 2137,
+ SUB_FpI32m80 = 2138,
+ SUB_FrST0 = 2139,
+ SYSCALL = 2140,
+ SYSENTER = 2141,
+ SYSEXIT = 2142,
+ SYSEXIT64 = 2143,
+ SYSRET = 2144,
+ TAILJMPd = 2145,
+ TAILJMPm = 2146,
+ TAILJMPr = 2147,
+ TAILJMPr64 = 2148,
+ TCRETURNdi = 2149,
+ TCRETURNdi64 = 2150,
+ TCRETURNri = 2151,
+ TCRETURNri64 = 2152,
+ TEST16i16 = 2153,
+ TEST16mi = 2154,
+ TEST16ri = 2155,
+ TEST16rm = 2156,
+ TEST16rr = 2157,
+ TEST32i32 = 2158,
+ TEST32mi = 2159,
+ TEST32ri = 2160,
+ TEST32rm = 2161,
+ TEST32rr = 2162,
+ TEST64i32 = 2163,
+ TEST64mi32 = 2164,
+ TEST64ri32 = 2165,
+ TEST64rm = 2166,
+ TEST64rr = 2167,
+ TEST8i8 = 2168,
+ TEST8mi = 2169,
+ TEST8ri = 2170,
+ TEST8rm = 2171,
+ TEST8rr = 2172,
+ TLS_addr32 = 2173,
+ TLS_addr64 = 2174,
+ TRAP = 2175,
+ TST_F = 2176,
+ TST_Fp32 = 2177,
+ TST_Fp64 = 2178,
+ TST_Fp80 = 2179,
+ UCOMISDrm = 2180,
+ UCOMISDrr = 2181,
+ UCOMISSrm = 2182,
+ UCOMISSrr = 2183,
+ UCOM_FIPr = 2184,
+ UCOM_FIr = 2185,
+ UCOM_FPPr = 2186,
+ UCOM_FPr = 2187,
+ UCOM_FpIr32 = 2188,
+ UCOM_FpIr64 = 2189,
+ UCOM_FpIr80 = 2190,
+ UCOM_Fpr32 = 2191,
+ UCOM_Fpr64 = 2192,
+ UCOM_Fpr80 = 2193,
+ UCOM_Fr = 2194,
+ UNPCKHPDrm = 2195,
+ UNPCKHPDrr = 2196,
+ UNPCKHPSrm = 2197,
+ UNPCKHPSrr = 2198,
+ UNPCKLPDrm = 2199,
+ UNPCKLPDrr = 2200,
+ UNPCKLPSrm = 2201,
+ UNPCKLPSrr = 2202,
+ VASTART_SAVE_XMM_REGS = 2203,
+ V_SET0 = 2204,
+ V_SETALLONES = 2205,
+ WAIT = 2206,
+ WINCALL64m = 2207,
+ WINCALL64pcrel32 = 2208,
+ WINCALL64r = 2209,
+ XCHG16rm = 2210,
+ XCHG32rm = 2211,
+ XCHG64rm = 2212,
+ XCHG8rm = 2213,
+ XCH_F = 2214,
+ XOR16i16 = 2215,
+ XOR16mi = 2216,
+ XOR16mi8 = 2217,
+ XOR16mr = 2218,
+ XOR16ri = 2219,
+ XOR16ri8 = 2220,
+ XOR16rm = 2221,
+ XOR16rr = 2222,
+ XOR32i32 = 2223,
+ XOR32mi = 2224,
+ XOR32mi8 = 2225,
+ XOR32mr = 2226,
+ XOR32ri = 2227,
+ XOR32ri8 = 2228,
+ XOR32rm = 2229,
+ XOR32rr = 2230,
+ XOR64i32 = 2231,
+ XOR64mi32 = 2232,
+ XOR64mi8 = 2233,
+ XOR64mr = 2234,
+ XOR64ri32 = 2235,
+ XOR64ri8 = 2236,
+ XOR64rm = 2237,
+ XOR64rr = 2238,
+ XOR8i8 = 2239,
+ XOR8mi = 2240,
+ XOR8mr = 2241,
+ XOR8ri = 2242,
+ XOR8rm = 2243,
+ XOR8rr = 2244,
+ XORPDrm = 2245,
+ XORPDrr = 2246,
+ XORPSrm = 2247,
+ XORPSrr = 2248,
+ INSTRUCTION_LIST_END = 2249
+ };
+}
+} // End llvm namespace
diff --git a/libclamav/c++/X86GenRegisterInfo.h.inc b/libclamav/c++/X86GenRegisterInfo.h.inc
new file mode 100644
index 0000000..9e5343e
--- /dev/null
+++ b/libclamav/c++/X86GenRegisterInfo.h.inc
@@ -0,0 +1,233 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Register Information Header Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <string>
+
+namespace llvm {
+
+struct X86GenRegisterInfo : public TargetRegisterInfo {
+ explicit X86GenRegisterInfo(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
+ virtual int getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) const;
+ virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
+ virtual bool needsStackRealignment(const MachineFunction &) const
+ { return false; }
+ unsigned getSubReg(unsigned RegNo, unsigned Index) const;
+ unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
+};
+
+namespace X86 { // Register classes
+ enum {
+ CCRRegClassID = 1,
+ FR32RegClassID = 2,
+ FR64RegClassID = 3,
+ GR16RegClassID = 4,
+ GR16_ABCDRegClassID = 5,
+ GR16_NOREXRegClassID = 6,
+ GR32RegClassID = 7,
+ GR32_ABCDRegClassID = 8,
+ GR32_ADRegClassID = 9,
+ GR32_NOREXRegClassID = 10,
+ GR32_NOSPRegClassID = 11,
+ GR64RegClassID = 12,
+ GR64_ABCDRegClassID = 13,
+ GR64_NOREXRegClassID = 14,
+ GR64_NOREX_NOSPRegClassID = 15,
+ GR64_NOSPRegClassID = 16,
+ GR8RegClassID = 17,
+ GR8_ABCD_HRegClassID = 18,
+ GR8_ABCD_LRegClassID = 19,
+ GR8_NOREXRegClassID = 20,
+ RFP32RegClassID = 21,
+ RFP64RegClassID = 22,
+ RFP80RegClassID = 23,
+ RSTRegClassID = 24,
+ SEGMENT_REGRegClassID = 25,
+ VR128RegClassID = 26,
+ VR256RegClassID = 27,
+ VR64RegClassID = 28
+ };
+
+ struct CCRClass : public TargetRegisterClass {
+ CCRClass();
+ };
+ extern CCRClass CCRRegClass;
+ static TargetRegisterClass * const CCRRegisterClass = &CCRRegClass;
+ struct FR32Class : public TargetRegisterClass {
+ FR32Class();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern FR32Class FR32RegClass;
+ static TargetRegisterClass * const FR32RegisterClass = &FR32RegClass;
+ struct FR64Class : public TargetRegisterClass {
+ FR64Class();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern FR64Class FR64RegClass;
+ static TargetRegisterClass * const FR64RegisterClass = &FR64RegClass;
+ struct GR16Class : public TargetRegisterClass {
+ GR16Class();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR16Class GR16RegClass;
+ static TargetRegisterClass * const GR16RegisterClass = &GR16RegClass;
+ struct GR16_ABCDClass : public TargetRegisterClass {
+ GR16_ABCDClass();
+ };
+ extern GR16_ABCDClass GR16_ABCDRegClass;
+ static TargetRegisterClass * const GR16_ABCDRegisterClass = &GR16_ABCDRegClass;
+ struct GR16_NOREXClass : public TargetRegisterClass {
+ GR16_NOREXClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR16_NOREXClass GR16_NOREXRegClass;
+ static TargetRegisterClass * const GR16_NOREXRegisterClass = &GR16_NOREXRegClass;
+ struct GR32Class : public TargetRegisterClass {
+ GR32Class();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR32Class GR32RegClass;
+ static TargetRegisterClass * const GR32RegisterClass = &GR32RegClass;
+ struct GR32_ABCDClass : public TargetRegisterClass {
+ GR32_ABCDClass();
+ };
+ extern GR32_ABCDClass GR32_ABCDRegClass;
+ static TargetRegisterClass * const GR32_ABCDRegisterClass = &GR32_ABCDRegClass;
+ struct GR32_ADClass : public TargetRegisterClass {
+ GR32_ADClass();
+ };
+ extern GR32_ADClass GR32_ADRegClass;
+ static TargetRegisterClass * const GR32_ADRegisterClass = &GR32_ADRegClass;
+ struct GR32_NOREXClass : public TargetRegisterClass {
+ GR32_NOREXClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR32_NOREXClass GR32_NOREXRegClass;
+ static TargetRegisterClass * const GR32_NOREXRegisterClass = &GR32_NOREXRegClass;
+ struct GR32_NOSPClass : public TargetRegisterClass {
+ GR32_NOSPClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR32_NOSPClass GR32_NOSPRegClass;
+ static TargetRegisterClass * const GR32_NOSPRegisterClass = &GR32_NOSPRegClass;
+ struct GR64Class : public TargetRegisterClass {
+ GR64Class();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR64Class GR64RegClass;
+ static TargetRegisterClass * const GR64RegisterClass = &GR64RegClass;
+ struct GR64_ABCDClass : public TargetRegisterClass {
+ GR64_ABCDClass();
+ };
+ extern GR64_ABCDClass GR64_ABCDRegClass;
+ static TargetRegisterClass * const GR64_ABCDRegisterClass = &GR64_ABCDRegClass;
+ struct GR64_NOREXClass : public TargetRegisterClass {
+ GR64_NOREXClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR64_NOREXClass GR64_NOREXRegClass;
+ static TargetRegisterClass * const GR64_NOREXRegisterClass = &GR64_NOREXRegClass;
+ struct GR64_NOREX_NOSPClass : public TargetRegisterClass {
+ GR64_NOREX_NOSPClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR64_NOREX_NOSPClass GR64_NOREX_NOSPRegClass;
+ static TargetRegisterClass * const GR64_NOREX_NOSPRegisterClass = &GR64_NOREX_NOSPRegClass;
+ struct GR64_NOSPClass : public TargetRegisterClass {
+ GR64_NOSPClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR64_NOSPClass GR64_NOSPRegClass;
+ static TargetRegisterClass * const GR64_NOSPRegisterClass = &GR64_NOSPRegClass;
+ struct GR8Class : public TargetRegisterClass {
+ GR8Class();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR8Class GR8RegClass;
+ static TargetRegisterClass * const GR8RegisterClass = &GR8RegClass;
+ struct GR8_ABCD_HClass : public TargetRegisterClass {
+ GR8_ABCD_HClass();
+ };
+ extern GR8_ABCD_HClass GR8_ABCD_HRegClass;
+ static TargetRegisterClass * const GR8_ABCD_HRegisterClass = &GR8_ABCD_HRegClass;
+ struct GR8_ABCD_LClass : public TargetRegisterClass {
+ GR8_ABCD_LClass();
+ };
+ extern GR8_ABCD_LClass GR8_ABCD_LRegClass;
+ static TargetRegisterClass * const GR8_ABCD_LRegisterClass = &GR8_ABCD_LRegClass;
+ struct GR8_NOREXClass : public TargetRegisterClass {
+ GR8_NOREXClass();
+
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern GR8_NOREXClass GR8_NOREXRegClass;
+ static TargetRegisterClass * const GR8_NOREXRegisterClass = &GR8_NOREXRegClass;
+ struct RFP32Class : public TargetRegisterClass {
+ RFP32Class();
+ };
+ extern RFP32Class RFP32RegClass;
+ static TargetRegisterClass * const RFP32RegisterClass = &RFP32RegClass;
+ struct RFP64Class : public TargetRegisterClass {
+ RFP64Class();
+ };
+ extern RFP64Class RFP64RegClass;
+ static TargetRegisterClass * const RFP64RegisterClass = &RFP64RegClass;
+ struct RFP80Class : public TargetRegisterClass {
+ RFP80Class();
+ };
+ extern RFP80Class RFP80RegClass;
+ static TargetRegisterClass * const RFP80RegisterClass = &RFP80RegClass;
+ struct RSTClass : public TargetRegisterClass {
+ RSTClass();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern RSTClass RSTRegClass;
+ static TargetRegisterClass * const RSTRegisterClass = &RSTRegClass;
+ struct SEGMENT_REGClass : public TargetRegisterClass {
+ SEGMENT_REGClass();
+ };
+ extern SEGMENT_REGClass SEGMENT_REGRegClass;
+ static TargetRegisterClass * const SEGMENT_REGRegisterClass = &SEGMENT_REGRegClass;
+ struct VR128Class : public TargetRegisterClass {
+ VR128Class();
+
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ };
+ extern VR128Class VR128RegClass;
+ static TargetRegisterClass * const VR128RegisterClass = &VR128RegClass;
+ struct VR256Class : public TargetRegisterClass {
+ VR256Class();
+ };
+ extern VR256Class VR256RegClass;
+ static TargetRegisterClass * const VR256RegisterClass = &VR256RegClass;
+ struct VR64Class : public TargetRegisterClass {
+ VR64Class();
+ };
+ extern VR64Class VR64RegClass;
+ static TargetRegisterClass * const VR64RegisterClass = &VR64RegClass;
+} // end of namespace X86
+
+} // End llvm namespace
diff --git a/libclamav/c++/X86GenRegisterInfo.inc b/libclamav/c++/X86GenRegisterInfo.inc
new file mode 100644
index 0000000..6f4b235
--- /dev/null
+++ b/libclamav/c++/X86GenRegisterInfo.inc
@@ -0,0 +1,5538 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Register Information Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace { // Register classes...
+ // CCR Register Class...
+ static const unsigned CCR[] = {
+ X86::EFLAGS,
+ };
+
+ // FR32 Register Class...
+ static const unsigned FR32[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
+ };
+
+ // FR64 Register Class...
+ static const unsigned FR64[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
+ };
+
+ // GR16 Register Class...
+ static const unsigned GR16[] = {
+ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
+ };
+
+ // GR16_ABCD Register Class...
+ static const unsigned GR16_ABCD[] = {
+ X86::AX, X86::CX, X86::DX, X86::BX,
+ };
+
+ // GR16_NOREX Register Class...
+ static const unsigned GR16_NOREX[] = {
+ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
+ };
+
+ // GR32 Register Class...
+ static const unsigned GR32[] = {
+ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
+ };
+
+ // GR32_ABCD Register Class...
+ static const unsigned GR32_ABCD[] = {
+ X86::EAX, X86::ECX, X86::EDX, X86::EBX,
+ };
+
+ // GR32_AD Register Class...
+ static const unsigned GR32_AD[] = {
+ X86::EAX, X86::EDX,
+ };
+
+ // GR32_NOREX Register Class...
+ static const unsigned GR32_NOREX[] = {
+ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
+ };
+
+ // GR32_NOSP Register Class...
+ static const unsigned GR32_NOSP[] = {
+ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
+ };
+
+ // GR64 Register Class...
+ static const unsigned GR64[] = {
+ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
+ };
+
+ // GR64_ABCD Register Class...
+ static const unsigned GR64_ABCD[] = {
+ X86::RAX, X86::RCX, X86::RDX, X86::RBX,
+ };
+
+ // GR64_NOREX Register Class...
+ static const unsigned GR64_NOREX[] = {
+ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
+ };
+
+ // GR64_NOREX_NOSP Register Class...
+ static const unsigned GR64_NOREX_NOSP[] = {
+ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
+ };
+
+ // GR64_NOSP Register Class...
+ static const unsigned GR64_NOSP[] = {
+ X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
+ };
+
+ // GR8 Register Class...
+ static const unsigned GR8[] = {
+ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
+ };
+
+ // GR8_ABCD_H Register Class...
+ static const unsigned GR8_ABCD_H[] = {
+ X86::AH, X86::CH, X86::DH, X86::BH,
+ };
+
+ // GR8_ABCD_L Register Class...
+ static const unsigned GR8_ABCD_L[] = {
+ X86::AL, X86::CL, X86::DL, X86::BL,
+ };
+
+ // GR8_NOREX Register Class...
+ static const unsigned GR8_NOREX[] = {
+ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL,
+ };
+
+ // RFP32 Register Class...
+ static const unsigned RFP32[] = {
+ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
+ };
+
+ // RFP64 Register Class...
+ static const unsigned RFP64[] = {
+ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
+ };
+
+ // RFP80 Register Class...
+ static const unsigned RFP80[] = {
+ X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
+ };
+
+ // RST Register Class...
+ static const unsigned RST[] = {
+ X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
+ };
+
+ // SEGMENT_REG Register Class...
+ static const unsigned SEGMENT_REG[] = {
+ X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
+ };
+
+ // VR128 Register Class...
+ static const unsigned VR128[] = {
+ X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
+ };
+
+ // VR256 Register Class...
+ static const unsigned VR256[] = {
+ X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
+ };
+
+ // VR64 Register Class...
+ static const unsigned VR64[] = {
+ X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
+ };
+
+ // CCRVTs Register Class Value Types...
+ static const EVT CCRVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // FR32VTs Register Class Value Types...
+ static const EVT FR32VTs[] = {
+ MVT::f32, MVT::Other
+ };
+
+ // FR64VTs Register Class Value Types...
+ static const EVT FR64VTs[] = {
+ MVT::f64, MVT::Other
+ };
+
+ // GR16VTs Register Class Value Types...
+ static const EVT GR16VTs[] = {
+ MVT::i16, MVT::Other
+ };
+
+ // GR16_ABCDVTs Register Class Value Types...
+ static const EVT GR16_ABCDVTs[] = {
+ MVT::i16, MVT::Other
+ };
+
+ // GR16_NOREXVTs Register Class Value Types...
+ static const EVT GR16_NOREXVTs[] = {
+ MVT::i16, MVT::Other
+ };
+
+ // GR32VTs Register Class Value Types...
+ static const EVT GR32VTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // GR32_ABCDVTs Register Class Value Types...
+ static const EVT GR32_ABCDVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // GR32_ADVTs Register Class Value Types...
+ static const EVT GR32_ADVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // GR32_NOREXVTs Register Class Value Types...
+ static const EVT GR32_NOREXVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // GR32_NOSPVTs Register Class Value Types...
+ static const EVT GR32_NOSPVTs[] = {
+ MVT::i32, MVT::Other
+ };
+
+ // GR64VTs Register Class Value Types...
+ static const EVT GR64VTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // GR64_ABCDVTs Register Class Value Types...
+ static const EVT GR64_ABCDVTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // GR64_NOREXVTs Register Class Value Types...
+ static const EVT GR64_NOREXVTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // GR64_NOREX_NOSPVTs Register Class Value Types...
+ static const EVT GR64_NOREX_NOSPVTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // GR64_NOSPVTs Register Class Value Types...
+ static const EVT GR64_NOSPVTs[] = {
+ MVT::i64, MVT::Other
+ };
+
+ // GR8VTs Register Class Value Types...
+ static const EVT GR8VTs[] = {
+ MVT::i8, MVT::Other
+ };
+
+ // GR8_ABCD_HVTs Register Class Value Types...
+ static const EVT GR8_ABCD_HVTs[] = {
+ MVT::i8, MVT::Other
+ };
+
+ // GR8_ABCD_LVTs Register Class Value Types...
+ static const EVT GR8_ABCD_LVTs[] = {
+ MVT::i8, MVT::Other
+ };
+
+ // GR8_NOREXVTs Register Class Value Types...
+ static const EVT GR8_NOREXVTs[] = {
+ MVT::i8, MVT::Other
+ };
+
+ // RFP32VTs Register Class Value Types...
+ static const EVT RFP32VTs[] = {
+ MVT::f32, MVT::Other
+ };
+
+ // RFP64VTs Register Class Value Types...
+ static const EVT RFP64VTs[] = {
+ MVT::f64, MVT::Other
+ };
+
+ // RFP80VTs Register Class Value Types...
+ static const EVT RFP80VTs[] = {
+ MVT::f80, MVT::Other
+ };
+
+ // RSTVTs Register Class Value Types...
+ static const EVT RSTVTs[] = {
+ MVT::f80, MVT::f64, MVT::f32, MVT::Other
+ };
+
+ // SEGMENT_REGVTs Register Class Value Types...
+ static const EVT SEGMENT_REGVTs[] = {
+ MVT::i16, MVT::Other
+ };
+
+ // VR128VTs Register Class Value Types...
+ static const EVT VR128VTs[] = {
+ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
+ };
+
+ // VR256VTs Register Class Value Types...
+ static const EVT VR256VTs[] = {
+ MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64, MVT::Other
+ };
+
+ // VR64VTs Register Class Value Types...
+ static const EVT VR64VTs[] = {
+ MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::Other
+ };
+
+} // end anonymous namespace
+
+namespace X86 { // Register class instances
+ CCRClass CCRRegClass;
+ FR32Class FR32RegClass;
+ FR64Class FR64RegClass;
+ GR16Class GR16RegClass;
+ GR16_ABCDClass GR16_ABCDRegClass;
+ GR16_NOREXClass GR16_NOREXRegClass;
+ GR32Class GR32RegClass;
+ GR32_ABCDClass GR32_ABCDRegClass;
+ GR32_ADClass GR32_ADRegClass;
+ GR32_NOREXClass GR32_NOREXRegClass;
+ GR32_NOSPClass GR32_NOSPRegClass;
+ GR64Class GR64RegClass;
+ GR64_ABCDClass GR64_ABCDRegClass;
+ GR64_NOREXClass GR64_NOREXRegClass;
+ GR64_NOREX_NOSPClass GR64_NOREX_NOSPRegClass;
+ GR64_NOSPClass GR64_NOSPRegClass;
+ GR8Class GR8RegClass;
+ GR8_ABCD_HClass GR8_ABCD_HRegClass;
+ GR8_ABCD_LClass GR8_ABCD_LRegClass;
+ GR8_NOREXClass GR8_NOREXRegClass;
+ RFP32Class RFP32RegClass;
+ RFP64Class RFP64RegClass;
+ RFP80Class RFP80RegClass;
+ RSTClass RSTRegClass;
+ SEGMENT_REGClass SEGMENT_REGRegClass;
+ VR128Class VR128RegClass;
+ VR256Class VR256RegClass;
+ VR64Class VR64RegClass;
+
+ // CCR Sub-register Classes...
+ static const TargetRegisterClass* const CCRSubRegClasses[] = {
+ NULL
+ };
+
+ // FR32 Sub-register Classes...
+ static const TargetRegisterClass* const FR32SubRegClasses[] = {
+ NULL
+ };
+
+ // FR64 Sub-register Classes...
+ static const TargetRegisterClass* const FR64SubRegClasses[] = {
+ NULL
+ };
+
+ // GR16 Sub-register Classes...
+ static const TargetRegisterClass* const GR16SubRegClasses[] = {
+ &X86::GR8RegClass, &X86::GR8RegClass, NULL
+ };
+
+ // GR16_ABCD Sub-register Classes...
+ static const TargetRegisterClass* const GR16_ABCDSubRegClasses[] = {
+ &X86::GR8_ABCD_LRegClass, &X86::GR8_ABCD_HRegClass, NULL
+ };
+
+ // GR16_NOREX Sub-register Classes...
+ static const TargetRegisterClass* const GR16_NOREXSubRegClasses[] = {
+ &X86::GR8_NOREXRegClass, &X86::GR8_NOREXRegClass, NULL
+ };
+
+ // GR32 Sub-register Classes...
+ static const TargetRegisterClass* const GR32SubRegClasses[] = {
+ &X86::GR8RegClass, &X86::GR8RegClass, &X86::GR16RegClass, NULL
+ };
+
+ // GR32_ABCD Sub-register Classes...
+ static const TargetRegisterClass* const GR32_ABCDSubRegClasses[] = {
+ &X86::GR8_ABCD_LRegClass, &X86::GR8_ABCD_HRegClass, &X86::GR16_ABCDRegClass, NULL
+ };
+
+ // GR32_AD Sub-register Classes...
+ static const TargetRegisterClass* const GR32_ADSubRegClasses[] = {
+ &X86::GR8_ABCD_LRegClass, &X86::GR8_ABCD_HRegClass, &X86::GR16_ABCDRegClass, NULL
+ };
+
+ // GR32_NOREX Sub-register Classes...
+ static const TargetRegisterClass* const GR32_NOREXSubRegClasses[] = {
+ &X86::GR8_NOREXRegClass, &X86::GR8_NOREXRegClass, &X86::GR16_NOREXRegClass, NULL
+ };
+
+ // GR32_NOSP Sub-register Classes...
+ static const TargetRegisterClass* const GR32_NOSPSubRegClasses[] = {
+ &X86::GR8RegClass, &X86::GR8RegClass, &X86::GR16RegClass, NULL
+ };
+
+ // GR64 Sub-register Classes...
+ static const TargetRegisterClass* const GR64SubRegClasses[] = {
+ &X86::GR8RegClass, &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass, NULL
+ };
+
+ // GR64_ABCD Sub-register Classes...
+ static const TargetRegisterClass* const GR64_ABCDSubRegClasses[] = {
+ &X86::GR8_ABCD_LRegClass, &X86::GR8_ABCD_HRegClass, &X86::GR16_ABCDRegClass, &X86::GR32_ABCDRegClass, NULL
+ };
+
+ // GR64_NOREX Sub-register Classes...
+ static const TargetRegisterClass* const GR64_NOREXSubRegClasses[] = {
+ &X86::GR8_NOREXRegClass, &X86::GR8_NOREXRegClass, &X86::GR16_NOREXRegClass, &X86::GR32_NOREXRegClass, NULL
+ };
+
+ // GR64_NOREX_NOSP Sub-register Classes...
+ static const TargetRegisterClass* const GR64_NOREX_NOSPSubRegClasses[] = {
+ &X86::GR8_NOREXRegClass, &X86::GR8_NOREXRegClass, &X86::GR16_NOREXRegClass, &X86::GR32_NOREXRegClass, NULL
+ };
+
+ // GR64_NOSP Sub-register Classes...
+ static const TargetRegisterClass* const GR64_NOSPSubRegClasses[] = {
+ &X86::GR8RegClass, &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32_NOSPRegClass, NULL
+ };
+
+ // GR8 Sub-register Classes...
+ static const TargetRegisterClass* const GR8SubRegClasses[] = {
+ NULL
+ };
+
+ // GR8_ABCD_H Sub-register Classes...
+ static const TargetRegisterClass* const GR8_ABCD_HSubRegClasses[] = {
+ NULL
+ };
+
+ // GR8_ABCD_L Sub-register Classes...
+ static const TargetRegisterClass* const GR8_ABCD_LSubRegClasses[] = {
+ NULL
+ };
+
+ // GR8_NOREX Sub-register Classes...
+ static const TargetRegisterClass* const GR8_NOREXSubRegClasses[] = {
+ NULL
+ };
+
+ // RFP32 Sub-register Classes...
+ static const TargetRegisterClass* const RFP32SubRegClasses[] = {
+ NULL
+ };
+
+ // RFP64 Sub-register Classes...
+ static const TargetRegisterClass* const RFP64SubRegClasses[] = {
+ NULL
+ };
+
+ // RFP80 Sub-register Classes...
+ static const TargetRegisterClass* const RFP80SubRegClasses[] = {
+ NULL
+ };
+
+ // RST Sub-register Classes...
+ static const TargetRegisterClass* const RSTSubRegClasses[] = {
+ NULL
+ };
+
+ // SEGMENT_REG Sub-register Classes...
+ static const TargetRegisterClass* const SEGMENT_REGSubRegClasses[] = {
+ NULL
+ };
+
+ // VR128 Sub-register Classes...
+ static const TargetRegisterClass* const VR128SubRegClasses[] = {
+ NULL
+ };
+
+ // VR256 Sub-register Classes...
+ static const TargetRegisterClass* const VR256SubRegClasses[] = {
+ NULL
+ };
+
+ // VR64 Sub-register Classes...
+ static const TargetRegisterClass* const VR64SubRegClasses[] = {
+ NULL
+ };
+
+ // CCR Super-register Classes...
+ static const TargetRegisterClass* const CCRSuperRegClasses[] = {
+ NULL
+ };
+
+ // FR32 Super-register Classes...
+ static const TargetRegisterClass* const FR32SuperRegClasses[] = {
+ NULL
+ };
+
+ // FR64 Super-register Classes...
+ static const TargetRegisterClass* const FR64SuperRegClasses[] = {
+ NULL
+ };
+
+ // GR16 Super-register Classes...
+ static const TargetRegisterClass* const GR16SuperRegClasses[] = {
+ &X86::GR32RegClass, &X86::GR32_NOSPRegClass, &X86::GR64RegClass, &X86::GR64_NOSPRegClass, NULL
+ };
+
+ // GR16_ABCD Super-register Classes...
+ static const TargetRegisterClass* const GR16_ABCDSuperRegClasses[] = {
+ &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, &X86::GR64_ABCDRegClass, NULL
+ };
+
+ // GR16_NOREX Super-register Classes...
+ static const TargetRegisterClass* const GR16_NOREXSuperRegClasses[] = {
+ &X86::GR32_NOREXRegClass, &X86::GR64_NOREXRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL
+ };
+
+ // GR32 Super-register Classes...
+ static const TargetRegisterClass* const GR32SuperRegClasses[] = {
+ &X86::GR64RegClass, NULL
+ };
+
+ // GR32_ABCD Super-register Classes...
+ static const TargetRegisterClass* const GR32_ABCDSuperRegClasses[] = {
+ &X86::GR64_ABCDRegClass, NULL
+ };
+
+ // GR32_AD Super-register Classes...
+ static const TargetRegisterClass* const GR32_ADSuperRegClasses[] = {
+ NULL
+ };
+
+ // GR32_NOREX Super-register Classes...
+ static const TargetRegisterClass* const GR32_NOREXSuperRegClasses[] = {
+ &X86::GR64_NOREXRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL
+ };
+
+ // GR32_NOSP Super-register Classes...
+ static const TargetRegisterClass* const GR32_NOSPSuperRegClasses[] = {
+ &X86::GR64_NOSPRegClass, NULL
+ };
+
+ // GR64 Super-register Classes...
+ static const TargetRegisterClass* const GR64SuperRegClasses[] = {
+ NULL
+ };
+
+ // GR64_ABCD Super-register Classes...
+ static const TargetRegisterClass* const GR64_ABCDSuperRegClasses[] = {
+ NULL
+ };
+
+ // GR64_NOREX Super-register Classes...
+ static const TargetRegisterClass* const GR64_NOREXSuperRegClasses[] = {
+ NULL
+ };
+
+ // GR64_NOREX_NOSP Super-register Classes...
+ static const TargetRegisterClass* const GR64_NOREX_NOSPSuperRegClasses[] = {
+ NULL
+ };
+
+ // GR64_NOSP Super-register Classes...
+ static const TargetRegisterClass* const GR64_NOSPSuperRegClasses[] = {
+ NULL
+ };
+
+ // GR8 Super-register Classes...
+ static const TargetRegisterClass* const GR8SuperRegClasses[] = {
+ &X86::GR16RegClass, &X86::GR32RegClass, &X86::GR32_NOSPRegClass, &X86::GR64RegClass, &X86::GR64_NOSPRegClass, NULL
+ };
+
+ // GR8_ABCD_H Super-register Classes...
+ static const TargetRegisterClass* const GR8_ABCD_HSuperRegClasses[] = {
+ &X86::GR16_ABCDRegClass, &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, &X86::GR64_ABCDRegClass, NULL
+ };
+
+ // GR8_ABCD_L Super-register Classes...
+ static const TargetRegisterClass* const GR8_ABCD_LSuperRegClasses[] = {
+ &X86::GR16_ABCDRegClass, &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, &X86::GR64_ABCDRegClass, NULL
+ };
+
+ // GR8_NOREX Super-register Classes...
+ static const TargetRegisterClass* const GR8_NOREXSuperRegClasses[] = {
+ &X86::GR16_NOREXRegClass, &X86::GR32_NOREXRegClass, &X86::GR64_NOREXRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL
+ };
+
+ // RFP32 Super-register Classes...
+ static const TargetRegisterClass* const RFP32SuperRegClasses[] = {
+ NULL
+ };
+
+ // RFP64 Super-register Classes...
+ static const TargetRegisterClass* const RFP64SuperRegClasses[] = {
+ NULL
+ };
+
+ // RFP80 Super-register Classes...
+ static const TargetRegisterClass* const RFP80SuperRegClasses[] = {
+ NULL
+ };
+
+ // RST Super-register Classes...
+ static const TargetRegisterClass* const RSTSuperRegClasses[] = {
+ NULL
+ };
+
+ // SEGMENT_REG Super-register Classes...
+ static const TargetRegisterClass* const SEGMENT_REGSuperRegClasses[] = {
+ NULL
+ };
+
+ // VR128 Super-register Classes...
+ static const TargetRegisterClass* const VR128SuperRegClasses[] = {
+ NULL
+ };
+
+ // VR256 Super-register Classes...
+ static const TargetRegisterClass* const VR256SuperRegClasses[] = {
+ NULL
+ };
+
+ // VR64 Super-register Classes...
+ static const TargetRegisterClass* const VR64SuperRegClasses[] = {
+ NULL
+ };
+
+ // CCR Register Class sub-classes...
+ static const TargetRegisterClass* const CCRSubclasses[] = {
+ NULL
+ };
+
+ // FR32 Register Class sub-classes...
+ static const TargetRegisterClass* const FR32Subclasses[] = {
+ &X86::FR64RegClass, &X86::VR128RegClass, NULL
+ };
+
+ // FR64 Register Class sub-classes...
+ static const TargetRegisterClass* const FR64Subclasses[] = {
+ &X86::VR128RegClass, NULL
+ };
+
+ // GR16 Register Class sub-classes...
+ static const TargetRegisterClass* const GR16Subclasses[] = {
+ &X86::GR16_ABCDRegClass, &X86::GR16_NOREXRegClass, NULL
+ };
+
+ // GR16_ABCD Register Class sub-classes...
+ static const TargetRegisterClass* const GR16_ABCDSubclasses[] = {
+ NULL
+ };
+
+ // GR16_NOREX Register Class sub-classes...
+ static const TargetRegisterClass* const GR16_NOREXSubclasses[] = {
+ &X86::GR16_ABCDRegClass, NULL
+ };
+
+ // GR32 Register Class sub-classes...
+ static const TargetRegisterClass* const GR32Subclasses[] = {
+ &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, &X86::GR32_NOREXRegClass, &X86::GR32_NOSPRegClass, NULL
+ };
+
+ // GR32_ABCD Register Class sub-classes...
+ static const TargetRegisterClass* const GR32_ABCDSubclasses[] = {
+ &X86::GR32_ADRegClass, NULL
+ };
+
+ // GR32_AD Register Class sub-classes...
+ static const TargetRegisterClass* const GR32_ADSubclasses[] = {
+ NULL
+ };
+
+ // GR32_NOREX Register Class sub-classes...
+ static const TargetRegisterClass* const GR32_NOREXSubclasses[] = {
+ &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, NULL
+ };
+
+ // GR32_NOSP Register Class sub-classes...
+ static const TargetRegisterClass* const GR32_NOSPSubclasses[] = {
+ &X86::GR32_ABCDRegClass, &X86::GR32_ADRegClass, NULL
+ };
+
+ // GR64 Register Class sub-classes...
+ static const TargetRegisterClass* const GR64Subclasses[] = {
+ &X86::GR64_ABCDRegClass, &X86::GR64_NOREXRegClass, &X86::GR64_NOREX_NOSPRegClass, &X86::GR64_NOSPRegClass, NULL
+ };
+
+ // GR64_ABCD Register Class sub-classes...
+ static const TargetRegisterClass* const GR64_ABCDSubclasses[] = {
+ NULL
+ };
+
+ // GR64_NOREX Register Class sub-classes...
+ static const TargetRegisterClass* const GR64_NOREXSubclasses[] = {
+ &X86::GR64_ABCDRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL
+ };
+
+ // GR64_NOREX_NOSP Register Class sub-classes...
+ static const TargetRegisterClass* const GR64_NOREX_NOSPSubclasses[] = {
+ &X86::GR64_ABCDRegClass, NULL
+ };
+
+ // GR64_NOSP Register Class sub-classes...
+ static const TargetRegisterClass* const GR64_NOSPSubclasses[] = {
+ &X86::GR64_ABCDRegClass, &X86::GR64_NOREX_NOSPRegClass, NULL
+ };
+
+ // GR8 Register Class sub-classes...
+ static const TargetRegisterClass* const GR8Subclasses[] = {
+ &X86::GR8_ABCD_HRegClass, &X86::GR8_ABCD_LRegClass, &X86::GR8_NOREXRegClass, NULL
+ };
+
+ // GR8_ABCD_H Register Class sub-classes...
+ static const TargetRegisterClass* const GR8_ABCD_HSubclasses[] = {
+ NULL
+ };
+
+ // GR8_ABCD_L Register Class sub-classes...
+ static const TargetRegisterClass* const GR8_ABCD_LSubclasses[] = {
+ NULL
+ };
+
+ // GR8_NOREX Register Class sub-classes...
+ static const TargetRegisterClass* const GR8_NOREXSubclasses[] = {
+ &X86::GR8_ABCD_HRegClass, &X86::GR8_ABCD_LRegClass, NULL
+ };
+
+ // RFP32 Register Class sub-classes...
+ static const TargetRegisterClass* const RFP32Subclasses[] = {
+ &X86::RFP64RegClass, &X86::RFP80RegClass, NULL
+ };
+
+ // RFP64 Register Class sub-classes...
+ static const TargetRegisterClass* const RFP64Subclasses[] = {
+ &X86::RFP80RegClass, NULL
+ };
+
+ // RFP80 Register Class sub-classes...
+ static const TargetRegisterClass* const RFP80Subclasses[] = {
+ NULL
+ };
+
+ // RST Register Class sub-classes...
+ static const TargetRegisterClass* const RSTSubclasses[] = {
+ NULL
+ };
+
+ // SEGMENT_REG Register Class sub-classes...
+ static const TargetRegisterClass* const SEGMENT_REGSubclasses[] = {
+ NULL
+ };
+
+ // VR128 Register Class sub-classes...
+ static const TargetRegisterClass* const VR128Subclasses[] = {
+ NULL
+ };
+
+ // VR256 Register Class sub-classes...
+ static const TargetRegisterClass* const VR256Subclasses[] = {
+ NULL
+ };
+
+ // VR64 Register Class sub-classes...
+ static const TargetRegisterClass* const VR64Subclasses[] = {
+ NULL
+ };
+
+ // CCR Register Class super-classes...
+ static const TargetRegisterClass* const CCRSuperclasses[] = {
+ NULL
+ };
+
+ // FR32 Register Class super-classes...
+ static const TargetRegisterClass* const FR32Superclasses[] = {
+ NULL
+ };
+
+ // FR64 Register Class super-classes...
+ static const TargetRegisterClass* const FR64Superclasses[] = {
+ &X86::FR32RegClass, NULL
+ };
+
+ // GR16 Register Class super-classes...
+ static const TargetRegisterClass* const GR16Superclasses[] = {
+ NULL
+ };
+
+ // GR16_ABCD Register Class super-classes...
+ static const TargetRegisterClass* const GR16_ABCDSuperclasses[] = {
+ &X86::GR16RegClass, &X86::GR16_NOREXRegClass, NULL
+ };
+
+ // GR16_NOREX Register Class super-classes...
+ static const TargetRegisterClass* const GR16_NOREXSuperclasses[] = {
+ &X86::GR16RegClass, NULL
+ };
+
+ // GR32 Register Class super-classes...
+ static const TargetRegisterClass* const GR32Superclasses[] = {
+ NULL
+ };
+
+ // GR32_ABCD Register Class super-classes...
+ static const TargetRegisterClass* const GR32_ABCDSuperclasses[] = {
+ &X86::GR32RegClass, &X86::GR32_NOREXRegClass, &X86::GR32_NOSPRegClass, NULL
+ };
+
+ // GR32_AD Register Class super-classes...
+ static const TargetRegisterClass* const GR32_ADSuperclasses[] = {
+ &X86::GR32RegClass, &X86::GR32_ABCDRegClass, &X86::GR32_NOREXRegClass, &X86::GR32_NOSPRegClass, NULL
+ };
+
+ // GR32_NOREX Register Class super-classes...
+ static const TargetRegisterClass* const GR32_NOREXSuperclasses[] = {
+ &X86::GR32RegClass, NULL
+ };
+
+ // GR32_NOSP Register Class super-classes...
+ static const TargetRegisterClass* const GR32_NOSPSuperclasses[] = {
+ &X86::GR32RegClass, NULL
+ };
+
+ // GR64 Register Class super-classes...
+ static const TargetRegisterClass* const GR64Superclasses[] = {
+ NULL
+ };
+
+ // GR64_ABCD Register Class super-classes...
+ static const TargetRegisterClass* const GR64_ABCDSuperclasses[] = {
+ &X86::GR64RegClass, &X86::GR64_NOREXRegClass, &X86::GR64_NOREX_NOSPRegClass, &X86::GR64_NOSPRegClass, NULL
+ };
+
+ // GR64_NOREX Register Class super-classes...
+ static const TargetRegisterClass* const GR64_NOREXSuperclasses[] = {
+ &X86::GR64RegClass, NULL
+ };
+
+ // GR64_NOREX_NOSP Register Class super-classes...
+ static const TargetRegisterClass* const GR64_NOREX_NOSPSuperclasses[] = {
+ &X86::GR64RegClass, &X86::GR64_NOREXRegClass, &X86::GR64_NOSPRegClass, NULL
+ };
+
+ // GR64_NOSP Register Class super-classes...
+ static const TargetRegisterClass* const GR64_NOSPSuperclasses[] = {
+ &X86::GR64RegClass, NULL
+ };
+
+ // GR8 Register Class super-classes...
+ static const TargetRegisterClass* const GR8Superclasses[] = {
+ NULL
+ };
+
+ // GR8_ABCD_H Register Class super-classes...
+ static const TargetRegisterClass* const GR8_ABCD_HSuperclasses[] = {
+ &X86::GR8RegClass, &X86::GR8_NOREXRegClass, NULL
+ };
+
+ // GR8_ABCD_L Register Class super-classes...
+ static const TargetRegisterClass* const GR8_ABCD_LSuperclasses[] = {
+ &X86::GR8RegClass, &X86::GR8_NOREXRegClass, NULL
+ };
+
+ // GR8_NOREX Register Class super-classes...
+ static const TargetRegisterClass* const GR8_NOREXSuperclasses[] = {
+ &X86::GR8RegClass, NULL
+ };
+
+ // RFP32 Register Class super-classes...
+ static const TargetRegisterClass* const RFP32Superclasses[] = {
+ NULL
+ };
+
+ // RFP64 Register Class super-classes...
+ static const TargetRegisterClass* const RFP64Superclasses[] = {
+ &X86::RFP32RegClass, NULL
+ };
+
+ // RFP80 Register Class super-classes...
+ static const TargetRegisterClass* const RFP80Superclasses[] = {
+ &X86::RFP32RegClass, &X86::RFP64RegClass, NULL
+ };
+
+ // RST Register Class super-classes...
+ static const TargetRegisterClass* const RSTSuperclasses[] = {
+ NULL
+ };
+
+ // SEGMENT_REG Register Class super-classes...
+ static const TargetRegisterClass* const SEGMENT_REGSuperclasses[] = {
+ NULL
+ };
+
+ // VR128 Register Class super-classes...
+ static const TargetRegisterClass* const VR128Superclasses[] = {
+ &X86::FR32RegClass, &X86::FR64RegClass, NULL
+ };
+
+ // VR256 Register Class super-classes...
+ static const TargetRegisterClass* const VR256Superclasses[] = {
+ NULL
+ };
+
+ // VR64 Register Class super-classes...
+ static const TargetRegisterClass* const VR64Superclasses[] = {
+ NULL
+ };
+
+
+CCRClass::CCRClass() : TargetRegisterClass(CCRRegClassID, "CCR", CCRVTs, CCRSubclasses, CCRSuperclasses, CCRSubRegClasses, CCRSuperRegClasses, 4, 4, -1, CCR, CCR + 1) {}
+
+ FR32Class::iterator
+ FR32Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (!Subtarget.is64Bit())
+ return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
+ else
+ return end();
+ }
+
+FR32Class::FR32Class() : TargetRegisterClass(FR32RegClassID, "FR32", FR32VTs, FR32Subclasses, FR32Superclasses, FR32SubRegClasses, FR32SuperRegClasses, 4, 4, 1, FR32, FR32 + 16) {}
+
+ FR64Class::iterator
+ FR64Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (!Subtarget.is64Bit())
+ return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
+ else
+ return end();
+ }
+
+FR64Class::FR64Class() : TargetRegisterClass(FR64RegClassID, "FR64", FR64VTs, FR64Subclasses, FR64Superclasses, FR64SubRegClasses, FR64SuperRegClasses, 8, 8, 1, FR64, FR64 + 16) {}
+
+ static const unsigned X86_GR16_AO_64[] = {
+ X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
+ X86::R8W, X86::R9W, X86::R10W, X86::R11W,
+ X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
+ };
+
+ GR16Class::iterator
+ GR16Class::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit())
+ return X86_GR16_AO_64;
+ else
+ return begin();
+ }
+
+ GR16Class::iterator
+ GR16Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit()) {
+ // Does the function dedicate RBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate SP or BP.
+ return array_endof(X86_GR16_AO_64) - 1;
+ else
+ // If not, just don't allocate SP.
+ return array_endof(X86_GR16_AO_64);
+ } else {
+ // Does the function dedicate EBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate SP or BP.
+ return begin() + 6;
+ else
+ // If not, just don't allocate SP.
+ return begin() + 7;
+ }
+ }
+
+GR16Class::GR16Class() : TargetRegisterClass(GR16RegClassID, "GR16", GR16VTs, GR16Subclasses, GR16Superclasses, GR16SubRegClasses, GR16SuperRegClasses, 2, 2, 1, GR16, GR16 + 16) {}
+
+GR16_ABCDClass::GR16_ABCDClass() : TargetRegisterClass(GR16_ABCDRegClassID, "GR16_ABCD", GR16_ABCDVTs, GR16_ABCDSubclasses, GR16_ABCDSuperclasses, GR16_ABCDSubRegClasses, GR16_ABCDSuperRegClasses, 2, 2, 1, GR16_ABCD, GR16_ABCD + 4) {}
+
+ GR16_NOREXClass::iterator
+ GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ // Does the function dedicate RBP / EBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate SP or BP.
+ return end() - 2;
+ else
+ // If not, just don't allocate SP.
+ return end() - 1;
+ }
+
+GR16_NOREXClass::GR16_NOREXClass() : TargetRegisterClass(GR16_NOREXRegClassID, "GR16_NOREX", GR16_NOREXVTs, GR16_NOREXSubclasses, GR16_NOREXSuperclasses, GR16_NOREXSubRegClasses, GR16_NOREXSuperRegClasses, 2, 2, 1, GR16_NOREX, GR16_NOREX + 8) {}
+
+ static const unsigned X86_GR32_AO_64[] = {
+ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
+ X86::R8D, X86::R9D, X86::R10D, X86::R11D,
+ X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
+ };
+
+ GR32Class::iterator
+ GR32Class::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit())
+ return X86_GR32_AO_64;
+ else
+ return begin();
+ }
+
+ GR32Class::iterator
+ GR32Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit()) {
+ // Does the function dedicate RBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate ESP or EBP.
+ return array_endof(X86_GR32_AO_64) - 1;
+ else
+ // If not, just don't allocate ESP.
+ return array_endof(X86_GR32_AO_64);
+ } else {
+ // Does the function dedicate EBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate ESP or EBP.
+ return begin() + 6;
+ else
+ // If not, just don't allocate ESP.
+ return begin() + 7;
+ }
+ }
+
+GR32Class::GR32Class() : TargetRegisterClass(GR32RegClassID, "GR32", GR32VTs, GR32Subclasses, GR32Superclasses, GR32SubRegClasses, GR32SuperRegClasses, 4, 4, 1, GR32, GR32 + 16) {}
+
+GR32_ABCDClass::GR32_ABCDClass() : TargetRegisterClass(GR32_ABCDRegClassID, "GR32_ABCD", GR32_ABCDVTs, GR32_ABCDSubclasses, GR32_ABCDSuperclasses, GR32_ABCDSubRegClasses, GR32_ABCDSuperRegClasses, 4, 4, 1, GR32_ABCD, GR32_ABCD + 4) {}
+
+GR32_ADClass::GR32_ADClass() : TargetRegisterClass(GR32_ADRegClassID, "GR32_AD", GR32_ADVTs, GR32_ADSubclasses, GR32_ADSuperclasses, GR32_ADSubRegClasses, GR32_ADSuperRegClasses, 4, 4, 1, GR32_AD, GR32_AD + 2) {}
+
+ GR32_NOREXClass::iterator
+ GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ // Does the function dedicate RBP / EBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate ESP or EBP.
+ return end() - 2;
+ else
+ // If not, just don't allocate ESP.
+ return end() - 1;
+ }
+
+GR32_NOREXClass::GR32_NOREXClass() : TargetRegisterClass(GR32_NOREXRegClassID, "GR32_NOREX", GR32_NOREXVTs, GR32_NOREXSubclasses, GR32_NOREXSuperclasses, GR32_NOREXSubRegClasses, GR32_NOREXSuperRegClasses, 4, 4, 1, GR32_NOREX, GR32_NOREX + 8) {}
+
+ static const unsigned X86_GR32_NOSP_AO_64[] = {
+ X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
+ X86::R8D, X86::R9D, X86::R10D, X86::R11D,
+ X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
+ };
+
+ GR32_NOSPClass::iterator
+ GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit())
+ return X86_GR32_NOSP_AO_64;
+ else
+ return begin();
+ }
+
+ GR32_NOSPClass::iterator
+ GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit()) {
+ // Does the function dedicate RBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate EBP.
+ return array_endof(X86_GR32_NOSP_AO_64) - 1;
+ else
+ // If not, any reg in this class is ok.
+ return array_endof(X86_GR32_NOSP_AO_64);
+ } else {
+ // Does the function dedicate EBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate EBP.
+ return begin() + 6;
+ else
+ // If not, any reg in this class is ok.
+ return begin() + 7;
+ }
+ }
+
+GR32_NOSPClass::GR32_NOSPClass() : TargetRegisterClass(GR32_NOSPRegClassID, "GR32_NOSP", GR32_NOSPVTs, GR32_NOSPSubclasses, GR32_NOSPSuperclasses, GR32_NOSPSubRegClasses, GR32_NOSPSuperRegClasses, 4, 4, 1, GR32_NOSP, GR32_NOSP + 15) {}
+
+ GR64Class::iterator
+ GR64Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (!Subtarget.is64Bit())
+ return begin(); // None of these are allocatable in 32-bit.
+ if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
+ return end()-3; // If so, don't allocate RIP, RSP or RBP
+ else
+ return end()-2; // If not, just don't allocate RIP or RSP
+ }
+
+GR64Class::GR64Class() : TargetRegisterClass(GR64RegClassID, "GR64", GR64VTs, GR64Subclasses, GR64Superclasses, GR64SubRegClasses, GR64SuperRegClasses, 8, 8, 1, GR64, GR64 + 17) {}
+
+GR64_ABCDClass::GR64_ABCDClass() : TargetRegisterClass(GR64_ABCDRegClassID, "GR64_ABCD", GR64_ABCDVTs, GR64_ABCDSubclasses, GR64_ABCDSuperclasses, GR64_ABCDSubRegClasses, GR64_ABCDSuperRegClasses, 8, 8, 1, GR64_ABCD, GR64_ABCD + 4) {}
+
+ GR64_NOREXClass::iterator
+ GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ // Does the function dedicate RBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate RIP, RSP or RBP.
+ return end() - 3;
+ else
+ // If not, just don't allocate RIP or RSP.
+ return end() - 2;
+ }
+
+GR64_NOREXClass::GR64_NOREXClass() : TargetRegisterClass(GR64_NOREXRegClassID, "GR64_NOREX", GR64_NOREXVTs, GR64_NOREXSubclasses, GR64_NOREXSuperclasses, GR64_NOREXSubRegClasses, GR64_NOREXSuperRegClasses, 8, 8, 1, GR64_NOREX, GR64_NOREX + 9) {}
+
+ GR64_NOREX_NOSPClass::iterator
+ GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ // Does the function dedicate RBP to being a frame ptr?
+ if (RI->hasFP(MF))
+ // If so, don't allocate RBP.
+ return end() - 1;
+ else
+ // If not, any reg in this class is ok.
+ return end();
+ }
+
+GR64_NOREX_NOSPClass::GR64_NOREX_NOSPClass() : TargetRegisterClass(GR64_NOREX_NOSPRegClassID, "GR64_NOREX_NOSP", GR64_NOREX_NOSPVTs, GR64_NOREX_NOSPSubclasses, GR64_NOREX_NOSPSuperclasses, GR64_NOREX_NOSPSubRegClasses, GR64_NOREX_NOSPSuperRegClasses, 8, 8, 1, GR64_NOREX_NOSP, GR64_NOREX_NOSP + 7) {}
+
+ GR64_NOSPClass::iterator
+ GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (!Subtarget.is64Bit())
+ return begin(); // None of these are allocatable in 32-bit.
+ if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
+ return end()-1; // If so, don't allocate RBP
+ else
+ return end(); // If not, any reg in this class is ok.
+ }
+
+GR64_NOSPClass::GR64_NOSPClass() : TargetRegisterClass(GR64_NOSPRegClassID, "GR64_NOSP", GR64_NOSPVTs, GR64_NOSPSubclasses, GR64_NOSPSuperclasses, GR64_NOSPSubRegClasses, GR64_NOSPSuperRegClasses, 8, 8, 1, GR64_NOSP, GR64_NOSP + 15) {}
+
+ static const unsigned X86_GR8_AO_64[] = {
+ X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
+ X86::R8B, X86::R9B, X86::R10B, X86::R11B,
+ X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
+ };
+
+ GR8Class::iterator
+ GR8Class::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit())
+ return X86_GR8_AO_64;
+ else
+ return begin();
+ }
+
+ GR8Class::iterator
+ GR8Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ // Does the function dedicate RBP / EBP to being a frame ptr?
+ if (!Subtarget.is64Bit())
+ // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
+ return begin() + 8;
+ else if (RI->hasFP(MF))
+ // If so, don't allocate SPL or BPL.
+ return array_endof(X86_GR8_AO_64) - 1;
+ else
+ // If not, just don't allocate SPL.
+ return array_endof(X86_GR8_AO_64);
+ }
+
+GR8Class::GR8Class() : TargetRegisterClass(GR8RegClassID, "GR8", GR8VTs, GR8Subclasses, GR8Superclasses, GR8SubRegClasses, GR8SuperRegClasses, 1, 1, 1, GR8, GR8 + 20) {}
+
+GR8_ABCD_HClass::GR8_ABCD_HClass() : TargetRegisterClass(GR8_ABCD_HRegClassID, "GR8_ABCD_H", GR8_ABCD_HVTs, GR8_ABCD_HSubclasses, GR8_ABCD_HSuperclasses, GR8_ABCD_HSubRegClasses, GR8_ABCD_HSuperRegClasses, 1, 1, 1, GR8_ABCD_H, GR8_ABCD_H + 4) {}
+
+GR8_ABCD_LClass::GR8_ABCD_LClass() : TargetRegisterClass(GR8_ABCD_LRegClassID, "GR8_ABCD_L", GR8_ABCD_LVTs, GR8_ABCD_LSubclasses, GR8_ABCD_LSuperclasses, GR8_ABCD_LSubRegClasses, GR8_ABCD_LSuperRegClasses, 1, 1, 1, GR8_ABCD_L, GR8_ABCD_L + 4) {}
+
+ static const unsigned X86_GR8_NOREX_AO_64[] = {
+ X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
+ };
+
+ GR8_NOREXClass::iterator
+ GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (Subtarget.is64Bit())
+ return X86_GR8_NOREX_AO_64;
+ else
+ return begin();
+ }
+
+ GR8_NOREXClass::iterator
+ GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ // Does the function dedicate RBP / EBP to being a frame ptr?
+ if (!Subtarget.is64Bit())
+ // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
+ return begin() + 8;
+ else if (RI->hasFP(MF))
+ // If so, don't allocate SPL or BPL.
+ return array_endof(X86_GR8_NOREX_AO_64) - 1;
+ else
+ // If not, just don't allocate SPL.
+ return array_endof(X86_GR8_NOREX_AO_64);
+ }
+
+GR8_NOREXClass::GR8_NOREXClass() : TargetRegisterClass(GR8_NOREXRegClassID, "GR8_NOREX", GR8_NOREXVTs, GR8_NOREXSubclasses, GR8_NOREXSuperclasses, GR8_NOREXSubRegClasses, GR8_NOREXSuperRegClasses, 1, 1, 1, GR8_NOREX, GR8_NOREX + 12) {}
+
+RFP32Class::RFP32Class() : TargetRegisterClass(RFP32RegClassID, "RFP32", RFP32VTs, RFP32Subclasses, RFP32Superclasses, RFP32SubRegClasses, RFP32SuperRegClasses, 4, 4, 1, RFP32, RFP32 + 7) {}
+
+RFP64Class::RFP64Class() : TargetRegisterClass(RFP64RegClassID, "RFP64", RFP64VTs, RFP64Subclasses, RFP64Superclasses, RFP64SubRegClasses, RFP64SuperRegClasses, 8, 4, 1, RFP64, RFP64 + 7) {}
+
+RFP80Class::RFP80Class() : TargetRegisterClass(RFP80RegClassID, "RFP80", RFP80VTs, RFP80Subclasses, RFP80Superclasses, RFP80SubRegClasses, RFP80SuperRegClasses, 10, 4, 1, RFP80, RFP80 + 7) {}
+
+ RSTClass::iterator
+ RSTClass::allocation_order_end(const MachineFunction &MF) const {
+ return begin();
+ }
+
+RSTClass::RSTClass() : TargetRegisterClass(RSTRegClassID, "RST", RSTVTs, RSTSubclasses, RSTSuperclasses, RSTSubRegClasses, RSTSuperRegClasses, 10, 4, 1, RST, RST + 8) {}
+
+SEGMENT_REGClass::SEGMENT_REGClass() : TargetRegisterClass(SEGMENT_REGRegClassID, "SEGMENT_REG", SEGMENT_REGVTs, SEGMENT_REGSubclasses, SEGMENT_REGSuperclasses, SEGMENT_REGSubRegClasses, SEGMENT_REGSuperRegClasses, 2, 2, 1, SEGMENT_REG, SEGMENT_REG + 6) {}
+
+ VR128Class::iterator
+ VR128Class::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+ if (!Subtarget.is64Bit())
+ return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
+ else
+ return end();
+ }
+
+VR128Class::VR128Class() : TargetRegisterClass(VR128RegClassID, "VR128", VR128VTs, VR128Subclasses, VR128Superclasses, VR128SubRegClasses, VR128SuperRegClasses, 16, 16, 1, VR128, VR128 + 16) {}
+
+VR256Class::VR256Class() : TargetRegisterClass(VR256RegClassID, "VR256", VR256VTs, VR256Subclasses, VR256Superclasses, VR256SubRegClasses, VR256SuperRegClasses, 32, 32, 1, VR256, VR256 + 16) {}
+
+VR64Class::VR64Class() : TargetRegisterClass(VR64RegClassID, "VR64", VR64VTs, VR64Subclasses, VR64Superclasses, VR64SubRegClasses, VR64SuperRegClasses, 8, 8, 1, VR64, VR64 + 8) {}
+}
+
+namespace {
+ const TargetRegisterClass* const RegisterClasses[] = {
+ &X86::CCRRegClass,
+ &X86::FR32RegClass,
+ &X86::FR64RegClass,
+ &X86::GR16RegClass,
+ &X86::GR16_ABCDRegClass,
+ &X86::GR16_NOREXRegClass,
+ &X86::GR32RegClass,
+ &X86::GR32_ABCDRegClass,
+ &X86::GR32_ADRegClass,
+ &X86::GR32_NOREXRegClass,
+ &X86::GR32_NOSPRegClass,
+ &X86::GR64RegClass,
+ &X86::GR64_ABCDRegClass,
+ &X86::GR64_NOREXRegClass,
+ &X86::GR64_NOREX_NOSPRegClass,
+ &X86::GR64_NOSPRegClass,
+ &X86::GR8RegClass,
+ &X86::GR8_ABCD_HRegClass,
+ &X86::GR8_ABCD_LRegClass,
+ &X86::GR8_NOREXRegClass,
+ &X86::RFP32RegClass,
+ &X86::RFP64RegClass,
+ &X86::RFP80RegClass,
+ &X86::RSTRegClass,
+ &X86::SEGMENT_REGRegClass,
+ &X86::VR128RegClass,
+ &X86::VR256RegClass,
+ &X86::VR64RegClass,
+ };
+
+
+ // Number of hash collisions: 20
+ const unsigned SubregHashTable[] = { X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::EIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::DI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11W,
+ X86::AX, X86::AH,
+ X86::R11D, X86::R11W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DH,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AH,
+ X86::DI, X86::DIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15, X86::R15B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15D, X86::R15B,
+ X86::R15W, X86::R15B,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::DIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::AX, X86::AL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DL,
+ X86::RSI, X86::ESI,
+ X86::R15, X86::R15D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12D, X86::R12B,
+ X86::R12W, X86::R12B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15, X86::R15W,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15D, X86::R15W,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSP, X86::ESP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12D,
+ X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::BH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12W,
+ X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::BL,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12D, X86::R12W,
+ X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8, X86::R8B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8D, X86::R8B,
+ X86::R8W, X86::R8B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::SI,
+ X86::R8, X86::R8D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::BPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BL,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13B,
+ X86::R13W, X86::R13B,
+ X86::RAX, X86::EAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::SIL,
+ X86::R8, X86::R8W,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8D, X86::R8W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::BP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13D,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSI, X86::SI,
+ X86::RBP, X86::EBP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SP,
+ X86::R10, X86::R10B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10D, X86::R10B,
+ X86::R10W, X86::R10B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::BPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13W,
+ X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CH,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13W,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::EBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSI, X86::SIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::SIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SPL,
+ X86::R10, X86::R10D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9D, X86::R9B,
+ X86::R9W, X86::R9B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CL,
+ X86::RSP, X86::SP,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::ECX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10W,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10D, X86::R10W,
+ X86::R9, X86::R9D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSP, X86::SPL,
+ X86::R14, X86::R14B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14D, X86::R14B,
+ X86::R14W, X86::R14B,
+ X86::RDI, X86::EDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::SPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9W,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9D, X86::R9W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EIP, X86::IP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11D, X86::R11B,
+ X86::R11W, X86::R11B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14W,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14D, X86::R14W,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DH,
+ X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::IP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+X86::NoRegister, X86::NoRegister };
+ const unsigned SubregHashTableSize = 512;
+
+
+ // Number of hash collisions: 15
+ const unsigned SuperregHashTable[] = { X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11B, X86::R11D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11W, X86::R11D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::RCX,
+ X86::CL, X86::RCX,
+ X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::RCX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DIL, X86::DI,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::RCX,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15,
+ X86::R15D, X86::R15,
+ X86::R15W, X86::R15,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11B, X86::R11W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::RDI,
+ X86::DIL, X86::RDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::RDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12,
+ X86::R12D, X86::R12,
+ X86::R12W, X86::R12,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15W, X86::R15D,
+ X86::SIL, X86::ESI,
+ X86::SI, X86::ESI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::AX,
+ X86::AL, X86::AX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EIP, X86::RIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15W,
+ X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::ESP,
+ X86::SPL, X86::ESP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::RIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12W, X86::R12D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::RSI,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8,
+ X86::R8D, X86::R8,
+ X86::R8W, X86::R8,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::EAX,
+ X86::AL, X86::EAX,
+ X86::AX, X86::EAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::RSP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BPL, X86::BP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13,
+ X86::BP, X86::EBP,
+ X86::BPL, X86::EBP,
+ X86::R13D, X86::R13,
+ X86::R13W, X86::R13,
+ X86::SI, X86::RSI,
+ X86::SIL, X86::RSI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8W, X86::R8D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::EBX,
+ X86::BL, X86::EBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::EBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::RSP,
+ X86::SPL, X86::RSP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8W,
+ X86::R10B, X86::R10,
+ X86::R10D, X86::R10,
+ X86::R10W, X86::R10,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::BX,
+ X86::BL, X86::BX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13W, X86::R13D,
+ X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::ECX,
+ X86::CL, X86::ECX,
+ X86::SIL, X86::SI,
+ X86::CX, X86::ECX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9B, X86::R9,
+ X86::R9D, X86::R9,
+ X86::R9W, X86::R9,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::EDI,
+ X86::DIL, X86::EDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10B, X86::R10D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10W, X86::R10D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14B, X86::R14,
+ X86::R14D, X86::R14,
+ X86::R14W, X86::R14,
+ X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::EDX,
+ X86::SPL, X86::SP,
+ X86::DX, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10B, X86::R10W,
+ X86::AH, X86::RAX,
+ X86::AL, X86::RAX,
+ X86::AX, X86::RAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9B, X86::R9D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9W, X86::R9D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::RAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9B, X86::R9W,
+ X86::R11B, X86::R11,
+ X86::R11D, X86::R11,
+ X86::BP, X86::RBP,
+ X86::BPL, X86::RBP,
+ X86::R11W, X86::R11,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::CX,
+ X86::CL, X86::CX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::RBP,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14B, X86::R14D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14W, X86::R14D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::RBX,
+ X86::BL, X86::RBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::RBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::EIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::RBX,
+ X86::R14B, X86::R14W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+X86::NoRegister, X86::NoRegister };
+ const unsigned SuperregHashTableSize = 512;
+
+
+ // Number of hash collisions: 32
+ const unsigned AliasesHashTable[] = { X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11D,
+ X86::R11B, X86::R11D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11W, X86::R11D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::RCX,
+ X86::CL, X86::RCX,
+ X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::RCX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::RCX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::EIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11W,
+ X86::AX, X86::AH,
+ X86::R11D, X86::R11W,
+ X86::R11B, X86::R11W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::RDI,
+ X86::DIL, X86::RDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::RDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::AX, X86::AL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12B, X86::R12,
+ X86::R12D, X86::R12,
+ X86::R12W, X86::R12,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::RDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSI, X86::ESI,
+ X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::ESI,
+ X86::SIL, X86::ESI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::AX,
+ X86::AL, X86::AX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12D, X86::R12B,
+ X86::R12W, X86::R12B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::AX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EIP, X86::RIP,
+ X86::RSP, X86::ESP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::ESP,
+ X86::SPL, X86::ESP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::RIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12D,
+ X86::R12B, X86::R12D,
+ X86::BX, X86::BH,
+ X86::R12W, X86::R12D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::RSI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12, X86::R12W,
+ X86::R12B, X86::R12W,
+ X86::BX, X86::BL,
+ X86::NoRegister, X86::NoRegister,
+ X86::R12D, X86::R12W,
+ X86::NoRegister, X86::NoRegister,
+ X86::RAX, X86::AX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::RSP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BPL, X86::BP,
+ X86::RBX, X86::BH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13B, X86::R13,
+ X86::R13D, X86::R13,
+ X86::R13W, X86::R13,
+ X86::SI, X86::RSI,
+ X86::SIL, X86::RSI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::SI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::BPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BL,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13B,
+ X86::R13W, X86::R13B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::SP, X86::RSP,
+ X86::SPL, X86::RSP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::BPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESI, X86::SIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::BX,
+ X86::BL, X86::BX,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::BP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13D,
+ X86::R13B, X86::R13D,
+ X86::RSI, X86::SI,
+ X86::R13W, X86::R13D,
+ X86::NoRegister, X86::NoRegister,
+ X86::SIL, X86::SI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::BX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::BPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13, X86::R13W,
+ X86::R13B, X86::R13W,
+ X86::CX, X86::CH,
+ X86::NoRegister, X86::NoRegister,
+ X86::R13D, X86::R13W,
+ X86::NoRegister, X86::NoRegister,
+ X86::SI, X86::SIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSI, X86::SIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ESP, X86::SPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::BX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::CL,
+ X86::RSP, X86::SP,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14B, X86::R14,
+ X86::R14D, X86::R14,
+ X86::R14W, X86::R14,
+ X86::NoRegister, X86::NoRegister,
+ X86::SPL, X86::SP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RSP, X86::SPL,
+ X86::R14, X86::R14B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14D, X86::R14B,
+ X86::R14W, X86::R14B,
+ X86::SP, X86::SPL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EIP, X86::IP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::CX,
+ X86::CL, X86::CX,
+ X86::RCX, X86::CL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14D,
+ X86::R14B, X86::R14D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14W, X86::R14D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::ECX, X86::CX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R14, X86::R14W,
+ X86::R14B, X86::R14W,
+ X86::R14D, X86::R14W,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DH,
+ X86::NoRegister, X86::NoRegister,
+ X86::RIP, X86::IP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::CX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DIL, X86::DI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15B, X86::R15,
+ X86::R15D, X86::R15,
+ X86::R15W, X86::R15,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::DI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DH,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::DIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15, X86::R15B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15D, X86::R15B,
+ X86::R15W, X86::R15B,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDI, X86::DIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::DL,
+ X86::R15B, X86::R15D,
+ X86::R15, X86::R15D,
+ X86::R15W, X86::R15D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EDX, X86::DL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::DIL,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R15, X86::R15W,
+ X86::R15B, X86::R15W,
+ X86::R15D, X86::R15W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DL,
+ X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8B, X86::R8,
+ X86::EDX, X86::DX,
+ X86::R8W, X86::R8,
+ X86::R8D, X86::R8,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::AH, X86::EAX,
+ X86::AL, X86::EAX,
+ X86::AX, X86::EAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8, X86::R8B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8D, X86::R8B,
+ X86::R8W, X86::R8B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BP, X86::EBP,
+ X86::BPL, X86::EBP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::DX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8, X86::R8D,
+ X86::R8B, X86::R8D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8W, X86::R8D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::BH, X86::EBX,
+ X86::BL, X86::EBX,
+ X86::RAX, X86::EAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::BX, X86::EBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8, X86::R8W,
+ X86::R8B, X86::R8W,
+ X86::R10B, X86::R10,
+ X86::R10D, X86::R10,
+ X86::R10W, X86::R10,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R8D, X86::R8W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBP, X86::EBP,
+ X86::NoRegister, X86::NoRegister,
+ X86::CH, X86::ECX,
+ X86::CL, X86::ECX,
+ X86::NoRegister, X86::NoRegister,
+ X86::CX, X86::ECX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10B,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10D, X86::R10B,
+ X86::R10W, X86::R10B,
+ X86::R9B, X86::R9,
+ X86::R9D, X86::R9,
+ X86::R9W, X86::R9,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RBX, X86::EBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DI, X86::EDI,
+ X86::DIL, X86::EDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10D,
+ X86::R10B, X86::R10D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10W, X86::R10D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9B,
+ X86::R9W, X86::R9B,
+ X86::R9D, X86::R9B,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RCX, X86::ECX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DH, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::DL, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::DX, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10, X86::R10W,
+ X86::R10B, X86::R10W,
+ X86::AH, X86::RAX,
+ X86::AL, X86::RAX,
+ X86::AX, X86::RAX,
+ X86::R9, X86::R9D,
+ X86::R9B, X86::R9D,
+ X86::NoRegister, X86::NoRegister,
+ X86::R10D, X86::R10W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9W, X86::R9D,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EAX, X86::RAX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDI, X86::EDI,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9, X86::R9W,
+ X86::R9B, X86::R9W,
+ X86::R11B, X86::R11,
+ X86::R11D, X86::R11,
+ X86::BP, X86::RBP,
+ X86::BPL, X86::RBP,
+ X86::R11W, X86::R11,
+ X86::NoRegister, X86::NoRegister,
+ X86::R9D, X86::R9W,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBP, X86::RBP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::RDX, X86::EDX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::R11, X86::R11B,
+ X86::BH, X86::RBX,
+ X86::BL, X86::RBX,
+ X86::R11W, X86::R11B,
+ X86::R11D, X86::R11B,
+ X86::BX, X86::RBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::IP, X86::EIP,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::EBX, X86::RBX,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+ X86::NoRegister, X86::NoRegister,
+X86::NoRegister, X86::NoRegister };
+ const unsigned AliasesHashTableSize = 1024;
+
+
+ // Register Alias Sets...
+ const unsigned Empty_AliasSet[] = { 0 };
+ const unsigned AH_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
+ const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
+ const unsigned AX_AliasSet[] = { X86::AL, X86::AH, X86::EAX, X86::RAX, 0 };
+ const unsigned BH_AliasSet[] = { X86::BX, X86::EBX, X86::RBX, 0 };
+ const unsigned BL_AliasSet[] = { X86::BX, X86::EBX, X86::RBX, 0 };
+ const unsigned BP_AliasSet[] = { X86::BPL, X86::EBP, X86::RBP, 0 };
+ const unsigned BPL_AliasSet[] = { X86::BP, X86::EBP, X86::RBP, 0 };
+ const unsigned BX_AliasSet[] = { X86::BL, X86::BH, X86::EBX, X86::RBX, 0 };
+ const unsigned CH_AliasSet[] = { X86::CX, X86::ECX, X86::RCX, 0 };
+ const unsigned CL_AliasSet[] = { X86::CX, X86::ECX, X86::RCX, 0 };
+ const unsigned CS_AliasSet[] = { 0 };
+ const unsigned CX_AliasSet[] = { X86::CL, X86::CH, X86::ECX, X86::RCX, 0 };
+ const unsigned DH_AliasSet[] = { X86::DX, X86::EDX, X86::RDX, 0 };
+ const unsigned DI_AliasSet[] = { X86::DIL, X86::EDI, X86::RDI, 0 };
+ const unsigned DIL_AliasSet[] = { X86::DI, X86::EDI, X86::RDI, 0 };
+ const unsigned DL_AliasSet[] = { X86::DX, X86::EDX, X86::RDX, 0 };
+ const unsigned DS_AliasSet[] = { 0 };
+ const unsigned DX_AliasSet[] = { X86::DL, X86::DH, X86::EDX, X86::RDX, 0 };
+ const unsigned EAX_AliasSet[] = { X86::AL, X86::AH, X86::AX, X86::RAX, 0 };
+ const unsigned EBP_AliasSet[] = { X86::BPL, X86::BP, X86::RBP, 0 };
+ const unsigned EBX_AliasSet[] = { X86::BL, X86::BH, X86::BX, X86::RBX, 0 };
+ const unsigned ECX_AliasSet[] = { X86::CL, X86::CH, X86::CX, X86::RCX, 0 };
+ const unsigned EDI_AliasSet[] = { X86::DIL, X86::DI, X86::RDI, 0 };
+ const unsigned EDX_AliasSet[] = { X86::DL, X86::DH, X86::DX, X86::RDX, 0 };
+ const unsigned EFLAGS_AliasSet[] = { 0 };
+ const unsigned EIP_AliasSet[] = { X86::IP, X86::RIP, 0 };
+ const unsigned ES_AliasSet[] = { 0 };
+ const unsigned ESI_AliasSet[] = { X86::SIL, X86::SI, X86::RSI, 0 };
+ const unsigned ESP_AliasSet[] = { X86::SPL, X86::SP, X86::RSP, 0 };
+ const unsigned FP0_AliasSet[] = { 0 };
+ const unsigned FP1_AliasSet[] = { 0 };
+ const unsigned FP2_AliasSet[] = { 0 };
+ const unsigned FP3_AliasSet[] = { 0 };
+ const unsigned FP4_AliasSet[] = { 0 };
+ const unsigned FP5_AliasSet[] = { 0 };
+ const unsigned FP6_AliasSet[] = { 0 };
+ const unsigned FS_AliasSet[] = { 0 };
+ const unsigned GS_AliasSet[] = { 0 };
+ const unsigned IP_AliasSet[] = { X86::EIP, X86::RIP, 0 };
+ const unsigned MM0_AliasSet[] = { 0 };
+ const unsigned MM1_AliasSet[] = { 0 };
+ const unsigned MM2_AliasSet[] = { 0 };
+ const unsigned MM3_AliasSet[] = { 0 };
+ const unsigned MM4_AliasSet[] = { 0 };
+ const unsigned MM5_AliasSet[] = { 0 };
+ const unsigned MM6_AliasSet[] = { 0 };
+ const unsigned MM7_AliasSet[] = { 0 };
+ const unsigned R10_AliasSet[] = { X86::R10B, X86::R10W, X86::R10D, 0 };
+ const unsigned R10B_AliasSet[] = { X86::R10W, X86::R10D, X86::R10, 0 };
+ const unsigned R10D_AliasSet[] = { X86::R10B, X86::R10W, X86::R10, 0 };
+ const unsigned R10W_AliasSet[] = { X86::R10B, X86::R10D, X86::R10, 0 };
+ const unsigned R11_AliasSet[] = { X86::R11B, X86::R11W, X86::R11D, 0 };
+ const unsigned R11B_AliasSet[] = { X86::R11W, X86::R11D, X86::R11, 0 };
+ const unsigned R11D_AliasSet[] = { X86::R11B, X86::R11W, X86::R11, 0 };
+ const unsigned R11W_AliasSet[] = { X86::R11B, X86::R11D, X86::R11, 0 };
+ const unsigned R12_AliasSet[] = { X86::R12B, X86::R12W, X86::R12D, 0 };
+ const unsigned R12B_AliasSet[] = { X86::R12W, X86::R12D, X86::R12, 0 };
+ const unsigned R12D_AliasSet[] = { X86::R12B, X86::R12W, X86::R12, 0 };
+ const unsigned R12W_AliasSet[] = { X86::R12B, X86::R12D, X86::R12, 0 };
+ const unsigned R13_AliasSet[] = { X86::R13B, X86::R13W, X86::R13D, 0 };
+ const unsigned R13B_AliasSet[] = { X86::R13W, X86::R13D, X86::R13, 0 };
+ const unsigned R13D_AliasSet[] = { X86::R13B, X86::R13W, X86::R13, 0 };
+ const unsigned R13W_AliasSet[] = { X86::R13B, X86::R13D, X86::R13, 0 };
+ const unsigned R14_AliasSet[] = { X86::R14B, X86::R14W, X86::R14D, 0 };
+ const unsigned R14B_AliasSet[] = { X86::R14W, X86::R14D, X86::R14, 0 };
+ const unsigned R14D_AliasSet[] = { X86::R14B, X86::R14W, X86::R14, 0 };
+ const unsigned R14W_AliasSet[] = { X86::R14B, X86::R14D, X86::R14, 0 };
+ const unsigned R15_AliasSet[] = { X86::R15B, X86::R15W, X86::R15D, 0 };
+ const unsigned R15B_AliasSet[] = { X86::R15W, X86::R15D, X86::R15, 0 };
+ const unsigned R15D_AliasSet[] = { X86::R15B, X86::R15W, X86::R15, 0 };
+ const unsigned R15W_AliasSet[] = { X86::R15B, X86::R15D, X86::R15, 0 };
+ const unsigned R8_AliasSet[] = { X86::R8B, X86::R8W, X86::R8D, 0 };
+ const unsigned R8B_AliasSet[] = { X86::R8W, X86::R8D, X86::R8, 0 };
+ const unsigned R8D_AliasSet[] = { X86::R8B, X86::R8W, X86::R8, 0 };
+ const unsigned R8W_AliasSet[] = { X86::R8B, X86::R8D, X86::R8, 0 };
+ const unsigned R9_AliasSet[] = { X86::R9B, X86::R9W, X86::R9D, 0 };
+ const unsigned R9B_AliasSet[] = { X86::R9W, X86::R9D, X86::R9, 0 };
+ const unsigned R9D_AliasSet[] = { X86::R9B, X86::R9W, X86::R9, 0 };
+ const unsigned R9W_AliasSet[] = { X86::R9B, X86::R9D, X86::R9, 0 };
+ const unsigned RAX_AliasSet[] = { X86::AL, X86::AH, X86::AX, X86::EAX, 0 };
+ const unsigned RBP_AliasSet[] = { X86::BPL, X86::BP, X86::EBP, 0 };
+ const unsigned RBX_AliasSet[] = { X86::BL, X86::BH, X86::BX, X86::EBX, 0 };
+ const unsigned RCX_AliasSet[] = { X86::CL, X86::CH, X86::CX, X86::ECX, 0 };
+ const unsigned RDI_AliasSet[] = { X86::DIL, X86::DI, X86::EDI, 0 };
+ const unsigned RDX_AliasSet[] = { X86::DL, X86::DH, X86::DX, X86::EDX, 0 };
+ const unsigned RIP_AliasSet[] = { X86::IP, X86::EIP, 0 };
+ const unsigned RSI_AliasSet[] = { X86::SIL, X86::SI, X86::ESI, 0 };
+ const unsigned RSP_AliasSet[] = { X86::SPL, X86::SP, X86::ESP, 0 };
+ const unsigned SI_AliasSet[] = { X86::SIL, X86::ESI, X86::RSI, 0 };
+ const unsigned SIL_AliasSet[] = { X86::SI, X86::ESI, X86::RSI, 0 };
+ const unsigned SP_AliasSet[] = { X86::SPL, X86::ESP, X86::RSP, 0 };
+ const unsigned SPL_AliasSet[] = { X86::SP, X86::ESP, X86::RSP, 0 };
+ const unsigned SS_AliasSet[] = { 0 };
+ const unsigned ST0_AliasSet[] = { 0 };
+ const unsigned ST1_AliasSet[] = { 0 };
+ const unsigned ST2_AliasSet[] = { 0 };
+ const unsigned ST3_AliasSet[] = { 0 };
+ const unsigned ST4_AliasSet[] = { 0 };
+ const unsigned ST5_AliasSet[] = { 0 };
+ const unsigned ST6_AliasSet[] = { 0 };
+ const unsigned ST7_AliasSet[] = { 0 };
+ const unsigned XMM0_AliasSet[] = { 0 };
+ const unsigned XMM1_AliasSet[] = { 0 };
+ const unsigned XMM10_AliasSet[] = { 0 };
+ const unsigned XMM11_AliasSet[] = { 0 };
+ const unsigned XMM12_AliasSet[] = { 0 };
+ const unsigned XMM13_AliasSet[] = { 0 };
+ const unsigned XMM14_AliasSet[] = { 0 };
+ const unsigned XMM15_AliasSet[] = { 0 };
+ const unsigned XMM2_AliasSet[] = { 0 };
+ const unsigned XMM3_AliasSet[] = { 0 };
+ const unsigned XMM4_AliasSet[] = { 0 };
+ const unsigned XMM5_AliasSet[] = { 0 };
+ const unsigned XMM6_AliasSet[] = { 0 };
+ const unsigned XMM7_AliasSet[] = { 0 };
+ const unsigned XMM8_AliasSet[] = { 0 };
+ const unsigned XMM9_AliasSet[] = { 0 };
+ const unsigned YMM0_AliasSet[] = { 0 };
+ const unsigned YMM1_AliasSet[] = { 0 };
+ const unsigned YMM10_AliasSet[] = { 0 };
+ const unsigned YMM11_AliasSet[] = { 0 };
+ const unsigned YMM12_AliasSet[] = { 0 };
+ const unsigned YMM13_AliasSet[] = { 0 };
+ const unsigned YMM14_AliasSet[] = { 0 };
+ const unsigned YMM15_AliasSet[] = { 0 };
+ const unsigned YMM2_AliasSet[] = { 0 };
+ const unsigned YMM3_AliasSet[] = { 0 };
+ const unsigned YMM4_AliasSet[] = { 0 };
+ const unsigned YMM5_AliasSet[] = { 0 };
+ const unsigned YMM6_AliasSet[] = { 0 };
+ const unsigned YMM7_AliasSet[] = { 0 };
+ const unsigned YMM8_AliasSet[] = { 0 };
+ const unsigned YMM9_AliasSet[] = { 0 };
+
+
+ // Register Sub-registers Sets...
+ const unsigned Empty_SubRegsSet[] = { 0 };
+ const unsigned AH_SubRegsSet[] = { 0 };
+ const unsigned AL_SubRegsSet[] = { 0 };
+ const unsigned AX_SubRegsSet[] = { X86::AL, X86::AH, 0 };
+ const unsigned BH_SubRegsSet[] = { 0 };
+ const unsigned BL_SubRegsSet[] = { 0 };
+ const unsigned BP_SubRegsSet[] = { X86::BPL, 0 };
+ const unsigned BPL_SubRegsSet[] = { 0 };
+ const unsigned BX_SubRegsSet[] = { X86::BL, X86::BH, 0 };
+ const unsigned CH_SubRegsSet[] = { 0 };
+ const unsigned CL_SubRegsSet[] = { 0 };
+ const unsigned CS_SubRegsSet[] = { 0 };
+ const unsigned CX_SubRegsSet[] = { X86::CL, X86::CH, 0 };
+ const unsigned DH_SubRegsSet[] = { 0 };
+ const unsigned DI_SubRegsSet[] = { X86::DIL, 0 };
+ const unsigned DIL_SubRegsSet[] = { 0 };
+ const unsigned DL_SubRegsSet[] = { 0 };
+ const unsigned DS_SubRegsSet[] = { 0 };
+ const unsigned DX_SubRegsSet[] = { X86::DL, X86::DH, 0 };
+ const unsigned EAX_SubRegsSet[] = { X86::AX, X86::AL, X86::AH, 0 };
+ const unsigned EBP_SubRegsSet[] = { X86::BP, X86::BPL, 0 };
+ const unsigned EBX_SubRegsSet[] = { X86::BX, X86::BL, X86::BH, 0 };
+ const unsigned ECX_SubRegsSet[] = { X86::CX, X86::CL, X86::CH, 0 };
+ const unsigned EDI_SubRegsSet[] = { X86::DI, X86::DIL, 0 };
+ const unsigned EDX_SubRegsSet[] = { X86::DX, X86::DL, X86::DH, 0 };
+ const unsigned EFLAGS_SubRegsSet[] = { 0 };
+ const unsigned EIP_SubRegsSet[] = { X86::IP, 0 };
+ const unsigned ES_SubRegsSet[] = { 0 };
+ const unsigned ESI_SubRegsSet[] = { X86::SI, X86::SIL, 0 };
+ const unsigned ESP_SubRegsSet[] = { X86::SP, X86::SPL, 0 };
+ const unsigned FP0_SubRegsSet[] = { 0 };
+ const unsigned FP1_SubRegsSet[] = { 0 };
+ const unsigned FP2_SubRegsSet[] = { 0 };
+ const unsigned FP3_SubRegsSet[] = { 0 };
+ const unsigned FP4_SubRegsSet[] = { 0 };
+ const unsigned FP5_SubRegsSet[] = { 0 };
+ const unsigned FP6_SubRegsSet[] = { 0 };
+ const unsigned FS_SubRegsSet[] = { 0 };
+ const unsigned GS_SubRegsSet[] = { 0 };
+ const unsigned IP_SubRegsSet[] = { 0 };
+ const unsigned MM0_SubRegsSet[] = { 0 };
+ const unsigned MM1_SubRegsSet[] = { 0 };
+ const unsigned MM2_SubRegsSet[] = { 0 };
+ const unsigned MM3_SubRegsSet[] = { 0 };
+ const unsigned MM4_SubRegsSet[] = { 0 };
+ const unsigned MM5_SubRegsSet[] = { 0 };
+ const unsigned MM6_SubRegsSet[] = { 0 };
+ const unsigned MM7_SubRegsSet[] = { 0 };
+ const unsigned R10_SubRegsSet[] = { X86::R10D, X86::R10W, X86::R10B, 0 };
+ const unsigned R10B_SubRegsSet[] = { 0 };
+ const unsigned R10D_SubRegsSet[] = { X86::R10W, X86::R10B, 0 };
+ const unsigned R10W_SubRegsSet[] = { X86::R10B, 0 };
+ const unsigned R11_SubRegsSet[] = { X86::R11D, X86::R11W, X86::R11B, 0 };
+ const unsigned R11B_SubRegsSet[] = { 0 };
+ const unsigned R11D_SubRegsSet[] = { X86::R11W, X86::R11B, 0 };
+ const unsigned R11W_SubRegsSet[] = { X86::R11B, 0 };
+ const unsigned R12_SubRegsSet[] = { X86::R12D, X86::R12W, X86::R12B, 0 };
+ const unsigned R12B_SubRegsSet[] = { 0 };
+ const unsigned R12D_SubRegsSet[] = { X86::R12W, X86::R12B, 0 };
+ const unsigned R12W_SubRegsSet[] = { X86::R12B, 0 };
+ const unsigned R13_SubRegsSet[] = { X86::R13D, X86::R13W, X86::R13B, 0 };
+ const unsigned R13B_SubRegsSet[] = { 0 };
+ const unsigned R13D_SubRegsSet[] = { X86::R13W, X86::R13B, 0 };
+ const unsigned R13W_SubRegsSet[] = { X86::R13B, 0 };
+ const unsigned R14_SubRegsSet[] = { X86::R14D, X86::R14W, X86::R14B, 0 };
+ const unsigned R14B_SubRegsSet[] = { 0 };
+ const unsigned R14D_SubRegsSet[] = { X86::R14W, X86::R14B, 0 };
+ const unsigned R14W_SubRegsSet[] = { X86::R14B, 0 };
+ const unsigned R15_SubRegsSet[] = { X86::R15D, X86::R15W, X86::R15B, 0 };
+ const unsigned R15B_SubRegsSet[] = { 0 };
+ const unsigned R15D_SubRegsSet[] = { X86::R15W, X86::R15B, 0 };
+ const unsigned R15W_SubRegsSet[] = { X86::R15B, 0 };
+ const unsigned R8_SubRegsSet[] = { X86::R8D, X86::R8W, X86::R8B, 0 };
+ const unsigned R8B_SubRegsSet[] = { 0 };
+ const unsigned R8D_SubRegsSet[] = { X86::R8W, X86::R8B, 0 };
+ const unsigned R8W_SubRegsSet[] = { X86::R8B, 0 };
+ const unsigned R9_SubRegsSet[] = { X86::R9D, X86::R9W, X86::R9B, 0 };
+ const unsigned R9B_SubRegsSet[] = { 0 };
+ const unsigned R9D_SubRegsSet[] = { X86::R9W, X86::R9B, 0 };
+ const unsigned R9W_SubRegsSet[] = { X86::R9B, 0 };
+ const unsigned RAX_SubRegsSet[] = { X86::EAX, X86::AX, X86::AL, X86::AH, 0 };
+ const unsigned RBP_SubRegsSet[] = { X86::EBP, X86::BP, X86::BPL, 0 };
+ const unsigned RBX_SubRegsSet[] = { X86::EBX, X86::BX, X86::BL, X86::BH, 0 };
+ const unsigned RCX_SubRegsSet[] = { X86::ECX, X86::CX, X86::CL, X86::CH, 0 };
+ const unsigned RDI_SubRegsSet[] = { X86::EDI, X86::DI, X86::DIL, 0 };
+ const unsigned RDX_SubRegsSet[] = { X86::EDX, X86::DX, X86::DL, X86::DH, 0 };
+ const unsigned RIP_SubRegsSet[] = { X86::EIP, X86::IP, 0 };
+ const unsigned RSI_SubRegsSet[] = { X86::ESI, X86::SI, X86::SIL, 0 };
+ const unsigned RSP_SubRegsSet[] = { X86::ESP, X86::SP, X86::SPL, 0 };
+ const unsigned SI_SubRegsSet[] = { X86::SIL, 0 };
+ const unsigned SIL_SubRegsSet[] = { 0 };
+ const unsigned SP_SubRegsSet[] = { X86::SPL, 0 };
+ const unsigned SPL_SubRegsSet[] = { 0 };
+ const unsigned SS_SubRegsSet[] = { 0 };
+ const unsigned ST0_SubRegsSet[] = { 0 };
+ const unsigned ST1_SubRegsSet[] = { 0 };
+ const unsigned ST2_SubRegsSet[] = { 0 };
+ const unsigned ST3_SubRegsSet[] = { 0 };
+ const unsigned ST4_SubRegsSet[] = { 0 };
+ const unsigned ST5_SubRegsSet[] = { 0 };
+ const unsigned ST6_SubRegsSet[] = { 0 };
+ const unsigned ST7_SubRegsSet[] = { 0 };
+ const unsigned XMM0_SubRegsSet[] = { 0 };
+ const unsigned XMM1_SubRegsSet[] = { 0 };
+ const unsigned XMM10_SubRegsSet[] = { 0 };
+ const unsigned XMM11_SubRegsSet[] = { 0 };
+ const unsigned XMM12_SubRegsSet[] = { 0 };
+ const unsigned XMM13_SubRegsSet[] = { 0 };
+ const unsigned XMM14_SubRegsSet[] = { 0 };
+ const unsigned XMM15_SubRegsSet[] = { 0 };
+ const unsigned XMM2_SubRegsSet[] = { 0 };
+ const unsigned XMM3_SubRegsSet[] = { 0 };
+ const unsigned XMM4_SubRegsSet[] = { 0 };
+ const unsigned XMM5_SubRegsSet[] = { 0 };
+ const unsigned XMM6_SubRegsSet[] = { 0 };
+ const unsigned XMM7_SubRegsSet[] = { 0 };
+ const unsigned XMM8_SubRegsSet[] = { 0 };
+ const unsigned XMM9_SubRegsSet[] = { 0 };
+ const unsigned YMM0_SubRegsSet[] = { 0 };
+ const unsigned YMM1_SubRegsSet[] = { 0 };
+ const unsigned YMM10_SubRegsSet[] = { 0 };
+ const unsigned YMM11_SubRegsSet[] = { 0 };
+ const unsigned YMM12_SubRegsSet[] = { 0 };
+ const unsigned YMM13_SubRegsSet[] = { 0 };
+ const unsigned YMM14_SubRegsSet[] = { 0 };
+ const unsigned YMM15_SubRegsSet[] = { 0 };
+ const unsigned YMM2_SubRegsSet[] = { 0 };
+ const unsigned YMM3_SubRegsSet[] = { 0 };
+ const unsigned YMM4_SubRegsSet[] = { 0 };
+ const unsigned YMM5_SubRegsSet[] = { 0 };
+ const unsigned YMM6_SubRegsSet[] = { 0 };
+ const unsigned YMM7_SubRegsSet[] = { 0 };
+ const unsigned YMM8_SubRegsSet[] = { 0 };
+ const unsigned YMM9_SubRegsSet[] = { 0 };
+
+
+ // Register Super-registers Sets...
+ const unsigned Empty_SuperRegsSet[] = { 0 };
+ const unsigned AH_SuperRegsSet[] = { X86::RAX, X86::EAX, X86::AX, 0 };
+ const unsigned AL_SuperRegsSet[] = { X86::RAX, X86::EAX, X86::AX, 0 };
+ const unsigned AX_SuperRegsSet[] = { X86::RAX, X86::EAX, 0 };
+ const unsigned BH_SuperRegsSet[] = { X86::RBX, X86::EBX, X86::BX, 0 };
+ const unsigned BL_SuperRegsSet[] = { X86::RBX, X86::EBX, X86::BX, 0 };
+ const unsigned BP_SuperRegsSet[] = { X86::RBP, X86::EBP, 0 };
+ const unsigned BPL_SuperRegsSet[] = { X86::RBP, X86::EBP, X86::BP, 0 };
+ const unsigned BX_SuperRegsSet[] = { X86::RBX, X86::EBX, 0 };
+ const unsigned CH_SuperRegsSet[] = { X86::RCX, X86::ECX, X86::CX, 0 };
+ const unsigned CL_SuperRegsSet[] = { X86::RCX, X86::ECX, X86::CX, 0 };
+ const unsigned CS_SuperRegsSet[] = { 0 };
+ const unsigned CX_SuperRegsSet[] = { X86::RCX, X86::ECX, 0 };
+ const unsigned DH_SuperRegsSet[] = { X86::RDX, X86::EDX, X86::DX, 0 };
+ const unsigned DI_SuperRegsSet[] = { X86::RDI, X86::EDI, 0 };
+ const unsigned DIL_SuperRegsSet[] = { X86::RDI, X86::EDI, X86::DI, 0 };
+ const unsigned DL_SuperRegsSet[] = { X86::RDX, X86::EDX, X86::DX, 0 };
+ const unsigned DS_SuperRegsSet[] = { 0 };
+ const unsigned DX_SuperRegsSet[] = { X86::RDX, X86::EDX, 0 };
+ const unsigned EAX_SuperRegsSet[] = { X86::RAX, 0 };
+ const unsigned EBP_SuperRegsSet[] = { X86::RBP, 0 };
+ const unsigned EBX_SuperRegsSet[] = { X86::RBX, 0 };
+ const unsigned ECX_SuperRegsSet[] = { X86::RCX, 0 };
+ const unsigned EDI_SuperRegsSet[] = { X86::RDI, 0 };
+ const unsigned EDX_SuperRegsSet[] = { X86::RDX, 0 };
+ const unsigned EFLAGS_SuperRegsSet[] = { 0 };
+ const unsigned EIP_SuperRegsSet[] = { X86::RIP, 0 };
+ const unsigned ES_SuperRegsSet[] = { 0 };
+ const unsigned ESI_SuperRegsSet[] = { X86::RSI, 0 };
+ const unsigned ESP_SuperRegsSet[] = { X86::RSP, 0 };
+ const unsigned FP0_SuperRegsSet[] = { 0 };
+ const unsigned FP1_SuperRegsSet[] = { 0 };
+ const unsigned FP2_SuperRegsSet[] = { 0 };
+ const unsigned FP3_SuperRegsSet[] = { 0 };
+ const unsigned FP4_SuperRegsSet[] = { 0 };
+ const unsigned FP5_SuperRegsSet[] = { 0 };
+ const unsigned FP6_SuperRegsSet[] = { 0 };
+ const unsigned FS_SuperRegsSet[] = { 0 };
+ const unsigned GS_SuperRegsSet[] = { 0 };
+ const unsigned IP_SuperRegsSet[] = { X86::RIP, X86::EIP, 0 };
+ const unsigned MM0_SuperRegsSet[] = { 0 };
+ const unsigned MM1_SuperRegsSet[] = { 0 };
+ const unsigned MM2_SuperRegsSet[] = { 0 };
+ const unsigned MM3_SuperRegsSet[] = { 0 };
+ const unsigned MM4_SuperRegsSet[] = { 0 };
+ const unsigned MM5_SuperRegsSet[] = { 0 };
+ const unsigned MM6_SuperRegsSet[] = { 0 };
+ const unsigned MM7_SuperRegsSet[] = { 0 };
+ const unsigned R10_SuperRegsSet[] = { 0 };
+ const unsigned R10B_SuperRegsSet[] = { X86::R10, X86::R10D, X86::R10W, 0 };
+ const unsigned R10D_SuperRegsSet[] = { X86::R10, 0 };
+ const unsigned R10W_SuperRegsSet[] = { X86::R10, X86::R10D, 0 };
+ const unsigned R11_SuperRegsSet[] = { 0 };
+ const unsigned R11B_SuperRegsSet[] = { X86::R11, X86::R11D, X86::R11W, 0 };
+ const unsigned R11D_SuperRegsSet[] = { X86::R11, 0 };
+ const unsigned R11W_SuperRegsSet[] = { X86::R11, X86::R11D, 0 };
+ const unsigned R12_SuperRegsSet[] = { 0 };
+ const unsigned R12B_SuperRegsSet[] = { X86::R12, X86::R12D, X86::R12W, 0 };
+ const unsigned R12D_SuperRegsSet[] = { X86::R12, 0 };
+ const unsigned R12W_SuperRegsSet[] = { X86::R12, X86::R12D, 0 };
+ const unsigned R13_SuperRegsSet[] = { 0 };
+ const unsigned R13B_SuperRegsSet[] = { X86::R13, X86::R13D, X86::R13W, 0 };
+ const unsigned R13D_SuperRegsSet[] = { X86::R13, 0 };
+ const unsigned R13W_SuperRegsSet[] = { X86::R13, X86::R13D, 0 };
+ const unsigned R14_SuperRegsSet[] = { 0 };
+ const unsigned R14B_SuperRegsSet[] = { X86::R14, X86::R14D, X86::R14W, 0 };
+ const unsigned R14D_SuperRegsSet[] = { X86::R14, 0 };
+ const unsigned R14W_SuperRegsSet[] = { X86::R14, X86::R14D, 0 };
+ const unsigned R15_SuperRegsSet[] = { 0 };
+ const unsigned R15B_SuperRegsSet[] = { X86::R15, X86::R15D, X86::R15W, 0 };
+ const unsigned R15D_SuperRegsSet[] = { X86::R15, 0 };
+ const unsigned R15W_SuperRegsSet[] = { X86::R15, X86::R15D, 0 };
+ const unsigned R8_SuperRegsSet[] = { 0 };
+ const unsigned R8B_SuperRegsSet[] = { X86::R8, X86::R8D, X86::R8W, 0 };
+ const unsigned R8D_SuperRegsSet[] = { X86::R8, 0 };
+ const unsigned R8W_SuperRegsSet[] = { X86::R8, X86::R8D, 0 };
+ const unsigned R9_SuperRegsSet[] = { 0 };
+ const unsigned R9B_SuperRegsSet[] = { X86::R9, X86::R9D, X86::R9W, 0 };
+ const unsigned R9D_SuperRegsSet[] = { X86::R9, 0 };
+ const unsigned R9W_SuperRegsSet[] = { X86::R9, X86::R9D, 0 };
+ const unsigned RAX_SuperRegsSet[] = { 0 };
+ const unsigned RBP_SuperRegsSet[] = { 0 };
+ const unsigned RBX_SuperRegsSet[] = { 0 };
+ const unsigned RCX_SuperRegsSet[] = { 0 };
+ const unsigned RDI_SuperRegsSet[] = { 0 };
+ const unsigned RDX_SuperRegsSet[] = { 0 };
+ const unsigned RIP_SuperRegsSet[] = { 0 };
+ const unsigned RSI_SuperRegsSet[] = { 0 };
+ const unsigned RSP_SuperRegsSet[] = { 0 };
+ const unsigned SI_SuperRegsSet[] = { X86::RSI, X86::ESI, 0 };
+ const unsigned SIL_SuperRegsSet[] = { X86::RSI, X86::ESI, X86::SI, 0 };
+ const unsigned SP_SuperRegsSet[] = { X86::RSP, X86::ESP, 0 };
+ const unsigned SPL_SuperRegsSet[] = { X86::RSP, X86::ESP, X86::SP, 0 };
+ const unsigned SS_SuperRegsSet[] = { 0 };
+ const unsigned ST0_SuperRegsSet[] = { 0 };
+ const unsigned ST1_SuperRegsSet[] = { 0 };
+ const unsigned ST2_SuperRegsSet[] = { 0 };
+ const unsigned ST3_SuperRegsSet[] = { 0 };
+ const unsigned ST4_SuperRegsSet[] = { 0 };
+ const unsigned ST5_SuperRegsSet[] = { 0 };
+ const unsigned ST6_SuperRegsSet[] = { 0 };
+ const unsigned ST7_SuperRegsSet[] = { 0 };
+ const unsigned XMM0_SuperRegsSet[] = { 0 };
+ const unsigned XMM1_SuperRegsSet[] = { 0 };
+ const unsigned XMM10_SuperRegsSet[] = { 0 };
+ const unsigned XMM11_SuperRegsSet[] = { 0 };
+ const unsigned XMM12_SuperRegsSet[] = { 0 };
+ const unsigned XMM13_SuperRegsSet[] = { 0 };
+ const unsigned XMM14_SuperRegsSet[] = { 0 };
+ const unsigned XMM15_SuperRegsSet[] = { 0 };
+ const unsigned XMM2_SuperRegsSet[] = { 0 };
+ const unsigned XMM3_SuperRegsSet[] = { 0 };
+ const unsigned XMM4_SuperRegsSet[] = { 0 };
+ const unsigned XMM5_SuperRegsSet[] = { 0 };
+ const unsigned XMM6_SuperRegsSet[] = { 0 };
+ const unsigned XMM7_SuperRegsSet[] = { 0 };
+ const unsigned XMM8_SuperRegsSet[] = { 0 };
+ const unsigned XMM9_SuperRegsSet[] = { 0 };
+ const unsigned YMM0_SuperRegsSet[] = { 0 };
+ const unsigned YMM1_SuperRegsSet[] = { 0 };
+ const unsigned YMM10_SuperRegsSet[] = { 0 };
+ const unsigned YMM11_SuperRegsSet[] = { 0 };
+ const unsigned YMM12_SuperRegsSet[] = { 0 };
+ const unsigned YMM13_SuperRegsSet[] = { 0 };
+ const unsigned YMM14_SuperRegsSet[] = { 0 };
+ const unsigned YMM15_SuperRegsSet[] = { 0 };
+ const unsigned YMM2_SuperRegsSet[] = { 0 };
+ const unsigned YMM3_SuperRegsSet[] = { 0 };
+ const unsigned YMM4_SuperRegsSet[] = { 0 };
+ const unsigned YMM5_SuperRegsSet[] = { 0 };
+ const unsigned YMM6_SuperRegsSet[] = { 0 };
+ const unsigned YMM7_SuperRegsSet[] = { 0 };
+ const unsigned YMM8_SuperRegsSet[] = { 0 };
+ const unsigned YMM9_SuperRegsSet[] = { 0 };
+
+ const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors
+ { "NOREG", 0, 0, 0 },
+ { "AH", AH_AliasSet, AH_SubRegsSet, AH_SuperRegsSet },
+ { "AL", AL_AliasSet, AL_SubRegsSet, AL_SuperRegsSet },
+ { "AX", AX_AliasSet, AX_SubRegsSet, AX_SuperRegsSet },
+ { "BH", BH_AliasSet, BH_SubRegsSet, BH_SuperRegsSet },
+ { "BL", BL_AliasSet, BL_SubRegsSet, BL_SuperRegsSet },
+ { "BP", BP_AliasSet, BP_SubRegsSet, BP_SuperRegsSet },
+ { "BPL", BPL_AliasSet, BPL_SubRegsSet, BPL_SuperRegsSet },
+ { "BX", BX_AliasSet, BX_SubRegsSet, BX_SuperRegsSet },
+ { "CH", CH_AliasSet, CH_SubRegsSet, CH_SuperRegsSet },
+ { "CL", CL_AliasSet, CL_SubRegsSet, CL_SuperRegsSet },
+ { "CS", CS_AliasSet, CS_SubRegsSet, CS_SuperRegsSet },
+ { "CX", CX_AliasSet, CX_SubRegsSet, CX_SuperRegsSet },
+ { "DH", DH_AliasSet, DH_SubRegsSet, DH_SuperRegsSet },
+ { "DI", DI_AliasSet, DI_SubRegsSet, DI_SuperRegsSet },
+ { "DIL", DIL_AliasSet, DIL_SubRegsSet, DIL_SuperRegsSet },
+ { "DL", DL_AliasSet, DL_SubRegsSet, DL_SuperRegsSet },
+ { "DS", DS_AliasSet, DS_SubRegsSet, DS_SuperRegsSet },
+ { "DX", DX_AliasSet, DX_SubRegsSet, DX_SuperRegsSet },
+ { "EAX", EAX_AliasSet, EAX_SubRegsSet, EAX_SuperRegsSet },
+ { "EBP", EBP_AliasSet, EBP_SubRegsSet, EBP_SuperRegsSet },
+ { "EBX", EBX_AliasSet, EBX_SubRegsSet, EBX_SuperRegsSet },
+ { "ECX", ECX_AliasSet, ECX_SubRegsSet, ECX_SuperRegsSet },
+ { "EDI", EDI_AliasSet, EDI_SubRegsSet, EDI_SuperRegsSet },
+ { "EDX", EDX_AliasSet, EDX_SubRegsSet, EDX_SuperRegsSet },
+ { "EFLAGS", EFLAGS_AliasSet, EFLAGS_SubRegsSet, EFLAGS_SuperRegsSet },
+ { "EIP", EIP_AliasSet, EIP_SubRegsSet, EIP_SuperRegsSet },
+ { "ES", ES_AliasSet, ES_SubRegsSet, ES_SuperRegsSet },
+ { "ESI", ESI_AliasSet, ESI_SubRegsSet, ESI_SuperRegsSet },
+ { "ESP", ESP_AliasSet, ESP_SubRegsSet, ESP_SuperRegsSet },
+ { "FP0", FP0_AliasSet, FP0_SubRegsSet, FP0_SuperRegsSet },
+ { "FP1", FP1_AliasSet, FP1_SubRegsSet, FP1_SuperRegsSet },
+ { "FP2", FP2_AliasSet, FP2_SubRegsSet, FP2_SuperRegsSet },
+ { "FP3", FP3_AliasSet, FP3_SubRegsSet, FP3_SuperRegsSet },
+ { "FP4", FP4_AliasSet, FP4_SubRegsSet, FP4_SuperRegsSet },
+ { "FP5", FP5_AliasSet, FP5_SubRegsSet, FP5_SuperRegsSet },
+ { "FP6", FP6_AliasSet, FP6_SubRegsSet, FP6_SuperRegsSet },
+ { "FS", FS_AliasSet, FS_SubRegsSet, FS_SuperRegsSet },
+ { "GS", GS_AliasSet, GS_SubRegsSet, GS_SuperRegsSet },
+ { "IP", IP_AliasSet, IP_SubRegsSet, IP_SuperRegsSet },
+ { "MM0", MM0_AliasSet, MM0_SubRegsSet, MM0_SuperRegsSet },
+ { "MM1", MM1_AliasSet, MM1_SubRegsSet, MM1_SuperRegsSet },
+ { "MM2", MM2_AliasSet, MM2_SubRegsSet, MM2_SuperRegsSet },
+ { "MM3", MM3_AliasSet, MM3_SubRegsSet, MM3_SuperRegsSet },
+ { "MM4", MM4_AliasSet, MM4_SubRegsSet, MM4_SuperRegsSet },
+ { "MM5", MM5_AliasSet, MM5_SubRegsSet, MM5_SuperRegsSet },
+ { "MM6", MM6_AliasSet, MM6_SubRegsSet, MM6_SuperRegsSet },
+ { "MM7", MM7_AliasSet, MM7_SubRegsSet, MM7_SuperRegsSet },
+ { "R10", R10_AliasSet, R10_SubRegsSet, R10_SuperRegsSet },
+ { "R10B", R10B_AliasSet, R10B_SubRegsSet, R10B_SuperRegsSet },
+ { "R10D", R10D_AliasSet, R10D_SubRegsSet, R10D_SuperRegsSet },
+ { "R10W", R10W_AliasSet, R10W_SubRegsSet, R10W_SuperRegsSet },
+ { "R11", R11_AliasSet, R11_SubRegsSet, R11_SuperRegsSet },
+ { "R11B", R11B_AliasSet, R11B_SubRegsSet, R11B_SuperRegsSet },
+ { "R11D", R11D_AliasSet, R11D_SubRegsSet, R11D_SuperRegsSet },
+ { "R11W", R11W_AliasSet, R11W_SubRegsSet, R11W_SuperRegsSet },
+ { "R12", R12_AliasSet, R12_SubRegsSet, R12_SuperRegsSet },
+ { "R12B", R12B_AliasSet, R12B_SubRegsSet, R12B_SuperRegsSet },
+ { "R12D", R12D_AliasSet, R12D_SubRegsSet, R12D_SuperRegsSet },
+ { "R12W", R12W_AliasSet, R12W_SubRegsSet, R12W_SuperRegsSet },
+ { "R13", R13_AliasSet, R13_SubRegsSet, R13_SuperRegsSet },
+ { "R13B", R13B_AliasSet, R13B_SubRegsSet, R13B_SuperRegsSet },
+ { "R13D", R13D_AliasSet, R13D_SubRegsSet, R13D_SuperRegsSet },
+ { "R13W", R13W_AliasSet, R13W_SubRegsSet, R13W_SuperRegsSet },
+ { "R14", R14_AliasSet, R14_SubRegsSet, R14_SuperRegsSet },
+ { "R14B", R14B_AliasSet, R14B_SubRegsSet, R14B_SuperRegsSet },
+ { "R14D", R14D_AliasSet, R14D_SubRegsSet, R14D_SuperRegsSet },
+ { "R14W", R14W_AliasSet, R14W_SubRegsSet, R14W_SuperRegsSet },
+ { "R15", R15_AliasSet, R15_SubRegsSet, R15_SuperRegsSet },
+ { "R15B", R15B_AliasSet, R15B_SubRegsSet, R15B_SuperRegsSet },
+ { "R15D", R15D_AliasSet, R15D_SubRegsSet, R15D_SuperRegsSet },
+ { "R15W", R15W_AliasSet, R15W_SubRegsSet, R15W_SuperRegsSet },
+ { "R8", R8_AliasSet, R8_SubRegsSet, R8_SuperRegsSet },
+ { "R8B", R8B_AliasSet, R8B_SubRegsSet, R8B_SuperRegsSet },
+ { "R8D", R8D_AliasSet, R8D_SubRegsSet, R8D_SuperRegsSet },
+ { "R8W", R8W_AliasSet, R8W_SubRegsSet, R8W_SuperRegsSet },
+ { "R9", R9_AliasSet, R9_SubRegsSet, R9_SuperRegsSet },
+ { "R9B", R9B_AliasSet, R9B_SubRegsSet, R9B_SuperRegsSet },
+ { "R9D", R9D_AliasSet, R9D_SubRegsSet, R9D_SuperRegsSet },
+ { "R9W", R9W_AliasSet, R9W_SubRegsSet, R9W_SuperRegsSet },
+ { "RAX", RAX_AliasSet, RAX_SubRegsSet, RAX_SuperRegsSet },
+ { "RBP", RBP_AliasSet, RBP_SubRegsSet, RBP_SuperRegsSet },
+ { "RBX", RBX_AliasSet, RBX_SubRegsSet, RBX_SuperRegsSet },
+ { "RCX", RCX_AliasSet, RCX_SubRegsSet, RCX_SuperRegsSet },
+ { "RDI", RDI_AliasSet, RDI_SubRegsSet, RDI_SuperRegsSet },
+ { "RDX", RDX_AliasSet, RDX_SubRegsSet, RDX_SuperRegsSet },
+ { "RIP", RIP_AliasSet, RIP_SubRegsSet, RIP_SuperRegsSet },
+ { "RSI", RSI_AliasSet, RSI_SubRegsSet, RSI_SuperRegsSet },
+ { "RSP", RSP_AliasSet, RSP_SubRegsSet, RSP_SuperRegsSet },
+ { "SI", SI_AliasSet, SI_SubRegsSet, SI_SuperRegsSet },
+ { "SIL", SIL_AliasSet, SIL_SubRegsSet, SIL_SuperRegsSet },
+ { "SP", SP_AliasSet, SP_SubRegsSet, SP_SuperRegsSet },
+ { "SPL", SPL_AliasSet, SPL_SubRegsSet, SPL_SuperRegsSet },
+ { "SS", SS_AliasSet, SS_SubRegsSet, SS_SuperRegsSet },
+ { "ST0", ST0_AliasSet, ST0_SubRegsSet, ST0_SuperRegsSet },
+ { "ST1", ST1_AliasSet, ST1_SubRegsSet, ST1_SuperRegsSet },
+ { "ST2", ST2_AliasSet, ST2_SubRegsSet, ST2_SuperRegsSet },
+ { "ST3", ST3_AliasSet, ST3_SubRegsSet, ST3_SuperRegsSet },
+ { "ST4", ST4_AliasSet, ST4_SubRegsSet, ST4_SuperRegsSet },
+ { "ST5", ST5_AliasSet, ST5_SubRegsSet, ST5_SuperRegsSet },
+ { "ST6", ST6_AliasSet, ST6_SubRegsSet, ST6_SuperRegsSet },
+ { "ST7", ST7_AliasSet, ST7_SubRegsSet, ST7_SuperRegsSet },
+ { "XMM0", XMM0_AliasSet, XMM0_SubRegsSet, XMM0_SuperRegsSet },
+ { "XMM1", XMM1_AliasSet, XMM1_SubRegsSet, XMM1_SuperRegsSet },
+ { "XMM10", XMM10_AliasSet, XMM10_SubRegsSet, XMM10_SuperRegsSet },
+ { "XMM11", XMM11_AliasSet, XMM11_SubRegsSet, XMM11_SuperRegsSet },
+ { "XMM12", XMM12_AliasSet, XMM12_SubRegsSet, XMM12_SuperRegsSet },
+ { "XMM13", XMM13_AliasSet, XMM13_SubRegsSet, XMM13_SuperRegsSet },
+ { "XMM14", XMM14_AliasSet, XMM14_SubRegsSet, XMM14_SuperRegsSet },
+ { "XMM15", XMM15_AliasSet, XMM15_SubRegsSet, XMM15_SuperRegsSet },
+ { "XMM2", XMM2_AliasSet, XMM2_SubRegsSet, XMM2_SuperRegsSet },
+ { "XMM3", XMM3_AliasSet, XMM3_SubRegsSet, XMM3_SuperRegsSet },
+ { "XMM4", XMM4_AliasSet, XMM4_SubRegsSet, XMM4_SuperRegsSet },
+ { "XMM5", XMM5_AliasSet, XMM5_SubRegsSet, XMM5_SuperRegsSet },
+ { "XMM6", XMM6_AliasSet, XMM6_SubRegsSet, XMM6_SuperRegsSet },
+ { "XMM7", XMM7_AliasSet, XMM7_SubRegsSet, XMM7_SuperRegsSet },
+ { "XMM8", XMM8_AliasSet, XMM8_SubRegsSet, XMM8_SuperRegsSet },
+ { "XMM9", XMM9_AliasSet, XMM9_SubRegsSet, XMM9_SuperRegsSet },
+ { "YMM0", YMM0_AliasSet, YMM0_SubRegsSet, YMM0_SuperRegsSet },
+ { "YMM1", YMM1_AliasSet, YMM1_SubRegsSet, YMM1_SuperRegsSet },
+ { "YMM10", YMM10_AliasSet, YMM10_SubRegsSet, YMM10_SuperRegsSet },
+ { "YMM11", YMM11_AliasSet, YMM11_SubRegsSet, YMM11_SuperRegsSet },
+ { "YMM12", YMM12_AliasSet, YMM12_SubRegsSet, YMM12_SuperRegsSet },
+ { "YMM13", YMM13_AliasSet, YMM13_SubRegsSet, YMM13_SuperRegsSet },
+ { "YMM14", YMM14_AliasSet, YMM14_SubRegsSet, YMM14_SuperRegsSet },
+ { "YMM15", YMM15_AliasSet, YMM15_SubRegsSet, YMM15_SuperRegsSet },
+ { "YMM2", YMM2_AliasSet, YMM2_SubRegsSet, YMM2_SuperRegsSet },
+ { "YMM3", YMM3_AliasSet, YMM3_SubRegsSet, YMM3_SuperRegsSet },
+ { "YMM4", YMM4_AliasSet, YMM4_SubRegsSet, YMM4_SuperRegsSet },
+ { "YMM5", YMM5_AliasSet, YMM5_SubRegsSet, YMM5_SuperRegsSet },
+ { "YMM6", YMM6_AliasSet, YMM6_SubRegsSet, YMM6_SuperRegsSet },
+ { "YMM7", YMM7_AliasSet, YMM7_SubRegsSet, YMM7_SuperRegsSet },
+ { "YMM8", YMM8_AliasSet, YMM8_SubRegsSet, YMM8_SuperRegsSet },
+ { "YMM9", YMM9_AliasSet, YMM9_SubRegsSet, YMM9_SuperRegsSet },
+ };
+}
+
+unsigned X86GenRegisterInfo::getSubReg(unsigned RegNo, unsigned Index) const {
+ switch (RegNo) {
+ default:
+ return 0;
+ case X86::AX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::AL;
+ case 2: return X86::AH;
+ };
+ break;
+ case X86::DX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::DL;
+ case 2: return X86::DH;
+ };
+ break;
+ case X86::CX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::CL;
+ case 2: return X86::CH;
+ };
+ break;
+ case X86::BX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::BL;
+ case 2: return X86::BH;
+ };
+ break;
+ case X86::SI:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::SIL;
+ };
+ break;
+ case X86::DI:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::DIL;
+ };
+ break;
+ case X86::BP:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::BPL;
+ };
+ break;
+ case X86::SP:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::SPL;
+ };
+ break;
+ case X86::R8W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R8B;
+ };
+ break;
+ case X86::R9W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R9B;
+ };
+ break;
+ case X86::R10W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R10B;
+ };
+ break;
+ case X86::R11W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R11B;
+ };
+ break;
+ case X86::R12W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R12B;
+ };
+ break;
+ case X86::R13W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R13B;
+ };
+ break;
+ case X86::R14W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R14B;
+ };
+ break;
+ case X86::R15W:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R15B;
+ };
+ break;
+ case X86::EAX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::AL;
+ case 2: return X86::AH;
+ case 3: return X86::AX;
+ };
+ break;
+ case X86::EDX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::DL;
+ case 2: return X86::DH;
+ case 3: return X86::DX;
+ };
+ break;
+ case X86::ECX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::CL;
+ case 2: return X86::CH;
+ case 3: return X86::CX;
+ };
+ break;
+ case X86::EBX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::BL;
+ case 2: return X86::BH;
+ case 3: return X86::BX;
+ };
+ break;
+ case X86::ESI:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::SIL;
+ case 3: return X86::SI;
+ };
+ break;
+ case X86::EDI:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::DIL;
+ case 3: return X86::DI;
+ };
+ break;
+ case X86::EBP:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::BPL;
+ case 3: return X86::BP;
+ };
+ break;
+ case X86::ESP:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::SPL;
+ case 3: return X86::SP;
+ };
+ break;
+ case X86::R8D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R8B;
+ case 3: return X86::R8W;
+ };
+ break;
+ case X86::R9D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R9B;
+ case 3: return X86::R9W;
+ };
+ break;
+ case X86::R10D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R10B;
+ case 3: return X86::R10W;
+ };
+ break;
+ case X86::R11D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R11B;
+ case 3: return X86::R11W;
+ };
+ break;
+ case X86::R12D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R12B;
+ case 3: return X86::R12W;
+ };
+ break;
+ case X86::R13D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R13B;
+ case 3: return X86::R13W;
+ };
+ break;
+ case X86::R14D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R14B;
+ case 3: return X86::R14W;
+ };
+ break;
+ case X86::R15D:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R15B;
+ case 3: return X86::R15W;
+ };
+ break;
+ case X86::RAX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::AL;
+ case 2: return X86::AH;
+ case 3: return X86::AX;
+ case 4: return X86::EAX;
+ };
+ break;
+ case X86::RDX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::DL;
+ case 2: return X86::DH;
+ case 3: return X86::DX;
+ case 4: return X86::EDX;
+ };
+ break;
+ case X86::RCX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::CL;
+ case 2: return X86::CH;
+ case 3: return X86::CX;
+ case 4: return X86::ECX;
+ };
+ break;
+ case X86::RBX:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::BL;
+ case 2: return X86::BH;
+ case 3: return X86::BX;
+ case 4: return X86::EBX;
+ };
+ break;
+ case X86::RSI:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::SIL;
+ case 3: return X86::SI;
+ case 4: return X86::ESI;
+ };
+ break;
+ case X86::RDI:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::DIL;
+ case 3: return X86::DI;
+ case 4: return X86::EDI;
+ };
+ break;
+ case X86::RBP:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::BPL;
+ case 3: return X86::BP;
+ case 4: return X86::EBP;
+ };
+ break;
+ case X86::RSP:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::SPL;
+ case 3: return X86::SP;
+ case 4: return X86::ESP;
+ };
+ break;
+ case X86::R8:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R8B;
+ case 3: return X86::R8W;
+ case 4: return X86::R8D;
+ };
+ break;
+ case X86::R9:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R9B;
+ case 3: return X86::R9W;
+ case 4: return X86::R9D;
+ };
+ break;
+ case X86::R10:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R10B;
+ case 3: return X86::R10W;
+ case 4: return X86::R10D;
+ };
+ break;
+ case X86::R11:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R11B;
+ case 3: return X86::R11W;
+ case 4: return X86::R11D;
+ };
+ break;
+ case X86::R12:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R12B;
+ case 3: return X86::R12W;
+ case 4: return X86::R12D;
+ };
+ break;
+ case X86::R13:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R13B;
+ case 3: return X86::R13W;
+ case 4: return X86::R13D;
+ };
+ break;
+ case X86::R14:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R14B;
+ case 3: return X86::R14W;
+ case 4: return X86::R14D;
+ };
+ break;
+ case X86::R15:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::R15B;
+ case 3: return X86::R15W;
+ case 4: return X86::R15D;
+ };
+ break;
+ case X86::YMM0:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM0;
+ };
+ break;
+ case X86::YMM1:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM1;
+ };
+ break;
+ case X86::YMM2:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM2;
+ };
+ break;
+ case X86::YMM3:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM3;
+ };
+ break;
+ case X86::YMM4:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM4;
+ };
+ break;
+ case X86::YMM5:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM5;
+ };
+ break;
+ case X86::YMM6:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM6;
+ };
+ break;
+ case X86::YMM7:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM7;
+ };
+ break;
+ case X86::YMM8:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM8;
+ };
+ break;
+ case X86::YMM9:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM9;
+ };
+ break;
+ case X86::YMM10:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM10;
+ };
+ break;
+ case X86::YMM11:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM11;
+ };
+ break;
+ case X86::YMM12:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM12;
+ };
+ break;
+ case X86::YMM13:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM13;
+ };
+ break;
+ case X86::YMM14:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM14;
+ };
+ break;
+ case X86::YMM15:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM15;
+ };
+ break;
+ };
+ return 0;
+}
+
+unsigned X86GenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
+ switch (RegNo) {
+ default:
+ return 0;
+ case X86::AX:
+ if (SubRegNo == X86::AL) return 1;
+ if (SubRegNo == X86::AH) return 2;
+ return 0;
+ case X86::DX:
+ if (SubRegNo == X86::DL) return 1;
+ if (SubRegNo == X86::DH) return 2;
+ return 0;
+ case X86::CX:
+ if (SubRegNo == X86::CL) return 1;
+ if (SubRegNo == X86::CH) return 2;
+ return 0;
+ case X86::BX:
+ if (SubRegNo == X86::BL) return 1;
+ if (SubRegNo == X86::BH) return 2;
+ return 0;
+ case X86::SI:
+ if (SubRegNo == X86::SIL) return 1;
+ return 0;
+ case X86::DI:
+ if (SubRegNo == X86::DIL) return 1;
+ return 0;
+ case X86::BP:
+ if (SubRegNo == X86::BPL) return 1;
+ return 0;
+ case X86::SP:
+ if (SubRegNo == X86::SPL) return 1;
+ return 0;
+ case X86::R8W:
+ if (SubRegNo == X86::R8B) return 1;
+ return 0;
+ case X86::R9W:
+ if (SubRegNo == X86::R9B) return 1;
+ return 0;
+ case X86::R10W:
+ if (SubRegNo == X86::R10B) return 1;
+ return 0;
+ case X86::R11W:
+ if (SubRegNo == X86::R11B) return 1;
+ return 0;
+ case X86::R12W:
+ if (SubRegNo == X86::R12B) return 1;
+ return 0;
+ case X86::R13W:
+ if (SubRegNo == X86::R13B) return 1;
+ return 0;
+ case X86::R14W:
+ if (SubRegNo == X86::R14B) return 1;
+ return 0;
+ case X86::R15W:
+ if (SubRegNo == X86::R15B) return 1;
+ return 0;
+ case X86::EAX:
+ if (SubRegNo == X86::AL) return 1;
+ if (SubRegNo == X86::AH) return 2;
+ if (SubRegNo == X86::AX) return 3;
+ return 0;
+ case X86::EDX:
+ if (SubRegNo == X86::DL) return 1;
+ if (SubRegNo == X86::DH) return 2;
+ if (SubRegNo == X86::DX) return 3;
+ return 0;
+ case X86::ECX:
+ if (SubRegNo == X86::CL) return 1;
+ if (SubRegNo == X86::CH) return 2;
+ if (SubRegNo == X86::CX) return 3;
+ return 0;
+ case X86::EBX:
+ if (SubRegNo == X86::BL) return 1;
+ if (SubRegNo == X86::BH) return 2;
+ if (SubRegNo == X86::BX) return 3;
+ return 0;
+ case X86::ESI:
+ if (SubRegNo == X86::SIL) return 1;
+ if (SubRegNo == X86::SI) return 3;
+ return 0;
+ case X86::EDI:
+ if (SubRegNo == X86::DIL) return 1;
+ if (SubRegNo == X86::DI) return 3;
+ return 0;
+ case X86::EBP:
+ if (SubRegNo == X86::BPL) return 1;
+ if (SubRegNo == X86::BP) return 3;
+ return 0;
+ case X86::ESP:
+ if (SubRegNo == X86::SPL) return 1;
+ if (SubRegNo == X86::SP) return 3;
+ return 0;
+ case X86::R8D:
+ if (SubRegNo == X86::R8B) return 1;
+ if (SubRegNo == X86::R8W) return 3;
+ return 0;
+ case X86::R9D:
+ if (SubRegNo == X86::R9B) return 1;
+ if (SubRegNo == X86::R9W) return 3;
+ return 0;
+ case X86::R10D:
+ if (SubRegNo == X86::R10B) return 1;
+ if (SubRegNo == X86::R10W) return 3;
+ return 0;
+ case X86::R11D:
+ if (SubRegNo == X86::R11B) return 1;
+ if (SubRegNo == X86::R11W) return 3;
+ return 0;
+ case X86::R12D:
+ if (SubRegNo == X86::R12B) return 1;
+ if (SubRegNo == X86::R12W) return 3;
+ return 0;
+ case X86::R13D:
+ if (SubRegNo == X86::R13B) return 1;
+ if (SubRegNo == X86::R13W) return 3;
+ return 0;
+ case X86::R14D:
+ if (SubRegNo == X86::R14B) return 1;
+ if (SubRegNo == X86::R14W) return 3;
+ return 0;
+ case X86::R15D:
+ if (SubRegNo == X86::R15B) return 1;
+ if (SubRegNo == X86::R15W) return 3;
+ return 0;
+ case X86::RAX:
+ if (SubRegNo == X86::AL) return 1;
+ if (SubRegNo == X86::AH) return 2;
+ if (SubRegNo == X86::AX) return 3;
+ if (SubRegNo == X86::EAX) return 4;
+ return 0;
+ case X86::RDX:
+ if (SubRegNo == X86::DL) return 1;
+ if (SubRegNo == X86::DH) return 2;
+ if (SubRegNo == X86::DX) return 3;
+ if (SubRegNo == X86::EDX) return 4;
+ return 0;
+ case X86::RCX:
+ if (SubRegNo == X86::CL) return 1;
+ if (SubRegNo == X86::CH) return 2;
+ if (SubRegNo == X86::CX) return 3;
+ if (SubRegNo == X86::ECX) return 4;
+ return 0;
+ case X86::RBX:
+ if (SubRegNo == X86::BL) return 1;
+ if (SubRegNo == X86::BH) return 2;
+ if (SubRegNo == X86::BX) return 3;
+ if (SubRegNo == X86::EBX) return 4;
+ return 0;
+ case X86::RSI:
+ if (SubRegNo == X86::SIL) return 1;
+ if (SubRegNo == X86::SI) return 3;
+ if (SubRegNo == X86::ESI) return 4;
+ return 0;
+ case X86::RDI:
+ if (SubRegNo == X86::DIL) return 1;
+ if (SubRegNo == X86::DI) return 3;
+ if (SubRegNo == X86::EDI) return 4;
+ return 0;
+ case X86::RBP:
+ if (SubRegNo == X86::BPL) return 1;
+ if (SubRegNo == X86::BP) return 3;
+ if (SubRegNo == X86::EBP) return 4;
+ return 0;
+ case X86::RSP:
+ if (SubRegNo == X86::SPL) return 1;
+ if (SubRegNo == X86::SP) return 3;
+ if (SubRegNo == X86::ESP) return 4;
+ return 0;
+ case X86::R8:
+ if (SubRegNo == X86::R8B) return 1;
+ if (SubRegNo == X86::R8W) return 3;
+ if (SubRegNo == X86::R8D) return 4;
+ return 0;
+ case X86::R9:
+ if (SubRegNo == X86::R9B) return 1;
+ if (SubRegNo == X86::R9W) return 3;
+ if (SubRegNo == X86::R9D) return 4;
+ return 0;
+ case X86::R10:
+ if (SubRegNo == X86::R10B) return 1;
+ if (SubRegNo == X86::R10W) return 3;
+ if (SubRegNo == X86::R10D) return 4;
+ return 0;
+ case X86::R11:
+ if (SubRegNo == X86::R11B) return 1;
+ if (SubRegNo == X86::R11W) return 3;
+ if (SubRegNo == X86::R11D) return 4;
+ return 0;
+ case X86::R12:
+ if (SubRegNo == X86::R12B) return 1;
+ if (SubRegNo == X86::R12W) return 3;
+ if (SubRegNo == X86::R12D) return 4;
+ return 0;
+ case X86::R13:
+ if (SubRegNo == X86::R13B) return 1;
+ if (SubRegNo == X86::R13W) return 3;
+ if (SubRegNo == X86::R13D) return 4;
+ return 0;
+ case X86::R14:
+ if (SubRegNo == X86::R14B) return 1;
+ if (SubRegNo == X86::R14W) return 3;
+ if (SubRegNo == X86::R14D) return 4;
+ return 0;
+ case X86::R15:
+ if (SubRegNo == X86::R15B) return 1;
+ if (SubRegNo == X86::R15W) return 3;
+ if (SubRegNo == X86::R15D) return 4;
+ return 0;
+ case X86::YMM0:
+ if (SubRegNo == X86::XMM0) return 1;
+ return 0;
+ case X86::YMM1:
+ if (SubRegNo == X86::XMM1) return 1;
+ return 0;
+ case X86::YMM2:
+ if (SubRegNo == X86::XMM2) return 1;
+ return 0;
+ case X86::YMM3:
+ if (SubRegNo == X86::XMM3) return 1;
+ return 0;
+ case X86::YMM4:
+ if (SubRegNo == X86::XMM4) return 1;
+ return 0;
+ case X86::YMM5:
+ if (SubRegNo == X86::XMM5) return 1;
+ return 0;
+ case X86::YMM6:
+ if (SubRegNo == X86::XMM6) return 1;
+ return 0;
+ case X86::YMM7:
+ if (SubRegNo == X86::XMM7) return 1;
+ return 0;
+ case X86::YMM8:
+ if (SubRegNo == X86::XMM8) return 1;
+ return 0;
+ case X86::YMM9:
+ if (SubRegNo == X86::XMM9) return 1;
+ return 0;
+ case X86::YMM10:
+ if (SubRegNo == X86::XMM10) return 1;
+ return 0;
+ case X86::YMM11:
+ if (SubRegNo == X86::XMM11) return 1;
+ return 0;
+ case X86::YMM12:
+ if (SubRegNo == X86::XMM12) return 1;
+ return 0;
+ case X86::YMM13:
+ if (SubRegNo == X86::XMM13) return 1;
+ return 0;
+ case X86::YMM14:
+ if (SubRegNo == X86::XMM14) return 1;
+ return 0;
+ case X86::YMM15:
+ if (SubRegNo == X86::XMM15) return 1;
+ return 0;
+ };
+ return 0;
+}
+
+X86GenRegisterInfo::X86GenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
+ : TargetRegisterInfo(RegisterDescriptors, 134, RegisterClasses, RegisterClasses+28,
+ CallFrameSetupOpcode, CallFrameDestroyOpcode,
+ SubregHashTable, SubregHashTableSize,
+ SuperregHashTable, SuperregHashTableSize,
+ AliasesHashTable, AliasesHashTableSize) {
+}
+
+int X86GenRegisterInfo::getDwarfRegNumFull(unsigned RegNum, unsigned Flavour) const {
+ switch (Flavour) {
+ default:
+ assert(0 && "Unknown DWARF flavour");
+ return -1;
+ case 0:
+ switch (RegNum) {
+ default:
+ assert(0 && "Invalid RegNum");
+ return -1;
+ case X86::AH:
+ return 0;
+ case X86::AL:
+ return 0;
+ case X86::AX:
+ return 0;
+ case X86::BH:
+ return 3;
+ case X86::BL:
+ return 3;
+ case X86::BP:
+ return 6;
+ case X86::BPL:
+ return 6;
+ case X86::BX:
+ return 3;
+ case X86::CH:
+ return 2;
+ case X86::CL:
+ return 2;
+ case X86::CS:
+ return -1;
+ case X86::CX:
+ return 2;
+ case X86::DH:
+ return 1;
+ case X86::DI:
+ return 5;
+ case X86::DIL:
+ return 5;
+ case X86::DL:
+ return 1;
+ case X86::DS:
+ return -1;
+ case X86::DX:
+ return 1;
+ case X86::EAX:
+ return 0;
+ case X86::EBP:
+ return 6;
+ case X86::EBX:
+ return 3;
+ case X86::ECX:
+ return 2;
+ case X86::EDI:
+ return 5;
+ case X86::EDX:
+ return 1;
+ case X86::EFLAGS:
+ return -1;
+ case X86::EIP:
+ return 16;
+ case X86::ES:
+ return -1;
+ case X86::ESI:
+ return 4;
+ case X86::ESP:
+ return 7;
+ case X86::FP0:
+ return -1;
+ case X86::FP1:
+ return -1;
+ case X86::FP2:
+ return -1;
+ case X86::FP3:
+ return -1;
+ case X86::FP4:
+ return -1;
+ case X86::FP5:
+ return -1;
+ case X86::FP6:
+ return -1;
+ case X86::FS:
+ return -1;
+ case X86::GS:
+ return -1;
+ case X86::IP:
+ return 16;
+ case X86::MM0:
+ return 41;
+ case X86::MM1:
+ return 42;
+ case X86::MM2:
+ return 43;
+ case X86::MM3:
+ return 44;
+ case X86::MM4:
+ return 45;
+ case X86::MM5:
+ return 46;
+ case X86::MM6:
+ return 47;
+ case X86::MM7:
+ return 48;
+ case X86::R10:
+ return 10;
+ case X86::R10B:
+ return 10;
+ case X86::R10D:
+ return 10;
+ case X86::R10W:
+ return 10;
+ case X86::R11:
+ return 11;
+ case X86::R11B:
+ return 11;
+ case X86::R11D:
+ return 11;
+ case X86::R11W:
+ return 11;
+ case X86::R12:
+ return 12;
+ case X86::R12B:
+ return 12;
+ case X86::R12D:
+ return 12;
+ case X86::R12W:
+ return 12;
+ case X86::R13:
+ return 13;
+ case X86::R13B:
+ return 13;
+ case X86::R13D:
+ return 13;
+ case X86::R13W:
+ return 13;
+ case X86::R14:
+ return 14;
+ case X86::R14B:
+ return 14;
+ case X86::R14D:
+ return 14;
+ case X86::R14W:
+ return 14;
+ case X86::R15:
+ return 15;
+ case X86::R15B:
+ return 15;
+ case X86::R15D:
+ return 15;
+ case X86::R15W:
+ return 15;
+ case X86::R8:
+ return 8;
+ case X86::R8B:
+ return 8;
+ case X86::R8D:
+ return 8;
+ case X86::R8W:
+ return 8;
+ case X86::R9:
+ return 9;
+ case X86::R9B:
+ return 9;
+ case X86::R9D:
+ return 9;
+ case X86::R9W:
+ return 9;
+ case X86::RAX:
+ return 0;
+ case X86::RBP:
+ return 6;
+ case X86::RBX:
+ return 3;
+ case X86::RCX:
+ return 2;
+ case X86::RDI:
+ return 5;
+ case X86::RDX:
+ return 1;
+ case X86::RIP:
+ return 16;
+ case X86::RSI:
+ return 4;
+ case X86::RSP:
+ return 7;
+ case X86::SI:
+ return 4;
+ case X86::SIL:
+ return 4;
+ case X86::SP:
+ return 7;
+ case X86::SPL:
+ return 7;
+ case X86::SS:
+ return -1;
+ case X86::ST0:
+ return 33;
+ case X86::ST1:
+ return 34;
+ case X86::ST2:
+ return 35;
+ case X86::ST3:
+ return 36;
+ case X86::ST4:
+ return 37;
+ case X86::ST5:
+ return 38;
+ case X86::ST6:
+ return 39;
+ case X86::ST7:
+ return 40;
+ case X86::XMM0:
+ return 17;
+ case X86::XMM1:
+ return 18;
+ case X86::XMM10:
+ return 27;
+ case X86::XMM11:
+ return 28;
+ case X86::XMM12:
+ return 29;
+ case X86::XMM13:
+ return 30;
+ case X86::XMM14:
+ return 31;
+ case X86::XMM15:
+ return 32;
+ case X86::XMM2:
+ return 19;
+ case X86::XMM3:
+ return 20;
+ case X86::XMM4:
+ return 21;
+ case X86::XMM5:
+ return 22;
+ case X86::XMM6:
+ return 23;
+ case X86::XMM7:
+ return 24;
+ case X86::XMM8:
+ return 25;
+ case X86::XMM9:
+ return 26;
+ case X86::YMM0:
+ return 17;
+ case X86::YMM1:
+ return 18;
+ case X86::YMM10:
+ return 27;
+ case X86::YMM11:
+ return 28;
+ case X86::YMM12:
+ return 29;
+ case X86::YMM13:
+ return 30;
+ case X86::YMM14:
+ return 31;
+ case X86::YMM15:
+ return 32;
+ case X86::YMM2:
+ return 19;
+ case X86::YMM3:
+ return 20;
+ case X86::YMM4:
+ return 21;
+ case X86::YMM5:
+ return 22;
+ case X86::YMM6:
+ return 23;
+ case X86::YMM7:
+ return 24;
+ case X86::YMM8:
+ return 25;
+ case X86::YMM9:
+ return 26;
+ };
+ case 1:
+ switch (RegNum) {
+ default:
+ assert(0 && "Invalid RegNum");
+ return -1;
+ case X86::AH:
+ return 0;
+ case X86::AL:
+ return 0;
+ case X86::AX:
+ return 0;
+ case X86::BH:
+ return 3;
+ case X86::BL:
+ return 3;
+ case X86::BP:
+ return 4;
+ case X86::BPL:
+ return 4;
+ case X86::BX:
+ return 3;
+ case X86::CH:
+ return 1;
+ case X86::CL:
+ return 1;
+ case X86::CS:
+ return -1;
+ case X86::CX:
+ return 1;
+ case X86::DH:
+ return 2;
+ case X86::DI:
+ return 7;
+ case X86::DIL:
+ return 7;
+ case X86::DL:
+ return 2;
+ case X86::DS:
+ return -1;
+ case X86::DX:
+ return 2;
+ case X86::EAX:
+ return 0;
+ case X86::EBP:
+ return 4;
+ case X86::EBX:
+ return 3;
+ case X86::ECX:
+ return 1;
+ case X86::EDI:
+ return 7;
+ case X86::EDX:
+ return 2;
+ case X86::EFLAGS:
+ return -1;
+ case X86::EIP:
+ return 8;
+ case X86::ES:
+ return -1;
+ case X86::ESI:
+ return 6;
+ case X86::ESP:
+ return 5;
+ case X86::FP0:
+ return -1;
+ case X86::FP1:
+ return -1;
+ case X86::FP2:
+ return -1;
+ case X86::FP3:
+ return -1;
+ case X86::FP4:
+ return -1;
+ case X86::FP5:
+ return -1;
+ case X86::FP6:
+ return -1;
+ case X86::FS:
+ return -1;
+ case X86::GS:
+ return -1;
+ case X86::IP:
+ return -1;
+ case X86::MM0:
+ return 29;
+ case X86::MM1:
+ return 30;
+ case X86::MM2:
+ return 31;
+ case X86::MM3:
+ return 32;
+ case X86::MM4:
+ return 33;
+ case X86::MM5:
+ return 34;
+ case X86::MM6:
+ return 35;
+ case X86::MM7:
+ return 36;
+ case X86::R10:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R10B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R10D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R10W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RAX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RBP:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RBX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RCX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RDI:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RDX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RIP:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RSI:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RSP:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::SI:
+ return 6;
+ case X86::SIL:
+ return 6;
+ case X86::SP:
+ return 5;
+ case X86::SPL:
+ return 5;
+ case X86::SS:
+ return -1;
+ case X86::ST0:
+ return 12;
+ case X86::ST1:
+ return 13;
+ case X86::ST2:
+ return 14;
+ case X86::ST3:
+ return 15;
+ case X86::ST4:
+ return 16;
+ case X86::ST5:
+ return 17;
+ case X86::ST6:
+ return 18;
+ case X86::ST7:
+ return 19;
+ case X86::XMM0:
+ return 21;
+ case X86::XMM1:
+ return 22;
+ case X86::XMM10:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM11:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM12:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM13:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM14:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM15:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM2:
+ return 23;
+ case X86::XMM3:
+ return 24;
+ case X86::XMM4:
+ return 25;
+ case X86::XMM5:
+ return 26;
+ case X86::XMM6:
+ return 27;
+ case X86::XMM7:
+ return 28;
+ case X86::XMM8:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM9:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM0:
+ return 21;
+ case X86::YMM1:
+ return 22;
+ case X86::YMM10:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM11:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM12:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM13:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM14:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM15:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM2:
+ return 23;
+ case X86::YMM3:
+ return 24;
+ case X86::YMM4:
+ return 25;
+ case X86::YMM5:
+ return 26;
+ case X86::YMM6:
+ return 27;
+ case X86::YMM7:
+ return 28;
+ case X86::YMM8:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM9:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ };
+ case 2:
+ switch (RegNum) {
+ default:
+ assert(0 && "Invalid RegNum");
+ return -1;
+ case X86::AH:
+ return 0;
+ case X86::AL:
+ return 0;
+ case X86::AX:
+ return 0;
+ case X86::BH:
+ return 3;
+ case X86::BL:
+ return 3;
+ case X86::BP:
+ return 5;
+ case X86::BPL:
+ return 5;
+ case X86::BX:
+ return 3;
+ case X86::CH:
+ return 1;
+ case X86::CL:
+ return 1;
+ case X86::CS:
+ return -1;
+ case X86::CX:
+ return 1;
+ case X86::DH:
+ return 2;
+ case X86::DI:
+ return 7;
+ case X86::DIL:
+ return 7;
+ case X86::DL:
+ return 2;
+ case X86::DS:
+ return -1;
+ case X86::DX:
+ return 2;
+ case X86::EAX:
+ return 0;
+ case X86::EBP:
+ return 5;
+ case X86::EBX:
+ return 3;
+ case X86::ECX:
+ return 1;
+ case X86::EDI:
+ return 7;
+ case X86::EDX:
+ return 2;
+ case X86::EFLAGS:
+ return -1;
+ case X86::EIP:
+ return 8;
+ case X86::ES:
+ return -1;
+ case X86::ESI:
+ return 6;
+ case X86::ESP:
+ return 4;
+ case X86::FP0:
+ return -1;
+ case X86::FP1:
+ return -1;
+ case X86::FP2:
+ return -1;
+ case X86::FP3:
+ return -1;
+ case X86::FP4:
+ return -1;
+ case X86::FP5:
+ return -1;
+ case X86::FP6:
+ return -1;
+ case X86::FS:
+ return -1;
+ case X86::GS:
+ return -1;
+ case X86::IP:
+ return -1;
+ case X86::MM0:
+ return 29;
+ case X86::MM1:
+ return 30;
+ case X86::MM2:
+ return 31;
+ case X86::MM3:
+ return 32;
+ case X86::MM4:
+ return 33;
+ case X86::MM5:
+ return 34;
+ case X86::MM6:
+ return 35;
+ case X86::MM7:
+ return 36;
+ case X86::R10:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R10B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R10D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R10W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R11W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R12W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R13W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R14W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R15W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R8W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9B:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9D:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::R9W:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RAX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RBP:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RBX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RCX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RDI:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RDX:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RIP:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RSI:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::RSP:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::SI:
+ return 6;
+ case X86::SIL:
+ return 6;
+ case X86::SP:
+ return 4;
+ case X86::SPL:
+ return 4;
+ case X86::SS:
+ return -1;
+ case X86::ST0:
+ return 11;
+ case X86::ST1:
+ return 12;
+ case X86::ST2:
+ return 13;
+ case X86::ST3:
+ return 14;
+ case X86::ST4:
+ return 15;
+ case X86::ST5:
+ return 16;
+ case X86::ST6:
+ return 17;
+ case X86::ST7:
+ return 18;
+ case X86::XMM0:
+ return 21;
+ case X86::XMM1:
+ return 22;
+ case X86::XMM10:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM11:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM12:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM13:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM14:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM15:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM2:
+ return 23;
+ case X86::XMM3:
+ return 24;
+ case X86::XMM4:
+ return 25;
+ case X86::XMM5:
+ return 26;
+ case X86::XMM6:
+ return 27;
+ case X86::XMM7:
+ return 28;
+ case X86::XMM8:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::XMM9:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM0:
+ return 21;
+ case X86::YMM1:
+ return 22;
+ case X86::YMM10:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM11:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM12:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM13:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM14:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM15:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM2:
+ return 23;
+ case X86::YMM3:
+ return 24;
+ case X86::YMM4:
+ return 25;
+ case X86::YMM5:
+ return 26;
+ case X86::YMM6:
+ return 27;
+ case X86::YMM7:
+ return 28;
+ case X86::YMM8:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ case X86::YMM9:
+ assert(0 && "Invalid register for this mode");
+ return -1;
+ };
+ };
+}
+
+} // End llvm namespace
diff --git a/libclamav/c++/X86GenRegisterNames.inc b/libclamav/c++/X86GenRegisterNames.inc
new file mode 100644
index 0000000..49dbe75
--- /dev/null
+++ b/libclamav/c++/X86GenRegisterNames.inc
@@ -0,0 +1,150 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Target Register Enum Values
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+
+namespace X86 {
+ enum {
+ NoRegister,
+ AH, // 1
+ AL, // 2
+ AX, // 3
+ BH, // 4
+ BL, // 5
+ BP, // 6
+ BPL, // 7
+ BX, // 8
+ CH, // 9
+ CL, // 10
+ CS, // 11
+ CX, // 12
+ DH, // 13
+ DI, // 14
+ DIL, // 15
+ DL, // 16
+ DS, // 17
+ DX, // 18
+ EAX, // 19
+ EBP, // 20
+ EBX, // 21
+ ECX, // 22
+ EDI, // 23
+ EDX, // 24
+ EFLAGS, // 25
+ EIP, // 26
+ ES, // 27
+ ESI, // 28
+ ESP, // 29
+ FP0, // 30
+ FP1, // 31
+ FP2, // 32
+ FP3, // 33
+ FP4, // 34
+ FP5, // 35
+ FP6, // 36
+ FS, // 37
+ GS, // 38
+ IP, // 39
+ MM0, // 40
+ MM1, // 41
+ MM2, // 42
+ MM3, // 43
+ MM4, // 44
+ MM5, // 45
+ MM6, // 46
+ MM7, // 47
+ R10, // 48
+ R10B, // 49
+ R10D, // 50
+ R10W, // 51
+ R11, // 52
+ R11B, // 53
+ R11D, // 54
+ R11W, // 55
+ R12, // 56
+ R12B, // 57
+ R12D, // 58
+ R12W, // 59
+ R13, // 60
+ R13B, // 61
+ R13D, // 62
+ R13W, // 63
+ R14, // 64
+ R14B, // 65
+ R14D, // 66
+ R14W, // 67
+ R15, // 68
+ R15B, // 69
+ R15D, // 70
+ R15W, // 71
+ R8, // 72
+ R8B, // 73
+ R8D, // 74
+ R8W, // 75
+ R9, // 76
+ R9B, // 77
+ R9D, // 78
+ R9W, // 79
+ RAX, // 80
+ RBP, // 81
+ RBX, // 82
+ RCX, // 83
+ RDI, // 84
+ RDX, // 85
+ RIP, // 86
+ RSI, // 87
+ RSP, // 88
+ SI, // 89
+ SIL, // 90
+ SP, // 91
+ SPL, // 92
+ SS, // 93
+ ST0, // 94
+ ST1, // 95
+ ST2, // 96
+ ST3, // 97
+ ST4, // 98
+ ST5, // 99
+ ST6, // 100
+ ST7, // 101
+ XMM0, // 102
+ XMM1, // 103
+ XMM10, // 104
+ XMM11, // 105
+ XMM12, // 106
+ XMM13, // 107
+ XMM14, // 108
+ XMM15, // 109
+ XMM2, // 110
+ XMM3, // 111
+ XMM4, // 112
+ XMM5, // 113
+ XMM6, // 114
+ XMM7, // 115
+ XMM8, // 116
+ XMM9, // 117
+ YMM0, // 118
+ YMM1, // 119
+ YMM10, // 120
+ YMM11, // 121
+ YMM12, // 122
+ YMM13, // 123
+ YMM14, // 124
+ YMM15, // 125
+ YMM2, // 126
+ YMM3, // 127
+ YMM4, // 128
+ YMM5, // 129
+ YMM6, // 130
+ YMM7, // 131
+ YMM8, // 132
+ YMM9, // 133
+ NUM_TARGET_REGS // 134
+ };
+}
+} // End llvm namespace
diff --git a/libclamav/c++/X86GenSubtarget.inc b/libclamav/c++/X86GenSubtarget.inc
new file mode 100644
index 0000000..270465a
--- /dev/null
+++ b/libclamav/c++/X86GenSubtarget.inc
@@ -0,0 +1,145 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Subtarget Enumeration Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/SubtargetFeature.h"
+#include "llvm/Target/TargetInstrItineraries.h"
+
+enum {
+};
+
+enum {
+ Feature3DNow = 1 << 0,
+ Feature3DNowA = 1 << 1,
+ Feature64Bit = 1 << 2,
+ FeatureAVX = 1 << 3,
+ FeatureCMOV = 1 << 4,
+ FeatureFMA3 = 1 << 5,
+ FeatureFMA4 = 1 << 6,
+ FeatureMMX = 1 << 7,
+ FeatureSSE1 = 1 << 8,
+ FeatureSSE2 = 1 << 9,
+ FeatureSSE3 = 1 << 10,
+ FeatureSSE41 = 1 << 11,
+ FeatureSSE42 = 1 << 12,
+ FeatureSSE4A = 1 << 13,
+ FeatureSSSE3 = 1 << 14,
+ FeatureSlowBTMem = 1 << 15
+};
+
+// Sorted (by key) array of values for CPU features.
+static const llvm::SubtargetFeatureKV FeatureKV[] = {
+ { "3dnow", "Enable 3DNow! instructions", Feature3DNow, 0 },
+ { "3dnowa", "Enable 3DNow! Athlon instructions", Feature3DNowA, Feature3DNow },
+ { "64bit", "Support 64-bit instructions", Feature64Bit, 0 },
+ { "avx", "Enable AVX instructions", FeatureAVX, 0 },
+ { "cmov", "Enable conditional move instructions", FeatureCMOV, 0 },
+ { "fma3", "Enable three-operand fused multiple-add", FeatureFMA3, 0 },
+ { "fma4", "Enable four-operand fused multiple-add", FeatureFMA4, 0 },
+ { "mmx", "Enable MMX instructions", FeatureMMX, 0 },
+ { "slow-bt-mem", "Bit testing of memory is slow", FeatureSlowBTMem, 0 },
+ { "sse", "Enable SSE instructions", FeatureSSE1, FeatureMMX | FeatureCMOV },
+ { "sse2", "Enable SSE2 instructions", FeatureSSE2, FeatureSSE1 },
+ { "sse3", "Enable SSE3 instructions", FeatureSSE3, FeatureSSE2 },
+ { "sse41", "Enable SSE 4.1 instructions", FeatureSSE41, FeatureSSSE3 },
+ { "sse42", "Enable SSE 4.2 instructions", FeatureSSE42, FeatureSSE41 },
+ { "sse4a", "Support SSE 4a instructions", FeatureSSE4A, 0 },
+ { "ssse3", "Enable SSSE3 instructions", FeatureSSSE3, FeatureSSE3 }
+};
+
+enum {
+ FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)
+};
+
+// Sorted (by key) array of values for CPU subtype.
+static const llvm::SubtargetFeatureKV SubTypeKV[] = {
+ { "amdfam10", "Select the amdfam10 processor", FeatureSSE3 | FeatureSSE4A | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "athlon", "Select the athlon processor", FeatureMMX | Feature3DNowA | FeatureSlowBTMem, 0 },
+ { "athlon-4", "Select the athlon-4 processor", FeatureSSE1 | Feature3DNowA | FeatureSlowBTMem, 0 },
+ { "athlon-fx", "Select the athlon-fx processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "athlon-mp", "Select the athlon-mp processor", FeatureSSE1 | Feature3DNowA | FeatureSlowBTMem, 0 },
+ { "athlon-tbird", "Select the athlon-tbird processor", FeatureMMX | Feature3DNowA | FeatureSlowBTMem, 0 },
+ { "athlon-xp", "Select the athlon-xp processor", FeatureSSE1 | Feature3DNowA | FeatureSlowBTMem, 0 },
+ { "athlon64", "Select the athlon64 processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "athlon64-sse3", "Select the athlon64-sse3 processor", FeatureSSE3 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "atom", "Select the atom processor", FeatureSSE3 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "barcelona", "Select the barcelona processor", FeatureSSE3 | FeatureSSE4A | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "c3", "Select the c3 processor", FeatureMMX | Feature3DNow, 0 },
+ { "c3-2", "Select the c3-2 processor", FeatureSSE1, 0 },
+ { "core2", "Select the core2 processor", FeatureSSSE3 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "corei7", "Select the corei7 processor", FeatureSSE42 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "generic", "Select the generic processor", 0, 0 },
+ { "i386", "Select the i386 processor", 0, 0 },
+ { "i486", "Select the i486 processor", 0, 0 },
+ { "i586", "Select the i586 processor", 0, 0 },
+ { "i686", "Select the i686 processor", 0, 0 },
+ { "istanbul", "Select the istanbul processor", Feature3DNowA | Feature64Bit | FeatureSSE4A | Feature3DNowA, 0 },
+ { "k6", "Select the k6 processor", FeatureMMX, 0 },
+ { "k6-2", "Select the k6-2 processor", FeatureMMX | Feature3DNow, 0 },
+ { "k6-3", "Select the k6-3 processor", FeatureMMX | Feature3DNow, 0 },
+ { "k8", "Select the k8 processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "k8-sse3", "Select the k8-sse3 processor", FeatureSSE3 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "nehalem", "Select the nehalem processor", FeatureSSE42 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "nocona", "Select the nocona processor", FeatureSSE3 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "opteron", "Select the opteron processor", FeatureSSE2 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "opteron-sse3", "Select the opteron-sse3 processor", FeatureSSE3 | Feature3DNowA | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "penryn", "Select the penryn processor", FeatureSSE41 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "pentium", "Select the pentium processor", 0, 0 },
+ { "pentium-m", "Select the pentium-m processor", FeatureSSE2 | FeatureSlowBTMem, 0 },
+ { "pentium-mmx", "Select the pentium-mmx processor", FeatureMMX, 0 },
+ { "pentium2", "Select the pentium2 processor", FeatureMMX | FeatureCMOV, 0 },
+ { "pentium3", "Select the pentium3 processor", FeatureSSE1, 0 },
+ { "pentium4", "Select the pentium4 processor", FeatureSSE2, 0 },
+ { "pentiumpro", "Select the pentiumpro processor", FeatureCMOV, 0 },
+ { "prescott", "Select the prescott processor", FeatureSSE3 | FeatureSlowBTMem, 0 },
+ { "sandybridge", "Select the sandybridge processor", FeatureSSE42 | FeatureAVX | Feature64Bit, 0 },
+ { "shanghai", "Select the shanghai processor", Feature3DNowA | Feature64Bit | FeatureSSE4A | Feature3DNowA, 0 },
+ { "winchip-c6", "Select the winchip-c6 processor", FeatureMMX, 0 },
+ { "winchip2", "Select the winchip2 processor", FeatureMMX | Feature3DNow, 0 },
+ { "x86-64", "Select the x86-64 processor", FeatureSSE2 | Feature64Bit | FeatureSlowBTMem, 0 },
+ { "yonah", "Select the yonah processor", FeatureSSE3 | FeatureSlowBTMem, 0 }
+};
+
+enum {
+ SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)
+};
+
+
+enum {
+ ItinClassesSize = 1
+};
+
+// ParseSubtargetFeatures - Parses features string setting specified
+// subtarget options.
+std::string llvm::X86Subtarget::ParseSubtargetFeatures(const std::string &FS,
+ const std::string &CPU) {
+ DEBUG(errs() << "\nFeatures:" << FS);
+ DEBUG(errs() << "\nCPU:" << CPU);
+ SubtargetFeatures Features(FS);
+ Features.setCPUIfNone(CPU);
+ uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,
+ FeatureKV, FeatureKVSize);
+ if ((Bits & Feature3DNow) != 0 && X863DNowLevel < ThreeDNow) X863DNowLevel = ThreeDNow;
+ if ((Bits & Feature3DNowA) != 0 && X863DNowLevel < ThreeDNowA) X863DNowLevel = ThreeDNowA;
+ if ((Bits & Feature64Bit) != 0) HasX86_64 = true;
+ if ((Bits & FeatureAVX) != 0) HasAVX = true;
+ if ((Bits & FeatureCMOV) != 0) HasCMov = true;
+ if ((Bits & FeatureFMA3) != 0) HasFMA3 = true;
+ if ((Bits & FeatureFMA4) != 0) HasFMA4 = true;
+ if ((Bits & FeatureMMX) != 0 && X86SSELevel < MMX) X86SSELevel = MMX;
+ if ((Bits & FeatureSSE1) != 0 && X86SSELevel < SSE1) X86SSELevel = SSE1;
+ if ((Bits & FeatureSSE2) != 0 && X86SSELevel < SSE2) X86SSELevel = SSE2;
+ if ((Bits & FeatureSSE3) != 0 && X86SSELevel < SSE3) X86SSELevel = SSE3;
+ if ((Bits & FeatureSSE41) != 0 && X86SSELevel < SSE41) X86SSELevel = SSE41;
+ if ((Bits & FeatureSSE42) != 0 && X86SSELevel < SSE42) X86SSELevel = SSE42;
+ if ((Bits & FeatureSSE4A) != 0) HasSSE4A = true;
+ if ((Bits & FeatureSSSE3) != 0 && X86SSELevel < SSSE3) X86SSELevel = SSSE3;
+ if ((Bits & FeatureSlowBTMem) != 0) IsBTMemSlow = true;
+ return Features.getCPU();
+}
diff --git a/libclamav/c++/llvm/include/llvm/Intrinsics.gen b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
new file mode 100644
index 0000000..96cbbfa
--- /dev/null
+++ b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
@@ -0,0 +1,12293 @@
+//===- TableGen'erated file -------------------------------------*- C++ -*-===//
+//
+// Intrinsic Function Source Fragment
+//
+// Automatically generated file, do not edit!
+//
+//===----------------------------------------------------------------------===//
+
+// Enum values for Intrinsics.h
+#ifdef GET_INTRINSIC_ENUM_VALUES
+ alpha_umulh, // llvm.alpha.umulh
+ annotation, // llvm.annotation
+ arm_neon_vabals, // llvm.arm.neon.vabals
+ arm_neon_vabalu, // llvm.arm.neon.vabalu
+ arm_neon_vabas, // llvm.arm.neon.vabas
+ arm_neon_vabau, // llvm.arm.neon.vabau
+ arm_neon_vabdls, // llvm.arm.neon.vabdls
+ arm_neon_vabdlu, // llvm.arm.neon.vabdlu
+ arm_neon_vabds, // llvm.arm.neon.vabds
+ arm_neon_vabdu, // llvm.arm.neon.vabdu
+ arm_neon_vabs, // llvm.arm.neon.vabs
+ arm_neon_vacged, // llvm.arm.neon.vacged
+ arm_neon_vacgeq, // llvm.arm.neon.vacgeq
+ arm_neon_vacgtd, // llvm.arm.neon.vacgtd
+ arm_neon_vacgtq, // llvm.arm.neon.vacgtq
+ arm_neon_vaddhn, // llvm.arm.neon.vaddhn
+ arm_neon_vaddls, // llvm.arm.neon.vaddls
+ arm_neon_vaddlu, // llvm.arm.neon.vaddlu
+ arm_neon_vaddws, // llvm.arm.neon.vaddws
+ arm_neon_vaddwu, // llvm.arm.neon.vaddwu
+ arm_neon_vcls, // llvm.arm.neon.vcls
+ arm_neon_vclz, // llvm.arm.neon.vclz
+ arm_neon_vcnt, // llvm.arm.neon.vcnt
+ arm_neon_vcvtfp2fxs, // llvm.arm.neon.vcvtfp2fxs
+ arm_neon_vcvtfp2fxu, // llvm.arm.neon.vcvtfp2fxu
+ arm_neon_vcvtfxs2fp, // llvm.arm.neon.vcvtfxs2fp
+ arm_neon_vcvtfxu2fp, // llvm.arm.neon.vcvtfxu2fp
+ arm_neon_vhadds, // llvm.arm.neon.vhadds
+ arm_neon_vhaddu, // llvm.arm.neon.vhaddu
+ arm_neon_vhsubs, // llvm.arm.neon.vhsubs
+ arm_neon_vhsubu, // llvm.arm.neon.vhsubu
+ arm_neon_vld1, // llvm.arm.neon.vld1
+ arm_neon_vld2, // llvm.arm.neon.vld2
+ arm_neon_vld2lane, // llvm.arm.neon.vld2lane
+ arm_neon_vld3, // llvm.arm.neon.vld3
+ arm_neon_vld3lane, // llvm.arm.neon.vld3lane
+ arm_neon_vld4, // llvm.arm.neon.vld4
+ arm_neon_vld4lane, // llvm.arm.neon.vld4lane
+ arm_neon_vmaxs, // llvm.arm.neon.vmaxs
+ arm_neon_vmaxu, // llvm.arm.neon.vmaxu
+ arm_neon_vmins, // llvm.arm.neon.vmins
+ arm_neon_vminu, // llvm.arm.neon.vminu
+ arm_neon_vmlals, // llvm.arm.neon.vmlals
+ arm_neon_vmlalu, // llvm.arm.neon.vmlalu
+ arm_neon_vmlsls, // llvm.arm.neon.vmlsls
+ arm_neon_vmlslu, // llvm.arm.neon.vmlslu
+ arm_neon_vmovls, // llvm.arm.neon.vmovls
+ arm_neon_vmovlu, // llvm.arm.neon.vmovlu
+ arm_neon_vmovn, // llvm.arm.neon.vmovn
+ arm_neon_vmullp, // llvm.arm.neon.vmullp
+ arm_neon_vmulls, // llvm.arm.neon.vmulls
+ arm_neon_vmullu, // llvm.arm.neon.vmullu
+ arm_neon_vmulp, // llvm.arm.neon.vmulp
+ arm_neon_vpadals, // llvm.arm.neon.vpadals
+ arm_neon_vpadalu, // llvm.arm.neon.vpadalu
+ arm_neon_vpadd, // llvm.arm.neon.vpadd
+ arm_neon_vpaddls, // llvm.arm.neon.vpaddls
+ arm_neon_vpaddlu, // llvm.arm.neon.vpaddlu
+ arm_neon_vpmaxs, // llvm.arm.neon.vpmaxs
+ arm_neon_vpmaxu, // llvm.arm.neon.vpmaxu
+ arm_neon_vpmins, // llvm.arm.neon.vpmins
+ arm_neon_vpminu, // llvm.arm.neon.vpminu
+ arm_neon_vqabs, // llvm.arm.neon.vqabs
+ arm_neon_vqadds, // llvm.arm.neon.vqadds
+ arm_neon_vqaddu, // llvm.arm.neon.vqaddu
+ arm_neon_vqdmlal, // llvm.arm.neon.vqdmlal
+ arm_neon_vqdmlsl, // llvm.arm.neon.vqdmlsl
+ arm_neon_vqdmulh, // llvm.arm.neon.vqdmulh
+ arm_neon_vqdmull, // llvm.arm.neon.vqdmull
+ arm_neon_vqmovns, // llvm.arm.neon.vqmovns
+ arm_neon_vqmovnsu, // llvm.arm.neon.vqmovnsu
+ arm_neon_vqmovnu, // llvm.arm.neon.vqmovnu
+ arm_neon_vqneg, // llvm.arm.neon.vqneg
+ arm_neon_vqrdmulh, // llvm.arm.neon.vqrdmulh
+ arm_neon_vqrshiftns, // llvm.arm.neon.vqrshiftns
+ arm_neon_vqrshiftnsu, // llvm.arm.neon.vqrshiftnsu
+ arm_neon_vqrshiftnu, // llvm.arm.neon.vqrshiftnu
+ arm_neon_vqrshifts, // llvm.arm.neon.vqrshifts
+ arm_neon_vqrshiftu, // llvm.arm.neon.vqrshiftu
+ arm_neon_vqshiftns, // llvm.arm.neon.vqshiftns
+ arm_neon_vqshiftnsu, // llvm.arm.neon.vqshiftnsu
+ arm_neon_vqshiftnu, // llvm.arm.neon.vqshiftnu
+ arm_neon_vqshifts, // llvm.arm.neon.vqshifts
+ arm_neon_vqshiftsu, // llvm.arm.neon.vqshiftsu
+ arm_neon_vqshiftu, // llvm.arm.neon.vqshiftu
+ arm_neon_vqsubs, // llvm.arm.neon.vqsubs
+ arm_neon_vqsubu, // llvm.arm.neon.vqsubu
+ arm_neon_vraddhn, // llvm.arm.neon.vraddhn
+ arm_neon_vrecpe, // llvm.arm.neon.vrecpe
+ arm_neon_vrecps, // llvm.arm.neon.vrecps
+ arm_neon_vrhadds, // llvm.arm.neon.vrhadds
+ arm_neon_vrhaddu, // llvm.arm.neon.vrhaddu
+ arm_neon_vrshiftn, // llvm.arm.neon.vrshiftn
+ arm_neon_vrshifts, // llvm.arm.neon.vrshifts
+ arm_neon_vrshiftu, // llvm.arm.neon.vrshiftu
+ arm_neon_vrsqrte, // llvm.arm.neon.vrsqrte
+ arm_neon_vrsqrts, // llvm.arm.neon.vrsqrts
+ arm_neon_vrsubhn, // llvm.arm.neon.vrsubhn
+ arm_neon_vshiftins, // llvm.arm.neon.vshiftins
+ arm_neon_vshiftls, // llvm.arm.neon.vshiftls
+ arm_neon_vshiftlu, // llvm.arm.neon.vshiftlu
+ arm_neon_vshiftn, // llvm.arm.neon.vshiftn
+ arm_neon_vshifts, // llvm.arm.neon.vshifts
+ arm_neon_vshiftu, // llvm.arm.neon.vshiftu
+ arm_neon_vst1, // llvm.arm.neon.vst1
+ arm_neon_vst2, // llvm.arm.neon.vst2
+ arm_neon_vst2lane, // llvm.arm.neon.vst2lane
+ arm_neon_vst3, // llvm.arm.neon.vst3
+ arm_neon_vst3lane, // llvm.arm.neon.vst3lane
+ arm_neon_vst4, // llvm.arm.neon.vst4
+ arm_neon_vst4lane, // llvm.arm.neon.vst4lane
+ arm_neon_vsubhn, // llvm.arm.neon.vsubhn
+ arm_neon_vsubls, // llvm.arm.neon.vsubls
+ arm_neon_vsublu, // llvm.arm.neon.vsublu
+ arm_neon_vsubws, // llvm.arm.neon.vsubws
+ arm_neon_vsubwu, // llvm.arm.neon.vsubwu
+ arm_neon_vtbl1, // llvm.arm.neon.vtbl1
+ arm_neon_vtbl2, // llvm.arm.neon.vtbl2
+ arm_neon_vtbl3, // llvm.arm.neon.vtbl3
+ arm_neon_vtbl4, // llvm.arm.neon.vtbl4
+ arm_neon_vtbx1, // llvm.arm.neon.vtbx1
+ arm_neon_vtbx2, // llvm.arm.neon.vtbx2
+ arm_neon_vtbx3, // llvm.arm.neon.vtbx3
+ arm_neon_vtbx4, // llvm.arm.neon.vtbx4
+ arm_thread_pointer, // llvm.arm.thread.pointer
+ atomic_cmp_swap, // llvm.atomic.cmp.swap
+ atomic_load_add, // llvm.atomic.load.add
+ atomic_load_and, // llvm.atomic.load.and
+ atomic_load_max, // llvm.atomic.load.max
+ atomic_load_min, // llvm.atomic.load.min
+ atomic_load_nand, // llvm.atomic.load.nand
+ atomic_load_or, // llvm.atomic.load.or
+ atomic_load_sub, // llvm.atomic.load.sub
+ atomic_load_umax, // llvm.atomic.load.umax
+ atomic_load_umin, // llvm.atomic.load.umin
+ atomic_load_xor, // llvm.atomic.load.xor
+ atomic_swap, // llvm.atomic.swap
+ bswap, // llvm.bswap
+ convertff, // llvm.convertff
+ convertfsi, // llvm.convertfsi
+ convertfui, // llvm.convertfui
+ convertsif, // llvm.convertsif
+ convertss, // llvm.convertss
+ convertsu, // llvm.convertsu
+ convertuif, // llvm.convertuif
+ convertus, // llvm.convertus
+ convertuu, // llvm.convertuu
+ cos, // llvm.cos
+ ctlz, // llvm.ctlz
+ ctpop, // llvm.ctpop
+ cttz, // llvm.cttz
+ dbg_declare, // llvm.dbg.declare
+ dbg_func_start, // llvm.dbg.func.start
+ dbg_region_end, // llvm.dbg.region.end
+ dbg_region_start, // llvm.dbg.region.start
+ dbg_stoppoint, // llvm.dbg.stoppoint
+ dbg_value, // llvm.dbg.value
+ eh_dwarf_cfa, // llvm.eh.dwarf.cfa
+ eh_exception, // llvm.eh.exception
+ eh_return_i32, // llvm.eh.return.i32
+ eh_return_i64, // llvm.eh.return.i64
+ eh_selector, // llvm.eh.selector
+ eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp
+ eh_sjlj_lsda, // llvm.eh.sjlj.lsda
+ eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp
+ eh_typeid_for, // llvm.eh.typeid.for
+ eh_unwind_init, // llvm.eh.unwind.init
+ exp, // llvm.exp
+ exp2, // llvm.exp2
+ flt_rounds, // llvm.flt.rounds
+ frameaddress, // llvm.frameaddress
+ gcread, // llvm.gcread
+ gcroot, // llvm.gcroot
+ gcwrite, // llvm.gcwrite
+ init_trampoline, // llvm.init.trampoline
+ invariant_end, // llvm.invariant.end
+ invariant_start, // llvm.invariant.start
+ lifetime_end, // llvm.lifetime.end
+ lifetime_start, // llvm.lifetime.start
+ log, // llvm.log
+ log10, // llvm.log10
+ log2, // llvm.log2
+ longjmp, // llvm.longjmp
+ memcpy, // llvm.memcpy
+ memmove, // llvm.memmove
+ memory_barrier, // llvm.memory.barrier
+ memset, // llvm.memset
+ objectsize, // llvm.objectsize
+ pcmarker, // llvm.pcmarker
+ pow, // llvm.pow
+ powi, // llvm.powi
+ ppc_altivec_dss, // llvm.ppc.altivec.dss
+ ppc_altivec_dssall, // llvm.ppc.altivec.dssall
+ ppc_altivec_dst, // llvm.ppc.altivec.dst
+ ppc_altivec_dstst, // llvm.ppc.altivec.dstst
+ ppc_altivec_dststt, // llvm.ppc.altivec.dststt
+ ppc_altivec_dstt, // llvm.ppc.altivec.dstt
+ ppc_altivec_lvebx, // llvm.ppc.altivec.lvebx
+ ppc_altivec_lvehx, // llvm.ppc.altivec.lvehx
+ ppc_altivec_lvewx, // llvm.ppc.altivec.lvewx
+ ppc_altivec_lvsl, // llvm.ppc.altivec.lvsl
+ ppc_altivec_lvsr, // llvm.ppc.altivec.lvsr
+ ppc_altivec_lvx, // llvm.ppc.altivec.lvx
+ ppc_altivec_lvxl, // llvm.ppc.altivec.lvxl
+ ppc_altivec_mfvscr, // llvm.ppc.altivec.mfvscr
+ ppc_altivec_mtvscr, // llvm.ppc.altivec.mtvscr
+ ppc_altivec_stvebx, // llvm.ppc.altivec.stvebx
+ ppc_altivec_stvehx, // llvm.ppc.altivec.stvehx
+ ppc_altivec_stvewx, // llvm.ppc.altivec.stvewx
+ ppc_altivec_stvx, // llvm.ppc.altivec.stvx
+ ppc_altivec_stvxl, // llvm.ppc.altivec.stvxl
+ ppc_altivec_vaddcuw, // llvm.ppc.altivec.vaddcuw
+ ppc_altivec_vaddsbs, // llvm.ppc.altivec.vaddsbs
+ ppc_altivec_vaddshs, // llvm.ppc.altivec.vaddshs
+ ppc_altivec_vaddsws, // llvm.ppc.altivec.vaddsws
+ ppc_altivec_vaddubs, // llvm.ppc.altivec.vaddubs
+ ppc_altivec_vadduhs, // llvm.ppc.altivec.vadduhs
+ ppc_altivec_vadduws, // llvm.ppc.altivec.vadduws
+ ppc_altivec_vavgsb, // llvm.ppc.altivec.vavgsb
+ ppc_altivec_vavgsh, // llvm.ppc.altivec.vavgsh
+ ppc_altivec_vavgsw, // llvm.ppc.altivec.vavgsw
+ ppc_altivec_vavgub, // llvm.ppc.altivec.vavgub
+ ppc_altivec_vavguh, // llvm.ppc.altivec.vavguh
+ ppc_altivec_vavguw, // llvm.ppc.altivec.vavguw
+ ppc_altivec_vcfsx, // llvm.ppc.altivec.vcfsx
+ ppc_altivec_vcfux, // llvm.ppc.altivec.vcfux
+ ppc_altivec_vcmpbfp, // llvm.ppc.altivec.vcmpbfp
+ ppc_altivec_vcmpbfp_p, // llvm.ppc.altivec.vcmpbfp.p
+ ppc_altivec_vcmpeqfp, // llvm.ppc.altivec.vcmpeqfp
+ ppc_altivec_vcmpeqfp_p, // llvm.ppc.altivec.vcmpeqfp.p
+ ppc_altivec_vcmpequb, // llvm.ppc.altivec.vcmpequb
+ ppc_altivec_vcmpequb_p, // llvm.ppc.altivec.vcmpequb.p
+ ppc_altivec_vcmpequh, // llvm.ppc.altivec.vcmpequh
+ ppc_altivec_vcmpequh_p, // llvm.ppc.altivec.vcmpequh.p
+ ppc_altivec_vcmpequw, // llvm.ppc.altivec.vcmpequw
+ ppc_altivec_vcmpequw_p, // llvm.ppc.altivec.vcmpequw.p
+ ppc_altivec_vcmpgefp, // llvm.ppc.altivec.vcmpgefp
+ ppc_altivec_vcmpgefp_p, // llvm.ppc.altivec.vcmpgefp.p
+ ppc_altivec_vcmpgtfp, // llvm.ppc.altivec.vcmpgtfp
+ ppc_altivec_vcmpgtfp_p, // llvm.ppc.altivec.vcmpgtfp.p
+ ppc_altivec_vcmpgtsb, // llvm.ppc.altivec.vcmpgtsb
+ ppc_altivec_vcmpgtsb_p, // llvm.ppc.altivec.vcmpgtsb.p
+ ppc_altivec_vcmpgtsh, // llvm.ppc.altivec.vcmpgtsh
+ ppc_altivec_vcmpgtsh_p, // llvm.ppc.altivec.vcmpgtsh.p
+ ppc_altivec_vcmpgtsw, // llvm.ppc.altivec.vcmpgtsw
+ ppc_altivec_vcmpgtsw_p, // llvm.ppc.altivec.vcmpgtsw.p
+ ppc_altivec_vcmpgtub, // llvm.ppc.altivec.vcmpgtub
+ ppc_altivec_vcmpgtub_p, // llvm.ppc.altivec.vcmpgtub.p
+ ppc_altivec_vcmpgtuh, // llvm.ppc.altivec.vcmpgtuh
+ ppc_altivec_vcmpgtuh_p, // llvm.ppc.altivec.vcmpgtuh.p
+ ppc_altivec_vcmpgtuw, // llvm.ppc.altivec.vcmpgtuw
+ ppc_altivec_vcmpgtuw_p, // llvm.ppc.altivec.vcmpgtuw.p
+ ppc_altivec_vctsxs, // llvm.ppc.altivec.vctsxs
+ ppc_altivec_vctuxs, // llvm.ppc.altivec.vctuxs
+ ppc_altivec_vexptefp, // llvm.ppc.altivec.vexptefp
+ ppc_altivec_vlogefp, // llvm.ppc.altivec.vlogefp
+ ppc_altivec_vmaddfp, // llvm.ppc.altivec.vmaddfp
+ ppc_altivec_vmaxfp, // llvm.ppc.altivec.vmaxfp
+ ppc_altivec_vmaxsb, // llvm.ppc.altivec.vmaxsb
+ ppc_altivec_vmaxsh, // llvm.ppc.altivec.vmaxsh
+ ppc_altivec_vmaxsw, // llvm.ppc.altivec.vmaxsw
+ ppc_altivec_vmaxub, // llvm.ppc.altivec.vmaxub
+ ppc_altivec_vmaxuh, // llvm.ppc.altivec.vmaxuh
+ ppc_altivec_vmaxuw, // llvm.ppc.altivec.vmaxuw
+ ppc_altivec_vmhaddshs, // llvm.ppc.altivec.vmhaddshs
+ ppc_altivec_vmhraddshs, // llvm.ppc.altivec.vmhraddshs
+ ppc_altivec_vminfp, // llvm.ppc.altivec.vminfp
+ ppc_altivec_vminsb, // llvm.ppc.altivec.vminsb
+ ppc_altivec_vminsh, // llvm.ppc.altivec.vminsh
+ ppc_altivec_vminsw, // llvm.ppc.altivec.vminsw
+ ppc_altivec_vminub, // llvm.ppc.altivec.vminub
+ ppc_altivec_vminuh, // llvm.ppc.altivec.vminuh
+ ppc_altivec_vminuw, // llvm.ppc.altivec.vminuw
+ ppc_altivec_vmladduhm, // llvm.ppc.altivec.vmladduhm
+ ppc_altivec_vmsummbm, // llvm.ppc.altivec.vmsummbm
+ ppc_altivec_vmsumshm, // llvm.ppc.altivec.vmsumshm
+ ppc_altivec_vmsumshs, // llvm.ppc.altivec.vmsumshs
+ ppc_altivec_vmsumubm, // llvm.ppc.altivec.vmsumubm
+ ppc_altivec_vmsumuhm, // llvm.ppc.altivec.vmsumuhm
+ ppc_altivec_vmsumuhs, // llvm.ppc.altivec.vmsumuhs
+ ppc_altivec_vmulesb, // llvm.ppc.altivec.vmulesb
+ ppc_altivec_vmulesh, // llvm.ppc.altivec.vmulesh
+ ppc_altivec_vmuleub, // llvm.ppc.altivec.vmuleub
+ ppc_altivec_vmuleuh, // llvm.ppc.altivec.vmuleuh
+ ppc_altivec_vmulosb, // llvm.ppc.altivec.vmulosb
+ ppc_altivec_vmulosh, // llvm.ppc.altivec.vmulosh
+ ppc_altivec_vmuloub, // llvm.ppc.altivec.vmuloub
+ ppc_altivec_vmulouh, // llvm.ppc.altivec.vmulouh
+ ppc_altivec_vnmsubfp, // llvm.ppc.altivec.vnmsubfp
+ ppc_altivec_vperm, // llvm.ppc.altivec.vperm
+ ppc_altivec_vpkpx, // llvm.ppc.altivec.vpkpx
+ ppc_altivec_vpkshss, // llvm.ppc.altivec.vpkshss
+ ppc_altivec_vpkshus, // llvm.ppc.altivec.vpkshus
+ ppc_altivec_vpkswss, // llvm.ppc.altivec.vpkswss
+ ppc_altivec_vpkswus, // llvm.ppc.altivec.vpkswus
+ ppc_altivec_vpkuhus, // llvm.ppc.altivec.vpkuhus
+ ppc_altivec_vpkuwus, // llvm.ppc.altivec.vpkuwus
+ ppc_altivec_vrefp, // llvm.ppc.altivec.vrefp
+ ppc_altivec_vrfim, // llvm.ppc.altivec.vrfim
+ ppc_altivec_vrfin, // llvm.ppc.altivec.vrfin
+ ppc_altivec_vrfip, // llvm.ppc.altivec.vrfip
+ ppc_altivec_vrfiz, // llvm.ppc.altivec.vrfiz
+ ppc_altivec_vrlb, // llvm.ppc.altivec.vrlb
+ ppc_altivec_vrlh, // llvm.ppc.altivec.vrlh
+ ppc_altivec_vrlw, // llvm.ppc.altivec.vrlw
+ ppc_altivec_vrsqrtefp, // llvm.ppc.altivec.vrsqrtefp
+ ppc_altivec_vsel, // llvm.ppc.altivec.vsel
+ ppc_altivec_vsl, // llvm.ppc.altivec.vsl
+ ppc_altivec_vslb, // llvm.ppc.altivec.vslb
+ ppc_altivec_vslh, // llvm.ppc.altivec.vslh
+ ppc_altivec_vslo, // llvm.ppc.altivec.vslo
+ ppc_altivec_vslw, // llvm.ppc.altivec.vslw
+ ppc_altivec_vsr, // llvm.ppc.altivec.vsr
+ ppc_altivec_vsrab, // llvm.ppc.altivec.vsrab
+ ppc_altivec_vsrah, // llvm.ppc.altivec.vsrah
+ ppc_altivec_vsraw, // llvm.ppc.altivec.vsraw
+ ppc_altivec_vsrb, // llvm.ppc.altivec.vsrb
+ ppc_altivec_vsrh, // llvm.ppc.altivec.vsrh
+ ppc_altivec_vsro, // llvm.ppc.altivec.vsro
+ ppc_altivec_vsrw, // llvm.ppc.altivec.vsrw
+ ppc_altivec_vsubcuw, // llvm.ppc.altivec.vsubcuw
+ ppc_altivec_vsubsbs, // llvm.ppc.altivec.vsubsbs
+ ppc_altivec_vsubshs, // llvm.ppc.altivec.vsubshs
+ ppc_altivec_vsubsws, // llvm.ppc.altivec.vsubsws
+ ppc_altivec_vsububs, // llvm.ppc.altivec.vsububs
+ ppc_altivec_vsubuhs, // llvm.ppc.altivec.vsubuhs
+ ppc_altivec_vsubuws, // llvm.ppc.altivec.vsubuws
+ ppc_altivec_vsum2sws, // llvm.ppc.altivec.vsum2sws
+ ppc_altivec_vsum4sbs, // llvm.ppc.altivec.vsum4sbs
+ ppc_altivec_vsum4shs, // llvm.ppc.altivec.vsum4shs
+ ppc_altivec_vsum4ubs, // llvm.ppc.altivec.vsum4ubs
+ ppc_altivec_vsumsws, // llvm.ppc.altivec.vsumsws
+ ppc_altivec_vupkhpx, // llvm.ppc.altivec.vupkhpx
+ ppc_altivec_vupkhsb, // llvm.ppc.altivec.vupkhsb
+ ppc_altivec_vupkhsh, // llvm.ppc.altivec.vupkhsh
+ ppc_altivec_vupklpx, // llvm.ppc.altivec.vupklpx
+ ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
+ ppc_altivec_vupklsh, // llvm.ppc.altivec.vupklsh
+ ppc_dcba, // llvm.ppc.dcba
+ ppc_dcbf, // llvm.ppc.dcbf
+ ppc_dcbi, // llvm.ppc.dcbi
+ ppc_dcbst, // llvm.ppc.dcbst
+ ppc_dcbt, // llvm.ppc.dcbt
+ ppc_dcbtst, // llvm.ppc.dcbtst
+ ppc_dcbz, // llvm.ppc.dcbz
+ ppc_dcbzl, // llvm.ppc.dcbzl
+ ppc_sync, // llvm.ppc.sync
+ prefetch, // llvm.prefetch
+ ptr_annotation, // llvm.ptr.annotation
+ readcyclecounter, // llvm.readcyclecounter
+ returnaddress, // llvm.returnaddress
+ sadd_with_overflow, // llvm.sadd.with.overflow
+ setjmp, // llvm.setjmp
+ siglongjmp, // llvm.siglongjmp
+ sigsetjmp, // llvm.sigsetjmp
+ sin, // llvm.sin
+ smul_with_overflow, // llvm.smul.with.overflow
+ spu_si_a, // llvm.spu.si.a
+ spu_si_addx, // llvm.spu.si.addx
+ spu_si_ah, // llvm.spu.si.ah
+ spu_si_ahi, // llvm.spu.si.ahi
+ spu_si_ai, // llvm.spu.si.ai
+ spu_si_and, // llvm.spu.si.and
+ spu_si_andbi, // llvm.spu.si.andbi
+ spu_si_andc, // llvm.spu.si.andc
+ spu_si_andhi, // llvm.spu.si.andhi
+ spu_si_andi, // llvm.spu.si.andi
+ spu_si_bg, // llvm.spu.si.bg
+ spu_si_bgx, // llvm.spu.si.bgx
+ spu_si_ceq, // llvm.spu.si.ceq
+ spu_si_ceqb, // llvm.spu.si.ceqb
+ spu_si_ceqbi, // llvm.spu.si.ceqbi
+ spu_si_ceqh, // llvm.spu.si.ceqh
+ spu_si_ceqhi, // llvm.spu.si.ceqhi
+ spu_si_ceqi, // llvm.spu.si.ceqi
+ spu_si_cg, // llvm.spu.si.cg
+ spu_si_cgt, // llvm.spu.si.cgt
+ spu_si_cgtb, // llvm.spu.si.cgtb
+ spu_si_cgtbi, // llvm.spu.si.cgtbi
+ spu_si_cgth, // llvm.spu.si.cgth
+ spu_si_cgthi, // llvm.spu.si.cgthi
+ spu_si_cgti, // llvm.spu.si.cgti
+ spu_si_cgx, // llvm.spu.si.cgx
+ spu_si_clgt, // llvm.spu.si.clgt
+ spu_si_clgtb, // llvm.spu.si.clgtb
+ spu_si_clgtbi, // llvm.spu.si.clgtbi
+ spu_si_clgth, // llvm.spu.si.clgth
+ spu_si_clgthi, // llvm.spu.si.clgthi
+ spu_si_clgti, // llvm.spu.si.clgti
+ spu_si_dfa, // llvm.spu.si.dfa
+ spu_si_dfm, // llvm.spu.si.dfm
+ spu_si_dfma, // llvm.spu.si.dfma
+ spu_si_dfms, // llvm.spu.si.dfms
+ spu_si_dfnma, // llvm.spu.si.dfnma
+ spu_si_dfnms, // llvm.spu.si.dfnms
+ spu_si_dfs, // llvm.spu.si.dfs
+ spu_si_fa, // llvm.spu.si.fa
+ spu_si_fceq, // llvm.spu.si.fceq
+ spu_si_fcgt, // llvm.spu.si.fcgt
+ spu_si_fcmeq, // llvm.spu.si.fcmeq
+ spu_si_fcmgt, // llvm.spu.si.fcmgt
+ spu_si_fm, // llvm.spu.si.fm
+ spu_si_fma, // llvm.spu.si.fma
+ spu_si_fms, // llvm.spu.si.fms
+ spu_si_fnms, // llvm.spu.si.fnms
+ spu_si_fs, // llvm.spu.si.fs
+ spu_si_fsmbi, // llvm.spu.si.fsmbi
+ spu_si_mpy, // llvm.spu.si.mpy
+ spu_si_mpya, // llvm.spu.si.mpya
+ spu_si_mpyh, // llvm.spu.si.mpyh
+ spu_si_mpyhh, // llvm.spu.si.mpyhh
+ spu_si_mpyhha, // llvm.spu.si.mpyhha
+ spu_si_mpyhhau, // llvm.spu.si.mpyhhau
+ spu_si_mpyhhu, // llvm.spu.si.mpyhhu
+ spu_si_mpyi, // llvm.spu.si.mpyi
+ spu_si_mpys, // llvm.spu.si.mpys
+ spu_si_mpyu, // llvm.spu.si.mpyu
+ spu_si_mpyui, // llvm.spu.si.mpyui
+ spu_si_nand, // llvm.spu.si.nand
+ spu_si_nor, // llvm.spu.si.nor
+ spu_si_or, // llvm.spu.si.or
+ spu_si_orbi, // llvm.spu.si.orbi
+ spu_si_orc, // llvm.spu.si.orc
+ spu_si_orhi, // llvm.spu.si.orhi
+ spu_si_ori, // llvm.spu.si.ori
+ spu_si_sf, // llvm.spu.si.sf
+ spu_si_sfh, // llvm.spu.si.sfh
+ spu_si_sfhi, // llvm.spu.si.sfhi
+ spu_si_sfi, // llvm.spu.si.sfi
+ spu_si_sfx, // llvm.spu.si.sfx
+ spu_si_shli, // llvm.spu.si.shli
+ spu_si_shlqbi, // llvm.spu.si.shlqbi
+ spu_si_shlqbii, // llvm.spu.si.shlqbii
+ spu_si_shlqby, // llvm.spu.si.shlqby
+ spu_si_shlqbyi, // llvm.spu.si.shlqbyi
+ spu_si_xor, // llvm.spu.si.xor
+ spu_si_xorbi, // llvm.spu.si.xorbi
+ spu_si_xorhi, // llvm.spu.si.xorhi
+ spu_si_xori, // llvm.spu.si.xori
+ sqrt, // llvm.sqrt
+ ssub_with_overflow, // llvm.ssub.with.overflow
+ stackprotector, // llvm.stackprotector
+ stackrestore, // llvm.stackrestore
+ stacksave, // llvm.stacksave
+ trap, // llvm.trap
+ uadd_with_overflow, // llvm.uadd.with.overflow
+ umul_with_overflow, // llvm.umul.with.overflow
+ usub_with_overflow, // llvm.usub.with.overflow
+ vacopy, // llvm.va_copy
+ vaend, // llvm.va_end
+ var_annotation, // llvm.var.annotation
+ vastart, // llvm.va_start
+ x86_mmx_emms, // llvm.x86.mmx.emms
+ x86_mmx_femms, // llvm.x86.mmx.femms
+ x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq
+ x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq
+ x86_mmx_packssdw, // llvm.x86.mmx.packssdw
+ x86_mmx_packsswb, // llvm.x86.mmx.packsswb
+ x86_mmx_packuswb, // llvm.x86.mmx.packuswb
+ x86_mmx_padds_b, // llvm.x86.mmx.padds.b
+ x86_mmx_padds_w, // llvm.x86.mmx.padds.w
+ x86_mmx_paddus_b, // llvm.x86.mmx.paddus.b
+ x86_mmx_paddus_w, // llvm.x86.mmx.paddus.w
+ x86_mmx_pavg_b, // llvm.x86.mmx.pavg.b
+ x86_mmx_pavg_w, // llvm.x86.mmx.pavg.w
+ x86_mmx_pcmpeq_b, // llvm.x86.mmx.pcmpeq.b
+ x86_mmx_pcmpeq_d, // llvm.x86.mmx.pcmpeq.d
+ x86_mmx_pcmpeq_w, // llvm.x86.mmx.pcmpeq.w
+ x86_mmx_pcmpgt_b, // llvm.x86.mmx.pcmpgt.b
+ x86_mmx_pcmpgt_d, // llvm.x86.mmx.pcmpgt.d
+ x86_mmx_pcmpgt_w, // llvm.x86.mmx.pcmpgt.w
+ x86_mmx_pmadd_wd, // llvm.x86.mmx.pmadd.wd
+ x86_mmx_pmaxs_w, // llvm.x86.mmx.pmaxs.w
+ x86_mmx_pmaxu_b, // llvm.x86.mmx.pmaxu.b
+ x86_mmx_pmins_w, // llvm.x86.mmx.pmins.w
+ x86_mmx_pminu_b, // llvm.x86.mmx.pminu.b
+ x86_mmx_pmovmskb, // llvm.x86.mmx.pmovmskb
+ x86_mmx_pmulh_w, // llvm.x86.mmx.pmulh.w
+ x86_mmx_pmulhu_w, // llvm.x86.mmx.pmulhu.w
+ x86_mmx_pmulu_dq, // llvm.x86.mmx.pmulu.dq
+ x86_mmx_psad_bw, // llvm.x86.mmx.psad.bw
+ x86_mmx_psll_d, // llvm.x86.mmx.psll.d
+ x86_mmx_psll_q, // llvm.x86.mmx.psll.q
+ x86_mmx_psll_w, // llvm.x86.mmx.psll.w
+ x86_mmx_pslli_d, // llvm.x86.mmx.pslli.d
+ x86_mmx_pslli_q, // llvm.x86.mmx.pslli.q
+ x86_mmx_pslli_w, // llvm.x86.mmx.pslli.w
+ x86_mmx_psra_d, // llvm.x86.mmx.psra.d
+ x86_mmx_psra_w, // llvm.x86.mmx.psra.w
+ x86_mmx_psrai_d, // llvm.x86.mmx.psrai.d
+ x86_mmx_psrai_w, // llvm.x86.mmx.psrai.w
+ x86_mmx_psrl_d, // llvm.x86.mmx.psrl.d
+ x86_mmx_psrl_q, // llvm.x86.mmx.psrl.q
+ x86_mmx_psrl_w, // llvm.x86.mmx.psrl.w
+ x86_mmx_psrli_d, // llvm.x86.mmx.psrli.d
+ x86_mmx_psrli_q, // llvm.x86.mmx.psrli.q
+ x86_mmx_psrli_w, // llvm.x86.mmx.psrli.w
+ x86_mmx_psubs_b, // llvm.x86.mmx.psubs.b
+ x86_mmx_psubs_w, // llvm.x86.mmx.psubs.w
+ x86_mmx_psubus_b, // llvm.x86.mmx.psubus.b
+ x86_mmx_psubus_w, // llvm.x86.mmx.psubus.w
+ x86_sse2_add_sd, // llvm.x86.sse2.add.sd
+ x86_sse2_clflush, // llvm.x86.sse2.clflush
+ x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd
+ x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd
+ x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd
+ x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd
+ x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd
+ x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd
+ x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd
+ x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd
+ x86_sse2_cvtdq2pd, // llvm.x86.sse2.cvtdq2pd
+ x86_sse2_cvtdq2ps, // llvm.x86.sse2.cvtdq2ps
+ x86_sse2_cvtpd2dq, // llvm.x86.sse2.cvtpd2dq
+ x86_sse2_cvtpd2ps, // llvm.x86.sse2.cvtpd2ps
+ x86_sse2_cvtps2dq, // llvm.x86.sse2.cvtps2dq
+ x86_sse2_cvtps2pd, // llvm.x86.sse2.cvtps2pd
+ x86_sse2_cvtsd2si, // llvm.x86.sse2.cvtsd2si
+ x86_sse2_cvtsd2si64, // llvm.x86.sse2.cvtsd2si64
+ x86_sse2_cvtsd2ss, // llvm.x86.sse2.cvtsd2ss
+ x86_sse2_cvtsi2sd, // llvm.x86.sse2.cvtsi2sd
+ x86_sse2_cvtsi642sd, // llvm.x86.sse2.cvtsi642sd
+ x86_sse2_cvtss2sd, // llvm.x86.sse2.cvtss2sd
+ x86_sse2_cvttpd2dq, // llvm.x86.sse2.cvttpd2dq
+ x86_sse2_cvttps2dq, // llvm.x86.sse2.cvttps2dq
+ x86_sse2_cvttsd2si, // llvm.x86.sse2.cvttsd2si
+ x86_sse2_cvttsd2si64, // llvm.x86.sse2.cvttsd2si64
+ x86_sse2_div_sd, // llvm.x86.sse2.div.sd
+ x86_sse2_lfence, // llvm.x86.sse2.lfence
+ x86_sse2_loadu_dq, // llvm.x86.sse2.loadu.dq
+ x86_sse2_loadu_pd, // llvm.x86.sse2.loadu.pd
+ x86_sse2_maskmov_dqu, // llvm.x86.sse2.maskmov.dqu
+ x86_sse2_max_pd, // llvm.x86.sse2.max.pd
+ x86_sse2_max_sd, // llvm.x86.sse2.max.sd
+ x86_sse2_mfence, // llvm.x86.sse2.mfence
+ x86_sse2_min_pd, // llvm.x86.sse2.min.pd
+ x86_sse2_min_sd, // llvm.x86.sse2.min.sd
+ x86_sse2_movmsk_pd, // llvm.x86.sse2.movmsk.pd
+ x86_sse2_movnt_dq, // llvm.x86.sse2.movnt.dq
+ x86_sse2_movnt_i, // llvm.x86.sse2.movnt.i
+ x86_sse2_movnt_pd, // llvm.x86.sse2.movnt.pd
+ x86_sse2_mul_sd, // llvm.x86.sse2.mul.sd
+ x86_sse2_packssdw_128, // llvm.x86.sse2.packssdw.128
+ x86_sse2_packsswb_128, // llvm.x86.sse2.packsswb.128
+ x86_sse2_packuswb_128, // llvm.x86.sse2.packuswb.128
+ x86_sse2_padds_b, // llvm.x86.sse2.padds.b
+ x86_sse2_padds_w, // llvm.x86.sse2.padds.w
+ x86_sse2_paddus_b, // llvm.x86.sse2.paddus.b
+ x86_sse2_paddus_w, // llvm.x86.sse2.paddus.w
+ x86_sse2_pavg_b, // llvm.x86.sse2.pavg.b
+ x86_sse2_pavg_w, // llvm.x86.sse2.pavg.w
+ x86_sse2_pcmpeq_b, // llvm.x86.sse2.pcmpeq.b
+ x86_sse2_pcmpeq_d, // llvm.x86.sse2.pcmpeq.d
+ x86_sse2_pcmpeq_w, // llvm.x86.sse2.pcmpeq.w
+ x86_sse2_pcmpgt_b, // llvm.x86.sse2.pcmpgt.b
+ x86_sse2_pcmpgt_d, // llvm.x86.sse2.pcmpgt.d
+ x86_sse2_pcmpgt_w, // llvm.x86.sse2.pcmpgt.w
+ x86_sse2_pmadd_wd, // llvm.x86.sse2.pmadd.wd
+ x86_sse2_pmaxs_w, // llvm.x86.sse2.pmaxs.w
+ x86_sse2_pmaxu_b, // llvm.x86.sse2.pmaxu.b
+ x86_sse2_pmins_w, // llvm.x86.sse2.pmins.w
+ x86_sse2_pminu_b, // llvm.x86.sse2.pminu.b
+ x86_sse2_pmovmskb_128, // llvm.x86.sse2.pmovmskb.128
+ x86_sse2_pmulh_w, // llvm.x86.sse2.pmulh.w
+ x86_sse2_pmulhu_w, // llvm.x86.sse2.pmulhu.w
+ x86_sse2_pmulu_dq, // llvm.x86.sse2.pmulu.dq
+ x86_sse2_psad_bw, // llvm.x86.sse2.psad.bw
+ x86_sse2_psll_d, // llvm.x86.sse2.psll.d
+ x86_sse2_psll_dq, // llvm.x86.sse2.psll.dq
+ x86_sse2_psll_dq_bs, // llvm.x86.sse2.psll.dq.bs
+ x86_sse2_psll_q, // llvm.x86.sse2.psll.q
+ x86_sse2_psll_w, // llvm.x86.sse2.psll.w
+ x86_sse2_pslli_d, // llvm.x86.sse2.pslli.d
+ x86_sse2_pslli_q, // llvm.x86.sse2.pslli.q
+ x86_sse2_pslli_w, // llvm.x86.sse2.pslli.w
+ x86_sse2_psra_d, // llvm.x86.sse2.psra.d
+ x86_sse2_psra_w, // llvm.x86.sse2.psra.w
+ x86_sse2_psrai_d, // llvm.x86.sse2.psrai.d
+ x86_sse2_psrai_w, // llvm.x86.sse2.psrai.w
+ x86_sse2_psrl_d, // llvm.x86.sse2.psrl.d
+ x86_sse2_psrl_dq, // llvm.x86.sse2.psrl.dq
+ x86_sse2_psrl_dq_bs, // llvm.x86.sse2.psrl.dq.bs
+ x86_sse2_psrl_q, // llvm.x86.sse2.psrl.q
+ x86_sse2_psrl_w, // llvm.x86.sse2.psrl.w
+ x86_sse2_psrli_d, // llvm.x86.sse2.psrli.d
+ x86_sse2_psrli_q, // llvm.x86.sse2.psrli.q
+ x86_sse2_psrli_w, // llvm.x86.sse2.psrli.w
+ x86_sse2_psubs_b, // llvm.x86.sse2.psubs.b
+ x86_sse2_psubs_w, // llvm.x86.sse2.psubs.w
+ x86_sse2_psubus_b, // llvm.x86.sse2.psubus.b
+ x86_sse2_psubus_w, // llvm.x86.sse2.psubus.w
+ x86_sse2_sqrt_pd, // llvm.x86.sse2.sqrt.pd
+ x86_sse2_sqrt_sd, // llvm.x86.sse2.sqrt.sd
+ x86_sse2_storel_dq, // llvm.x86.sse2.storel.dq
+ x86_sse2_storeu_dq, // llvm.x86.sse2.storeu.dq
+ x86_sse2_storeu_pd, // llvm.x86.sse2.storeu.pd
+ x86_sse2_sub_sd, // llvm.x86.sse2.sub.sd
+ x86_sse2_ucomieq_sd, // llvm.x86.sse2.ucomieq.sd
+ x86_sse2_ucomige_sd, // llvm.x86.sse2.ucomige.sd
+ x86_sse2_ucomigt_sd, // llvm.x86.sse2.ucomigt.sd
+ x86_sse2_ucomile_sd, // llvm.x86.sse2.ucomile.sd
+ x86_sse2_ucomilt_sd, // llvm.x86.sse2.ucomilt.sd
+ x86_sse2_ucomineq_sd, // llvm.x86.sse2.ucomineq.sd
+ x86_sse3_addsub_pd, // llvm.x86.sse3.addsub.pd
+ x86_sse3_addsub_ps, // llvm.x86.sse3.addsub.ps
+ x86_sse3_hadd_pd, // llvm.x86.sse3.hadd.pd
+ x86_sse3_hadd_ps, // llvm.x86.sse3.hadd.ps
+ x86_sse3_hsub_pd, // llvm.x86.sse3.hsub.pd
+ x86_sse3_hsub_ps, // llvm.x86.sse3.hsub.ps
+ x86_sse3_ldu_dq, // llvm.x86.sse3.ldu.dq
+ x86_sse3_monitor, // llvm.x86.sse3.monitor
+ x86_sse3_mwait, // llvm.x86.sse3.mwait
+ x86_sse41_blendpd, // llvm.x86.sse41.blendpd
+ x86_sse41_blendps, // llvm.x86.sse41.blendps
+ x86_sse41_blendvpd, // llvm.x86.sse41.blendvpd
+ x86_sse41_blendvps, // llvm.x86.sse41.blendvps
+ x86_sse41_dppd, // llvm.x86.sse41.dppd
+ x86_sse41_dpps, // llvm.x86.sse41.dpps
+ x86_sse41_extractps, // llvm.x86.sse41.extractps
+ x86_sse41_insertps, // llvm.x86.sse41.insertps
+ x86_sse41_movntdqa, // llvm.x86.sse41.movntdqa
+ x86_sse41_mpsadbw, // llvm.x86.sse41.mpsadbw
+ x86_sse41_packusdw, // llvm.x86.sse41.packusdw
+ x86_sse41_pblendvb, // llvm.x86.sse41.pblendvb
+ x86_sse41_pblendw, // llvm.x86.sse41.pblendw
+ x86_sse41_pcmpeqq, // llvm.x86.sse41.pcmpeqq
+ x86_sse41_pextrb, // llvm.x86.sse41.pextrb
+ x86_sse41_pextrd, // llvm.x86.sse41.pextrd
+ x86_sse41_pextrq, // llvm.x86.sse41.pextrq
+ x86_sse41_phminposuw, // llvm.x86.sse41.phminposuw
+ x86_sse41_pmaxsb, // llvm.x86.sse41.pmaxsb
+ x86_sse41_pmaxsd, // llvm.x86.sse41.pmaxsd
+ x86_sse41_pmaxud, // llvm.x86.sse41.pmaxud
+ x86_sse41_pmaxuw, // llvm.x86.sse41.pmaxuw
+ x86_sse41_pminsb, // llvm.x86.sse41.pminsb
+ x86_sse41_pminsd, // llvm.x86.sse41.pminsd
+ x86_sse41_pminud, // llvm.x86.sse41.pminud
+ x86_sse41_pminuw, // llvm.x86.sse41.pminuw
+ x86_sse41_pmovsxbd, // llvm.x86.sse41.pmovsxbd
+ x86_sse41_pmovsxbq, // llvm.x86.sse41.pmovsxbq
+ x86_sse41_pmovsxbw, // llvm.x86.sse41.pmovsxbw
+ x86_sse41_pmovsxdq, // llvm.x86.sse41.pmovsxdq
+ x86_sse41_pmovsxwd, // llvm.x86.sse41.pmovsxwd
+ x86_sse41_pmovsxwq, // llvm.x86.sse41.pmovsxwq
+ x86_sse41_pmovzxbd, // llvm.x86.sse41.pmovzxbd
+ x86_sse41_pmovzxbq, // llvm.x86.sse41.pmovzxbq
+ x86_sse41_pmovzxbw, // llvm.x86.sse41.pmovzxbw
+ x86_sse41_pmovzxdq, // llvm.x86.sse41.pmovzxdq
+ x86_sse41_pmovzxwd, // llvm.x86.sse41.pmovzxwd
+ x86_sse41_pmovzxwq, // llvm.x86.sse41.pmovzxwq
+ x86_sse41_pmuldq, // llvm.x86.sse41.pmuldq
+ x86_sse41_pmulld, // llvm.x86.sse41.pmulld
+ x86_sse41_ptestc, // llvm.x86.sse41.ptestc
+ x86_sse41_ptestnzc, // llvm.x86.sse41.ptestnzc
+ x86_sse41_ptestz, // llvm.x86.sse41.ptestz
+ x86_sse41_round_pd, // llvm.x86.sse41.round.pd
+ x86_sse41_round_ps, // llvm.x86.sse41.round.ps
+ x86_sse41_round_sd, // llvm.x86.sse41.round.sd
+ x86_sse41_round_ss, // llvm.x86.sse41.round.ss
+ x86_sse42_crc32_16, // llvm.x86.sse42.crc32.16
+ x86_sse42_crc32_32, // llvm.x86.sse42.crc32.32
+ x86_sse42_crc32_64, // llvm.x86.sse42.crc32.64
+ x86_sse42_crc32_8, // llvm.x86.sse42.crc32.8
+ x86_sse42_pcmpestri128, // llvm.x86.sse42.pcmpestri128
+ x86_sse42_pcmpestria128, // llvm.x86.sse42.pcmpestria128
+ x86_sse42_pcmpestric128, // llvm.x86.sse42.pcmpestric128
+ x86_sse42_pcmpestrio128, // llvm.x86.sse42.pcmpestrio128
+ x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris128
+ x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz128
+ x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm128
+ x86_sse42_pcmpgtq, // llvm.x86.sse42.pcmpgtq
+ x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri128
+ x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria128
+ x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric128
+ x86_sse42_pcmpistrio128, // llvm.x86.sse42.pcmpistrio128
+ x86_sse42_pcmpistris128, // llvm.x86.sse42.pcmpistris128
+ x86_sse42_pcmpistriz128, // llvm.x86.sse42.pcmpistriz128
+ x86_sse42_pcmpistrm128, // llvm.x86.sse42.pcmpistrm128
+ x86_sse_add_ss, // llvm.x86.sse.add.ss
+ x86_sse_cmp_ps, // llvm.x86.sse.cmp.ps
+ x86_sse_cmp_ss, // llvm.x86.sse.cmp.ss
+ x86_sse_comieq_ss, // llvm.x86.sse.comieq.ss
+ x86_sse_comige_ss, // llvm.x86.sse.comige.ss
+ x86_sse_comigt_ss, // llvm.x86.sse.comigt.ss
+ x86_sse_comile_ss, // llvm.x86.sse.comile.ss
+ x86_sse_comilt_ss, // llvm.x86.sse.comilt.ss
+ x86_sse_comineq_ss, // llvm.x86.sse.comineq.ss
+ x86_sse_cvtpd2pi, // llvm.x86.sse.cvtpd2pi
+ x86_sse_cvtpi2pd, // llvm.x86.sse.cvtpi2pd
+ x86_sse_cvtpi2ps, // llvm.x86.sse.cvtpi2ps
+ x86_sse_cvtps2pi, // llvm.x86.sse.cvtps2pi
+ x86_sse_cvtsi2ss, // llvm.x86.sse.cvtsi2ss
+ x86_sse_cvtsi642ss, // llvm.x86.sse.cvtsi642ss
+ x86_sse_cvtss2si, // llvm.x86.sse.cvtss2si
+ x86_sse_cvtss2si64, // llvm.x86.sse.cvtss2si64
+ x86_sse_cvttpd2pi, // llvm.x86.sse.cvttpd2pi
+ x86_sse_cvttps2pi, // llvm.x86.sse.cvttps2pi
+ x86_sse_cvttss2si, // llvm.x86.sse.cvttss2si
+ x86_sse_cvttss2si64, // llvm.x86.sse.cvttss2si64
+ x86_sse_div_ss, // llvm.x86.sse.div.ss
+ x86_sse_ldmxcsr, // llvm.x86.sse.ldmxcsr
+ x86_sse_loadu_ps, // llvm.x86.sse.loadu.ps
+ x86_sse_max_ps, // llvm.x86.sse.max.ps
+ x86_sse_max_ss, // llvm.x86.sse.max.ss
+ x86_sse_min_ps, // llvm.x86.sse.min.ps
+ x86_sse_min_ss, // llvm.x86.sse.min.ss
+ x86_sse_movmsk_ps, // llvm.x86.sse.movmsk.ps
+ x86_sse_movnt_ps, // llvm.x86.sse.movnt.ps
+ x86_sse_mul_ss, // llvm.x86.sse.mul.ss
+ x86_sse_rcp_ps, // llvm.x86.sse.rcp.ps
+ x86_sse_rcp_ss, // llvm.x86.sse.rcp.ss
+ x86_sse_rsqrt_ps, // llvm.x86.sse.rsqrt.ps
+ x86_sse_rsqrt_ss, // llvm.x86.sse.rsqrt.ss
+ x86_sse_sfence, // llvm.x86.sse.sfence
+ x86_sse_sqrt_ps, // llvm.x86.sse.sqrt.ps
+ x86_sse_sqrt_ss, // llvm.x86.sse.sqrt.ss
+ x86_sse_stmxcsr, // llvm.x86.sse.stmxcsr
+ x86_sse_storeu_ps, // llvm.x86.sse.storeu.ps
+ x86_sse_sub_ss, // llvm.x86.sse.sub.ss
+ x86_sse_ucomieq_ss, // llvm.x86.sse.ucomieq.ss
+ x86_sse_ucomige_ss, // llvm.x86.sse.ucomige.ss
+ x86_sse_ucomigt_ss, // llvm.x86.sse.ucomigt.ss
+ x86_sse_ucomile_ss, // llvm.x86.sse.ucomile.ss
+ x86_sse_ucomilt_ss, // llvm.x86.sse.ucomilt.ss
+ x86_sse_ucomineq_ss, // llvm.x86.sse.ucomineq.ss
+ x86_ssse3_pabs_b, // llvm.x86.ssse3.pabs.b
+ x86_ssse3_pabs_b_128, // llvm.x86.ssse3.pabs.b.128
+ x86_ssse3_pabs_d, // llvm.x86.ssse3.pabs.d
+ x86_ssse3_pabs_d_128, // llvm.x86.ssse3.pabs.d.128
+ x86_ssse3_pabs_w, // llvm.x86.ssse3.pabs.w
+ x86_ssse3_pabs_w_128, // llvm.x86.ssse3.pabs.w.128
+ x86_ssse3_palign_r, // llvm.x86.ssse3.palign.r
+ x86_ssse3_palign_r_128, // llvm.x86.ssse3.palign.r.128
+ x86_ssse3_phadd_d, // llvm.x86.ssse3.phadd.d
+ x86_ssse3_phadd_d_128, // llvm.x86.ssse3.phadd.d.128
+ x86_ssse3_phadd_sw, // llvm.x86.ssse3.phadd.sw
+ x86_ssse3_phadd_sw_128, // llvm.x86.ssse3.phadd.sw.128
+ x86_ssse3_phadd_w, // llvm.x86.ssse3.phadd.w
+ x86_ssse3_phadd_w_128, // llvm.x86.ssse3.phadd.w.128
+ x86_ssse3_phsub_d, // llvm.x86.ssse3.phsub.d
+ x86_ssse3_phsub_d_128, // llvm.x86.ssse3.phsub.d.128
+ x86_ssse3_phsub_sw, // llvm.x86.ssse3.phsub.sw
+ x86_ssse3_phsub_sw_128, // llvm.x86.ssse3.phsub.sw.128
+ x86_ssse3_phsub_w, // llvm.x86.ssse3.phsub.w
+ x86_ssse3_phsub_w_128, // llvm.x86.ssse3.phsub.w.128
+ x86_ssse3_pmadd_ub_sw, // llvm.x86.ssse3.pmadd.ub.sw
+ x86_ssse3_pmadd_ub_sw_128, // llvm.x86.ssse3.pmadd.ub.sw.128
+ x86_ssse3_pmul_hr_sw, // llvm.x86.ssse3.pmul.hr.sw
+ x86_ssse3_pmul_hr_sw_128, // llvm.x86.ssse3.pmul.hr.sw.128
+ x86_ssse3_pshuf_b, // llvm.x86.ssse3.pshuf.b
+ x86_ssse3_pshuf_b_128, // llvm.x86.ssse3.pshuf.b.128
+ x86_ssse3_psign_b, // llvm.x86.ssse3.psign.b
+ x86_ssse3_psign_b_128, // llvm.x86.ssse3.psign.b.128
+ x86_ssse3_psign_d, // llvm.x86.ssse3.psign.d
+ x86_ssse3_psign_d_128, // llvm.x86.ssse3.psign.d.128
+ x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w
+ x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128
+ xcore_bitrev, // llvm.xcore.bitrev
+ xcore_getid // llvm.xcore.getid
+#endif
+
+// Intrinsic ID to name table
+#ifdef GET_INTRINSIC_NAME_TABLE
+ // Note that entry #0 is the invalid intrinsic!
+ "llvm.alpha.umulh",
+ "llvm.annotation",
+ "llvm.arm.neon.vabals",
+ "llvm.arm.neon.vabalu",
+ "llvm.arm.neon.vabas",
+ "llvm.arm.neon.vabau",
+ "llvm.arm.neon.vabdls",
+ "llvm.arm.neon.vabdlu",
+ "llvm.arm.neon.vabds",
+ "llvm.arm.neon.vabdu",
+ "llvm.arm.neon.vabs",
+ "llvm.arm.neon.vacged",
+ "llvm.arm.neon.vacgeq",
+ "llvm.arm.neon.vacgtd",
+ "llvm.arm.neon.vacgtq",
+ "llvm.arm.neon.vaddhn",
+ "llvm.arm.neon.vaddls",
+ "llvm.arm.neon.vaddlu",
+ "llvm.arm.neon.vaddws",
+ "llvm.arm.neon.vaddwu",
+ "llvm.arm.neon.vcls",
+ "llvm.arm.neon.vclz",
+ "llvm.arm.neon.vcnt",
+ "llvm.arm.neon.vcvtfp2fxs",
+ "llvm.arm.neon.vcvtfp2fxu",
+ "llvm.arm.neon.vcvtfxs2fp",
+ "llvm.arm.neon.vcvtfxu2fp",
+ "llvm.arm.neon.vhadds",
+ "llvm.arm.neon.vhaddu",
+ "llvm.arm.neon.vhsubs",
+ "llvm.arm.neon.vhsubu",
+ "llvm.arm.neon.vld1",
+ "llvm.arm.neon.vld2",
+ "llvm.arm.neon.vld2lane",
+ "llvm.arm.neon.vld3",
+ "llvm.arm.neon.vld3lane",
+ "llvm.arm.neon.vld4",
+ "llvm.arm.neon.vld4lane",
+ "llvm.arm.neon.vmaxs",
+ "llvm.arm.neon.vmaxu",
+ "llvm.arm.neon.vmins",
+ "llvm.arm.neon.vminu",
+ "llvm.arm.neon.vmlals",
+ "llvm.arm.neon.vmlalu",
+ "llvm.arm.neon.vmlsls",
+ "llvm.arm.neon.vmlslu",
+ "llvm.arm.neon.vmovls",
+ "llvm.arm.neon.vmovlu",
+ "llvm.arm.neon.vmovn",
+ "llvm.arm.neon.vmullp",
+ "llvm.arm.neon.vmulls",
+ "llvm.arm.neon.vmullu",
+ "llvm.arm.neon.vmulp",
+ "llvm.arm.neon.vpadals",
+ "llvm.arm.neon.vpadalu",
+ "llvm.arm.neon.vpadd",
+ "llvm.arm.neon.vpaddls",
+ "llvm.arm.neon.vpaddlu",
+ "llvm.arm.neon.vpmaxs",
+ "llvm.arm.neon.vpmaxu",
+ "llvm.arm.neon.vpmins",
+ "llvm.arm.neon.vpminu",
+ "llvm.arm.neon.vqabs",
+ "llvm.arm.neon.vqadds",
+ "llvm.arm.neon.vqaddu",
+ "llvm.arm.neon.vqdmlal",
+ "llvm.arm.neon.vqdmlsl",
+ "llvm.arm.neon.vqdmulh",
+ "llvm.arm.neon.vqdmull",
+ "llvm.arm.neon.vqmovns",
+ "llvm.arm.neon.vqmovnsu",
+ "llvm.arm.neon.vqmovnu",
+ "llvm.arm.neon.vqneg",
+ "llvm.arm.neon.vqrdmulh",
+ "llvm.arm.neon.vqrshiftns",
+ "llvm.arm.neon.vqrshiftnsu",
+ "llvm.arm.neon.vqrshiftnu",
+ "llvm.arm.neon.vqrshifts",
+ "llvm.arm.neon.vqrshiftu",
+ "llvm.arm.neon.vqshiftns",
+ "llvm.arm.neon.vqshiftnsu",
+ "llvm.arm.neon.vqshiftnu",
+ "llvm.arm.neon.vqshifts",
+ "llvm.arm.neon.vqshiftsu",
+ "llvm.arm.neon.vqshiftu",
+ "llvm.arm.neon.vqsubs",
+ "llvm.arm.neon.vqsubu",
+ "llvm.arm.neon.vraddhn",
+ "llvm.arm.neon.vrecpe",
+ "llvm.arm.neon.vrecps",
+ "llvm.arm.neon.vrhadds",
+ "llvm.arm.neon.vrhaddu",
+ "llvm.arm.neon.vrshiftn",
+ "llvm.arm.neon.vrshifts",
+ "llvm.arm.neon.vrshiftu",
+ "llvm.arm.neon.vrsqrte",
+ "llvm.arm.neon.vrsqrts",
+ "llvm.arm.neon.vrsubhn",
+ "llvm.arm.neon.vshiftins",
+ "llvm.arm.neon.vshiftls",
+ "llvm.arm.neon.vshiftlu",
+ "llvm.arm.neon.vshiftn",
+ "llvm.arm.neon.vshifts",
+ "llvm.arm.neon.vshiftu",
+ "llvm.arm.neon.vst1",
+ "llvm.arm.neon.vst2",
+ "llvm.arm.neon.vst2lane",
+ "llvm.arm.neon.vst3",
+ "llvm.arm.neon.vst3lane",
+ "llvm.arm.neon.vst4",
+ "llvm.arm.neon.vst4lane",
+ "llvm.arm.neon.vsubhn",
+ "llvm.arm.neon.vsubls",
+ "llvm.arm.neon.vsublu",
+ "llvm.arm.neon.vsubws",
+ "llvm.arm.neon.vsubwu",
+ "llvm.arm.neon.vtbl1",
+ "llvm.arm.neon.vtbl2",
+ "llvm.arm.neon.vtbl3",
+ "llvm.arm.neon.vtbl4",
+ "llvm.arm.neon.vtbx1",
+ "llvm.arm.neon.vtbx2",
+ "llvm.arm.neon.vtbx3",
+ "llvm.arm.neon.vtbx4",
+ "llvm.arm.thread.pointer",
+ "llvm.atomic.cmp.swap",
+ "llvm.atomic.load.add",
+ "llvm.atomic.load.and",
+ "llvm.atomic.load.max",
+ "llvm.atomic.load.min",
+ "llvm.atomic.load.nand",
+ "llvm.atomic.load.or",
+ "llvm.atomic.load.sub",
+ "llvm.atomic.load.umax",
+ "llvm.atomic.load.umin",
+ "llvm.atomic.load.xor",
+ "llvm.atomic.swap",
+ "llvm.bswap",
+ "llvm.convertff",
+ "llvm.convertfsi",
+ "llvm.convertfui",
+ "llvm.convertsif",
+ "llvm.convertss",
+ "llvm.convertsu",
+ "llvm.convertuif",
+ "llvm.convertus",
+ "llvm.convertuu",
+ "llvm.cos",
+ "llvm.ctlz",
+ "llvm.ctpop",
+ "llvm.cttz",
+ "llvm.dbg.declare",
+ "llvm.dbg.func.start",
+ "llvm.dbg.region.end",
+ "llvm.dbg.region.start",
+ "llvm.dbg.stoppoint",
+ "llvm.dbg.value",
+ "llvm.eh.dwarf.cfa",
+ "llvm.eh.exception",
+ "llvm.eh.return.i32",
+ "llvm.eh.return.i64",
+ "llvm.eh.selector",
+ "llvm.eh.sjlj.longjmp",
+ "llvm.eh.sjlj.lsda",
+ "llvm.eh.sjlj.setjmp",
+ "llvm.eh.typeid.for",
+ "llvm.eh.unwind.init",
+ "llvm.exp",
+ "llvm.exp2",
+ "llvm.flt.rounds",
+ "llvm.frameaddress",
+ "llvm.gcread",
+ "llvm.gcroot",
+ "llvm.gcwrite",
+ "llvm.init.trampoline",
+ "llvm.invariant.end",
+ "llvm.invariant.start",
+ "llvm.lifetime.end",
+ "llvm.lifetime.start",
+ "llvm.log",
+ "llvm.log10",
+ "llvm.log2",
+ "llvm.longjmp",
+ "llvm.memcpy",
+ "llvm.memmove",
+ "llvm.memory.barrier",
+ "llvm.memset",
+ "llvm.objectsize",
+ "llvm.pcmarker",
+ "llvm.pow",
+ "llvm.powi",
+ "llvm.ppc.altivec.dss",
+ "llvm.ppc.altivec.dssall",
+ "llvm.ppc.altivec.dst",
+ "llvm.ppc.altivec.dstst",
+ "llvm.ppc.altivec.dststt",
+ "llvm.ppc.altivec.dstt",
+ "llvm.ppc.altivec.lvebx",
+ "llvm.ppc.altivec.lvehx",
+ "llvm.ppc.altivec.lvewx",
+ "llvm.ppc.altivec.lvsl",
+ "llvm.ppc.altivec.lvsr",
+ "llvm.ppc.altivec.lvx",
+ "llvm.ppc.altivec.lvxl",
+ "llvm.ppc.altivec.mfvscr",
+ "llvm.ppc.altivec.mtvscr",
+ "llvm.ppc.altivec.stvebx",
+ "llvm.ppc.altivec.stvehx",
+ "llvm.ppc.altivec.stvewx",
+ "llvm.ppc.altivec.stvx",
+ "llvm.ppc.altivec.stvxl",
+ "llvm.ppc.altivec.vaddcuw",
+ "llvm.ppc.altivec.vaddsbs",
+ "llvm.ppc.altivec.vaddshs",
+ "llvm.ppc.altivec.vaddsws",
+ "llvm.ppc.altivec.vaddubs",
+ "llvm.ppc.altivec.vadduhs",
+ "llvm.ppc.altivec.vadduws",
+ "llvm.ppc.altivec.vavgsb",
+ "llvm.ppc.altivec.vavgsh",
+ "llvm.ppc.altivec.vavgsw",
+ "llvm.ppc.altivec.vavgub",
+ "llvm.ppc.altivec.vavguh",
+ "llvm.ppc.altivec.vavguw",
+ "llvm.ppc.altivec.vcfsx",
+ "llvm.ppc.altivec.vcfux",
+ "llvm.ppc.altivec.vcmpbfp",
+ "llvm.ppc.altivec.vcmpbfp.p",
+ "llvm.ppc.altivec.vcmpeqfp",
+ "llvm.ppc.altivec.vcmpeqfp.p",
+ "llvm.ppc.altivec.vcmpequb",
+ "llvm.ppc.altivec.vcmpequb.p",
+ "llvm.ppc.altivec.vcmpequh",
+ "llvm.ppc.altivec.vcmpequh.p",
+ "llvm.ppc.altivec.vcmpequw",
+ "llvm.ppc.altivec.vcmpequw.p",
+ "llvm.ppc.altivec.vcmpgefp",
+ "llvm.ppc.altivec.vcmpgefp.p",
+ "llvm.ppc.altivec.vcmpgtfp",
+ "llvm.ppc.altivec.vcmpgtfp.p",
+ "llvm.ppc.altivec.vcmpgtsb",
+ "llvm.ppc.altivec.vcmpgtsb.p",
+ "llvm.ppc.altivec.vcmpgtsh",
+ "llvm.ppc.altivec.vcmpgtsh.p",
+ "llvm.ppc.altivec.vcmpgtsw",
+ "llvm.ppc.altivec.vcmpgtsw.p",
+ "llvm.ppc.altivec.vcmpgtub",
+ "llvm.ppc.altivec.vcmpgtub.p",
+ "llvm.ppc.altivec.vcmpgtuh",
+ "llvm.ppc.altivec.vcmpgtuh.p",
+ "llvm.ppc.altivec.vcmpgtuw",
+ "llvm.ppc.altivec.vcmpgtuw.p",
+ "llvm.ppc.altivec.vctsxs",
+ "llvm.ppc.altivec.vctuxs",
+ "llvm.ppc.altivec.vexptefp",
+ "llvm.ppc.altivec.vlogefp",
+ "llvm.ppc.altivec.vmaddfp",
+ "llvm.ppc.altivec.vmaxfp",
+ "llvm.ppc.altivec.vmaxsb",
+ "llvm.ppc.altivec.vmaxsh",
+ "llvm.ppc.altivec.vmaxsw",
+ "llvm.ppc.altivec.vmaxub",
+ "llvm.ppc.altivec.vmaxuh",
+ "llvm.ppc.altivec.vmaxuw",
+ "llvm.ppc.altivec.vmhaddshs",
+ "llvm.ppc.altivec.vmhraddshs",
+ "llvm.ppc.altivec.vminfp",
+ "llvm.ppc.altivec.vminsb",
+ "llvm.ppc.altivec.vminsh",
+ "llvm.ppc.altivec.vminsw",
+ "llvm.ppc.altivec.vminub",
+ "llvm.ppc.altivec.vminuh",
+ "llvm.ppc.altivec.vminuw",
+ "llvm.ppc.altivec.vmladduhm",
+ "llvm.ppc.altivec.vmsummbm",
+ "llvm.ppc.altivec.vmsumshm",
+ "llvm.ppc.altivec.vmsumshs",
+ "llvm.ppc.altivec.vmsumubm",
+ "llvm.ppc.altivec.vmsumuhm",
+ "llvm.ppc.altivec.vmsumuhs",
+ "llvm.ppc.altivec.vmulesb",
+ "llvm.ppc.altivec.vmulesh",
+ "llvm.ppc.altivec.vmuleub",
+ "llvm.ppc.altivec.vmuleuh",
+ "llvm.ppc.altivec.vmulosb",
+ "llvm.ppc.altivec.vmulosh",
+ "llvm.ppc.altivec.vmuloub",
+ "llvm.ppc.altivec.vmulouh",
+ "llvm.ppc.altivec.vnmsubfp",
+ "llvm.ppc.altivec.vperm",
+ "llvm.ppc.altivec.vpkpx",
+ "llvm.ppc.altivec.vpkshss",
+ "llvm.ppc.altivec.vpkshus",
+ "llvm.ppc.altivec.vpkswss",
+ "llvm.ppc.altivec.vpkswus",
+ "llvm.ppc.altivec.vpkuhus",
+ "llvm.ppc.altivec.vpkuwus",
+ "llvm.ppc.altivec.vrefp",
+ "llvm.ppc.altivec.vrfim",
+ "llvm.ppc.altivec.vrfin",
+ "llvm.ppc.altivec.vrfip",
+ "llvm.ppc.altivec.vrfiz",
+ "llvm.ppc.altivec.vrlb",
+ "llvm.ppc.altivec.vrlh",
+ "llvm.ppc.altivec.vrlw",
+ "llvm.ppc.altivec.vrsqrtefp",
+ "llvm.ppc.altivec.vsel",
+ "llvm.ppc.altivec.vsl",
+ "llvm.ppc.altivec.vslb",
+ "llvm.ppc.altivec.vslh",
+ "llvm.ppc.altivec.vslo",
+ "llvm.ppc.altivec.vslw",
+ "llvm.ppc.altivec.vsr",
+ "llvm.ppc.altivec.vsrab",
+ "llvm.ppc.altivec.vsrah",
+ "llvm.ppc.altivec.vsraw",
+ "llvm.ppc.altivec.vsrb",
+ "llvm.ppc.altivec.vsrh",
+ "llvm.ppc.altivec.vsro",
+ "llvm.ppc.altivec.vsrw",
+ "llvm.ppc.altivec.vsubcuw",
+ "llvm.ppc.altivec.vsubsbs",
+ "llvm.ppc.altivec.vsubshs",
+ "llvm.ppc.altivec.vsubsws",
+ "llvm.ppc.altivec.vsububs",
+ "llvm.ppc.altivec.vsubuhs",
+ "llvm.ppc.altivec.vsubuws",
+ "llvm.ppc.altivec.vsum2sws",
+ "llvm.ppc.altivec.vsum4sbs",
+ "llvm.ppc.altivec.vsum4shs",
+ "llvm.ppc.altivec.vsum4ubs",
+ "llvm.ppc.altivec.vsumsws",
+ "llvm.ppc.altivec.vupkhpx",
+ "llvm.ppc.altivec.vupkhsb",
+ "llvm.ppc.altivec.vupkhsh",
+ "llvm.ppc.altivec.vupklpx",
+ "llvm.ppc.altivec.vupklsb",
+ "llvm.ppc.altivec.vupklsh",
+ "llvm.ppc.dcba",
+ "llvm.ppc.dcbf",
+ "llvm.ppc.dcbi",
+ "llvm.ppc.dcbst",
+ "llvm.ppc.dcbt",
+ "llvm.ppc.dcbtst",
+ "llvm.ppc.dcbz",
+ "llvm.ppc.dcbzl",
+ "llvm.ppc.sync",
+ "llvm.prefetch",
+ "llvm.ptr.annotation",
+ "llvm.readcyclecounter",
+ "llvm.returnaddress",
+ "llvm.sadd.with.overflow",
+ "llvm.setjmp",
+ "llvm.siglongjmp",
+ "llvm.sigsetjmp",
+ "llvm.sin",
+ "llvm.smul.with.overflow",
+ "llvm.spu.si.a",
+ "llvm.spu.si.addx",
+ "llvm.spu.si.ah",
+ "llvm.spu.si.ahi",
+ "llvm.spu.si.ai",
+ "llvm.spu.si.and",
+ "llvm.spu.si.andbi",
+ "llvm.spu.si.andc",
+ "llvm.spu.si.andhi",
+ "llvm.spu.si.andi",
+ "llvm.spu.si.bg",
+ "llvm.spu.si.bgx",
+ "llvm.spu.si.ceq",
+ "llvm.spu.si.ceqb",
+ "llvm.spu.si.ceqbi",
+ "llvm.spu.si.ceqh",
+ "llvm.spu.si.ceqhi",
+ "llvm.spu.si.ceqi",
+ "llvm.spu.si.cg",
+ "llvm.spu.si.cgt",
+ "llvm.spu.si.cgtb",
+ "llvm.spu.si.cgtbi",
+ "llvm.spu.si.cgth",
+ "llvm.spu.si.cgthi",
+ "llvm.spu.si.cgti",
+ "llvm.spu.si.cgx",
+ "llvm.spu.si.clgt",
+ "llvm.spu.si.clgtb",
+ "llvm.spu.si.clgtbi",
+ "llvm.spu.si.clgth",
+ "llvm.spu.si.clgthi",
+ "llvm.spu.si.clgti",
+ "llvm.spu.si.dfa",
+ "llvm.spu.si.dfm",
+ "llvm.spu.si.dfma",
+ "llvm.spu.si.dfms",
+ "llvm.spu.si.dfnma",
+ "llvm.spu.si.dfnms",
+ "llvm.spu.si.dfs",
+ "llvm.spu.si.fa",
+ "llvm.spu.si.fceq",
+ "llvm.spu.si.fcgt",
+ "llvm.spu.si.fcmeq",
+ "llvm.spu.si.fcmgt",
+ "llvm.spu.si.fm",
+ "llvm.spu.si.fma",
+ "llvm.spu.si.fms",
+ "llvm.spu.si.fnms",
+ "llvm.spu.si.fs",
+ "llvm.spu.si.fsmbi",
+ "llvm.spu.si.mpy",
+ "llvm.spu.si.mpya",
+ "llvm.spu.si.mpyh",
+ "llvm.spu.si.mpyhh",
+ "llvm.spu.si.mpyhha",
+ "llvm.spu.si.mpyhhau",
+ "llvm.spu.si.mpyhhu",
+ "llvm.spu.si.mpyi",
+ "llvm.spu.si.mpys",
+ "llvm.spu.si.mpyu",
+ "llvm.spu.si.mpyui",
+ "llvm.spu.si.nand",
+ "llvm.spu.si.nor",
+ "llvm.spu.si.or",
+ "llvm.spu.si.orbi",
+ "llvm.spu.si.orc",
+ "llvm.spu.si.orhi",
+ "llvm.spu.si.ori",
+ "llvm.spu.si.sf",
+ "llvm.spu.si.sfh",
+ "llvm.spu.si.sfhi",
+ "llvm.spu.si.sfi",
+ "llvm.spu.si.sfx",
+ "llvm.spu.si.shli",
+ "llvm.spu.si.shlqbi",
+ "llvm.spu.si.shlqbii",
+ "llvm.spu.si.shlqby",
+ "llvm.spu.si.shlqbyi",
+ "llvm.spu.si.xor",
+ "llvm.spu.si.xorbi",
+ "llvm.spu.si.xorhi",
+ "llvm.spu.si.xori",
+ "llvm.sqrt",
+ "llvm.ssub.with.overflow",
+ "llvm.stackprotector",
+ "llvm.stackrestore",
+ "llvm.stacksave",
+ "llvm.trap",
+ "llvm.uadd.with.overflow",
+ "llvm.umul.with.overflow",
+ "llvm.usub.with.overflow",
+ "llvm.va_copy",
+ "llvm.va_end",
+ "llvm.var.annotation",
+ "llvm.va_start",
+ "llvm.x86.mmx.emms",
+ "llvm.x86.mmx.femms",
+ "llvm.x86.mmx.maskmovq",
+ "llvm.x86.mmx.movnt.dq",
+ "llvm.x86.mmx.packssdw",
+ "llvm.x86.mmx.packsswb",
+ "llvm.x86.mmx.packuswb",
+ "llvm.x86.mmx.padds.b",
+ "llvm.x86.mmx.padds.w",
+ "llvm.x86.mmx.paddus.b",
+ "llvm.x86.mmx.paddus.w",
+ "llvm.x86.mmx.pavg.b",
+ "llvm.x86.mmx.pavg.w",
+ "llvm.x86.mmx.pcmpeq.b",
+ "llvm.x86.mmx.pcmpeq.d",
+ "llvm.x86.mmx.pcmpeq.w",
+ "llvm.x86.mmx.pcmpgt.b",
+ "llvm.x86.mmx.pcmpgt.d",
+ "llvm.x86.mmx.pcmpgt.w",
+ "llvm.x86.mmx.pmadd.wd",
+ "llvm.x86.mmx.pmaxs.w",
+ "llvm.x86.mmx.pmaxu.b",
+ "llvm.x86.mmx.pmins.w",
+ "llvm.x86.mmx.pminu.b",
+ "llvm.x86.mmx.pmovmskb",
+ "llvm.x86.mmx.pmulh.w",
+ "llvm.x86.mmx.pmulhu.w",
+ "llvm.x86.mmx.pmulu.dq",
+ "llvm.x86.mmx.psad.bw",
+ "llvm.x86.mmx.psll.d",
+ "llvm.x86.mmx.psll.q",
+ "llvm.x86.mmx.psll.w",
+ "llvm.x86.mmx.pslli.d",
+ "llvm.x86.mmx.pslli.q",
+ "llvm.x86.mmx.pslli.w",
+ "llvm.x86.mmx.psra.d",
+ "llvm.x86.mmx.psra.w",
+ "llvm.x86.mmx.psrai.d",
+ "llvm.x86.mmx.psrai.w",
+ "llvm.x86.mmx.psrl.d",
+ "llvm.x86.mmx.psrl.q",
+ "llvm.x86.mmx.psrl.w",
+ "llvm.x86.mmx.psrli.d",
+ "llvm.x86.mmx.psrli.q",
+ "llvm.x86.mmx.psrli.w",
+ "llvm.x86.mmx.psubs.b",
+ "llvm.x86.mmx.psubs.w",
+ "llvm.x86.mmx.psubus.b",
+ "llvm.x86.mmx.psubus.w",
+ "llvm.x86.sse2.add.sd",
+ "llvm.x86.sse2.clflush",
+ "llvm.x86.sse2.cmp.pd",
+ "llvm.x86.sse2.cmp.sd",
+ "llvm.x86.sse2.comieq.sd",
+ "llvm.x86.sse2.comige.sd",
+ "llvm.x86.sse2.comigt.sd",
+ "llvm.x86.sse2.comile.sd",
+ "llvm.x86.sse2.comilt.sd",
+ "llvm.x86.sse2.comineq.sd",
+ "llvm.x86.sse2.cvtdq2pd",
+ "llvm.x86.sse2.cvtdq2ps",
+ "llvm.x86.sse2.cvtpd2dq",
+ "llvm.x86.sse2.cvtpd2ps",
+ "llvm.x86.sse2.cvtps2dq",
+ "llvm.x86.sse2.cvtps2pd",
+ "llvm.x86.sse2.cvtsd2si",
+ "llvm.x86.sse2.cvtsd2si64",
+ "llvm.x86.sse2.cvtsd2ss",
+ "llvm.x86.sse2.cvtsi2sd",
+ "llvm.x86.sse2.cvtsi642sd",
+ "llvm.x86.sse2.cvtss2sd",
+ "llvm.x86.sse2.cvttpd2dq",
+ "llvm.x86.sse2.cvttps2dq",
+ "llvm.x86.sse2.cvttsd2si",
+ "llvm.x86.sse2.cvttsd2si64",
+ "llvm.x86.sse2.div.sd",
+ "llvm.x86.sse2.lfence",
+ "llvm.x86.sse2.loadu.dq",
+ "llvm.x86.sse2.loadu.pd",
+ "llvm.x86.sse2.maskmov.dqu",
+ "llvm.x86.sse2.max.pd",
+ "llvm.x86.sse2.max.sd",
+ "llvm.x86.sse2.mfence",
+ "llvm.x86.sse2.min.pd",
+ "llvm.x86.sse2.min.sd",
+ "llvm.x86.sse2.movmsk.pd",
+ "llvm.x86.sse2.movnt.dq",
+ "llvm.x86.sse2.movnt.i",
+ "llvm.x86.sse2.movnt.pd",
+ "llvm.x86.sse2.mul.sd",
+ "llvm.x86.sse2.packssdw.128",
+ "llvm.x86.sse2.packsswb.128",
+ "llvm.x86.sse2.packuswb.128",
+ "llvm.x86.sse2.padds.b",
+ "llvm.x86.sse2.padds.w",
+ "llvm.x86.sse2.paddus.b",
+ "llvm.x86.sse2.paddus.w",
+ "llvm.x86.sse2.pavg.b",
+ "llvm.x86.sse2.pavg.w",
+ "llvm.x86.sse2.pcmpeq.b",
+ "llvm.x86.sse2.pcmpeq.d",
+ "llvm.x86.sse2.pcmpeq.w",
+ "llvm.x86.sse2.pcmpgt.b",
+ "llvm.x86.sse2.pcmpgt.d",
+ "llvm.x86.sse2.pcmpgt.w",
+ "llvm.x86.sse2.pmadd.wd",
+ "llvm.x86.sse2.pmaxs.w",
+ "llvm.x86.sse2.pmaxu.b",
+ "llvm.x86.sse2.pmins.w",
+ "llvm.x86.sse2.pminu.b",
+ "llvm.x86.sse2.pmovmskb.128",
+ "llvm.x86.sse2.pmulh.w",
+ "llvm.x86.sse2.pmulhu.w",
+ "llvm.x86.sse2.pmulu.dq",
+ "llvm.x86.sse2.psad.bw",
+ "llvm.x86.sse2.psll.d",
+ "llvm.x86.sse2.psll.dq",
+ "llvm.x86.sse2.psll.dq.bs",
+ "llvm.x86.sse2.psll.q",
+ "llvm.x86.sse2.psll.w",
+ "llvm.x86.sse2.pslli.d",
+ "llvm.x86.sse2.pslli.q",
+ "llvm.x86.sse2.pslli.w",
+ "llvm.x86.sse2.psra.d",
+ "llvm.x86.sse2.psra.w",
+ "llvm.x86.sse2.psrai.d",
+ "llvm.x86.sse2.psrai.w",
+ "llvm.x86.sse2.psrl.d",
+ "llvm.x86.sse2.psrl.dq",
+ "llvm.x86.sse2.psrl.dq.bs",
+ "llvm.x86.sse2.psrl.q",
+ "llvm.x86.sse2.psrl.w",
+ "llvm.x86.sse2.psrli.d",
+ "llvm.x86.sse2.psrli.q",
+ "llvm.x86.sse2.psrli.w",
+ "llvm.x86.sse2.psubs.b",
+ "llvm.x86.sse2.psubs.w",
+ "llvm.x86.sse2.psubus.b",
+ "llvm.x86.sse2.psubus.w",
+ "llvm.x86.sse2.sqrt.pd",
+ "llvm.x86.sse2.sqrt.sd",
+ "llvm.x86.sse2.storel.dq",
+ "llvm.x86.sse2.storeu.dq",
+ "llvm.x86.sse2.storeu.pd",
+ "llvm.x86.sse2.sub.sd",
+ "llvm.x86.sse2.ucomieq.sd",
+ "llvm.x86.sse2.ucomige.sd",
+ "llvm.x86.sse2.ucomigt.sd",
+ "llvm.x86.sse2.ucomile.sd",
+ "llvm.x86.sse2.ucomilt.sd",
+ "llvm.x86.sse2.ucomineq.sd",
+ "llvm.x86.sse3.addsub.pd",
+ "llvm.x86.sse3.addsub.ps",
+ "llvm.x86.sse3.hadd.pd",
+ "llvm.x86.sse3.hadd.ps",
+ "llvm.x86.sse3.hsub.pd",
+ "llvm.x86.sse3.hsub.ps",
+ "llvm.x86.sse3.ldu.dq",
+ "llvm.x86.sse3.monitor",
+ "llvm.x86.sse3.mwait",
+ "llvm.x86.sse41.blendpd",
+ "llvm.x86.sse41.blendps",
+ "llvm.x86.sse41.blendvpd",
+ "llvm.x86.sse41.blendvps",
+ "llvm.x86.sse41.dppd",
+ "llvm.x86.sse41.dpps",
+ "llvm.x86.sse41.extractps",
+ "llvm.x86.sse41.insertps",
+ "llvm.x86.sse41.movntdqa",
+ "llvm.x86.sse41.mpsadbw",
+ "llvm.x86.sse41.packusdw",
+ "llvm.x86.sse41.pblendvb",
+ "llvm.x86.sse41.pblendw",
+ "llvm.x86.sse41.pcmpeqq",
+ "llvm.x86.sse41.pextrb",
+ "llvm.x86.sse41.pextrd",
+ "llvm.x86.sse41.pextrq",
+ "llvm.x86.sse41.phminposuw",
+ "llvm.x86.sse41.pmaxsb",
+ "llvm.x86.sse41.pmaxsd",
+ "llvm.x86.sse41.pmaxud",
+ "llvm.x86.sse41.pmaxuw",
+ "llvm.x86.sse41.pminsb",
+ "llvm.x86.sse41.pminsd",
+ "llvm.x86.sse41.pminud",
+ "llvm.x86.sse41.pminuw",
+ "llvm.x86.sse41.pmovsxbd",
+ "llvm.x86.sse41.pmovsxbq",
+ "llvm.x86.sse41.pmovsxbw",
+ "llvm.x86.sse41.pmovsxdq",
+ "llvm.x86.sse41.pmovsxwd",
+ "llvm.x86.sse41.pmovsxwq",
+ "llvm.x86.sse41.pmovzxbd",
+ "llvm.x86.sse41.pmovzxbq",
+ "llvm.x86.sse41.pmovzxbw",
+ "llvm.x86.sse41.pmovzxdq",
+ "llvm.x86.sse41.pmovzxwd",
+ "llvm.x86.sse41.pmovzxwq",
+ "llvm.x86.sse41.pmuldq",
+ "llvm.x86.sse41.pmulld",
+ "llvm.x86.sse41.ptestc",
+ "llvm.x86.sse41.ptestnzc",
+ "llvm.x86.sse41.ptestz",
+ "llvm.x86.sse41.round.pd",
+ "llvm.x86.sse41.round.ps",
+ "llvm.x86.sse41.round.sd",
+ "llvm.x86.sse41.round.ss",
+ "llvm.x86.sse42.crc32.16",
+ "llvm.x86.sse42.crc32.32",
+ "llvm.x86.sse42.crc32.64",
+ "llvm.x86.sse42.crc32.8",
+ "llvm.x86.sse42.pcmpestri128",
+ "llvm.x86.sse42.pcmpestria128",
+ "llvm.x86.sse42.pcmpestric128",
+ "llvm.x86.sse42.pcmpestrio128",
+ "llvm.x86.sse42.pcmpestris128",
+ "llvm.x86.sse42.pcmpestriz128",
+ "llvm.x86.sse42.pcmpestrm128",
+ "llvm.x86.sse42.pcmpgtq",
+ "llvm.x86.sse42.pcmpistri128",
+ "llvm.x86.sse42.pcmpistria128",
+ "llvm.x86.sse42.pcmpistric128",
+ "llvm.x86.sse42.pcmpistrio128",
+ "llvm.x86.sse42.pcmpistris128",
+ "llvm.x86.sse42.pcmpistriz128",
+ "llvm.x86.sse42.pcmpistrm128",
+ "llvm.x86.sse.add.ss",
+ "llvm.x86.sse.cmp.ps",
+ "llvm.x86.sse.cmp.ss",
+ "llvm.x86.sse.comieq.ss",
+ "llvm.x86.sse.comige.ss",
+ "llvm.x86.sse.comigt.ss",
+ "llvm.x86.sse.comile.ss",
+ "llvm.x86.sse.comilt.ss",
+ "llvm.x86.sse.comineq.ss",
+ "llvm.x86.sse.cvtpd2pi",
+ "llvm.x86.sse.cvtpi2pd",
+ "llvm.x86.sse.cvtpi2ps",
+ "llvm.x86.sse.cvtps2pi",
+ "llvm.x86.sse.cvtsi2ss",
+ "llvm.x86.sse.cvtsi642ss",
+ "llvm.x86.sse.cvtss2si",
+ "llvm.x86.sse.cvtss2si64",
+ "llvm.x86.sse.cvttpd2pi",
+ "llvm.x86.sse.cvttps2pi",
+ "llvm.x86.sse.cvttss2si",
+ "llvm.x86.sse.cvttss2si64",
+ "llvm.x86.sse.div.ss",
+ "llvm.x86.sse.ldmxcsr",
+ "llvm.x86.sse.loadu.ps",
+ "llvm.x86.sse.max.ps",
+ "llvm.x86.sse.max.ss",
+ "llvm.x86.sse.min.ps",
+ "llvm.x86.sse.min.ss",
+ "llvm.x86.sse.movmsk.ps",
+ "llvm.x86.sse.movnt.ps",
+ "llvm.x86.sse.mul.ss",
+ "llvm.x86.sse.rcp.ps",
+ "llvm.x86.sse.rcp.ss",
+ "llvm.x86.sse.rsqrt.ps",
+ "llvm.x86.sse.rsqrt.ss",
+ "llvm.x86.sse.sfence",
+ "llvm.x86.sse.sqrt.ps",
+ "llvm.x86.sse.sqrt.ss",
+ "llvm.x86.sse.stmxcsr",
+ "llvm.x86.sse.storeu.ps",
+ "llvm.x86.sse.sub.ss",
+ "llvm.x86.sse.ucomieq.ss",
+ "llvm.x86.sse.ucomige.ss",
+ "llvm.x86.sse.ucomigt.ss",
+ "llvm.x86.sse.ucomile.ss",
+ "llvm.x86.sse.ucomilt.ss",
+ "llvm.x86.sse.ucomineq.ss",
+ "llvm.x86.ssse3.pabs.b",
+ "llvm.x86.ssse3.pabs.b.128",
+ "llvm.x86.ssse3.pabs.d",
+ "llvm.x86.ssse3.pabs.d.128",
+ "llvm.x86.ssse3.pabs.w",
+ "llvm.x86.ssse3.pabs.w.128",
+ "llvm.x86.ssse3.palign.r",
+ "llvm.x86.ssse3.palign.r.128",
+ "llvm.x86.ssse3.phadd.d",
+ "llvm.x86.ssse3.phadd.d.128",
+ "llvm.x86.ssse3.phadd.sw",
+ "llvm.x86.ssse3.phadd.sw.128",
+ "llvm.x86.ssse3.phadd.w",
+ "llvm.x86.ssse3.phadd.w.128",
+ "llvm.x86.ssse3.phsub.d",
+ "llvm.x86.ssse3.phsub.d.128",
+ "llvm.x86.ssse3.phsub.sw",
+ "llvm.x86.ssse3.phsub.sw.128",
+ "llvm.x86.ssse3.phsub.w",
+ "llvm.x86.ssse3.phsub.w.128",
+ "llvm.x86.ssse3.pmadd.ub.sw",
+ "llvm.x86.ssse3.pmadd.ub.sw.128",
+ "llvm.x86.ssse3.pmul.hr.sw",
+ "llvm.x86.ssse3.pmul.hr.sw.128",
+ "llvm.x86.ssse3.pshuf.b",
+ "llvm.x86.ssse3.pshuf.b.128",
+ "llvm.x86.ssse3.psign.b",
+ "llvm.x86.ssse3.psign.b.128",
+ "llvm.x86.ssse3.psign.d",
+ "llvm.x86.ssse3.psign.d.128",
+ "llvm.x86.ssse3.psign.w",
+ "llvm.x86.ssse3.psign.w.128",
+ "llvm.xcore.bitrev",
+ "llvm.xcore.getid",
+#endif
+
+// Intrinsic ID to overload table
+#ifdef GET_INTRINSIC_OVERLOAD_TABLE
+ // Note that entry #0 is the invalid intrinsic!
+ false,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ true,
+ true,
+ true,
+ false,
+ true,
+ true,
+ false,
+ true,
+ true,
+ false,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ true,
+ false,
+ false,
+ true,
+ false,
+ false,
+ false,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ true,
+ true,
+ true,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+ false,
+#endif
+
+// Function name -> enum value recognizer code.
+#ifdef GET_FUNCTION_RECOGNIZER
+ switch (Name[5]) {
+ default:
+ break;
+ case 'a':
+ if (Len == 16 && !memcmp(Name, "llvm.alpha.umulh", 16)) return Intrinsic::alpha_umulh;
+ if (Len > 15 && !memcmp(Name, "llvm.annotation.", 16)) return Intrinsic::annotation;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vabals.", 21)) return Intrinsic::arm_neon_vabals;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vabalu.", 21)) return Intrinsic::arm_neon_vabalu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vabas.", 20)) return Intrinsic::arm_neon_vabas;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vabau.", 20)) return Intrinsic::arm_neon_vabau;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vabdls.", 21)) return Intrinsic::arm_neon_vabdls;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vabdlu.", 21)) return Intrinsic::arm_neon_vabdlu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vabds.", 20)) return Intrinsic::arm_neon_vabds;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vabdu.", 20)) return Intrinsic::arm_neon_vabdu;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vabs.", 19)) return Intrinsic::arm_neon_vabs;
+ if (Len == 20 && !memcmp(Name, "llvm.arm.neon.vacged", 20)) return Intrinsic::arm_neon_vacged;
+ if (Len == 20 && !memcmp(Name, "llvm.arm.neon.vacgeq", 20)) return Intrinsic::arm_neon_vacgeq;
+ if (Len == 20 && !memcmp(Name, "llvm.arm.neon.vacgtd", 20)) return Intrinsic::arm_neon_vacgtd;
+ if (Len == 20 && !memcmp(Name, "llvm.arm.neon.vacgtq", 20)) return Intrinsic::arm_neon_vacgtq;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vaddhn.", 21)) return Intrinsic::arm_neon_vaddhn;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vaddls.", 21)) return Intrinsic::arm_neon_vaddls;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vaddlu.", 21)) return Intrinsic::arm_neon_vaddlu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vaddws.", 21)) return Intrinsic::arm_neon_vaddws;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vaddwu.", 21)) return Intrinsic::arm_neon_vaddwu;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vcls.", 19)) return Intrinsic::arm_neon_vcls;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vclz.", 19)) return Intrinsic::arm_neon_vclz;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vcnt.", 19)) return Intrinsic::arm_neon_vcnt;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vcvtfp2fxs.", 25)) return Intrinsic::arm_neon_vcvtfp2fxs;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vcvtfp2fxu.", 25)) return Intrinsic::arm_neon_vcvtfp2fxu;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vcvtfxs2fp.", 25)) return Intrinsic::arm_neon_vcvtfxs2fp;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vcvtfxu2fp.", 25)) return Intrinsic::arm_neon_vcvtfxu2fp;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vhadds.", 21)) return Intrinsic::arm_neon_vhadds;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vhaddu.", 21)) return Intrinsic::arm_neon_vhaddu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vhsubs.", 21)) return Intrinsic::arm_neon_vhsubs;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vhsubu.", 21)) return Intrinsic::arm_neon_vhsubu;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vld1.", 19)) return Intrinsic::arm_neon_vld1;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vld2.", 19)) return Intrinsic::arm_neon_vld2;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vld2lane.", 23)) return Intrinsic::arm_neon_vld2lane;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vld3.", 19)) return Intrinsic::arm_neon_vld3;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vld3lane.", 23)) return Intrinsic::arm_neon_vld3lane;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vld4.", 19)) return Intrinsic::arm_neon_vld4;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vld4lane.", 23)) return Intrinsic::arm_neon_vld4lane;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vmaxs.", 20)) return Intrinsic::arm_neon_vmaxs;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vmaxu.", 20)) return Intrinsic::arm_neon_vmaxu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vmins.", 20)) return Intrinsic::arm_neon_vmins;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vminu.", 20)) return Intrinsic::arm_neon_vminu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmlals.", 21)) return Intrinsic::arm_neon_vmlals;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmlalu.", 21)) return Intrinsic::arm_neon_vmlalu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmlsls.", 21)) return Intrinsic::arm_neon_vmlsls;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmlslu.", 21)) return Intrinsic::arm_neon_vmlslu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmovls.", 21)) return Intrinsic::arm_neon_vmovls;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmovlu.", 21)) return Intrinsic::arm_neon_vmovlu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vmovn.", 20)) return Intrinsic::arm_neon_vmovn;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmullp.", 21)) return Intrinsic::arm_neon_vmullp;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmulls.", 21)) return Intrinsic::arm_neon_vmulls;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vmullu.", 21)) return Intrinsic::arm_neon_vmullu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vmulp.", 20)) return Intrinsic::arm_neon_vmulp;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vpadals.", 22)) return Intrinsic::arm_neon_vpadals;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vpadalu.", 22)) return Intrinsic::arm_neon_vpadalu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vpadd.", 20)) return Intrinsic::arm_neon_vpadd;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vpaddls.", 22)) return Intrinsic::arm_neon_vpaddls;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vpaddlu.", 22)) return Intrinsic::arm_neon_vpaddlu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vpmaxs.", 21)) return Intrinsic::arm_neon_vpmaxs;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vpmaxu.", 21)) return Intrinsic::arm_neon_vpmaxu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vpmins.", 21)) return Intrinsic::arm_neon_vpmins;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vpminu.", 21)) return Intrinsic::arm_neon_vpminu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vqabs.", 20)) return Intrinsic::arm_neon_vqabs;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vqadds.", 21)) return Intrinsic::arm_neon_vqadds;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vqaddu.", 21)) return Intrinsic::arm_neon_vqaddu;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vqdmlal.", 22)) return Intrinsic::arm_neon_vqdmlal;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vqdmlsl.", 22)) return Intrinsic::arm_neon_vqdmlsl;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vqdmulh.", 22)) return Intrinsic::arm_neon_vqdmulh;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vqdmull.", 22)) return Intrinsic::arm_neon_vqdmull;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vqmovns.", 22)) return Intrinsic::arm_neon_vqmovns;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vqmovnsu.", 23)) return Intrinsic::arm_neon_vqmovnsu;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vqmovnu.", 22)) return Intrinsic::arm_neon_vqmovnu;
+ if (Len > 19 && !memcmp(Name, "llvm.arm.neon.vqneg.", 20)) return Intrinsic::arm_neon_vqneg;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vqrdmulh.", 23)) return Intrinsic::arm_neon_vqrdmulh;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vqrshiftns.", 25)) return Intrinsic::arm_neon_vqrshiftns;
+ if (Len > 25 && !memcmp(Name, "llvm.arm.neon.vqrshiftnsu.", 26)) return Intrinsic::arm_neon_vqrshiftnsu;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vqrshiftnu.", 25)) return Intrinsic::arm_neon_vqrshiftnu;
+ if (Len > 23 && !memcmp(Name, "llvm.arm.neon.vqrshifts.", 24)) return Intrinsic::arm_neon_vqrshifts;
+ if (Len > 23 && !memcmp(Name, "llvm.arm.neon.vqrshiftu.", 24)) return Intrinsic::arm_neon_vqrshiftu;
+ if (Len > 23 && !memcmp(Name, "llvm.arm.neon.vqshiftns.", 24)) return Intrinsic::arm_neon_vqshiftns;
+ if (Len > 24 && !memcmp(Name, "llvm.arm.neon.vqshiftnsu.", 25)) return Intrinsic::arm_neon_vqshiftnsu;
+ if (Len > 23 && !memcmp(Name, "llvm.arm.neon.vqshiftnu.", 24)) return Intrinsic::arm_neon_vqshiftnu;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vqshifts.", 23)) return Intrinsic::arm_neon_vqshifts;
+ if (Len > 23 && !memcmp(Name, "llvm.arm.neon.vqshiftsu.", 24)) return Intrinsic::arm_neon_vqshiftsu;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vqshiftu.", 23)) return Intrinsic::arm_neon_vqshiftu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vqsubs.", 21)) return Intrinsic::arm_neon_vqsubs;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vqsubu.", 21)) return Intrinsic::arm_neon_vqsubu;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vraddhn.", 22)) return Intrinsic::arm_neon_vraddhn;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vrecpe.", 21)) return Intrinsic::arm_neon_vrecpe;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vrecps.", 21)) return Intrinsic::arm_neon_vrecps;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vrhadds.", 22)) return Intrinsic::arm_neon_vrhadds;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vrhaddu.", 22)) return Intrinsic::arm_neon_vrhaddu;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vrshiftn.", 23)) return Intrinsic::arm_neon_vrshiftn;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vrshifts.", 23)) return Intrinsic::arm_neon_vrshifts;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vrshiftu.", 23)) return Intrinsic::arm_neon_vrshiftu;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vrsqrte.", 22)) return Intrinsic::arm_neon_vrsqrte;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vrsqrts.", 22)) return Intrinsic::arm_neon_vrsqrts;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vrsubhn.", 22)) return Intrinsic::arm_neon_vrsubhn;
+ if (Len > 23 && !memcmp(Name, "llvm.arm.neon.vshiftins.", 24)) return Intrinsic::arm_neon_vshiftins;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vshiftls.", 23)) return Intrinsic::arm_neon_vshiftls;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vshiftlu.", 23)) return Intrinsic::arm_neon_vshiftlu;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vshiftn.", 22)) return Intrinsic::arm_neon_vshiftn;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vshifts.", 22)) return Intrinsic::arm_neon_vshifts;
+ if (Len > 21 && !memcmp(Name, "llvm.arm.neon.vshiftu.", 22)) return Intrinsic::arm_neon_vshiftu;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vst1.", 19)) return Intrinsic::arm_neon_vst1;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vst2.", 19)) return Intrinsic::arm_neon_vst2;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vst2lane.", 23)) return Intrinsic::arm_neon_vst2lane;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vst3.", 19)) return Intrinsic::arm_neon_vst3;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vst3lane.", 23)) return Intrinsic::arm_neon_vst3lane;
+ if (Len > 18 && !memcmp(Name, "llvm.arm.neon.vst4.", 19)) return Intrinsic::arm_neon_vst4;
+ if (Len > 22 && !memcmp(Name, "llvm.arm.neon.vst4lane.", 23)) return Intrinsic::arm_neon_vst4lane;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vsubhn.", 21)) return Intrinsic::arm_neon_vsubhn;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vsubls.", 21)) return Intrinsic::arm_neon_vsubls;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vsublu.", 21)) return Intrinsic::arm_neon_vsublu;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vsubws.", 21)) return Intrinsic::arm_neon_vsubws;
+ if (Len > 20 && !memcmp(Name, "llvm.arm.neon.vsubwu.", 21)) return Intrinsic::arm_neon_vsubwu;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbl1", 19)) return Intrinsic::arm_neon_vtbl1;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbl2", 19)) return Intrinsic::arm_neon_vtbl2;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbl3", 19)) return Intrinsic::arm_neon_vtbl3;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbl4", 19)) return Intrinsic::arm_neon_vtbl4;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbx1", 19)) return Intrinsic::arm_neon_vtbx1;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbx2", 19)) return Intrinsic::arm_neon_vtbx2;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbx3", 19)) return Intrinsic::arm_neon_vtbx3;
+ if (Len == 19 && !memcmp(Name, "llvm.arm.neon.vtbx4", 19)) return Intrinsic::arm_neon_vtbx4;
+ if (Len == 23 && !memcmp(Name, "llvm.arm.thread.pointer", 23)) return Intrinsic::arm_thread_pointer;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.cmp.swap.", 21)) return Intrinsic::atomic_cmp_swap;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.load.add.", 21)) return Intrinsic::atomic_load_add;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.load.and.", 21)) return Intrinsic::atomic_load_and;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.load.max.", 21)) return Intrinsic::atomic_load_max;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.load.min.", 21)) return Intrinsic::atomic_load_min;
+ if (Len > 21 && !memcmp(Name, "llvm.atomic.load.nand.", 22)) return Intrinsic::atomic_load_nand;
+ if (Len > 19 && !memcmp(Name, "llvm.atomic.load.or.", 20)) return Intrinsic::atomic_load_or;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.load.sub.", 21)) return Intrinsic::atomic_load_sub;
+ if (Len > 21 && !memcmp(Name, "llvm.atomic.load.umax.", 22)) return Intrinsic::atomic_load_umax;
+ if (Len > 21 && !memcmp(Name, "llvm.atomic.load.umin.", 22)) return Intrinsic::atomic_load_umin;
+ if (Len > 20 && !memcmp(Name, "llvm.atomic.load.xor.", 21)) return Intrinsic::atomic_load_xor;
+ if (Len > 16 && !memcmp(Name, "llvm.atomic.swap.", 17)) return Intrinsic::atomic_swap;
+ break;
+ case 'b':
+ if (Len > 10 && !memcmp(Name, "llvm.bswap.", 11)) return Intrinsic::bswap;
+ break;
+ case 'c':
+ if (Len > 14 && !memcmp(Name, "llvm.convertff.", 15)) return Intrinsic::convertff;
+ if (Len > 15 && !memcmp(Name, "llvm.convertfsi.", 16)) return Intrinsic::convertfsi;
+ if (Len > 15 && !memcmp(Name, "llvm.convertfui.", 16)) return Intrinsic::convertfui;
+ if (Len > 15 && !memcmp(Name, "llvm.convertsif.", 16)) return Intrinsic::convertsif;
+ if (Len > 14 && !memcmp(Name, "llvm.convertss.", 15)) return Intrinsic::convertss;
+ if (Len > 14 && !memcmp(Name, "llvm.convertsu.", 15)) return Intrinsic::convertsu;
+ if (Len > 15 && !memcmp(Name, "llvm.convertuif.", 16)) return Intrinsic::convertuif;
+ if (Len > 14 && !memcmp(Name, "llvm.convertus.", 15)) return Intrinsic::convertus;
+ if (Len > 14 && !memcmp(Name, "llvm.convertuu.", 15)) return Intrinsic::convertuu;
+ if (Len > 8 && !memcmp(Name, "llvm.cos.", 9)) return Intrinsic::cos;
+ if (Len > 9 && !memcmp(Name, "llvm.ctlz.", 10)) return Intrinsic::ctlz;
+ if (Len > 10 && !memcmp(Name, "llvm.ctpop.", 11)) return Intrinsic::ctpop;
+ if (Len > 9 && !memcmp(Name, "llvm.cttz.", 10)) return Intrinsic::cttz;
+ break;
+ case 'd':
+ if (Len == 16 && !memcmp(Name, "llvm.dbg.declare", 16)) return Intrinsic::dbg_declare;
+ if (Len == 19 && !memcmp(Name, "llvm.dbg.func.start", 19)) return Intrinsic::dbg_func_start;
+ if (Len == 19 && !memcmp(Name, "llvm.dbg.region.end", 19)) return Intrinsic::dbg_region_end;
+ if (Len == 21 && !memcmp(Name, "llvm.dbg.region.start", 21)) return Intrinsic::dbg_region_start;
+ if (Len == 18 && !memcmp(Name, "llvm.dbg.stoppoint", 18)) return Intrinsic::dbg_stoppoint;
+ if (Len == 14 && !memcmp(Name, "llvm.dbg.value", 14)) return Intrinsic::dbg_value;
+ break;
+ case 'e':
+ if (Len == 17 && !memcmp(Name, "llvm.eh.dwarf.cfa", 17)) return Intrinsic::eh_dwarf_cfa;
+ if (Len == 17 && !memcmp(Name, "llvm.eh.exception", 17)) return Intrinsic::eh_exception;
+ if (Len == 18 && !memcmp(Name, "llvm.eh.return.i32", 18)) return Intrinsic::eh_return_i32;
+ if (Len == 18 && !memcmp(Name, "llvm.eh.return.i64", 18)) return Intrinsic::eh_return_i64;
+ if (Len == 16 && !memcmp(Name, "llvm.eh.selector", 16)) return Intrinsic::eh_selector;
+ if (Len == 20 && !memcmp(Name, "llvm.eh.sjlj.longjmp", 20)) return Intrinsic::eh_sjlj_longjmp;
+ if (Len == 17 && !memcmp(Name, "llvm.eh.sjlj.lsda", 17)) return Intrinsic::eh_sjlj_lsda;
+ if (Len == 19 && !memcmp(Name, "llvm.eh.sjlj.setjmp", 19)) return Intrinsic::eh_sjlj_setjmp;
+ if (Len == 18 && !memcmp(Name, "llvm.eh.typeid.for", 18)) return Intrinsic::eh_typeid_for;
+ if (Len == 19 && !memcmp(Name, "llvm.eh.unwind.init", 19)) return Intrinsic::eh_unwind_init;
+ if (Len > 8 && !memcmp(Name, "llvm.exp.", 9)) return Intrinsic::exp;
+ if (Len > 9 && !memcmp(Name, "llvm.exp2.", 10)) return Intrinsic::exp2;
+ break;
+ case 'f':
+ if (Len == 15 && !memcmp(Name, "llvm.flt.rounds", 15)) return Intrinsic::flt_rounds;
+ if (Len == 17 && !memcmp(Name, "llvm.frameaddress", 17)) return Intrinsic::frameaddress;
+ break;
+ case 'g':
+ if (Len == 11 && !memcmp(Name, "llvm.gcread", 11)) return Intrinsic::gcread;
+ if (Len == 11 && !memcmp(Name, "llvm.gcroot", 11)) return Intrinsic::gcroot;
+ if (Len == 12 && !memcmp(Name, "llvm.gcwrite", 12)) return Intrinsic::gcwrite;
+ break;
+ case 'i':
+ if (Len == 20 && !memcmp(Name, "llvm.init.trampoline", 20)) return Intrinsic::init_trampoline;
+ if (Len == 18 && !memcmp(Name, "llvm.invariant.end", 18)) return Intrinsic::invariant_end;
+ if (Len == 20 && !memcmp(Name, "llvm.invariant.start", 20)) return Intrinsic::invariant_start;
+ break;
+ case 'l':
+ if (Len == 17 && !memcmp(Name, "llvm.lifetime.end", 17)) return Intrinsic::lifetime_end;
+ if (Len == 19 && !memcmp(Name, "llvm.lifetime.start", 19)) return Intrinsic::lifetime_start;
+ if (Len > 8 && !memcmp(Name, "llvm.log.", 9)) return Intrinsic::log;
+ if (Len > 10 && !memcmp(Name, "llvm.log10.", 11)) return Intrinsic::log10;
+ if (Len > 9 && !memcmp(Name, "llvm.log2.", 10)) return Intrinsic::log2;
+ if (Len == 12 && !memcmp(Name, "llvm.longjmp", 12)) return Intrinsic::longjmp;
+ break;
+ case 'm':
+ if (Len > 11 && !memcmp(Name, "llvm.memcpy.", 12)) return Intrinsic::memcpy;
+ if (Len > 12 && !memcmp(Name, "llvm.memmove.", 13)) return Intrinsic::memmove;
+ if (Len == 19 && !memcmp(Name, "llvm.memory.barrier", 19)) return Intrinsic::memory_barrier;
+ if (Len > 11 && !memcmp(Name, "llvm.memset.", 12)) return Intrinsic::memset;
+ break;
+ case 'o':
+ if (Len > 15 && !memcmp(Name, "llvm.objectsize.", 16)) return Intrinsic::objectsize;
+ break;
+ case 'p':
+ if (Len == 13 && !memcmp(Name, "llvm.pcmarker", 13)) return Intrinsic::pcmarker;
+ if (Len > 8 && !memcmp(Name, "llvm.pow.", 9)) return Intrinsic::pow;
+ if (Len > 9 && !memcmp(Name, "llvm.powi.", 10)) return Intrinsic::powi;
+ if (Len == 20 && !memcmp(Name, "llvm.ppc.altivec.dss", 20)) return Intrinsic::ppc_altivec_dss;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.dssall", 23)) return Intrinsic::ppc_altivec_dssall;
+ if (Len == 20 && !memcmp(Name, "llvm.ppc.altivec.dst", 20)) return Intrinsic::ppc_altivec_dst;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.dstst", 22)) return Intrinsic::ppc_altivec_dstst;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.dststt", 23)) return Intrinsic::ppc_altivec_dststt;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.dstt", 21)) return Intrinsic::ppc_altivec_dstt;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.lvebx", 22)) return Intrinsic::ppc_altivec_lvebx;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.lvehx", 22)) return Intrinsic::ppc_altivec_lvehx;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.lvewx", 22)) return Intrinsic::ppc_altivec_lvewx;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.lvsl", 21)) return Intrinsic::ppc_altivec_lvsl;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.lvsr", 21)) return Intrinsic::ppc_altivec_lvsr;
+ if (Len == 20 && !memcmp(Name, "llvm.ppc.altivec.lvx", 20)) return Intrinsic::ppc_altivec_lvx;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.lvxl", 21)) return Intrinsic::ppc_altivec_lvxl;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.mfvscr", 23)) return Intrinsic::ppc_altivec_mfvscr;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.mtvscr", 23)) return Intrinsic::ppc_altivec_mtvscr;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.stvebx", 23)) return Intrinsic::ppc_altivec_stvebx;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.stvehx", 23)) return Intrinsic::ppc_altivec_stvehx;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.stvewx", 23)) return Intrinsic::ppc_altivec_stvewx;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.stvx", 21)) return Intrinsic::ppc_altivec_stvx;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.stvxl", 22)) return Intrinsic::ppc_altivec_stvxl;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vaddcuw", 24)) return Intrinsic::ppc_altivec_vaddcuw;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vaddsbs", 24)) return Intrinsic::ppc_altivec_vaddsbs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vaddshs", 24)) return Intrinsic::ppc_altivec_vaddshs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vaddsws", 24)) return Intrinsic::ppc_altivec_vaddsws;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vaddubs", 24)) return Intrinsic::ppc_altivec_vaddubs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vadduhs", 24)) return Intrinsic::ppc_altivec_vadduhs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vadduws", 24)) return Intrinsic::ppc_altivec_vadduws;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vavgsb", 23)) return Intrinsic::ppc_altivec_vavgsb;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vavgsh", 23)) return Intrinsic::ppc_altivec_vavgsh;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vavgsw", 23)) return Intrinsic::ppc_altivec_vavgsw;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vavgub", 23)) return Intrinsic::ppc_altivec_vavgub;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vavguh", 23)) return Intrinsic::ppc_altivec_vavguh;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vavguw", 23)) return Intrinsic::ppc_altivec_vavguw;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vcfsx", 22)) return Intrinsic::ppc_altivec_vcfsx;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vcfux", 22)) return Intrinsic::ppc_altivec_vcfux;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vcmpbfp", 24)) return Intrinsic::ppc_altivec_vcmpbfp;
+ if (Len == 26 && !memcmp(Name, "llvm.ppc.altivec.vcmpbfp.p", 26)) return Intrinsic::ppc_altivec_vcmpbfp_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpeqfp", 25)) return Intrinsic::ppc_altivec_vcmpeqfp;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpeqfp.p", 27)) return Intrinsic::ppc_altivec_vcmpeqfp_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpequb", 25)) return Intrinsic::ppc_altivec_vcmpequb;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpequb.p", 27)) return Intrinsic::ppc_altivec_vcmpequb_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpequh", 25)) return Intrinsic::ppc_altivec_vcmpequh;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpequh.p", 27)) return Intrinsic::ppc_altivec_vcmpequh_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpequw", 25)) return Intrinsic::ppc_altivec_vcmpequw;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpequw.p", 27)) return Intrinsic::ppc_altivec_vcmpequw_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgefp", 25)) return Intrinsic::ppc_altivec_vcmpgefp;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgefp.p", 27)) return Intrinsic::ppc_altivec_vcmpgefp_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtfp", 25)) return Intrinsic::ppc_altivec_vcmpgtfp;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtfp.p", 27)) return Intrinsic::ppc_altivec_vcmpgtfp_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtsb", 25)) return Intrinsic::ppc_altivec_vcmpgtsb;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtsb.p", 27)) return Intrinsic::ppc_altivec_vcmpgtsb_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtsh", 25)) return Intrinsic::ppc_altivec_vcmpgtsh;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtsh.p", 27)) return Intrinsic::ppc_altivec_vcmpgtsh_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtsw", 25)) return Intrinsic::ppc_altivec_vcmpgtsw;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtsw.p", 27)) return Intrinsic::ppc_altivec_vcmpgtsw_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtub", 25)) return Intrinsic::ppc_altivec_vcmpgtub;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtub.p", 27)) return Intrinsic::ppc_altivec_vcmpgtub_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtuh", 25)) return Intrinsic::ppc_altivec_vcmpgtuh;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtuh.p", 27)) return Intrinsic::ppc_altivec_vcmpgtuh_p;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtuw", 25)) return Intrinsic::ppc_altivec_vcmpgtuw;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vcmpgtuw.p", 27)) return Intrinsic::ppc_altivec_vcmpgtuw_p;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vctsxs", 23)) return Intrinsic::ppc_altivec_vctsxs;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vctuxs", 23)) return Intrinsic::ppc_altivec_vctuxs;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vexptefp", 25)) return Intrinsic::ppc_altivec_vexptefp;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vlogefp", 24)) return Intrinsic::ppc_altivec_vlogefp;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmaddfp", 24)) return Intrinsic::ppc_altivec_vmaddfp;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxfp", 23)) return Intrinsic::ppc_altivec_vmaxfp;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxsb", 23)) return Intrinsic::ppc_altivec_vmaxsb;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxsh", 23)) return Intrinsic::ppc_altivec_vmaxsh;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxsw", 23)) return Intrinsic::ppc_altivec_vmaxsw;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxub", 23)) return Intrinsic::ppc_altivec_vmaxub;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxuh", 23)) return Intrinsic::ppc_altivec_vmaxuh;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vmaxuw", 23)) return Intrinsic::ppc_altivec_vmaxuw;
+ if (Len == 26 && !memcmp(Name, "llvm.ppc.altivec.vmhaddshs", 26)) return Intrinsic::ppc_altivec_vmhaddshs;
+ if (Len == 27 && !memcmp(Name, "llvm.ppc.altivec.vmhraddshs", 27)) return Intrinsic::ppc_altivec_vmhraddshs;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminfp", 23)) return Intrinsic::ppc_altivec_vminfp;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminsb", 23)) return Intrinsic::ppc_altivec_vminsb;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminsh", 23)) return Intrinsic::ppc_altivec_vminsh;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminsw", 23)) return Intrinsic::ppc_altivec_vminsw;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminub", 23)) return Intrinsic::ppc_altivec_vminub;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminuh", 23)) return Intrinsic::ppc_altivec_vminuh;
+ if (Len == 23 && !memcmp(Name, "llvm.ppc.altivec.vminuw", 23)) return Intrinsic::ppc_altivec_vminuw;
+ if (Len == 26 && !memcmp(Name, "llvm.ppc.altivec.vmladduhm", 26)) return Intrinsic::ppc_altivec_vmladduhm;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vmsummbm", 25)) return Intrinsic::ppc_altivec_vmsummbm;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vmsumshm", 25)) return Intrinsic::ppc_altivec_vmsumshm;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vmsumshs", 25)) return Intrinsic::ppc_altivec_vmsumshs;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vmsumubm", 25)) return Intrinsic::ppc_altivec_vmsumubm;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vmsumuhm", 25)) return Intrinsic::ppc_altivec_vmsumuhm;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vmsumuhs", 25)) return Intrinsic::ppc_altivec_vmsumuhs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmulesb", 24)) return Intrinsic::ppc_altivec_vmulesb;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmulesh", 24)) return Intrinsic::ppc_altivec_vmulesh;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmuleub", 24)) return Intrinsic::ppc_altivec_vmuleub;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmuleuh", 24)) return Intrinsic::ppc_altivec_vmuleuh;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmulosb", 24)) return Intrinsic::ppc_altivec_vmulosb;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmulosh", 24)) return Intrinsic::ppc_altivec_vmulosh;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmuloub", 24)) return Intrinsic::ppc_altivec_vmuloub;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vmulouh", 24)) return Intrinsic::ppc_altivec_vmulouh;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vnmsubfp", 25)) return Intrinsic::ppc_altivec_vnmsubfp;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vperm", 22)) return Intrinsic::ppc_altivec_vperm;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vpkpx", 22)) return Intrinsic::ppc_altivec_vpkpx;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vpkshss", 24)) return Intrinsic::ppc_altivec_vpkshss;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vpkshus", 24)) return Intrinsic::ppc_altivec_vpkshus;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vpkswss", 24)) return Intrinsic::ppc_altivec_vpkswss;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vpkswus", 24)) return Intrinsic::ppc_altivec_vpkswus;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vpkuhus", 24)) return Intrinsic::ppc_altivec_vpkuhus;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vpkuwus", 24)) return Intrinsic::ppc_altivec_vpkuwus;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vrefp", 22)) return Intrinsic::ppc_altivec_vrefp;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vrfim", 22)) return Intrinsic::ppc_altivec_vrfim;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vrfin", 22)) return Intrinsic::ppc_altivec_vrfin;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vrfip", 22)) return Intrinsic::ppc_altivec_vrfip;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vrfiz", 22)) return Intrinsic::ppc_altivec_vrfiz;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vrlb", 21)) return Intrinsic::ppc_altivec_vrlb;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vrlh", 21)) return Intrinsic::ppc_altivec_vrlh;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vrlw", 21)) return Intrinsic::ppc_altivec_vrlw;
+ if (Len == 26 && !memcmp(Name, "llvm.ppc.altivec.vrsqrtefp", 26)) return Intrinsic::ppc_altivec_vrsqrtefp;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vsel", 21)) return Intrinsic::ppc_altivec_vsel;
+ if (Len == 20 && !memcmp(Name, "llvm.ppc.altivec.vsl", 20)) return Intrinsic::ppc_altivec_vsl;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vslb", 21)) return Intrinsic::ppc_altivec_vslb;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vslh", 21)) return Intrinsic::ppc_altivec_vslh;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vslo", 21)) return Intrinsic::ppc_altivec_vslo;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vslw", 21)) return Intrinsic::ppc_altivec_vslw;
+ if (Len == 20 && !memcmp(Name, "llvm.ppc.altivec.vsr", 20)) return Intrinsic::ppc_altivec_vsr;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vsrab", 22)) return Intrinsic::ppc_altivec_vsrab;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vsrah", 22)) return Intrinsic::ppc_altivec_vsrah;
+ if (Len == 22 && !memcmp(Name, "llvm.ppc.altivec.vsraw", 22)) return Intrinsic::ppc_altivec_vsraw;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vsrb", 21)) return Intrinsic::ppc_altivec_vsrb;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vsrh", 21)) return Intrinsic::ppc_altivec_vsrh;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vsro", 21)) return Intrinsic::ppc_altivec_vsro;
+ if (Len == 21 && !memcmp(Name, "llvm.ppc.altivec.vsrw", 21)) return Intrinsic::ppc_altivec_vsrw;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsubcuw", 24)) return Intrinsic::ppc_altivec_vsubcuw;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsubsbs", 24)) return Intrinsic::ppc_altivec_vsubsbs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsubshs", 24)) return Intrinsic::ppc_altivec_vsubshs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsubsws", 24)) return Intrinsic::ppc_altivec_vsubsws;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsububs", 24)) return Intrinsic::ppc_altivec_vsububs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsubuhs", 24)) return Intrinsic::ppc_altivec_vsubuhs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsubuws", 24)) return Intrinsic::ppc_altivec_vsubuws;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vsum2sws", 25)) return Intrinsic::ppc_altivec_vsum2sws;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vsum4sbs", 25)) return Intrinsic::ppc_altivec_vsum4sbs;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vsum4shs", 25)) return Intrinsic::ppc_altivec_vsum4shs;
+ if (Len == 25 && !memcmp(Name, "llvm.ppc.altivec.vsum4ubs", 25)) return Intrinsic::ppc_altivec_vsum4ubs;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vsumsws", 24)) return Intrinsic::ppc_altivec_vsumsws;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vupkhpx", 24)) return Intrinsic::ppc_altivec_vupkhpx;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vupkhsb", 24)) return Intrinsic::ppc_altivec_vupkhsb;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vupkhsh", 24)) return Intrinsic::ppc_altivec_vupkhsh;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vupklpx", 24)) return Intrinsic::ppc_altivec_vupklpx;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vupklsb", 24)) return Intrinsic::ppc_altivec_vupklsb;
+ if (Len == 24 && !memcmp(Name, "llvm.ppc.altivec.vupklsh", 24)) return Intrinsic::ppc_altivec_vupklsh;
+ if (Len == 13 && !memcmp(Name, "llvm.ppc.dcba", 13)) return Intrinsic::ppc_dcba;
+ if (Len == 13 && !memcmp(Name, "llvm.ppc.dcbf", 13)) return Intrinsic::ppc_dcbf;
+ if (Len == 13 && !memcmp(Name, "llvm.ppc.dcbi", 13)) return Intrinsic::ppc_dcbi;
+ if (Len == 14 && !memcmp(Name, "llvm.ppc.dcbst", 14)) return Intrinsic::ppc_dcbst;
+ if (Len == 13 && !memcmp(Name, "llvm.ppc.dcbt", 13)) return Intrinsic::ppc_dcbt;
+ if (Len == 15 && !memcmp(Name, "llvm.ppc.dcbtst", 15)) return Intrinsic::ppc_dcbtst;
+ if (Len == 13 && !memcmp(Name, "llvm.ppc.dcbz", 13)) return Intrinsic::ppc_dcbz;
+ if (Len == 14 && !memcmp(Name, "llvm.ppc.dcbzl", 14)) return Intrinsic::ppc_dcbzl;
+ if (Len == 13 && !memcmp(Name, "llvm.ppc.sync", 13)) return Intrinsic::ppc_sync;
+ if (Len == 13 && !memcmp(Name, "llvm.prefetch", 13)) return Intrinsic::prefetch;
+ if (Len > 19 && !memcmp(Name, "llvm.ptr.annotation.", 20)) return Intrinsic::ptr_annotation;
+ break;
+ case 'r':
+ if (Len == 21 && !memcmp(Name, "llvm.readcyclecounter", 21)) return Intrinsic::readcyclecounter;
+ if (Len == 18 && !memcmp(Name, "llvm.returnaddress", 18)) return Intrinsic::returnaddress;
+ break;
+ case 's':
+ if (Len > 23 && !memcmp(Name, "llvm.sadd.with.overflow.", 24)) return Intrinsic::sadd_with_overflow;
+ if (Len == 11 && !memcmp(Name, "llvm.setjmp", 11)) return Intrinsic::setjmp;
+ if (Len == 15 && !memcmp(Name, "llvm.siglongjmp", 15)) return Intrinsic::siglongjmp;
+ if (Len == 14 && !memcmp(Name, "llvm.sigsetjmp", 14)) return Intrinsic::sigsetjmp;
+ if (Len > 8 && !memcmp(Name, "llvm.sin.", 9)) return Intrinsic::sin;
+ if (Len > 23 && !memcmp(Name, "llvm.smul.with.overflow.", 24)) return Intrinsic::smul_with_overflow;
+ if (Len == 13 && !memcmp(Name, "llvm.spu.si.a", 13)) return Intrinsic::spu_si_a;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.addx", 16)) return Intrinsic::spu_si_addx;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.ah", 14)) return Intrinsic::spu_si_ah;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.ahi", 15)) return Intrinsic::spu_si_ahi;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.ai", 14)) return Intrinsic::spu_si_ai;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.and", 15)) return Intrinsic::spu_si_and;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.andbi", 17)) return Intrinsic::spu_si_andbi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.andc", 16)) return Intrinsic::spu_si_andc;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.andhi", 17)) return Intrinsic::spu_si_andhi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.andi", 16)) return Intrinsic::spu_si_andi;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.bg", 14)) return Intrinsic::spu_si_bg;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.bgx", 15)) return Intrinsic::spu_si_bgx;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.ceq", 15)) return Intrinsic::spu_si_ceq;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.ceqb", 16)) return Intrinsic::spu_si_ceqb;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.ceqbi", 17)) return Intrinsic::spu_si_ceqbi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.ceqh", 16)) return Intrinsic::spu_si_ceqh;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.ceqhi", 17)) return Intrinsic::spu_si_ceqhi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.ceqi", 16)) return Intrinsic::spu_si_ceqi;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.cg", 14)) return Intrinsic::spu_si_cg;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.cgt", 15)) return Intrinsic::spu_si_cgt;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.cgtb", 16)) return Intrinsic::spu_si_cgtb;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.cgtbi", 17)) return Intrinsic::spu_si_cgtbi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.cgth", 16)) return Intrinsic::spu_si_cgth;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.cgthi", 17)) return Intrinsic::spu_si_cgthi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.cgti", 16)) return Intrinsic::spu_si_cgti;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.cgx", 15)) return Intrinsic::spu_si_cgx;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.clgt", 16)) return Intrinsic::spu_si_clgt;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.clgtb", 17)) return Intrinsic::spu_si_clgtb;
+ if (Len == 18 && !memcmp(Name, "llvm.spu.si.clgtbi", 18)) return Intrinsic::spu_si_clgtbi;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.clgth", 17)) return Intrinsic::spu_si_clgth;
+ if (Len == 18 && !memcmp(Name, "llvm.spu.si.clgthi", 18)) return Intrinsic::spu_si_clgthi;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.clgti", 17)) return Intrinsic::spu_si_clgti;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.dfa", 15)) return Intrinsic::spu_si_dfa;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.dfm", 15)) return Intrinsic::spu_si_dfm;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.dfma", 16)) return Intrinsic::spu_si_dfma;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.dfms", 16)) return Intrinsic::spu_si_dfms;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.dfnma", 17)) return Intrinsic::spu_si_dfnma;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.dfnms", 17)) return Intrinsic::spu_si_dfnms;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.dfs", 15)) return Intrinsic::spu_si_dfs;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.fa", 14)) return Intrinsic::spu_si_fa;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.fceq", 16)) return Intrinsic::spu_si_fceq;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.fcgt", 16)) return Intrinsic::spu_si_fcgt;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.fcmeq", 17)) return Intrinsic::spu_si_fcmeq;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.fcmgt", 17)) return Intrinsic::spu_si_fcmgt;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.fm", 14)) return Intrinsic::spu_si_fm;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.fma", 15)) return Intrinsic::spu_si_fma;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.fms", 15)) return Intrinsic::spu_si_fms;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.fnms", 16)) return Intrinsic::spu_si_fnms;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.fs", 14)) return Intrinsic::spu_si_fs;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.fsmbi", 17)) return Intrinsic::spu_si_fsmbi;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.mpy", 15)) return Intrinsic::spu_si_mpy;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.mpya", 16)) return Intrinsic::spu_si_mpya;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.mpyh", 16)) return Intrinsic::spu_si_mpyh;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.mpyhh", 17)) return Intrinsic::spu_si_mpyhh;
+ if (Len == 18 && !memcmp(Name, "llvm.spu.si.mpyhha", 18)) return Intrinsic::spu_si_mpyhha;
+ if (Len == 19 && !memcmp(Name, "llvm.spu.si.mpyhhau", 19)) return Intrinsic::spu_si_mpyhhau;
+ if (Len == 18 && !memcmp(Name, "llvm.spu.si.mpyhhu", 18)) return Intrinsic::spu_si_mpyhhu;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.mpyi", 16)) return Intrinsic::spu_si_mpyi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.mpys", 16)) return Intrinsic::spu_si_mpys;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.mpyu", 16)) return Intrinsic::spu_si_mpyu;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.mpyui", 17)) return Intrinsic::spu_si_mpyui;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.nand", 16)) return Intrinsic::spu_si_nand;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.nor", 15)) return Intrinsic::spu_si_nor;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.or", 14)) return Intrinsic::spu_si_or;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.orbi", 16)) return Intrinsic::spu_si_orbi;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.orc", 15)) return Intrinsic::spu_si_orc;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.orhi", 16)) return Intrinsic::spu_si_orhi;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.ori", 15)) return Intrinsic::spu_si_ori;
+ if (Len == 14 && !memcmp(Name, "llvm.spu.si.sf", 14)) return Intrinsic::spu_si_sf;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.sfh", 15)) return Intrinsic::spu_si_sfh;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.sfhi", 16)) return Intrinsic::spu_si_sfhi;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.sfi", 15)) return Intrinsic::spu_si_sfi;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.sfx", 15)) return Intrinsic::spu_si_sfx;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.shli", 16)) return Intrinsic::spu_si_shli;
+ if (Len == 18 && !memcmp(Name, "llvm.spu.si.shlqbi", 18)) return Intrinsic::spu_si_shlqbi;
+ if (Len == 19 && !memcmp(Name, "llvm.spu.si.shlqbii", 19)) return Intrinsic::spu_si_shlqbii;
+ if (Len == 18 && !memcmp(Name, "llvm.spu.si.shlqby", 18)) return Intrinsic::spu_si_shlqby;
+ if (Len == 19 && !memcmp(Name, "llvm.spu.si.shlqbyi", 19)) return Intrinsic::spu_si_shlqbyi;
+ if (Len == 15 && !memcmp(Name, "llvm.spu.si.xor", 15)) return Intrinsic::spu_si_xor;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.xorbi", 17)) return Intrinsic::spu_si_xorbi;
+ if (Len == 17 && !memcmp(Name, "llvm.spu.si.xorhi", 17)) return Intrinsic::spu_si_xorhi;
+ if (Len == 16 && !memcmp(Name, "llvm.spu.si.xori", 16)) return Intrinsic::spu_si_xori;
+ if (Len > 9 && !memcmp(Name, "llvm.sqrt.", 10)) return Intrinsic::sqrt;
+ if (Len > 23 && !memcmp(Name, "llvm.ssub.with.overflow.", 24)) return Intrinsic::ssub_with_overflow;
+ if (Len == 19 && !memcmp(Name, "llvm.stackprotector", 19)) return Intrinsic::stackprotector;
+ if (Len == 17 && !memcmp(Name, "llvm.stackrestore", 17)) return Intrinsic::stackrestore;
+ if (Len == 14 && !memcmp(Name, "llvm.stacksave", 14)) return Intrinsic::stacksave;
+ break;
+ case 't':
+ if (Len == 9 && !memcmp(Name, "llvm.trap", 9)) return Intrinsic::trap;
+ break;
+ case 'u':
+ if (Len > 23 && !memcmp(Name, "llvm.uadd.with.overflow.", 24)) return Intrinsic::uadd_with_overflow;
+ if (Len > 23 && !memcmp(Name, "llvm.umul.with.overflow.", 24)) return Intrinsic::umul_with_overflow;
+ if (Len > 23 && !memcmp(Name, "llvm.usub.with.overflow.", 24)) return Intrinsic::usub_with_overflow;
+ break;
+ case 'v':
+ if (Len == 12 && !memcmp(Name, "llvm.va_copy", 12)) return Intrinsic::vacopy;
+ if (Len == 11 && !memcmp(Name, "llvm.va_end", 11)) return Intrinsic::vaend;
+ if (Len == 13 && !memcmp(Name, "llvm.va_start", 13)) return Intrinsic::vastart;
+ if (Len == 19 && !memcmp(Name, "llvm.var.annotation", 19)) return Intrinsic::var_annotation;
+ break;
+ case 'x':
+ if (Len == 17 && !memcmp(Name, "llvm.x86.mmx.emms", 17)) return Intrinsic::x86_mmx_emms;
+ if (Len == 18 && !memcmp(Name, "llvm.x86.mmx.femms", 18)) return Intrinsic::x86_mmx_femms;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.maskmovq", 21)) return Intrinsic::x86_mmx_maskmovq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.movnt.dq", 21)) return Intrinsic::x86_mmx_movnt_dq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.packssdw", 21)) return Intrinsic::x86_mmx_packssdw;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.packsswb", 21)) return Intrinsic::x86_mmx_packsswb;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.packuswb", 21)) return Intrinsic::x86_mmx_packuswb;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.padds.b", 20)) return Intrinsic::x86_mmx_padds_b;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.padds.w", 20)) return Intrinsic::x86_mmx_padds_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.paddus.b", 21)) return Intrinsic::x86_mmx_paddus_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.paddus.w", 21)) return Intrinsic::x86_mmx_paddus_w;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.pavg.b", 19)) return Intrinsic::x86_mmx_pavg_b;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.pavg.w", 19)) return Intrinsic::x86_mmx_pavg_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pcmpeq.b", 21)) return Intrinsic::x86_mmx_pcmpeq_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pcmpeq.d", 21)) return Intrinsic::x86_mmx_pcmpeq_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pcmpeq.w", 21)) return Intrinsic::x86_mmx_pcmpeq_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pcmpgt.b", 21)) return Intrinsic::x86_mmx_pcmpgt_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pcmpgt.d", 21)) return Intrinsic::x86_mmx_pcmpgt_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pcmpgt.w", 21)) return Intrinsic::x86_mmx_pcmpgt_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pmadd.wd", 21)) return Intrinsic::x86_mmx_pmadd_wd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pmaxs.w", 20)) return Intrinsic::x86_mmx_pmaxs_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pmaxu.b", 20)) return Intrinsic::x86_mmx_pmaxu_b;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pmins.w", 20)) return Intrinsic::x86_mmx_pmins_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pminu.b", 20)) return Intrinsic::x86_mmx_pminu_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pmovmskb", 21)) return Intrinsic::x86_mmx_pmovmskb;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pmulh.w", 20)) return Intrinsic::x86_mmx_pmulh_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pmulhu.w", 21)) return Intrinsic::x86_mmx_pmulhu_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.pmulu.dq", 21)) return Intrinsic::x86_mmx_pmulu_dq;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psad.bw", 20)) return Intrinsic::x86_mmx_psad_bw;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psll.d", 19)) return Intrinsic::x86_mmx_psll_d;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psll.q", 19)) return Intrinsic::x86_mmx_psll_q;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psll.w", 19)) return Intrinsic::x86_mmx_psll_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pslli.d", 20)) return Intrinsic::x86_mmx_pslli_d;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pslli.q", 20)) return Intrinsic::x86_mmx_pslli_q;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.pslli.w", 20)) return Intrinsic::x86_mmx_pslli_w;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psra.d", 19)) return Intrinsic::x86_mmx_psra_d;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psra.w", 19)) return Intrinsic::x86_mmx_psra_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psrai.d", 20)) return Intrinsic::x86_mmx_psrai_d;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psrai.w", 20)) return Intrinsic::x86_mmx_psrai_w;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psrl.d", 19)) return Intrinsic::x86_mmx_psrl_d;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psrl.q", 19)) return Intrinsic::x86_mmx_psrl_q;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.mmx.psrl.w", 19)) return Intrinsic::x86_mmx_psrl_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psrli.d", 20)) return Intrinsic::x86_mmx_psrli_d;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psrli.q", 20)) return Intrinsic::x86_mmx_psrli_q;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psrli.w", 20)) return Intrinsic::x86_mmx_psrli_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psubs.b", 20)) return Intrinsic::x86_mmx_psubs_b;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.mmx.psubs.w", 20)) return Intrinsic::x86_mmx_psubs_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.psubus.b", 21)) return Intrinsic::x86_mmx_psubus_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.mmx.psubus.w", 21)) return Intrinsic::x86_mmx_psubus_w;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.add.ss", 19)) return Intrinsic::x86_sse_add_ss;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.cmp.ps", 19)) return Intrinsic::x86_sse_cmp_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.cmp.ss", 19)) return Intrinsic::x86_sse_cmp_ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.comieq.ss", 22)) return Intrinsic::x86_sse_comieq_ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.comige.ss", 22)) return Intrinsic::x86_sse_comige_ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.comigt.ss", 22)) return Intrinsic::x86_sse_comigt_ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.comile.ss", 22)) return Intrinsic::x86_sse_comile_ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.comilt.ss", 22)) return Intrinsic::x86_sse_comilt_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.comineq.ss", 23)) return Intrinsic::x86_sse_comineq_ss;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.cvtpd2pi", 21)) return Intrinsic::x86_sse_cvtpd2pi;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.cvtpi2pd", 21)) return Intrinsic::x86_sse_cvtpi2pd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.cvtpi2ps", 21)) return Intrinsic::x86_sse_cvtpi2ps;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.cvtps2pi", 21)) return Intrinsic::x86_sse_cvtps2pi;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.cvtsi2ss", 21)) return Intrinsic::x86_sse_cvtsi2ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.cvtsi642ss", 23)) return Intrinsic::x86_sse_cvtsi642ss;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.cvtss2si", 21)) return Intrinsic::x86_sse_cvtss2si;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.cvtss2si64", 23)) return Intrinsic::x86_sse_cvtss2si64;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.cvttpd2pi", 22)) return Intrinsic::x86_sse_cvttpd2pi;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.cvttps2pi", 22)) return Intrinsic::x86_sse_cvttps2pi;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.cvttss2si", 22)) return Intrinsic::x86_sse_cvttss2si;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse.cvttss2si64", 24)) return Intrinsic::x86_sse_cvttss2si64;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.div.ss", 19)) return Intrinsic::x86_sse_div_ss;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse.ldmxcsr", 20)) return Intrinsic::x86_sse_ldmxcsr;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.loadu.ps", 21)) return Intrinsic::x86_sse_loadu_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.max.ps", 19)) return Intrinsic::x86_sse_max_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.max.ss", 19)) return Intrinsic::x86_sse_max_ss;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.min.ps", 19)) return Intrinsic::x86_sse_min_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.min.ss", 19)) return Intrinsic::x86_sse_min_ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.movmsk.ps", 22)) return Intrinsic::x86_sse_movmsk_ps;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.movnt.ps", 21)) return Intrinsic::x86_sse_movnt_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.mul.ss", 19)) return Intrinsic::x86_sse_mul_ss;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.rcp.ps", 19)) return Intrinsic::x86_sse_rcp_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.rcp.ss", 19)) return Intrinsic::x86_sse_rcp_ss;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.rsqrt.ps", 21)) return Intrinsic::x86_sse_rsqrt_ps;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse.rsqrt.ss", 21)) return Intrinsic::x86_sse_rsqrt_ss;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.sfence", 19)) return Intrinsic::x86_sse_sfence;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse.sqrt.ps", 20)) return Intrinsic::x86_sse_sqrt_ps;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse.sqrt.ss", 20)) return Intrinsic::x86_sse_sqrt_ss;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse.stmxcsr", 20)) return Intrinsic::x86_sse_stmxcsr;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse.storeu.ps", 22)) return Intrinsic::x86_sse_storeu_ps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse.sub.ss", 19)) return Intrinsic::x86_sse_sub_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.ucomieq.ss", 23)) return Intrinsic::x86_sse_ucomieq_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.ucomige.ss", 23)) return Intrinsic::x86_sse_ucomige_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.ucomigt.ss", 23)) return Intrinsic::x86_sse_ucomigt_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.ucomile.ss", 23)) return Intrinsic::x86_sse_ucomile_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse.ucomilt.ss", 23)) return Intrinsic::x86_sse_ucomilt_ss;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse.ucomineq.ss", 24)) return Intrinsic::x86_sse_ucomineq_ss;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.add.sd", 20)) return Intrinsic::x86_sse2_add_sd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.clflush", 21)) return Intrinsic::x86_sse2_clflush;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.cmp.pd", 20)) return Intrinsic::x86_sse2_cmp_pd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.cmp.sd", 20)) return Intrinsic::x86_sse2_cmp_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.comieq.sd", 23)) return Intrinsic::x86_sse2_comieq_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.comige.sd", 23)) return Intrinsic::x86_sse2_comige_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.comigt.sd", 23)) return Intrinsic::x86_sse2_comigt_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.comile.sd", 23)) return Intrinsic::x86_sse2_comile_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.comilt.sd", 23)) return Intrinsic::x86_sse2_comilt_sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.comineq.sd", 24)) return Intrinsic::x86_sse2_comineq_sd;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtdq2pd", 22)) return Intrinsic::x86_sse2_cvtdq2pd;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtdq2ps", 22)) return Intrinsic::x86_sse2_cvtdq2ps;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtpd2dq", 22)) return Intrinsic::x86_sse2_cvtpd2dq;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtpd2ps", 22)) return Intrinsic::x86_sse2_cvtpd2ps;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtps2dq", 22)) return Intrinsic::x86_sse2_cvtps2dq;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtps2pd", 22)) return Intrinsic::x86_sse2_cvtps2pd;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtsd2si", 22)) return Intrinsic::x86_sse2_cvtsd2si;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.cvtsd2si64", 24)) return Intrinsic::x86_sse2_cvtsd2si64;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtsd2ss", 22)) return Intrinsic::x86_sse2_cvtsd2ss;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtsi2sd", 22)) return Intrinsic::x86_sse2_cvtsi2sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.cvtsi642sd", 24)) return Intrinsic::x86_sse2_cvtsi642sd;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.cvtss2sd", 22)) return Intrinsic::x86_sse2_cvtss2sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.cvttpd2dq", 23)) return Intrinsic::x86_sse2_cvttpd2dq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.cvttps2dq", 23)) return Intrinsic::x86_sse2_cvttps2dq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.cvttsd2si", 23)) return Intrinsic::x86_sse2_cvttsd2si;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.sse2.cvttsd2si64", 25)) return Intrinsic::x86_sse2_cvttsd2si64;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.div.sd", 20)) return Intrinsic::x86_sse2_div_sd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.lfence", 20)) return Intrinsic::x86_sse2_lfence;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.loadu.dq", 22)) return Intrinsic::x86_sse2_loadu_dq;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.loadu.pd", 22)) return Intrinsic::x86_sse2_loadu_pd;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.sse2.maskmov.dqu", 25)) return Intrinsic::x86_sse2_maskmov_dqu;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.max.pd", 20)) return Intrinsic::x86_sse2_max_pd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.max.sd", 20)) return Intrinsic::x86_sse2_max_sd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.mfence", 20)) return Intrinsic::x86_sse2_mfence;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.min.pd", 20)) return Intrinsic::x86_sse2_min_pd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.min.sd", 20)) return Intrinsic::x86_sse2_min_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.movmsk.pd", 23)) return Intrinsic::x86_sse2_movmsk_pd;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.movnt.dq", 22)) return Intrinsic::x86_sse2_movnt_dq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.movnt.i", 21)) return Intrinsic::x86_sse2_movnt_i;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.movnt.pd", 22)) return Intrinsic::x86_sse2_movnt_pd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.mul.sd", 20)) return Intrinsic::x86_sse2_mul_sd;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.sse2.packssdw.128", 26)) return Intrinsic::x86_sse2_packssdw_128;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.sse2.packsswb.128", 26)) return Intrinsic::x86_sse2_packsswb_128;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.sse2.packuswb.128", 26)) return Intrinsic::x86_sse2_packuswb_128;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.padds.b", 21)) return Intrinsic::x86_sse2_padds_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.padds.w", 21)) return Intrinsic::x86_sse2_padds_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.paddus.b", 22)) return Intrinsic::x86_sse2_paddus_b;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.paddus.w", 22)) return Intrinsic::x86_sse2_paddus_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.pavg.b", 20)) return Intrinsic::x86_sse2_pavg_b;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.pavg.w", 20)) return Intrinsic::x86_sse2_pavg_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pcmpeq.b", 22)) return Intrinsic::x86_sse2_pcmpeq_b;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pcmpeq.d", 22)) return Intrinsic::x86_sse2_pcmpeq_d;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pcmpeq.w", 22)) return Intrinsic::x86_sse2_pcmpeq_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pcmpgt.b", 22)) return Intrinsic::x86_sse2_pcmpgt_b;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pcmpgt.d", 22)) return Intrinsic::x86_sse2_pcmpgt_d;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pcmpgt.w", 22)) return Intrinsic::x86_sse2_pcmpgt_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pmadd.wd", 22)) return Intrinsic::x86_sse2_pmadd_wd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pmaxs.w", 21)) return Intrinsic::x86_sse2_pmaxs_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pmaxu.b", 21)) return Intrinsic::x86_sse2_pmaxu_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pmins.w", 21)) return Intrinsic::x86_sse2_pmins_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pminu.b", 21)) return Intrinsic::x86_sse2_pminu_b;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.sse2.pmovmskb.128", 26)) return Intrinsic::x86_sse2_pmovmskb_128;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pmulh.w", 21)) return Intrinsic::x86_sse2_pmulh_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pmulhu.w", 22)) return Intrinsic::x86_sse2_pmulhu_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.pmulu.dq", 22)) return Intrinsic::x86_sse2_pmulu_dq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psad.bw", 21)) return Intrinsic::x86_sse2_psad_bw;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psll.d", 20)) return Intrinsic::x86_sse2_psll_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psll.dq", 21)) return Intrinsic::x86_sse2_psll_dq;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.psll.dq.bs", 24)) return Intrinsic::x86_sse2_psll_dq_bs;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psll.q", 20)) return Intrinsic::x86_sse2_psll_q;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psll.w", 20)) return Intrinsic::x86_sse2_psll_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pslli.d", 21)) return Intrinsic::x86_sse2_pslli_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pslli.q", 21)) return Intrinsic::x86_sse2_pslli_q;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.pslli.w", 21)) return Intrinsic::x86_sse2_pslli_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psra.d", 20)) return Intrinsic::x86_sse2_psra_d;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psra.w", 20)) return Intrinsic::x86_sse2_psra_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psrai.d", 21)) return Intrinsic::x86_sse2_psrai_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psrai.w", 21)) return Intrinsic::x86_sse2_psrai_w;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psrl.d", 20)) return Intrinsic::x86_sse2_psrl_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psrl.dq", 21)) return Intrinsic::x86_sse2_psrl_dq;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.psrl.dq.bs", 24)) return Intrinsic::x86_sse2_psrl_dq_bs;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psrl.q", 20)) return Intrinsic::x86_sse2_psrl_q;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.psrl.w", 20)) return Intrinsic::x86_sse2_psrl_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psrli.d", 21)) return Intrinsic::x86_sse2_psrli_d;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psrli.q", 21)) return Intrinsic::x86_sse2_psrli_q;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psrli.w", 21)) return Intrinsic::x86_sse2_psrli_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psubs.b", 21)) return Intrinsic::x86_sse2_psubs_b;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.psubs.w", 21)) return Intrinsic::x86_sse2_psubs_w;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.psubus.b", 22)) return Intrinsic::x86_sse2_psubus_b;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse2.psubus.w", 22)) return Intrinsic::x86_sse2_psubus_w;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.sqrt.pd", 21)) return Intrinsic::x86_sse2_sqrt_pd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse2.sqrt.sd", 21)) return Intrinsic::x86_sse2_sqrt_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.storel.dq", 23)) return Intrinsic::x86_sse2_storel_dq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.storeu.dq", 23)) return Intrinsic::x86_sse2_storeu_dq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse2.storeu.pd", 23)) return Intrinsic::x86_sse2_storeu_pd;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse2.sub.sd", 20)) return Intrinsic::x86_sse2_sub_sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.ucomieq.sd", 24)) return Intrinsic::x86_sse2_ucomieq_sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.ucomige.sd", 24)) return Intrinsic::x86_sse2_ucomige_sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.ucomigt.sd", 24)) return Intrinsic::x86_sse2_ucomigt_sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.ucomile.sd", 24)) return Intrinsic::x86_sse2_ucomile_sd;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse2.ucomilt.sd", 24)) return Intrinsic::x86_sse2_ucomilt_sd;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.sse2.ucomineq.sd", 25)) return Intrinsic::x86_sse2_ucomineq_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse3.addsub.pd", 23)) return Intrinsic::x86_sse3_addsub_pd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse3.addsub.ps", 23)) return Intrinsic::x86_sse3_addsub_ps;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse3.hadd.pd", 21)) return Intrinsic::x86_sse3_hadd_pd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse3.hadd.ps", 21)) return Intrinsic::x86_sse3_hadd_ps;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse3.hsub.pd", 21)) return Intrinsic::x86_sse3_hsub_pd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse3.hsub.ps", 21)) return Intrinsic::x86_sse3_hsub_ps;
+ if (Len == 20 && !memcmp(Name, "llvm.x86.sse3.ldu.dq", 20)) return Intrinsic::x86_sse3_ldu_dq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse3.monitor", 21)) return Intrinsic::x86_sse3_monitor;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse3.mwait", 19)) return Intrinsic::x86_sse3_mwait;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse41.blendpd", 22)) return Intrinsic::x86_sse41_blendpd;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse41.blendps", 22)) return Intrinsic::x86_sse41_blendps;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.blendvpd", 23)) return Intrinsic::x86_sse41_blendvpd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.blendvps", 23)) return Intrinsic::x86_sse41_blendvps;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse41.dppd", 19)) return Intrinsic::x86_sse41_dppd;
+ if (Len == 19 && !memcmp(Name, "llvm.x86.sse41.dpps", 19)) return Intrinsic::x86_sse41_dpps;
+ if (Len == 24 && !memcmp(Name, "llvm.x86.sse41.extractps", 24)) return Intrinsic::x86_sse41_extractps;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.insertps", 23)) return Intrinsic::x86_sse41_insertps;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.movntdqa", 23)) return Intrinsic::x86_sse41_movntdqa;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse41.mpsadbw", 22)) return Intrinsic::x86_sse41_mpsadbw;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.packusdw", 23)) return Intrinsic::x86_sse41_packusdw;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pblendvb", 23)) return Intrinsic::x86_sse41_pblendvb;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse41.pblendw", 22)) return Intrinsic::x86_sse41_pblendw;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse41.pcmpeqq", 22)) return Intrinsic::x86_sse41_pcmpeqq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pextrb", 21)) return Intrinsic::x86_sse41_pextrb;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pextrd", 21)) return Intrinsic::x86_sse41_pextrd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pextrq", 21)) return Intrinsic::x86_sse41_pextrq;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.sse41.phminposuw", 25)) return Intrinsic::x86_sse41_phminposuw;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pmaxsb", 21)) return Intrinsic::x86_sse41_pmaxsb;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pmaxsd", 21)) return Intrinsic::x86_sse41_pmaxsd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pmaxud", 21)) return Intrinsic::x86_sse41_pmaxud;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pmaxuw", 21)) return Intrinsic::x86_sse41_pmaxuw;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pminsb", 21)) return Intrinsic::x86_sse41_pminsb;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pminsd", 21)) return Intrinsic::x86_sse41_pminsd;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pminud", 21)) return Intrinsic::x86_sse41_pminud;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pminuw", 21)) return Intrinsic::x86_sse41_pminuw;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovsxbd", 23)) return Intrinsic::x86_sse41_pmovsxbd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovsxbq", 23)) return Intrinsic::x86_sse41_pmovsxbq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovsxbw", 23)) return Intrinsic::x86_sse41_pmovsxbw;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovsxdq", 23)) return Intrinsic::x86_sse41_pmovsxdq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovsxwd", 23)) return Intrinsic::x86_sse41_pmovsxwd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovsxwq", 23)) return Intrinsic::x86_sse41_pmovsxwq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovzxbd", 23)) return Intrinsic::x86_sse41_pmovzxbd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovzxbq", 23)) return Intrinsic::x86_sse41_pmovzxbq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovzxbw", 23)) return Intrinsic::x86_sse41_pmovzxbw;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovzxdq", 23)) return Intrinsic::x86_sse41_pmovzxdq;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovzxwd", 23)) return Intrinsic::x86_sse41_pmovzxwd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.pmovzxwq", 23)) return Intrinsic::x86_sse41_pmovzxwq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pmuldq", 21)) return Intrinsic::x86_sse41_pmuldq;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.pmulld", 21)) return Intrinsic::x86_sse41_pmulld;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.ptestc", 21)) return Intrinsic::x86_sse41_ptestc;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.ptestnzc", 23)) return Intrinsic::x86_sse41_ptestnzc;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.sse41.ptestz", 21)) return Intrinsic::x86_sse41_ptestz;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.round.pd", 23)) return Intrinsic::x86_sse41_round_pd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.round.ps", 23)) return Intrinsic::x86_sse41_round_ps;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.round.sd", 23)) return Intrinsic::x86_sse41_round_sd;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse41.round.ss", 23)) return Intrinsic::x86_sse41_round_ss;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse42.crc32.16", 23)) return Intrinsic::x86_sse42_crc32_16;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse42.crc32.32", 23)) return Intrinsic::x86_sse42_crc32_32;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.sse42.crc32.64", 23)) return Intrinsic::x86_sse42_crc32_64;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse42.crc32.8", 22)) return Intrinsic::x86_sse42_crc32_8;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.sse42.pcmpestri128", 27)) return Intrinsic::x86_sse42_pcmpestri128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpestria128", 28)) return Intrinsic::x86_sse42_pcmpestria128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpestric128", 28)) return Intrinsic::x86_sse42_pcmpestric128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpestrio128", 28)) return Intrinsic::x86_sse42_pcmpestrio128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpestris128", 28)) return Intrinsic::x86_sse42_pcmpestris128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpestriz128", 28)) return Intrinsic::x86_sse42_pcmpestriz128;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.sse42.pcmpestrm128", 27)) return Intrinsic::x86_sse42_pcmpestrm128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.sse42.pcmpgtq", 22)) return Intrinsic::x86_sse42_pcmpgtq;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.sse42.pcmpistri128", 27)) return Intrinsic::x86_sse42_pcmpistri128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpistria128", 28)) return Intrinsic::x86_sse42_pcmpistria128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpistric128", 28)) return Intrinsic::x86_sse42_pcmpistric128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpistrio128", 28)) return Intrinsic::x86_sse42_pcmpistrio128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpistris128", 28)) return Intrinsic::x86_sse42_pcmpistris128;
+ if (Len == 28 && !memcmp(Name, "llvm.x86.sse42.pcmpistriz128", 28)) return Intrinsic::x86_sse42_pcmpistriz128;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.sse42.pcmpistrm128", 27)) return Intrinsic::x86_sse42_pcmpistrm128;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.ssse3.pabs.b", 21)) return Intrinsic::x86_ssse3_pabs_b;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.ssse3.pabs.b.128", 25)) return Intrinsic::x86_ssse3_pabs_b_128;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.ssse3.pabs.d", 21)) return Intrinsic::x86_ssse3_pabs_d;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.ssse3.pabs.d.128", 25)) return Intrinsic::x86_ssse3_pabs_d_128;
+ if (Len == 21 && !memcmp(Name, "llvm.x86.ssse3.pabs.w", 21)) return Intrinsic::x86_ssse3_pabs_w;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.ssse3.pabs.w.128", 25)) return Intrinsic::x86_ssse3_pabs_w_128;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.ssse3.palign.r", 23)) return Intrinsic::x86_ssse3_palign_r;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.ssse3.palign.r.128", 27)) return Intrinsic::x86_ssse3_palign_r_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.phadd.d", 22)) return Intrinsic::x86_ssse3_phadd_d;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.phadd.d.128", 26)) return Intrinsic::x86_ssse3_phadd_d_128;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.ssse3.phadd.sw", 23)) return Intrinsic::x86_ssse3_phadd_sw;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.ssse3.phadd.sw.128", 27)) return Intrinsic::x86_ssse3_phadd_sw_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.phadd.w", 22)) return Intrinsic::x86_ssse3_phadd_w;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.phadd.w.128", 26)) return Intrinsic::x86_ssse3_phadd_w_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.phsub.d", 22)) return Intrinsic::x86_ssse3_phsub_d;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.phsub.d.128", 26)) return Intrinsic::x86_ssse3_phsub_d_128;
+ if (Len == 23 && !memcmp(Name, "llvm.x86.ssse3.phsub.sw", 23)) return Intrinsic::x86_ssse3_phsub_sw;
+ if (Len == 27 && !memcmp(Name, "llvm.x86.ssse3.phsub.sw.128", 27)) return Intrinsic::x86_ssse3_phsub_sw_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.phsub.w", 22)) return Intrinsic::x86_ssse3_phsub_w;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.phsub.w.128", 26)) return Intrinsic::x86_ssse3_phsub_w_128;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.pmadd.ub.sw", 26)) return Intrinsic::x86_ssse3_pmadd_ub_sw;
+ if (Len == 30 && !memcmp(Name, "llvm.x86.ssse3.pmadd.ub.sw.128", 30)) return Intrinsic::x86_ssse3_pmadd_ub_sw_128;
+ if (Len == 25 && !memcmp(Name, "llvm.x86.ssse3.pmul.hr.sw", 25)) return Intrinsic::x86_ssse3_pmul_hr_sw;
+ if (Len == 29 && !memcmp(Name, "llvm.x86.ssse3.pmul.hr.sw.128", 29)) return Intrinsic::x86_ssse3_pmul_hr_sw_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.pshuf.b", 22)) return Intrinsic::x86_ssse3_pshuf_b;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.pshuf.b.128", 26)) return Intrinsic::x86_ssse3_pshuf_b_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.psign.b", 22)) return Intrinsic::x86_ssse3_psign_b;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.psign.b.128", 26)) return Intrinsic::x86_ssse3_psign_b_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.psign.d", 22)) return Intrinsic::x86_ssse3_psign_d;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.psign.d.128", 26)) return Intrinsic::x86_ssse3_psign_d_128;
+ if (Len == 22 && !memcmp(Name, "llvm.x86.ssse3.psign.w", 22)) return Intrinsic::x86_ssse3_psign_w;
+ if (Len == 26 && !memcmp(Name, "llvm.x86.ssse3.psign.w.128", 26)) return Intrinsic::x86_ssse3_psign_w_128;
+ if (Len == 17 && !memcmp(Name, "llvm.xcore.bitrev", 17)) return Intrinsic::xcore_bitrev;
+ if (Len == 16 && !memcmp(Name, "llvm.xcore.getid", 16)) return Intrinsic::xcore_getid;
+ }
+#endif
+
+// Verifier::visitIntrinsicFunctionCall code.
+#ifdef GET_INTRINSIC_VERIFIER
+ switch (ID) {
+ default: assert(0 && "Invalid intrinsic!");
+ case Intrinsic::ptr_annotation: // llvm.ptr.annotation
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::iPTRAny, ~0, MVT::iPTR, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::sin: // llvm.sin
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::cos: // llvm.cos
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::pow: // llvm.pow
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::fAny, ~0, ~0);
+ break;
+ case Intrinsic::log: // llvm.log
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::log10: // llvm.log10
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::log2: // llvm.log2
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::exp: // llvm.exp
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::exp2: // llvm.exp2
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::sqrt: // llvm.sqrt
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::fAny, ~0);
+ break;
+ case Intrinsic::powi: // llvm.powi
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::fAny, ~0, MVT::i32);
+ break;
+ case Intrinsic::convertff: // llvm.convertff
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::fAny, MVT::fAny, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::arm_neon_vcvtfxs2fp: // llvm.arm.neon.vcvtfxs2fp
+ case Intrinsic::arm_neon_vcvtfxu2fp: // llvm.arm.neon.vcvtfxu2fp
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::fAny, MVT::iAny, MVT::i32);
+ break;
+ case Intrinsic::convertfsi: // llvm.convertfsi
+ case Intrinsic::convertfui: // llvm.convertfui
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::fAny, MVT::iAny, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::bswap: // llvm.bswap
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);
+ break;
+ case Intrinsic::ctpop: // llvm.ctpop
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);
+ break;
+ case Intrinsic::ctlz: // llvm.ctlz
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);
+ break;
+ case Intrinsic::cttz: // llvm.cttz
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iAny, ~0);
+ break;
+ case Intrinsic::annotation: // llvm.annotation
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::iAny, ~0, MVT::iPTR, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::atomic_cmp_swap: // llvm.atomic.cmp.swap
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iAny, MVT::iPTRAny, ~0, ~0);
+ break;
+ case Intrinsic::atomic_load_add: // llvm.atomic.load.add
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_swap: // llvm.atomic.swap
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_sub: // llvm.atomic.load.sub
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_and: // llvm.atomic.load.and
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_or: // llvm.atomic.load.or
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_xor: // llvm.atomic.load.xor
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_nand: // llvm.atomic.load.nand
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_min: // llvm.atomic.load.min
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_max: // llvm.atomic.load.max
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_umin: // llvm.atomic.load.umin
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::atomic_load_umax: // llvm.atomic.load.umax
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTRAny, ~0);
+ break;
+ case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs
+ case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::fAny, MVT::i32);
+ break;
+ case Intrinsic::convertsif: // llvm.convertsif
+ case Intrinsic::convertuif: // llvm.convertuif
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iAny, MVT::fAny, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::convertss: // llvm.convertss
+ case Intrinsic::convertsu: // llvm.convertsu
+ case Intrinsic::convertus: // llvm.convertus
+ case Intrinsic::convertuu: // llvm.convertuu
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iAny, MVT::iAny, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::objectsize: // llvm.objectsize
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iAny, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::sadd_with_overflow: // llvm.sadd.with.overflow
+ VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
+ break;
+ case Intrinsic::uadd_with_overflow: // llvm.uadd.with.overflow
+ VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
+ break;
+ case Intrinsic::ssub_with_overflow: // llvm.ssub.with.overflow
+ VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
+ break;
+ case Intrinsic::usub_with_overflow: // llvm.usub.with.overflow
+ VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
+ break;
+ case Intrinsic::smul_with_overflow: // llvm.smul.with.overflow
+ VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
+ break;
+ case Intrinsic::umul_with_overflow: // llvm.umul.with.overflow
+ VerifyIntrinsicPrototype(ID, IF, 2, 2, MVT::iAny, MVT::i1, ~0, ~0);
+ break;
+ case Intrinsic::arm_neon_vaddws: // llvm.arm.neon.vaddws
+ case Intrinsic::arm_neon_vaddwu: // llvm.arm.neon.vaddwu
+ case Intrinsic::arm_neon_vsubws: // llvm.arm.neon.vsubws
+ case Intrinsic::arm_neon_vsubwu: // llvm.arm.neon.vsubwu
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, ~(TruncatedElementVectorType | 0));
+ break;
+ case Intrinsic::arm_neon_vabas: // llvm.arm.neon.vabas
+ case Intrinsic::arm_neon_vabau: // llvm.arm.neon.vabau
+ case Intrinsic::arm_neon_vshiftins: // llvm.arm.neon.vshiftins
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::vAny, ~0, ~0, ~0);
+ break;
+ case Intrinsic::arm_neon_vabals: // llvm.arm.neon.vabals
+ case Intrinsic::arm_neon_vabalu: // llvm.arm.neon.vabalu
+ case Intrinsic::arm_neon_vmlals: // llvm.arm.neon.vmlals
+ case Intrinsic::arm_neon_vmlalu: // llvm.arm.neon.vmlalu
+ case Intrinsic::arm_neon_vmlsls: // llvm.arm.neon.vmlsls
+ case Intrinsic::arm_neon_vmlslu: // llvm.arm.neon.vmlslu
+ case Intrinsic::arm_neon_vqdmlal: // llvm.arm.neon.vqdmlal
+ case Intrinsic::arm_neon_vqdmlsl: // llvm.arm.neon.vqdmlsl
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::vAny, ~0, ~(TruncatedElementVectorType | 0), ~(TruncatedElementVectorType | 0));
+ break;
+ case Intrinsic::arm_neon_vpadals: // llvm.arm.neon.vpadals
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, MVT::vAny);
+ break;
+ case Intrinsic::arm_neon_vpadalu: // llvm.arm.neon.vpadalu
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, MVT::vAny);
+ break;
+ case Intrinsic::arm_neon_vabs: // llvm.arm.neon.vabs
+ case Intrinsic::arm_neon_vcls: // llvm.arm.neon.vcls
+ case Intrinsic::arm_neon_vclz: // llvm.arm.neon.vclz
+ case Intrinsic::arm_neon_vcnt: // llvm.arm.neon.vcnt
+ case Intrinsic::arm_neon_vqabs: // llvm.arm.neon.vqabs
+ case Intrinsic::arm_neon_vqneg: // llvm.arm.neon.vqneg
+ case Intrinsic::arm_neon_vrecpe: // llvm.arm.neon.vrecpe
+ case Intrinsic::arm_neon_vrsqrte: // llvm.arm.neon.vrsqrte
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, ~0);
+ break;
+ case Intrinsic::arm_neon_vmovn: // llvm.arm.neon.vmovn
+ case Intrinsic::arm_neon_vqmovns: // llvm.arm.neon.vqmovns
+ case Intrinsic::arm_neon_vqmovnsu: // llvm.arm.neon.vqmovnsu
+ case Intrinsic::arm_neon_vqmovnu: // llvm.arm.neon.vqmovnu
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, ~(ExtendedElementVectorType | 0));
+ break;
+ case Intrinsic::arm_neon_vmovls: // llvm.arm.neon.vmovls
+ case Intrinsic::arm_neon_vmovlu: // llvm.arm.neon.vmovlu
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, ~(TruncatedElementVectorType | 0));
+ break;
+ case Intrinsic::arm_neon_vabds: // llvm.arm.neon.vabds
+ case Intrinsic::arm_neon_vabdu: // llvm.arm.neon.vabdu
+ case Intrinsic::arm_neon_vhadds: // llvm.arm.neon.vhadds
+ case Intrinsic::arm_neon_vhaddu: // llvm.arm.neon.vhaddu
+ case Intrinsic::arm_neon_vhsubs: // llvm.arm.neon.vhsubs
+ case Intrinsic::arm_neon_vhsubu: // llvm.arm.neon.vhsubu
+ case Intrinsic::arm_neon_vmaxs: // llvm.arm.neon.vmaxs
+ case Intrinsic::arm_neon_vmaxu: // llvm.arm.neon.vmaxu
+ case Intrinsic::arm_neon_vmins: // llvm.arm.neon.vmins
+ case Intrinsic::arm_neon_vminu: // llvm.arm.neon.vminu
+ case Intrinsic::arm_neon_vmulp: // llvm.arm.neon.vmulp
+ case Intrinsic::arm_neon_vpadd: // llvm.arm.neon.vpadd
+ case Intrinsic::arm_neon_vpmaxs: // llvm.arm.neon.vpmaxs
+ case Intrinsic::arm_neon_vpmaxu: // llvm.arm.neon.vpmaxu
+ case Intrinsic::arm_neon_vpmins: // llvm.arm.neon.vpmins
+ case Intrinsic::arm_neon_vpminu: // llvm.arm.neon.vpminu
+ case Intrinsic::arm_neon_vqadds: // llvm.arm.neon.vqadds
+ case Intrinsic::arm_neon_vqaddu: // llvm.arm.neon.vqaddu
+ case Intrinsic::arm_neon_vqdmulh: // llvm.arm.neon.vqdmulh
+ case Intrinsic::arm_neon_vqrdmulh: // llvm.arm.neon.vqrdmulh
+ case Intrinsic::arm_neon_vqrshifts: // llvm.arm.neon.vqrshifts
+ case Intrinsic::arm_neon_vqrshiftu: // llvm.arm.neon.vqrshiftu
+ case Intrinsic::arm_neon_vqshifts: // llvm.arm.neon.vqshifts
+ case Intrinsic::arm_neon_vqshiftsu: // llvm.arm.neon.vqshiftsu
+ case Intrinsic::arm_neon_vqshiftu: // llvm.arm.neon.vqshiftu
+ case Intrinsic::arm_neon_vqsubs: // llvm.arm.neon.vqsubs
+ case Intrinsic::arm_neon_vqsubu: // llvm.arm.neon.vqsubu
+ case Intrinsic::arm_neon_vrecps: // llvm.arm.neon.vrecps
+ case Intrinsic::arm_neon_vrhadds: // llvm.arm.neon.vrhadds
+ case Intrinsic::arm_neon_vrhaddu: // llvm.arm.neon.vrhaddu
+ case Intrinsic::arm_neon_vrshifts: // llvm.arm.neon.vrshifts
+ case Intrinsic::arm_neon_vrshiftu: // llvm.arm.neon.vrshiftu
+ case Intrinsic::arm_neon_vrsqrts: // llvm.arm.neon.vrsqrts
+ case Intrinsic::arm_neon_vshifts: // llvm.arm.neon.vshifts
+ case Intrinsic::arm_neon_vshiftu: // llvm.arm.neon.vshiftu
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~0, ~0);
+ break;
+ case Intrinsic::arm_neon_vaddhn: // llvm.arm.neon.vaddhn
+ case Intrinsic::arm_neon_vqrshiftns: // llvm.arm.neon.vqrshiftns
+ case Intrinsic::arm_neon_vqrshiftnsu: // llvm.arm.neon.vqrshiftnsu
+ case Intrinsic::arm_neon_vqrshiftnu: // llvm.arm.neon.vqrshiftnu
+ case Intrinsic::arm_neon_vqshiftns: // llvm.arm.neon.vqshiftns
+ case Intrinsic::arm_neon_vqshiftnsu: // llvm.arm.neon.vqshiftnsu
+ case Intrinsic::arm_neon_vqshiftnu: // llvm.arm.neon.vqshiftnu
+ case Intrinsic::arm_neon_vraddhn: // llvm.arm.neon.vraddhn
+ case Intrinsic::arm_neon_vrshiftn: // llvm.arm.neon.vrshiftn
+ case Intrinsic::arm_neon_vrsubhn: // llvm.arm.neon.vrsubhn
+ case Intrinsic::arm_neon_vshiftn: // llvm.arm.neon.vshiftn
+ case Intrinsic::arm_neon_vsubhn: // llvm.arm.neon.vsubhn
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~(ExtendedElementVectorType | 0), ~(ExtendedElementVectorType | 0));
+ break;
+ case Intrinsic::arm_neon_vabdls: // llvm.arm.neon.vabdls
+ case Intrinsic::arm_neon_vabdlu: // llvm.arm.neon.vabdlu
+ case Intrinsic::arm_neon_vaddls: // llvm.arm.neon.vaddls
+ case Intrinsic::arm_neon_vaddlu: // llvm.arm.neon.vaddlu
+ case Intrinsic::arm_neon_vmullp: // llvm.arm.neon.vmullp
+ case Intrinsic::arm_neon_vmulls: // llvm.arm.neon.vmulls
+ case Intrinsic::arm_neon_vmullu: // llvm.arm.neon.vmullu
+ case Intrinsic::arm_neon_vqdmull: // llvm.arm.neon.vqdmull
+ case Intrinsic::arm_neon_vshiftls: // llvm.arm.neon.vshiftls
+ case Intrinsic::arm_neon_vshiftlu: // llvm.arm.neon.vshiftlu
+ case Intrinsic::arm_neon_vsubls: // llvm.arm.neon.vsubls
+ case Intrinsic::arm_neon_vsublu: // llvm.arm.neon.vsublu
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::vAny, ~(TruncatedElementVectorType | 0), ~(TruncatedElementVectorType | 0));
+ break;
+ case Intrinsic::arm_neon_vpaddls: // llvm.arm.neon.vpaddls
+ case Intrinsic::arm_neon_vpaddlu: // llvm.arm.neon.vpaddlu
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, MVT::vAny);
+ break;
+ case Intrinsic::arm_neon_vld1: // llvm.arm.neon.vld1
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::vAny, MVT::iPTR);
+ break;
+ case Intrinsic::arm_neon_vld2: // llvm.arm.neon.vld2
+ VerifyIntrinsicPrototype(ID, IF, 2, 1, MVT::vAny, ~0, MVT::iPTR);
+ break;
+ case Intrinsic::arm_neon_vld3: // llvm.arm.neon.vld3
+ VerifyIntrinsicPrototype(ID, IF, 3, 1, MVT::vAny, ~0, ~0, MVT::iPTR);
+ break;
+ case Intrinsic::arm_neon_vld4: // llvm.arm.neon.vld4
+ VerifyIntrinsicPrototype(ID, IF, 4, 1, MVT::vAny, ~0, ~0, ~0, MVT::iPTR);
+ break;
+ case Intrinsic::arm_neon_vld2lane: // llvm.arm.neon.vld2lane
+ VerifyIntrinsicPrototype(ID, IF, 2, 4, MVT::vAny, ~0, MVT::iPTR, ~0, ~0, MVT::i32);
+ break;
+ case Intrinsic::arm_neon_vld3lane: // llvm.arm.neon.vld3lane
+ VerifyIntrinsicPrototype(ID, IF, 3, 5, MVT::vAny, ~0, ~0, MVT::iPTR, ~0, ~0, ~0, MVT::i32);
+ break;
+ case Intrinsic::arm_neon_vld4lane: // llvm.arm.neon.vld4lane
+ VerifyIntrinsicPrototype(ID, IF, 4, 6, MVT::vAny, ~0, ~0, ~0, MVT::iPTR, ~0, ~0, ~0, ~0, MVT::i32);
+ break;
+ case Intrinsic::invariant_start: // llvm.invariant.start
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iPTR, MVT::i64, MVT::iPTR);
+ break;
+ case Intrinsic::flt_rounds: // llvm.flt.rounds
+ case Intrinsic::xcore_getid: // llvm.xcore.getid
+ VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i32);
+ break;
+ case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::x86_sse42_crc32_16: // llvm.x86.sse42.crc32.16
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i16);
+ break;
+ case Intrinsic::x86_sse42_crc32_32: // llvm.x86.sse42.crc32.32
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::x86_sse42_crc32_8: // llvm.x86.sse42.crc32.8
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::i32, MVT::i8);
+ break;
+ case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec.vcmpequb.p
+ case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec.vcmpgtsb.p
+ case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec.vcmpgtub.p
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v16i8, MVT::v16i8);
+ break;
+ case Intrinsic::ppc_altivec_vcmpbfp_p: // llvm.ppc.altivec.vcmpbfp.p
+ case Intrinsic::ppc_altivec_vcmpeqfp_p: // llvm.ppc.altivec.vcmpeqfp.p
+ case Intrinsic::ppc_altivec_vcmpgefp_p: // llvm.ppc.altivec.vcmpgefp.p
+ case Intrinsic::ppc_altivec_vcmpgtfp_p: // llvm.ppc.altivec.vcmpgtfp.p
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v4f32, MVT::v4f32);
+ break;
+ case Intrinsic::ppc_altivec_vcmpequw_p: // llvm.ppc.altivec.vcmpequw.p
+ case Intrinsic::ppc_altivec_vcmpgtsw_p: // llvm.ppc.altivec.vcmpgtsw.p
+ case Intrinsic::ppc_altivec_vcmpgtuw_p: // llvm.ppc.altivec.vcmpgtuw.p
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec.vcmpequh.p
+ case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec.vcmpgtsh.p
+ case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec.vcmpgtuh.p
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::i32, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp
+ case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for
+ case Intrinsic::setjmp: // llvm.setjmp
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::iPTR);
+ break;
+ case Intrinsic::sigsetjmp: // llvm.sigsetjmp
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::eh_selector: // llvm.eh.selector
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::iPTR, MVT::iPTR, MVT::isVoid);
+ break;
+ case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmovmskb.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v16i8);
+ break;
+ case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v16i8, MVT::i32);
+ break;
+ case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pcmpestri128
+ case Intrinsic::x86_sse42_pcmpestria128: // llvm.x86.sse42.pcmpestria128
+ case Intrinsic::x86_sse42_pcmpestric128: // llvm.x86.sse42.pcmpestric128
+ case Intrinsic::x86_sse42_pcmpestrio128: // llvm.x86.sse42.pcmpestrio128
+ case Intrinsic::x86_sse42_pcmpestris128: // llvm.x86.sse42.pcmpestris128
+ case Intrinsic::x86_sse42_pcmpestriz128: // llvm.x86.sse42.pcmpestriz128
+ VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::i32, MVT::v16i8, MVT::i32, MVT::v16i8, MVT::i32, MVT::i8);
+ break;
+ case Intrinsic::x86_sse42_pcmpistri128: // llvm.x86.sse42.pcmpistri128
+ case Intrinsic::x86_sse42_pcmpistria128: // llvm.x86.sse42.pcmpistria128
+ case Intrinsic::x86_sse42_pcmpistric128: // llvm.x86.sse42.pcmpistric128
+ case Intrinsic::x86_sse42_pcmpistrio128: // llvm.x86.sse42.pcmpistrio128
+ case Intrinsic::x86_sse42_pcmpistris128: // llvm.x86.sse42.pcmpistris128
+ case Intrinsic::x86_sse42_pcmpistriz128: // llvm.x86.sse42.pcmpistriz128
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::i32, MVT::v16i8, MVT::v16i8, MVT::i8);
+ break;
+ case Intrinsic::x86_sse2_cvtsd2si: // llvm.x86.sse2.cvtsd2si
+ case Intrinsic::x86_sse2_cvttsd2si: // llvm.x86.sse2.cvttsd2si
+ case Intrinsic::x86_sse2_movmsk_pd: // llvm.x86.sse2.movmsk.pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse2_comieq_sd: // llvm.x86.sse2.comieq.sd
+ case Intrinsic::x86_sse2_comige_sd: // llvm.x86.sse2.comige.sd
+ case Intrinsic::x86_sse2_comigt_sd: // llvm.x86.sse2.comigt.sd
+ case Intrinsic::x86_sse2_comile_sd: // llvm.x86.sse2.comile.sd
+ case Intrinsic::x86_sse2_comilt_sd: // llvm.x86.sse2.comilt.sd
+ case Intrinsic::x86_sse2_comineq_sd: // llvm.x86.sse2.comineq.sd
+ case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd
+ case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd
+ case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd
+ case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd
+ case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd
+ case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.ucomineq.sd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v2f64, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si
+ case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si
+ case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f32, MVT::i32);
+ break;
+ case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
+ case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
+ case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
+ case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss
+ case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss
+ case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss
+ case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss
+ case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss
+ case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss
+ case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss
+ case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss
+ case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss
+ case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss
+ case Intrinsic::x86_sse_ucomilt_ss: // llvm.x86.sse.ucomilt.ss
+ case Intrinsic::x86_sse_ucomineq_ss: // llvm.x86.sse.ucomineq.ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4f32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse41_pextrd: // llvm.x86.sse41.pextrd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i32, MVT::v4i32, MVT::i32);
+ break;
+ case Intrinsic::x86_mmx_pmovmskb: // llvm.x86.mmx.pmovmskb
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i32, MVT::v8i8);
+ break;
+ case Intrinsic::readcyclecounter: // llvm.readcyclecounter
+ VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::i64);
+ break;
+ case Intrinsic::alpha_umulh: // llvm.alpha.umulh
+ case Intrinsic::x86_sse42_crc32_64: // llvm.x86.sse42.crc32.64
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::i64, MVT::i64);
+ break;
+ case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64
+ case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvttsd2si64
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse41_pextrq: // llvm.x86.sse41.pextrq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::i64, MVT::v2i64, MVT::i32);
+ break;
+ case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64
+ case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::i64, MVT::v4f32);
+ break;
+ case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer
+ case Intrinsic::eh_exception: // llvm.eh.exception
+ case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda
+ case Intrinsic::stacksave: // llvm.stacksave
+ VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::iPTR);
+ break;
+ case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa
+ case Intrinsic::frameaddress: // llvm.frameaddress
+ case Intrinsic::returnaddress: // llvm.returnaddress
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::init_trampoline: // llvm.init.trampoline
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::iPTR, MVT::iPTR, MVT::iPTR, MVT::iPTR);
+ break;
+ case Intrinsic::gcread: // llvm.gcread
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::iPTR, MVT::iPTR, MVT::iPTR);
+ break;
+ case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx
+ case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl
+ case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr
+ case Intrinsic::x86_sse2_loadu_dq: // llvm.x86.sse2.loadu.dq
+ case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::iPTR);
+ break;
+ case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pabs.b.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v16i8, MVT::v16i8);
+ break;
+ case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii
+ case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::i8);
+ break;
+ case Intrinsic::x86_sse42_pcmpestrm128: // llvm.x86.sse42.pcmpestrm128
+ VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::v16i8, MVT::v16i8, MVT::i32, MVT::v16i8, MVT::i32, MVT::i8);
+ break;
+ case Intrinsic::spu_si_andbi: // llvm.spu.si.andbi
+ case Intrinsic::spu_si_ceqbi: // llvm.spu.si.ceqbi
+ case Intrinsic::spu_si_cgtbi: // llvm.spu.si.cgtbi
+ case Intrinsic::spu_si_clgtbi: // llvm.spu.si.clgtbi
+ case Intrinsic::spu_si_orbi: // llvm.spu.si.orbi
+ case Intrinsic::spu_si_xorbi: // llvm.spu.si.xorbi
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::i8);
+ break;
+ case Intrinsic::ppc_altivec_vaddsbs: // llvm.ppc.altivec.vaddsbs
+ case Intrinsic::ppc_altivec_vaddubs: // llvm.ppc.altivec.vaddubs
+ case Intrinsic::ppc_altivec_vavgsb: // llvm.ppc.altivec.vavgsb
+ case Intrinsic::ppc_altivec_vavgub: // llvm.ppc.altivec.vavgub
+ case Intrinsic::ppc_altivec_vcmpequb: // llvm.ppc.altivec.vcmpequb
+ case Intrinsic::ppc_altivec_vcmpgtsb: // llvm.ppc.altivec.vcmpgtsb
+ case Intrinsic::ppc_altivec_vcmpgtub: // llvm.ppc.altivec.vcmpgtub
+ case Intrinsic::ppc_altivec_vmaxsb: // llvm.ppc.altivec.vmaxsb
+ case Intrinsic::ppc_altivec_vmaxub: // llvm.ppc.altivec.vmaxub
+ case Intrinsic::ppc_altivec_vminsb: // llvm.ppc.altivec.vminsb
+ case Intrinsic::ppc_altivec_vminub: // llvm.ppc.altivec.vminub
+ case Intrinsic::ppc_altivec_vrlb: // llvm.ppc.altivec.vrlb
+ case Intrinsic::ppc_altivec_vslb: // llvm.ppc.altivec.vslb
+ case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab
+ case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb
+ case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs
+ case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs
+ case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb
+ case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb
+ case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb
+ case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b
+ case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b
+ case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b
+ case Intrinsic::x86_sse2_pcmpeq_b: // llvm.x86.sse2.pcmpeq.b
+ case Intrinsic::x86_sse2_pcmpgt_b: // llvm.x86.sse2.pcmpgt.b
+ case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b
+ case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b
+ case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b
+ case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b
+ case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb
+ case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb
+ case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.pshuf.b.128
+ case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.psign.b.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v16i8, MVT::v16i8);
+ break;
+ case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16i8, MVT::i32);
+ break;
+ case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pcmpistrm128
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16i8, MVT::i8);
+ break;
+ case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v16i8, MVT::v16i8, MVT::v16i8, MVT::v16i8);
+ break;
+ case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_vpkshss: // llvm.ppc.altivec.vpkshss
+ case Intrinsic::ppc_altivec_vpkshus: // llvm.ppc.altivec.vpkshus
+ case Intrinsic::ppc_altivec_vpkuhus: // llvm.ppc.altivec.vpkuhus
+ case Intrinsic::x86_sse2_packsswb_128: // llvm.x86.sse2.packsswb.128
+ case Intrinsic::x86_sse2_packuswb_128: // llvm.x86.sse2.packuswb.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v16i8, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::x86_mmx_pslli_q: // llvm.x86.mmx.pslli.q
+ case Intrinsic::x86_mmx_psrli_q: // llvm.x86.mmx.psrli.q
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v1i64, MVT::v1i64, MVT::i32);
+ break;
+ case Intrinsic::x86_mmx_psll_q: // llvm.x86.mmx.psll.q
+ case Intrinsic::x86_mmx_psrl_q: // llvm.x86.mmx.psrl.q
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v1i64, MVT::v1i64, MVT::v1i64);
+ break;
+ case Intrinsic::x86_ssse3_palign_r: // llvm.x86.ssse3.palign.r
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v1i64, MVT::v1i64, MVT::v1i64, MVT::i8);
+ break;
+ case Intrinsic::x86_sse2_loadu_pd: // llvm.x86.sse2.loadu.pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::iPTR);
+ break;
+ case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd
+ case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd
+ case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i32);
+ break;
+ case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::i64);
+ break;
+ case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa
+ case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm
+ case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma
+ case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms
+ case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma
+ case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms
+ case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs
+ case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd
+ case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd
+ case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd
+ case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd
+ case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd
+ case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd
+ case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd
+ case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd
+ case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd
+ case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd
+ case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd
+ case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd
+ case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f64, MVT::i32);
+ break;
+ case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd
+ case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f64, MVT::i8);
+ break;
+ case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2f64, MVT::v2f64, MVT::v2f64, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2f64, MVT::v2f64, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse_cvtpi2pd: // llvm.x86.sse.cvtpi2pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v2i32);
+ break;
+ case Intrinsic::x86_sse2_cvtps2pd: // llvm.x86.sse2.cvtps2pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse2_cvtdq2pd: // llvm.x86.sse2.cvtdq2pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2f64, MVT::v4i32);
+ break;
+ case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged
+ case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2f32, MVT::v2f32);
+ break;
+ case Intrinsic::x86_sse_cvtpd2pi: // llvm.x86.sse.cvtpd2pi
+ case Intrinsic::x86_sse_cvttpd2pi: // llvm.x86.sse.cvttpd2pi
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i32, MVT::v2f64);
+ break;
+ case Intrinsic::x86_ssse3_pabs_d: // llvm.x86.ssse3.pabs.d
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i32, MVT::v2i32);
+ break;
+ case Intrinsic::x86_mmx_pslli_d: // llvm.x86.mmx.pslli.d
+ case Intrinsic::x86_mmx_psrai_d: // llvm.x86.mmx.psrai.d
+ case Intrinsic::x86_mmx_psrli_d: // llvm.x86.mmx.psrli.d
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2i32, MVT::i32);
+ break;
+ case Intrinsic::x86_mmx_psll_d: // llvm.x86.mmx.psll.d
+ case Intrinsic::x86_mmx_psra_d: // llvm.x86.mmx.psra.d
+ case Intrinsic::x86_mmx_psrl_d: // llvm.x86.mmx.psrl.d
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2i32, MVT::v1i64);
+ break;
+ case Intrinsic::x86_mmx_pcmpeq_d: // llvm.x86.mmx.pcmpeq.d
+ case Intrinsic::x86_mmx_pcmpgt_d: // llvm.x86.mmx.pcmpgt.d
+ case Intrinsic::x86_mmx_pmulu_dq: // llvm.x86.mmx.pmulu.dq
+ case Intrinsic::x86_ssse3_phadd_d: // llvm.x86.ssse3.phadd.d
+ case Intrinsic::x86_ssse3_phsub_d: // llvm.x86.ssse3.phsub.d
+ case Intrinsic::x86_ssse3_psign_d: // llvm.x86.ssse3.psign.d
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v2i32, MVT::v2i32);
+ break;
+ case Intrinsic::x86_sse_cvtps2pi: // llvm.x86.sse.cvtps2pi
+ case Intrinsic::x86_sse_cvttps2pi: // llvm.x86.sse.cvttps2pi
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_mmx_pmadd_wd: // llvm.x86.mmx.pmadd.wd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i32, MVT::v4i16, MVT::v4i16);
+ break;
+ case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::iPTR);
+ break;
+ case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq
+ case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v16i8);
+ break;
+ case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v16i8, MVT::v16i8);
+ break;
+ case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq
+ case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs
+ case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q
+ case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq
+ case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs
+ case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::i32);
+ break;
+ case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q
+ case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q
+ case Intrinsic::x86_sse41_pcmpeqq: // llvm.x86.sse41.pcmpeqq
+ case Intrinsic::x86_sse42_pcmpgtq: // llvm.x86.sse42.pcmpgtq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v2i64, MVT::v2i64);
+ break;
+ case Intrinsic::x86_ssse3_palign_r_128: // llvm.x86.ssse3.palign.r.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v2i64, MVT::v2i64, MVT::v2i64, MVT::i8);
+ break;
+ case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq
+ case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v4i32);
+ break;
+ case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq
+ case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v2i64, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq
+ case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v2i64, MVT::v8i16);
+ break;
+ case Intrinsic::x86_sse_loadu_ps: // llvm.x86.sse.loadu.ps
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::iPTR);
+ break;
+ case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v2f64);
+ break;
+ case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec.vexptefp
+ case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp
+ case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp
+ case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim
+ case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin
+ case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip
+ case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz
+ case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec.vrsqrtefp
+ case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps
+ case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss
+ case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps
+ case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss
+ case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps
+ case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps
+ case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i32);
+ break;
+ case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::i64);
+ break;
+ case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v2i32);
+ break;
+ case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp
+ case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp
+ case Intrinsic::spu_si_fa: // llvm.spu.si.fa
+ case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq
+ case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt
+ case Intrinsic::spu_si_fcmeq: // llvm.spu.si.fcmeq
+ case Intrinsic::spu_si_fcmgt: // llvm.spu.si.fcmgt
+ case Intrinsic::spu_si_fm: // llvm.spu.si.fm
+ case Intrinsic::spu_si_fs: // llvm.spu.si.fs
+ case Intrinsic::x86_sse3_addsub_ps: // llvm.x86.sse3.addsub.ps
+ case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps
+ case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps
+ case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss
+ case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss
+ case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps
+ case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss
+ case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps
+ case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss
+ case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss
+ case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4f32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps
+ case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps
+ case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps
+ case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f32, MVT::i32);
+ break;
+ case Intrinsic::x86_sse_cmp_ps: // llvm.x86.sse.cmp.ps
+ case Intrinsic::x86_sse_cmp_ss: // llvm.x86.sse.cmp.ss
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f32, MVT::i8);
+ break;
+ case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp
+ case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec.vnmsubfp
+ case Intrinsic::spu_si_fma: // llvm.spu.si.fma
+ case Intrinsic::spu_si_fms: // llvm.spu.si.fms
+ case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms
+ case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4f32, MVT::v4f32, MVT::v4f32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse2_cvtdq2ps: // llvm.x86.sse2.cvtdq2ps
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4f32, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_vcfsx: // llvm.ppc.altivec.vcfsx
+ case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4f32, MVT::v4i32, MVT::i32);
+ break;
+ case Intrinsic::x86_mmx_packssdw: // llvm.x86.mmx.packssdw
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i16, MVT::v2i32, MVT::v2i32);
+ break;
+ case Intrinsic::x86_ssse3_pabs_w: // llvm.x86.ssse3.pabs.w
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i16, MVT::v4i16);
+ break;
+ case Intrinsic::x86_mmx_pslli_w: // llvm.x86.mmx.pslli.w
+ case Intrinsic::x86_mmx_psrai_w: // llvm.x86.mmx.psrai.w
+ case Intrinsic::x86_mmx_psrli_w: // llvm.x86.mmx.psrli.w
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i16, MVT::v4i16, MVT::i32);
+ break;
+ case Intrinsic::x86_mmx_psll_w: // llvm.x86.mmx.psll.w
+ case Intrinsic::x86_mmx_psra_w: // llvm.x86.mmx.psra.w
+ case Intrinsic::x86_mmx_psrl_w: // llvm.x86.mmx.psrl.w
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i16, MVT::v4i16, MVT::v1i64);
+ break;
+ case Intrinsic::x86_mmx_padds_w: // llvm.x86.mmx.padds.w
+ case Intrinsic::x86_mmx_paddus_w: // llvm.x86.mmx.paddus.w
+ case Intrinsic::x86_mmx_pavg_w: // llvm.x86.mmx.pavg.w
+ case Intrinsic::x86_mmx_pcmpeq_w: // llvm.x86.mmx.pcmpeq.w
+ case Intrinsic::x86_mmx_pcmpgt_w: // llvm.x86.mmx.pcmpgt.w
+ case Intrinsic::x86_mmx_pmaxs_w: // llvm.x86.mmx.pmaxs.w
+ case Intrinsic::x86_mmx_pmins_w: // llvm.x86.mmx.pmins.w
+ case Intrinsic::x86_mmx_pmulh_w: // llvm.x86.mmx.pmulh.w
+ case Intrinsic::x86_mmx_pmulhu_w: // llvm.x86.mmx.pmulhu.w
+ case Intrinsic::x86_mmx_psubs_w: // llvm.x86.mmx.psubs.w
+ case Intrinsic::x86_mmx_psubus_w: // llvm.x86.mmx.psubus.w
+ case Intrinsic::x86_ssse3_phadd_sw: // llvm.x86.ssse3.phadd.sw
+ case Intrinsic::x86_ssse3_phadd_w: // llvm.x86.ssse3.phadd.w
+ case Intrinsic::x86_ssse3_phsub_sw: // llvm.x86.ssse3.phsub.sw
+ case Intrinsic::x86_ssse3_phsub_w: // llvm.x86.ssse3.phsub.w
+ case Intrinsic::x86_ssse3_pmadd_ub_sw: // llvm.x86.ssse3.pmadd.ub.sw
+ case Intrinsic::x86_ssse3_pmul_hr_sw: // llvm.x86.ssse3.pmul.hr.sw
+ case Intrinsic::x86_ssse3_psign_w: // llvm.x86.ssse3.psign.w
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i16, MVT::v4i16, MVT::v4i16);
+ break;
+ case Intrinsic::x86_mmx_psad_bw: // llvm.x86.mmx.psad.bw
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i16, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx
+ case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx
+ case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::iPTR);
+ break;
+ case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd
+ case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v16i8);
+ break;
+ case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec.vmsummbm
+ case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec.vmsumubm
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v16i8, MVT::v16i8, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_vsum4sbs: // llvm.ppc.altivec.vsum4sbs
+ case Intrinsic::ppc_altivec_vsum4ubs: // llvm.ppc.altivec.vsum4ubs
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v16i8, MVT::v4i32);
+ break;
+ case Intrinsic::x86_sse2_cvtpd2dq: // llvm.x86.sse2.cvtpd2dq
+ case Intrinsic::x86_sse2_cvttpd2dq: // llvm.x86.sse2.cvttpd2dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse2_cvtps2dq: // llvm.x86.sse2.cvtps2dq
+ case Intrinsic::x86_sse2_cvttps2dq: // llvm.x86.sse2.cvttps2dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4f32);
+ break;
+ case Intrinsic::ppc_altivec_vctsxs: // llvm.ppc.altivec.vctsxs
+ case Intrinsic::ppc_altivec_vctuxs: // llvm.ppc.altivec.vctuxs
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4f32, MVT::i32);
+ break;
+ case Intrinsic::arm_neon_vacgeq: // llvm.arm.neon.vacgeq
+ case Intrinsic::arm_neon_vacgtq: // llvm.arm.neon.vacgtq
+ case Intrinsic::ppc_altivec_vcmpbfp: // llvm.ppc.altivec.vcmpbfp
+ case Intrinsic::ppc_altivec_vcmpeqfp: // llvm.ppc.altivec.vcmpeqfp
+ case Intrinsic::ppc_altivec_vcmpgefp: // llvm.ppc.altivec.vcmpgefp
+ case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec.vcmpgtfp
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4f32, MVT::v4f32);
+ break;
+ case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pabs.d.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::spu_si_shli: // llvm.spu.si.shli
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i8);
+ break;
+ case Intrinsic::spu_si_ai: // llvm.spu.si.ai
+ case Intrinsic::spu_si_andi: // llvm.spu.si.andi
+ case Intrinsic::spu_si_ceqi: // llvm.spu.si.ceqi
+ case Intrinsic::spu_si_cgti: // llvm.spu.si.cgti
+ case Intrinsic::spu_si_clgti: // llvm.spu.si.clgti
+ case Intrinsic::spu_si_ori: // llvm.spu.si.ori
+ case Intrinsic::spu_si_sfi: // llvm.spu.si.sfi
+ case Intrinsic::spu_si_xori: // llvm.spu.si.xori
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i16);
+ break;
+ case Intrinsic::x86_sse2_pslli_d: // llvm.x86.sse2.pslli.d
+ case Intrinsic::x86_sse2_psrai_d: // llvm.x86.sse2.psrai.d
+ case Intrinsic::x86_sse2_psrli_d: // llvm.x86.sse2.psrli.d
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::i32);
+ break;
+ case Intrinsic::ppc_altivec_vaddcuw: // llvm.ppc.altivec.vaddcuw
+ case Intrinsic::ppc_altivec_vaddsws: // llvm.ppc.altivec.vaddsws
+ case Intrinsic::ppc_altivec_vadduws: // llvm.ppc.altivec.vadduws
+ case Intrinsic::ppc_altivec_vavgsw: // llvm.ppc.altivec.vavgsw
+ case Intrinsic::ppc_altivec_vavguw: // llvm.ppc.altivec.vavguw
+ case Intrinsic::ppc_altivec_vcmpequw: // llvm.ppc.altivec.vcmpequw
+ case Intrinsic::ppc_altivec_vcmpgtsw: // llvm.ppc.altivec.vcmpgtsw
+ case Intrinsic::ppc_altivec_vcmpgtuw: // llvm.ppc.altivec.vcmpgtuw
+ case Intrinsic::ppc_altivec_vmaxsw: // llvm.ppc.altivec.vmaxsw
+ case Intrinsic::ppc_altivec_vmaxuw: // llvm.ppc.altivec.vmaxuw
+ case Intrinsic::ppc_altivec_vminsw: // llvm.ppc.altivec.vminsw
+ case Intrinsic::ppc_altivec_vminuw: // llvm.ppc.altivec.vminuw
+ case Intrinsic::ppc_altivec_vrlw: // llvm.ppc.altivec.vrlw
+ case Intrinsic::ppc_altivec_vsl: // llvm.ppc.altivec.vsl
+ case Intrinsic::ppc_altivec_vslo: // llvm.ppc.altivec.vslo
+ case Intrinsic::ppc_altivec_vslw: // llvm.ppc.altivec.vslw
+ case Intrinsic::ppc_altivec_vsr: // llvm.ppc.altivec.vsr
+ case Intrinsic::ppc_altivec_vsraw: // llvm.ppc.altivec.vsraw
+ case Intrinsic::ppc_altivec_vsro: // llvm.ppc.altivec.vsro
+ case Intrinsic::ppc_altivec_vsrw: // llvm.ppc.altivec.vsrw
+ case Intrinsic::ppc_altivec_vsubcuw: // llvm.ppc.altivec.vsubcuw
+ case Intrinsic::ppc_altivec_vsubsws: // llvm.ppc.altivec.vsubsws
+ case Intrinsic::ppc_altivec_vsubuws: // llvm.ppc.altivec.vsubuws
+ case Intrinsic::ppc_altivec_vsum2sws: // llvm.ppc.altivec.vsum2sws
+ case Intrinsic::ppc_altivec_vsumsws: // llvm.ppc.altivec.vsumsws
+ case Intrinsic::spu_si_a: // llvm.spu.si.a
+ case Intrinsic::spu_si_addx: // llvm.spu.si.addx
+ case Intrinsic::spu_si_and: // llvm.spu.si.and
+ case Intrinsic::spu_si_andc: // llvm.spu.si.andc
+ case Intrinsic::spu_si_bg: // llvm.spu.si.bg
+ case Intrinsic::spu_si_bgx: // llvm.spu.si.bgx
+ case Intrinsic::spu_si_ceq: // llvm.spu.si.ceq
+ case Intrinsic::spu_si_cg: // llvm.spu.si.cg
+ case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt
+ case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx
+ case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt
+ case Intrinsic::spu_si_nand: // llvm.spu.si.nand
+ case Intrinsic::spu_si_nor: // llvm.spu.si.nor
+ case Intrinsic::spu_si_or: // llvm.spu.si.or
+ case Intrinsic::spu_si_orc: // llvm.spu.si.orc
+ case Intrinsic::spu_si_sf: // llvm.spu.si.sf
+ case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx
+ case Intrinsic::spu_si_xor: // llvm.spu.si.xor
+ case Intrinsic::x86_sse2_pcmpeq_d: // llvm.x86.sse2.pcmpeq.d
+ case Intrinsic::x86_sse2_pcmpgt_d: // llvm.x86.sse2.pcmpgt.d
+ case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d
+ case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d
+ case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d
+ case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd
+ case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud
+ case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd
+ case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud
+ case Intrinsic::x86_sse41_pmulld: // llvm.x86.sse41.pmulld
+ case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.phadd.d.128
+ case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.phadd.sw.128
+ case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.phsub.d.128
+ case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.psign.d.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i32, MVT::v16i8);
+ break;
+ case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v4i32, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v4i32, MVT::v8i16);
+ break;
+ case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx
+ case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh
+ case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx
+ case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh
+ case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd
+ case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v4i32, MVT::v8i16);
+ break;
+ case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi
+ case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::i16);
+ break;
+ case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec.vsum4shs
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh
+ case Intrinsic::ppc_altivec_vmuleuh: // llvm.ppc.altivec.vmuleuh
+ case Intrinsic::ppc_altivec_vmulosh: // llvm.ppc.altivec.vmulosh
+ case Intrinsic::ppc_altivec_vmulouh: // llvm.ppc.altivec.vmulouh
+ case Intrinsic::spu_si_mpy: // llvm.spu.si.mpy
+ case Intrinsic::spu_si_mpyhh: // llvm.spu.si.mpyhh
+ case Intrinsic::spu_si_mpyhha: // llvm.spu.si.mpyhha
+ case Intrinsic::spu_si_mpyhhau: // llvm.spu.si.mpyhhau
+ case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu
+ case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys
+ case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu
+ case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v4i32, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec.vmsumshm
+ case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec.vmsumshs
+ case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec.vmsumuhm
+ case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec.vmsumuhs
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i16, MVT::v4i32);
+ break;
+ case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v4i32, MVT::v8i16, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr
+ VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::v8i16);
+ break;
+ case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::iPTR);
+ break;
+ case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb
+ case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb
+ case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw
+ case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v16i8);
+ break;
+ case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb
+ case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub
+ case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb
+ case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v16i8, MVT::v16i8);
+ break;
+ case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx
+ case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus
+ case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus
+ case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.packssdw.128
+ case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v4i32, MVT::v4i32);
+ break;
+ case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.phminposuw
+ case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pabs.w.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi
+ case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi
+ case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi
+ case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi
+ case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi
+ case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi
+ case Intrinsic::spu_si_orhi: // llvm.spu.si.orhi
+ case Intrinsic::spu_si_sfhi: // llvm.spu.si.sfhi
+ case Intrinsic::spu_si_xorhi: // llvm.spu.si.xorhi
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::i16);
+ break;
+ case Intrinsic::spu_si_shlqbi: // llvm.spu.si.shlqbi
+ case Intrinsic::spu_si_shlqby: // llvm.spu.si.shlqby
+ case Intrinsic::x86_sse2_pslli_w: // llvm.x86.sse2.pslli.w
+ case Intrinsic::x86_sse2_psrai_w: // llvm.x86.sse2.psrai.w
+ case Intrinsic::x86_sse2_psrli_w: // llvm.x86.sse2.psrli.w
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::i32);
+ break;
+ case Intrinsic::ppc_altivec_vaddshs: // llvm.ppc.altivec.vaddshs
+ case Intrinsic::ppc_altivec_vadduhs: // llvm.ppc.altivec.vadduhs
+ case Intrinsic::ppc_altivec_vavgsh: // llvm.ppc.altivec.vavgsh
+ case Intrinsic::ppc_altivec_vavguh: // llvm.ppc.altivec.vavguh
+ case Intrinsic::ppc_altivec_vcmpequh: // llvm.ppc.altivec.vcmpequh
+ case Intrinsic::ppc_altivec_vcmpgtsh: // llvm.ppc.altivec.vcmpgtsh
+ case Intrinsic::ppc_altivec_vcmpgtuh: // llvm.ppc.altivec.vcmpgtuh
+ case Intrinsic::ppc_altivec_vmaxsh: // llvm.ppc.altivec.vmaxsh
+ case Intrinsic::ppc_altivec_vmaxuh: // llvm.ppc.altivec.vmaxuh
+ case Intrinsic::ppc_altivec_vminsh: // llvm.ppc.altivec.vminsh
+ case Intrinsic::ppc_altivec_vminuh: // llvm.ppc.altivec.vminuh
+ case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh
+ case Intrinsic::ppc_altivec_vslh: // llvm.ppc.altivec.vslh
+ case Intrinsic::ppc_altivec_vsrah: // llvm.ppc.altivec.vsrah
+ case Intrinsic::ppc_altivec_vsrh: // llvm.ppc.altivec.vsrh
+ case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs
+ case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs
+ case Intrinsic::spu_si_ah: // llvm.spu.si.ah
+ case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh
+ case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth
+ case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth
+ case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh
+ case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w
+ case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w
+ case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w
+ case Intrinsic::x86_sse2_pcmpeq_w: // llvm.x86.sse2.pcmpeq.w
+ case Intrinsic::x86_sse2_pcmpgt_w: // llvm.x86.sse2.pcmpgt.w
+ case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w
+ case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w
+ case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w
+ case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w
+ case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w
+ case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w
+ case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w
+ case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w
+ case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w
+ case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw
+ case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw
+ case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.phadd.w.128
+ case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.phsub.sw.128
+ case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.phsub.w.128
+ case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pmadd.ub.sw.128
+ case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pmul.hr.sw.128
+ case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.psign.w.128
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i16, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i16, MVT::i32);
+ break;
+ case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec.vmhaddshs
+ case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec.vmhraddshs
+ case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec.vmladduhm
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i16, MVT::v8i16, MVT::v8i16, MVT::v8i16);
+ break;
+ case Intrinsic::x86_mmx_packsswb: // llvm.x86.mmx.packsswb
+ case Intrinsic::x86_mmx_packuswb: // llvm.x86.mmx.packuswb
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i8, MVT::v4i16, MVT::v4i16);
+ break;
+ case Intrinsic::x86_ssse3_pabs_b: // llvm.x86.ssse3.pabs.b
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1
+ case Intrinsic::x86_mmx_padds_b: // llvm.x86.mmx.padds.b
+ case Intrinsic::x86_mmx_paddus_b: // llvm.x86.mmx.paddus.b
+ case Intrinsic::x86_mmx_pavg_b: // llvm.x86.mmx.pavg.b
+ case Intrinsic::x86_mmx_pcmpeq_b: // llvm.x86.mmx.pcmpeq.b
+ case Intrinsic::x86_mmx_pcmpgt_b: // llvm.x86.mmx.pcmpgt.b
+ case Intrinsic::x86_mmx_pmaxu_b: // llvm.x86.mmx.pmaxu.b
+ case Intrinsic::x86_mmx_pminu_b: // llvm.x86.mmx.pminu.b
+ case Intrinsic::x86_mmx_psubs_b: // llvm.x86.mmx.psubs.b
+ case Intrinsic::x86_mmx_psubus_b: // llvm.x86.mmx.psubus.b
+ case Intrinsic::x86_ssse3_pshuf_b: // llvm.x86.ssse3.pshuf.b
+ case Intrinsic::x86_ssse3_psign_b: // llvm.x86.ssse3.psign.b
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::v8i8, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2
+ case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::arm_neon_vtbl3: // llvm.arm.neon.vtbl3
+ case Intrinsic::arm_neon_vtbx2: // llvm.arm.neon.vtbx2
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::arm_neon_vtbl4: // llvm.arm.neon.vtbl4
+ case Intrinsic::arm_neon_vtbx3: // llvm.arm.neon.vtbx3
+ VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::arm_neon_vtbx4: // llvm.arm.neon.vtbx4
+ VerifyIntrinsicPrototype(ID, IF, 1, 6, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8, MVT::v8i8);
+ break;
+ case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init
+ case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall
+ case Intrinsic::ppc_sync: // llvm.ppc.sync
+ case Intrinsic::trap: // llvm.trap
+ case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms
+ case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms
+ case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence
+ case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence
+ case Intrinsic::x86_sse_sfence: // llvm.x86.sse.sfence
+ VerifyIntrinsicPrototype(ID, IF, 1, 0, MVT::isVoid);
+ break;
+ case Intrinsic::invariant_end: // llvm.invariant.end
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::iPTR, MVT::i64, MVT::iPTR);
+ break;
+ case Intrinsic::dbg_declare: // llvm.dbg.declare
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::Metadata);
+ break;
+ case Intrinsic::memory_barrier: // llvm.memory.barrier
+ VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::isVoid, MVT::i1, MVT::i1, MVT::i1, MVT::i1, MVT::i1);
+ break;
+ case Intrinsic::pcmarker: // llvm.pcmarker
+ case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::i32);
+ break;
+ case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::dbg_stoppoint: // llvm.dbg.stoppoint
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::i32, MVT::i32, MVT::Metadata);
+ break;
+ case Intrinsic::eh_return_i32: // llvm.eh.return.i32
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::i32, MVT::iPTR);
+ break;
+ case Intrinsic::eh_return_i64: // llvm.eh.return.i64
+ case Intrinsic::lifetime_end: // llvm.lifetime.end
+ case Intrinsic::lifetime_start: // llvm.lifetime.start
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::i64, MVT::iPTR);
+ break;
+ case Intrinsic::dbg_func_start: // llvm.dbg.func.start
+ case Intrinsic::dbg_region_end: // llvm.dbg.region.end
+ case Intrinsic::dbg_region_start: // llvm.dbg.region.start
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::Metadata);
+ break;
+ case Intrinsic::dbg_value: // llvm.dbg.value
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::Metadata, MVT::i64, MVT::Metadata);
+ break;
+ case Intrinsic::eh_sjlj_longjmp: // llvm.eh.sjlj.longjmp
+ case Intrinsic::ppc_dcba: // llvm.ppc.dcba
+ case Intrinsic::ppc_dcbf: // llvm.ppc.dcbf
+ case Intrinsic::ppc_dcbi: // llvm.ppc.dcbi
+ case Intrinsic::ppc_dcbst: // llvm.ppc.dcbst
+ case Intrinsic::ppc_dcbt: // llvm.ppc.dcbt
+ case Intrinsic::ppc_dcbtst: // llvm.ppc.dcbtst
+ case Intrinsic::ppc_dcbz: // llvm.ppc.dcbz
+ case Intrinsic::ppc_dcbzl: // llvm.ppc.dcbzl
+ case Intrinsic::stackrestore: // llvm.stackrestore
+ case Intrinsic::vaend: // llvm.va_end
+ case Intrinsic::vastart: // llvm.va_start
+ case Intrinsic::x86_sse2_clflush: // llvm.x86.sse2.clflush
+ case Intrinsic::x86_sse_ldmxcsr: // llvm.x86.sse.ldmxcsr
+ case Intrinsic::x86_sse_stmxcsr: // llvm.x86.sse.stmxcsr
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::iPTR);
+ break;
+ case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::vAny);
+ break;
+ case Intrinsic::arm_neon_vst2: // llvm.arm.neon.vst2
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::iPTR, MVT::vAny, ~2);
+ break;
+ case Intrinsic::arm_neon_vst3: // llvm.arm.neon.vst3
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::isVoid, MVT::iPTR, MVT::vAny, ~2, ~2);
+ break;
+ case Intrinsic::arm_neon_vst4: // llvm.arm.neon.vst4
+ VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::isVoid, MVT::iPTR, MVT::vAny, ~2, ~2, ~2);
+ break;
+ case Intrinsic::arm_neon_vst2lane: // llvm.arm.neon.vst2lane
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::isVoid, MVT::iPTR, MVT::vAny, ~2, MVT::i32);
+ break;
+ case Intrinsic::arm_neon_vst3lane: // llvm.arm.neon.vst3lane
+ VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::isVoid, MVT::iPTR, MVT::vAny, ~2, ~2, MVT::i32);
+ break;
+ case Intrinsic::arm_neon_vst4lane: // llvm.arm.neon.vst4lane
+ VerifyIntrinsicPrototype(ID, IF, 1, 6, MVT::isVoid, MVT::iPTR, MVT::vAny, ~2, ~2, ~2, MVT::i32);
+ break;
+ case Intrinsic::longjmp: // llvm.longjmp
+ case Intrinsic::siglongjmp: // llvm.siglongjmp
+ case Intrinsic::x86_sse2_movnt_i: // llvm.x86.sse2.movnt.i
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst
+ case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst
+ case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt
+ case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt
+ case Intrinsic::prefetch: // llvm.prefetch
+ case Intrinsic::x86_sse3_monitor: // llvm.x86.sse3.monitor
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::iPTR, MVT::i32, MVT::i32);
+ break;
+ case Intrinsic::memset: // llvm.memset
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::isVoid, MVT::iPTR, MVT::i8, MVT::iAny, MVT::i32);
+ break;
+ case Intrinsic::vacopy: // llvm.va_copy
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::iPTR);
+ break;
+ case Intrinsic::memcpy: // llvm.memcpy
+ case Intrinsic::memmove: // llvm.memmove
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::isVoid, MVT::iPTR, MVT::iPTR, MVT::iAny, MVT::i32);
+ break;
+ case Intrinsic::var_annotation: // llvm.var.annotation
+ VerifyIntrinsicPrototype(ID, IF, 1, 4, MVT::isVoid, MVT::iPTR, MVT::iPTR, MVT::iPTR, MVT::i32);
+ break;
+ case Intrinsic::gcwrite: // llvm.gcwrite
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::iPTR, MVT::iPTR, MVT::iPTR);
+ break;
+ case Intrinsic::stackprotector: // llvm.stackprotector
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::iPTR);
+ break;
+ case Intrinsic::x86_sse2_storeu_dq: // llvm.x86.sse2.storeu.dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::v16i8);
+ break;
+ case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::v1i64);
+ break;
+ case Intrinsic::x86_sse2_movnt_pd: // llvm.x86.sse2.movnt.pd
+ case Intrinsic::x86_sse2_storeu_pd: // llvm.x86.sse2.storeu.pd
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::v2f64);
+ break;
+ case Intrinsic::x86_sse2_movnt_dq: // llvm.x86.sse2.movnt.dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::v2i64);
+ break;
+ case Intrinsic::x86_sse_movnt_ps: // llvm.x86.sse.movnt.ps
+ case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::v4f32);
+ break;
+ case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::v4i32);
+ break;
+ case Intrinsic::gcroot: // llvm.gcroot
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::iPTR);
+ break;
+ case Intrinsic::ppc_altivec_stvebx: // llvm.ppc.altivec.stvebx
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::v16i8, MVT::iPTR);
+ break;
+ case Intrinsic::x86_sse2_maskmov_dqu: // llvm.x86.sse2.maskmov.dqu
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::v16i8, MVT::v16i8, MVT::iPTR);
+ break;
+ case Intrinsic::ppc_altivec_mtvscr: // llvm.ppc.altivec.mtvscr
+ VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::v4i32);
+ break;
+ case Intrinsic::ppc_altivec_stvewx: // llvm.ppc.altivec.stvewx
+ case Intrinsic::ppc_altivec_stvx: // llvm.ppc.altivec.stvx
+ case Intrinsic::ppc_altivec_stvxl: // llvm.ppc.altivec.stvxl
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::v4i32, MVT::iPTR);
+ break;
+ case Intrinsic::ppc_altivec_stvehx: // llvm.ppc.altivec.stvehx
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::v8i16, MVT::iPTR);
+ break;
+ case Intrinsic::x86_mmx_maskmovq: // llvm.x86.mmx.maskmovq
+ VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::v8i8, MVT::v8i8, MVT::iPTR);
+ break;
+ }
+#endif
+
+// Code for generating Intrinsic function declarations.
+#ifdef GET_INTRINSIC_GENERATOR
+ switch (id) {
+ default: assert(0 && "Invalid intrinsic!");
+ case Intrinsic::ptr_annotation: // llvm.ptr.annotation
+ ResultTy = (0 < numTys) ? Tys[0] : PointerType::getUnqual(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::sin: // llvm.sin
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::cos: // llvm.cos
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::pow: // llvm.pow
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::log: // llvm.log
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::log10: // llvm.log10
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::log2: // llvm.log2
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::exp: // llvm.exp
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::exp2: // llvm.exp2
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::sqrt: // llvm.sqrt
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::powi: // llvm.powi
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::convertff: // llvm.convertff
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::arm_neon_vcvtfxs2fp: // llvm.arm.neon.vcvtfxs2fp
+ case Intrinsic::arm_neon_vcvtfxu2fp: // llvm.arm.neon.vcvtfxu2fp
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::convertfsi: // llvm.convertfsi
+ case Intrinsic::convertfui: // llvm.convertfui
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::bswap: // llvm.bswap
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::ctpop: // llvm.ctpop
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::ctlz: // llvm.ctlz
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::cttz: // llvm.cttz
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::annotation: // llvm.annotation
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::atomic_cmp_swap: // llvm.atomic.cmp.swap
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_add: // llvm.atomic.load.add
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_swap: // llvm.atomic.swap
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_sub: // llvm.atomic.load.sub
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_and: // llvm.atomic.load.and
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_or: // llvm.atomic.load.or
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_xor: // llvm.atomic.load.xor
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_nand: // llvm.atomic.load.nand
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_min: // llvm.atomic.load.min
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_max: // llvm.atomic.load.max
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_umin: // llvm.atomic.load.umin
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::atomic_load_umax: // llvm.atomic.load.umax
+ ResultTy = Tys[0];
+ ArgTys.push_back((1 < numTys) ? Tys[1] : PointerType::getUnqual(Tys[0]));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vcvtfp2fxs: // llvm.arm.neon.vcvtfp2fxs
+ case Intrinsic::arm_neon_vcvtfp2fxu: // llvm.arm.neon.vcvtfp2fxu
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::convertsif: // llvm.convertsif
+ case Intrinsic::convertuif: // llvm.convertuif
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::convertss: // llvm.convertss
+ case Intrinsic::convertsu: // llvm.convertsu
+ case Intrinsic::convertus: // llvm.convertus
+ case Intrinsic::convertuu: // llvm.convertuu
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::objectsize: // llvm.objectsize
+ ResultTy = Tys[0];
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::sadd_with_overflow: // llvm.sadd.with.overflow
+ ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::uadd_with_overflow: // llvm.uadd.with.overflow
+ ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::ssub_with_overflow: // llvm.ssub.with.overflow
+ ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::usub_with_overflow: // llvm.usub.with.overflow
+ ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::smul_with_overflow: // llvm.smul.with.overflow
+ ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::umul_with_overflow: // llvm.umul.with.overflow
+ ResultTy = StructType::get(Context, Tys[0], IntegerType::get(Context, 1), NULL);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vaddws: // llvm.arm.neon.vaddws
+ case Intrinsic::arm_neon_vaddwu: // llvm.arm.neon.vaddwu
+ case Intrinsic::arm_neon_vsubws: // llvm.arm.neon.vsubws
+ case Intrinsic::arm_neon_vsubwu: // llvm.arm.neon.vsubwu
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ break;
+ case Intrinsic::arm_neon_vabas: // llvm.arm.neon.vabas
+ case Intrinsic::arm_neon_vabau: // llvm.arm.neon.vabau
+ case Intrinsic::arm_neon_vshiftins: // llvm.arm.neon.vshiftins
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vabals: // llvm.arm.neon.vabals
+ case Intrinsic::arm_neon_vabalu: // llvm.arm.neon.vabalu
+ case Intrinsic::arm_neon_vmlals: // llvm.arm.neon.vmlals
+ case Intrinsic::arm_neon_vmlalu: // llvm.arm.neon.vmlalu
+ case Intrinsic::arm_neon_vmlsls: // llvm.arm.neon.vmlsls
+ case Intrinsic::arm_neon_vmlslu: // llvm.arm.neon.vmlslu
+ case Intrinsic::arm_neon_vqdmlal: // llvm.arm.neon.vqdmlal
+ case Intrinsic::arm_neon_vqdmlsl: // llvm.arm.neon.vqdmlsl
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ break;
+ case Intrinsic::arm_neon_vpadals: // llvm.arm.neon.vpadals
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[1]);
+ break;
+ case Intrinsic::arm_neon_vpadalu: // llvm.arm.neon.vpadalu
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[1]);
+ break;
+ case Intrinsic::arm_neon_vabs: // llvm.arm.neon.vabs
+ case Intrinsic::arm_neon_vcls: // llvm.arm.neon.vcls
+ case Intrinsic::arm_neon_vclz: // llvm.arm.neon.vclz
+ case Intrinsic::arm_neon_vcnt: // llvm.arm.neon.vcnt
+ case Intrinsic::arm_neon_vqabs: // llvm.arm.neon.vqabs
+ case Intrinsic::arm_neon_vqneg: // llvm.arm.neon.vqneg
+ case Intrinsic::arm_neon_vrecpe: // llvm.arm.neon.vrecpe
+ case Intrinsic::arm_neon_vrsqrte: // llvm.arm.neon.vrsqrte
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vmovn: // llvm.arm.neon.vmovn
+ case Intrinsic::arm_neon_vqmovns: // llvm.arm.neon.vqmovns
+ case Intrinsic::arm_neon_vqmovnsu: // llvm.arm.neon.vqmovnsu
+ case Intrinsic::arm_neon_vqmovnu: // llvm.arm.neon.vqmovnu
+ ResultTy = Tys[0];
+ ArgTys.push_back(VectorType::getExtendedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ break;
+ case Intrinsic::arm_neon_vmovls: // llvm.arm.neon.vmovls
+ case Intrinsic::arm_neon_vmovlu: // llvm.arm.neon.vmovlu
+ ResultTy = Tys[0];
+ ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ break;
+ case Intrinsic::arm_neon_vabds: // llvm.arm.neon.vabds
+ case Intrinsic::arm_neon_vabdu: // llvm.arm.neon.vabdu
+ case Intrinsic::arm_neon_vhadds: // llvm.arm.neon.vhadds
+ case Intrinsic::arm_neon_vhaddu: // llvm.arm.neon.vhaddu
+ case Intrinsic::arm_neon_vhsubs: // llvm.arm.neon.vhsubs
+ case Intrinsic::arm_neon_vhsubu: // llvm.arm.neon.vhsubu
+ case Intrinsic::arm_neon_vmaxs: // llvm.arm.neon.vmaxs
+ case Intrinsic::arm_neon_vmaxu: // llvm.arm.neon.vmaxu
+ case Intrinsic::arm_neon_vmins: // llvm.arm.neon.vmins
+ case Intrinsic::arm_neon_vminu: // llvm.arm.neon.vminu
+ case Intrinsic::arm_neon_vmulp: // llvm.arm.neon.vmulp
+ case Intrinsic::arm_neon_vpadd: // llvm.arm.neon.vpadd
+ case Intrinsic::arm_neon_vpmaxs: // llvm.arm.neon.vpmaxs
+ case Intrinsic::arm_neon_vpmaxu: // llvm.arm.neon.vpmaxu
+ case Intrinsic::arm_neon_vpmins: // llvm.arm.neon.vpmins
+ case Intrinsic::arm_neon_vpminu: // llvm.arm.neon.vpminu
+ case Intrinsic::arm_neon_vqadds: // llvm.arm.neon.vqadds
+ case Intrinsic::arm_neon_vqaddu: // llvm.arm.neon.vqaddu
+ case Intrinsic::arm_neon_vqdmulh: // llvm.arm.neon.vqdmulh
+ case Intrinsic::arm_neon_vqrdmulh: // llvm.arm.neon.vqrdmulh
+ case Intrinsic::arm_neon_vqrshifts: // llvm.arm.neon.vqrshifts
+ case Intrinsic::arm_neon_vqrshiftu: // llvm.arm.neon.vqrshiftu
+ case Intrinsic::arm_neon_vqshifts: // llvm.arm.neon.vqshifts
+ case Intrinsic::arm_neon_vqshiftsu: // llvm.arm.neon.vqshiftsu
+ case Intrinsic::arm_neon_vqshiftu: // llvm.arm.neon.vqshiftu
+ case Intrinsic::arm_neon_vqsubs: // llvm.arm.neon.vqsubs
+ case Intrinsic::arm_neon_vqsubu: // llvm.arm.neon.vqsubu
+ case Intrinsic::arm_neon_vrecps: // llvm.arm.neon.vrecps
+ case Intrinsic::arm_neon_vrhadds: // llvm.arm.neon.vrhadds
+ case Intrinsic::arm_neon_vrhaddu: // llvm.arm.neon.vrhaddu
+ case Intrinsic::arm_neon_vrshifts: // llvm.arm.neon.vrshifts
+ case Intrinsic::arm_neon_vrshiftu: // llvm.arm.neon.vrshiftu
+ case Intrinsic::arm_neon_vrsqrts: // llvm.arm.neon.vrsqrts
+ case Intrinsic::arm_neon_vshifts: // llvm.arm.neon.vshifts
+ case Intrinsic::arm_neon_vshiftu: // llvm.arm.neon.vshiftu
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vaddhn: // llvm.arm.neon.vaddhn
+ case Intrinsic::arm_neon_vqrshiftns: // llvm.arm.neon.vqrshiftns
+ case Intrinsic::arm_neon_vqrshiftnsu: // llvm.arm.neon.vqrshiftnsu
+ case Intrinsic::arm_neon_vqrshiftnu: // llvm.arm.neon.vqrshiftnu
+ case Intrinsic::arm_neon_vqshiftns: // llvm.arm.neon.vqshiftns
+ case Intrinsic::arm_neon_vqshiftnsu: // llvm.arm.neon.vqshiftnsu
+ case Intrinsic::arm_neon_vqshiftnu: // llvm.arm.neon.vqshiftnu
+ case Intrinsic::arm_neon_vraddhn: // llvm.arm.neon.vraddhn
+ case Intrinsic::arm_neon_vrshiftn: // llvm.arm.neon.vrshiftn
+ case Intrinsic::arm_neon_vrsubhn: // llvm.arm.neon.vrsubhn
+ case Intrinsic::arm_neon_vshiftn: // llvm.arm.neon.vshiftn
+ case Intrinsic::arm_neon_vsubhn: // llvm.arm.neon.vsubhn
+ ResultTy = Tys[0];
+ ArgTys.push_back(VectorType::getExtendedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ ArgTys.push_back(VectorType::getExtendedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ break;
+ case Intrinsic::arm_neon_vabdls: // llvm.arm.neon.vabdls
+ case Intrinsic::arm_neon_vabdlu: // llvm.arm.neon.vabdlu
+ case Intrinsic::arm_neon_vaddls: // llvm.arm.neon.vaddls
+ case Intrinsic::arm_neon_vaddlu: // llvm.arm.neon.vaddlu
+ case Intrinsic::arm_neon_vmullp: // llvm.arm.neon.vmullp
+ case Intrinsic::arm_neon_vmulls: // llvm.arm.neon.vmulls
+ case Intrinsic::arm_neon_vmullu: // llvm.arm.neon.vmullu
+ case Intrinsic::arm_neon_vqdmull: // llvm.arm.neon.vqdmull
+ case Intrinsic::arm_neon_vshiftls: // llvm.arm.neon.vshiftls
+ case Intrinsic::arm_neon_vshiftlu: // llvm.arm.neon.vshiftlu
+ case Intrinsic::arm_neon_vsubls: // llvm.arm.neon.vsubls
+ case Intrinsic::arm_neon_vsublu: // llvm.arm.neon.vsublu
+ ResultTy = Tys[0];
+ ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ ArgTys.push_back(VectorType::getTruncatedElementVectorType(dyn_cast<VectorType>(Tys[0])));
+ break;
+ case Intrinsic::arm_neon_vpaddls: // llvm.arm.neon.vpaddls
+ case Intrinsic::arm_neon_vpaddlu: // llvm.arm.neon.vpaddlu
+ ResultTy = Tys[0];
+ ArgTys.push_back(Tys[1]);
+ break;
+ case Intrinsic::arm_neon_vld1: // llvm.arm.neon.vld1
+ ResultTy = Tys[0];
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::arm_neon_vld2: // llvm.arm.neon.vld2
+ ResultTy = StructType::get(Context, Tys[0], Tys[0], NULL);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::arm_neon_vld3: // llvm.arm.neon.vld3
+ ResultTy = StructType::get(Context, Tys[0], Tys[0], Tys[0], NULL);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::arm_neon_vld4: // llvm.arm.neon.vld4
+ ResultTy = StructType::get(Context, Tys[0], Tys[0], Tys[0], Tys[0], NULL);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::arm_neon_vld2lane: // llvm.arm.neon.vld2lane
+ ResultTy = StructType::get(Context, Tys[0], Tys[0], NULL);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::arm_neon_vld3lane: // llvm.arm.neon.vld3lane
+ ResultTy = StructType::get(Context, Tys[0], Tys[0], Tys[0], NULL);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::arm_neon_vld4lane: // llvm.arm.neon.vld4lane
+ ResultTy = StructType::get(Context, Tys[0], Tys[0], Tys[0], Tys[0], NULL);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::invariant_start: // llvm.invariant.start
+ ResultTy = PointerType::getUnqual(StructType::get(Context));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::flt_rounds: // llvm.flt.rounds
+ case Intrinsic::xcore_getid: // llvm.xcore.getid
+ ResultTy = IntegerType::get(Context, 32);
+ break;
+ case Intrinsic::xcore_bitrev: // llvm.xcore.bitrev
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse42_crc32_16: // llvm.x86.sse42.crc32.16
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 16));
+ break;
+ case Intrinsic::x86_sse42_crc32_32: // llvm.x86.sse42.crc32.32
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse42_crc32_8: // llvm.x86.sse42.crc32.8
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::ppc_altivec_vcmpequb_p: // llvm.ppc.altivec.vcmpequb.p
+ case Intrinsic::ppc_altivec_vcmpgtsb_p: // llvm.ppc.altivec.vcmpgtsb.p
+ case Intrinsic::ppc_altivec_vcmpgtub_p: // llvm.ppc.altivec.vcmpgtub.p
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::ppc_altivec_vcmpbfp_p: // llvm.ppc.altivec.vcmpbfp.p
+ case Intrinsic::ppc_altivec_vcmpeqfp_p: // llvm.ppc.altivec.vcmpeqfp.p
+ case Intrinsic::ppc_altivec_vcmpgefp_p: // llvm.ppc.altivec.vcmpgefp.p
+ case Intrinsic::ppc_altivec_vcmpgtfp_p: // llvm.ppc.altivec.vcmpgtfp.p
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::ppc_altivec_vcmpequw_p: // llvm.ppc.altivec.vcmpequw.p
+ case Intrinsic::ppc_altivec_vcmpgtsw_p: // llvm.ppc.altivec.vcmpgtsw.p
+ case Intrinsic::ppc_altivec_vcmpgtuw_p: // llvm.ppc.altivec.vcmpgtuw.p
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_vcmpequh_p: // llvm.ppc.altivec.vcmpequh.p
+ case Intrinsic::ppc_altivec_vcmpgtsh_p: // llvm.ppc.altivec.vcmpgtsh.p
+ case Intrinsic::ppc_altivec_vcmpgtuh_p: // llvm.ppc.altivec.vcmpgtuh.p
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::eh_sjlj_setjmp: // llvm.eh.sjlj.setjmp
+ case Intrinsic::eh_typeid_for: // llvm.eh.typeid.for
+ case Intrinsic::setjmp: // llvm.setjmp
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::sigsetjmp: // llvm.sigsetjmp
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::eh_selector: // llvm.eh.selector
+ IsVarArg = true;
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_sse2_pmovmskb_128: // llvm.x86.sse2.pmovmskb.128
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::x86_sse41_pextrb: // llvm.x86.sse41.pextrb
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse42_pcmpestri128: // llvm.x86.sse42.pcmpestri128
+ case Intrinsic::x86_sse42_pcmpestria128: // llvm.x86.sse42.pcmpestria128
+ case Intrinsic::x86_sse42_pcmpestric128: // llvm.x86.sse42.pcmpestric128
+ case Intrinsic::x86_sse42_pcmpestrio128: // llvm.x86.sse42.pcmpestrio128
+ case Intrinsic::x86_sse42_pcmpestris128: // llvm.x86.sse42.pcmpestris128
+ case Intrinsic::x86_sse42_pcmpestriz128: // llvm.x86.sse42.pcmpestriz128
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse42_pcmpistri128: // llvm.x86.sse42.pcmpistri128
+ case Intrinsic::x86_sse42_pcmpistria128: // llvm.x86.sse42.pcmpistria128
+ case Intrinsic::x86_sse42_pcmpistric128: // llvm.x86.sse42.pcmpistric128
+ case Intrinsic::x86_sse42_pcmpistrio128: // llvm.x86.sse42.pcmpistrio128
+ case Intrinsic::x86_sse42_pcmpistris128: // llvm.x86.sse42.pcmpistris128
+ case Intrinsic::x86_sse42_pcmpistriz128: // llvm.x86.sse42.pcmpistriz128
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse2_cvtsd2si: // llvm.x86.sse2.cvtsd2si
+ case Intrinsic::x86_sse2_cvttsd2si: // llvm.x86.sse2.cvttsd2si
+ case Intrinsic::x86_sse2_movmsk_pd: // llvm.x86.sse2.movmsk.pd
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse2_comieq_sd: // llvm.x86.sse2.comieq.sd
+ case Intrinsic::x86_sse2_comige_sd: // llvm.x86.sse2.comige.sd
+ case Intrinsic::x86_sse2_comigt_sd: // llvm.x86.sse2.comigt.sd
+ case Intrinsic::x86_sse2_comile_sd: // llvm.x86.sse2.comile.sd
+ case Intrinsic::x86_sse2_comilt_sd: // llvm.x86.sse2.comilt.sd
+ case Intrinsic::x86_sse2_comineq_sd: // llvm.x86.sse2.comineq.sd
+ case Intrinsic::x86_sse2_ucomieq_sd: // llvm.x86.sse2.ucomieq.sd
+ case Intrinsic::x86_sse2_ucomige_sd: // llvm.x86.sse2.ucomige.sd
+ case Intrinsic::x86_sse2_ucomigt_sd: // llvm.x86.sse2.ucomigt.sd
+ case Intrinsic::x86_sse2_ucomile_sd: // llvm.x86.sse2.ucomile.sd
+ case Intrinsic::x86_sse2_ucomilt_sd: // llvm.x86.sse2.ucomilt.sd
+ case Intrinsic::x86_sse2_ucomineq_sd: // llvm.x86.sse2.ucomineq.sd
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse_cvtss2si: // llvm.x86.sse.cvtss2si
+ case Intrinsic::x86_sse_cvttss2si: // llvm.x86.sse.cvttss2si
+ case Intrinsic::x86_sse_movmsk_ps: // llvm.x86.sse.movmsk.ps
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse41_extractps: // llvm.x86.sse41.extractps
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse41_ptestc: // llvm.x86.sse41.ptestc
+ case Intrinsic::x86_sse41_ptestnzc: // llvm.x86.sse41.ptestnzc
+ case Intrinsic::x86_sse41_ptestz: // llvm.x86.sse41.ptestz
+ case Intrinsic::x86_sse_comieq_ss: // llvm.x86.sse.comieq.ss
+ case Intrinsic::x86_sse_comige_ss: // llvm.x86.sse.comige.ss
+ case Intrinsic::x86_sse_comigt_ss: // llvm.x86.sse.comigt.ss
+ case Intrinsic::x86_sse_comile_ss: // llvm.x86.sse.comile.ss
+ case Intrinsic::x86_sse_comilt_ss: // llvm.x86.sse.comilt.ss
+ case Intrinsic::x86_sse_comineq_ss: // llvm.x86.sse.comineq.ss
+ case Intrinsic::x86_sse_ucomieq_ss: // llvm.x86.sse.ucomieq.ss
+ case Intrinsic::x86_sse_ucomige_ss: // llvm.x86.sse.ucomige.ss
+ case Intrinsic::x86_sse_ucomigt_ss: // llvm.x86.sse.ucomigt.ss
+ case Intrinsic::x86_sse_ucomile_ss: // llvm.x86.sse.ucomile.ss
+ case Intrinsic::x86_sse_ucomilt_ss: // llvm.x86.sse.ucomilt.ss
+ case Intrinsic::x86_sse_ucomineq_ss: // llvm.x86.sse.ucomineq.ss
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse41_pextrd: // llvm.x86.sse41.pextrd
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_mmx_pmovmskb: // llvm.x86.mmx.pmovmskb
+ ResultTy = IntegerType::get(Context, 32);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::readcyclecounter: // llvm.readcyclecounter
+ ResultTy = IntegerType::get(Context, 64);
+ break;
+ case Intrinsic::alpha_umulh: // llvm.alpha.umulh
+ case Intrinsic::x86_sse42_crc32_64: // llvm.x86.sse42.crc32.64
+ ResultTy = IntegerType::get(Context, 64);
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ break;
+ case Intrinsic::x86_sse2_cvtsd2si64: // llvm.x86.sse2.cvtsd2si64
+ case Intrinsic::x86_sse2_cvttsd2si64: // llvm.x86.sse2.cvttsd2si64
+ ResultTy = IntegerType::get(Context, 64);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse41_pextrq: // llvm.x86.sse41.pextrq
+ ResultTy = IntegerType::get(Context, 64);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse_cvtss2si64: // llvm.x86.sse.cvtss2si64
+ case Intrinsic::x86_sse_cvttss2si64: // llvm.x86.sse.cvttss2si64
+ ResultTy = IntegerType::get(Context, 64);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::arm_thread_pointer: // llvm.arm.thread.pointer
+ case Intrinsic::eh_exception: // llvm.eh.exception
+ case Intrinsic::eh_sjlj_lsda: // llvm.eh.sjlj.lsda
+ case Intrinsic::stacksave: // llvm.stacksave
+ ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::eh_dwarf_cfa: // llvm.eh.dwarf.cfa
+ case Intrinsic::frameaddress: // llvm.frameaddress
+ case Intrinsic::returnaddress: // llvm.returnaddress
+ ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::init_trampoline: // llvm.init.trampoline
+ ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::gcread: // llvm.gcread
+ ResultTy = PointerType::getUnqual(IntegerType::get(Context, 8));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerType::get(Context, 8))));
+ break;
+ case Intrinsic::ppc_altivec_lvebx: // llvm.ppc.altivec.lvebx
+ case Intrinsic::ppc_altivec_lvsl: // llvm.ppc.altivec.lvsl
+ case Intrinsic::ppc_altivec_lvsr: // llvm.ppc.altivec.lvsr
+ case Intrinsic::x86_sse2_loadu_dq: // llvm.x86.sse2.loadu.dq
+ case Intrinsic::x86_sse3_ldu_dq: // llvm.x86.sse3.ldu.dq
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_ssse3_pabs_b_128: // llvm.x86.ssse3.pabs.b.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::spu_si_shlqbii: // llvm.spu.si.shlqbii
+ case Intrinsic::spu_si_shlqbyi: // llvm.spu.si.shlqbyi
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse42_pcmpestrm128: // llvm.x86.sse42.pcmpestrm128
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::spu_si_andbi: // llvm.spu.si.andbi
+ case Intrinsic::spu_si_ceqbi: // llvm.spu.si.ceqbi
+ case Intrinsic::spu_si_cgtbi: // llvm.spu.si.cgtbi
+ case Intrinsic::spu_si_clgtbi: // llvm.spu.si.clgtbi
+ case Intrinsic::spu_si_orbi: // llvm.spu.si.orbi
+ case Intrinsic::spu_si_xorbi: // llvm.spu.si.xorbi
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::ppc_altivec_vaddsbs: // llvm.ppc.altivec.vaddsbs
+ case Intrinsic::ppc_altivec_vaddubs: // llvm.ppc.altivec.vaddubs
+ case Intrinsic::ppc_altivec_vavgsb: // llvm.ppc.altivec.vavgsb
+ case Intrinsic::ppc_altivec_vavgub: // llvm.ppc.altivec.vavgub
+ case Intrinsic::ppc_altivec_vcmpequb: // llvm.ppc.altivec.vcmpequb
+ case Intrinsic::ppc_altivec_vcmpgtsb: // llvm.ppc.altivec.vcmpgtsb
+ case Intrinsic::ppc_altivec_vcmpgtub: // llvm.ppc.altivec.vcmpgtub
+ case Intrinsic::ppc_altivec_vmaxsb: // llvm.ppc.altivec.vmaxsb
+ case Intrinsic::ppc_altivec_vmaxub: // llvm.ppc.altivec.vmaxub
+ case Intrinsic::ppc_altivec_vminsb: // llvm.ppc.altivec.vminsb
+ case Intrinsic::ppc_altivec_vminub: // llvm.ppc.altivec.vminub
+ case Intrinsic::ppc_altivec_vrlb: // llvm.ppc.altivec.vrlb
+ case Intrinsic::ppc_altivec_vslb: // llvm.ppc.altivec.vslb
+ case Intrinsic::ppc_altivec_vsrab: // llvm.ppc.altivec.vsrab
+ case Intrinsic::ppc_altivec_vsrb: // llvm.ppc.altivec.vsrb
+ case Intrinsic::ppc_altivec_vsubsbs: // llvm.ppc.altivec.vsubsbs
+ case Intrinsic::ppc_altivec_vsububs: // llvm.ppc.altivec.vsububs
+ case Intrinsic::spu_si_ceqb: // llvm.spu.si.ceqb
+ case Intrinsic::spu_si_cgtb: // llvm.spu.si.cgtb
+ case Intrinsic::spu_si_clgtb: // llvm.spu.si.clgtb
+ case Intrinsic::x86_sse2_padds_b: // llvm.x86.sse2.padds.b
+ case Intrinsic::x86_sse2_paddus_b: // llvm.x86.sse2.paddus.b
+ case Intrinsic::x86_sse2_pavg_b: // llvm.x86.sse2.pavg.b
+ case Intrinsic::x86_sse2_pcmpeq_b: // llvm.x86.sse2.pcmpeq.b
+ case Intrinsic::x86_sse2_pcmpgt_b: // llvm.x86.sse2.pcmpgt.b
+ case Intrinsic::x86_sse2_pmaxu_b: // llvm.x86.sse2.pmaxu.b
+ case Intrinsic::x86_sse2_pminu_b: // llvm.x86.sse2.pminu.b
+ case Intrinsic::x86_sse2_psubs_b: // llvm.x86.sse2.psubs.b
+ case Intrinsic::x86_sse2_psubus_b: // llvm.x86.sse2.psubus.b
+ case Intrinsic::x86_sse41_pmaxsb: // llvm.x86.sse41.pmaxsb
+ case Intrinsic::x86_sse41_pminsb: // llvm.x86.sse41.pminsb
+ case Intrinsic::x86_ssse3_pshuf_b_128: // llvm.x86.ssse3.pshuf.b.128
+ case Intrinsic::x86_ssse3_psign_b_128: // llvm.x86.ssse3.psign.b.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::x86_sse41_mpsadbw: // llvm.x86.sse41.mpsadbw
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse42_pcmpistrm128: // llvm.x86.sse42.pcmpistrm128
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse41_pblendvb: // llvm.x86.sse41.pblendvb
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::ppc_altivec_vpkswss: // llvm.ppc.altivec.vpkswss
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_vpkshss: // llvm.ppc.altivec.vpkshss
+ case Intrinsic::ppc_altivec_vpkshus: // llvm.ppc.altivec.vpkshus
+ case Intrinsic::ppc_altivec_vpkuhus: // llvm.ppc.altivec.vpkuhus
+ case Intrinsic::x86_sse2_packsswb_128: // llvm.x86.sse2.packsswb.128
+ case Intrinsic::x86_sse2_packuswb_128: // llvm.x86.sse2.packuswb.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 16);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::x86_mmx_pslli_q: // llvm.x86.mmx.pslli.q
+ case Intrinsic::x86_mmx_psrli_q: // llvm.x86.mmx.psrli.q
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 1);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_mmx_psll_q: // llvm.x86.mmx.psll.q
+ case Intrinsic::x86_mmx_psrl_q: // llvm.x86.mmx.psrl.q
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 1);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ break;
+ case Intrinsic::x86_ssse3_palign_r: // llvm.x86.ssse3.palign.r
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 1);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse2_loadu_pd: // llvm.x86.sse2.loadu.pd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_sse2_sqrt_pd: // llvm.x86.sse2.sqrt.pd
+ case Intrinsic::x86_sse2_sqrt_sd: // llvm.x86.sse2.sqrt.sd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse2_cvtsi2sd: // llvm.x86.sse2.cvtsi2sd
+ case Intrinsic::x86_sse41_round_pd: // llvm.x86.sse41.round.pd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse2_cvtsi642sd: // llvm.x86.sse2.cvtsi642sd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ break;
+ case Intrinsic::spu_si_dfa: // llvm.spu.si.dfa
+ case Intrinsic::spu_si_dfm: // llvm.spu.si.dfm
+ case Intrinsic::spu_si_dfma: // llvm.spu.si.dfma
+ case Intrinsic::spu_si_dfms: // llvm.spu.si.dfms
+ case Intrinsic::spu_si_dfnma: // llvm.spu.si.dfnma
+ case Intrinsic::spu_si_dfnms: // llvm.spu.si.dfnms
+ case Intrinsic::spu_si_dfs: // llvm.spu.si.dfs
+ case Intrinsic::x86_sse2_add_sd: // llvm.x86.sse2.add.sd
+ case Intrinsic::x86_sse2_div_sd: // llvm.x86.sse2.div.sd
+ case Intrinsic::x86_sse2_max_pd: // llvm.x86.sse2.max.pd
+ case Intrinsic::x86_sse2_max_sd: // llvm.x86.sse2.max.sd
+ case Intrinsic::x86_sse2_min_pd: // llvm.x86.sse2.min.pd
+ case Intrinsic::x86_sse2_min_sd: // llvm.x86.sse2.min.sd
+ case Intrinsic::x86_sse2_mul_sd: // llvm.x86.sse2.mul.sd
+ case Intrinsic::x86_sse2_sub_sd: // llvm.x86.sse2.sub.sd
+ case Intrinsic::x86_sse3_addsub_pd: // llvm.x86.sse3.addsub.pd
+ case Intrinsic::x86_sse3_hadd_pd: // llvm.x86.sse3.hadd.pd
+ case Intrinsic::x86_sse3_hsub_pd: // llvm.x86.sse3.hsub.pd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse41_blendpd: // llvm.x86.sse41.blendpd
+ case Intrinsic::x86_sse41_dppd: // llvm.x86.sse41.dppd
+ case Intrinsic::x86_sse41_round_sd: // llvm.x86.sse41.round.sd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse2_cmp_pd: // llvm.x86.sse2.cmp.pd
+ case Intrinsic::x86_sse2_cmp_sd: // llvm.x86.sse2.cmp.sd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse41_blendvpd: // llvm.x86.sse41.blendvpd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse2_cvtss2sd: // llvm.x86.sse2.cvtss2sd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse_cvtpi2pd: // llvm.x86.sse.cvtpi2pd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ break;
+ case Intrinsic::x86_sse2_cvtps2pd: // llvm.x86.sse2.cvtps2pd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse2_cvtdq2pd: // llvm.x86.sse2.cvtdq2pd
+ ResultTy = VectorType::get(Type::getDoubleTy(Context), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::arm_neon_vacged: // llvm.arm.neon.vacged
+ case Intrinsic::arm_neon_vacgtd: // llvm.arm.neon.vacgtd
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse_cvtpd2pi: // llvm.x86.sse.cvtpd2pi
+ case Intrinsic::x86_sse_cvttpd2pi: // llvm.x86.sse.cvttpd2pi
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_ssse3_pabs_d: // llvm.x86.ssse3.pabs.d
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ break;
+ case Intrinsic::x86_mmx_pslli_d: // llvm.x86.mmx.pslli.d
+ case Intrinsic::x86_mmx_psrai_d: // llvm.x86.mmx.psrai.d
+ case Intrinsic::x86_mmx_psrli_d: // llvm.x86.mmx.psrli.d
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_mmx_psll_d: // llvm.x86.mmx.psll.d
+ case Intrinsic::x86_mmx_psra_d: // llvm.x86.mmx.psra.d
+ case Intrinsic::x86_mmx_psrl_d: // llvm.x86.mmx.psrl.d
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ break;
+ case Intrinsic::x86_mmx_pcmpeq_d: // llvm.x86.mmx.pcmpeq.d
+ case Intrinsic::x86_mmx_pcmpgt_d: // llvm.x86.mmx.pcmpgt.d
+ case Intrinsic::x86_mmx_pmulu_dq: // llvm.x86.mmx.pmulu.dq
+ case Intrinsic::x86_ssse3_phadd_d: // llvm.x86.ssse3.phadd.d
+ case Intrinsic::x86_ssse3_phsub_d: // llvm.x86.ssse3.phsub.d
+ case Intrinsic::x86_ssse3_psign_d: // llvm.x86.ssse3.psign.d
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ break;
+ case Intrinsic::x86_sse_cvtps2pi: // llvm.x86.sse.cvtps2pi
+ case Intrinsic::x86_sse_cvttps2pi: // llvm.x86.sse.cvttps2pi
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_mmx_pmadd_wd: // llvm.x86.mmx.pmadd.wd
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ break;
+ case Intrinsic::x86_sse41_movntdqa: // llvm.x86.sse41.movntdqa
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_sse41_pmovsxbq: // llvm.x86.sse41.pmovsxbq
+ case Intrinsic::x86_sse41_pmovzxbq: // llvm.x86.sse41.pmovzxbq
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::x86_sse2_psad_bw: // llvm.x86.sse2.psad.bw
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::x86_sse2_psll_dq: // llvm.x86.sse2.psll.dq
+ case Intrinsic::x86_sse2_psll_dq_bs: // llvm.x86.sse2.psll.dq.bs
+ case Intrinsic::x86_sse2_pslli_q: // llvm.x86.sse2.pslli.q
+ case Intrinsic::x86_sse2_psrl_dq: // llvm.x86.sse2.psrl.dq
+ case Intrinsic::x86_sse2_psrl_dq_bs: // llvm.x86.sse2.psrl.dq.bs
+ case Intrinsic::x86_sse2_psrli_q: // llvm.x86.sse2.psrli.q
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse2_psll_q: // llvm.x86.sse2.psll.q
+ case Intrinsic::x86_sse2_psrl_q: // llvm.x86.sse2.psrl.q
+ case Intrinsic::x86_sse41_pcmpeqq: // llvm.x86.sse41.pcmpeqq
+ case Intrinsic::x86_sse42_pcmpgtq: // llvm.x86.sse42.pcmpgtq
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ break;
+ case Intrinsic::x86_ssse3_palign_r_128: // llvm.x86.ssse3.palign.r.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::x86_sse41_pmovsxdq: // llvm.x86.sse41.pmovsxdq
+ case Intrinsic::x86_sse41_pmovzxdq: // llvm.x86.sse41.pmovzxdq
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::x86_sse2_pmulu_dq: // llvm.x86.sse2.pmulu.dq
+ case Intrinsic::x86_sse41_pmuldq: // llvm.x86.sse41.pmuldq
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::x86_sse41_pmovsxwq: // llvm.x86.sse41.pmovsxwq
+ case Intrinsic::x86_sse41_pmovzxwq: // llvm.x86.sse41.pmovzxwq
+ ResultTy = VectorType::get(IntegerType::get(Context, 64), 2);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::x86_sse_loadu_ps: // llvm.x86.sse.loadu.ps
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_sse2_cvtpd2ps: // llvm.x86.sse2.cvtpd2ps
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::ppc_altivec_vexptefp: // llvm.ppc.altivec.vexptefp
+ case Intrinsic::ppc_altivec_vlogefp: // llvm.ppc.altivec.vlogefp
+ case Intrinsic::ppc_altivec_vrefp: // llvm.ppc.altivec.vrefp
+ case Intrinsic::ppc_altivec_vrfim: // llvm.ppc.altivec.vrfim
+ case Intrinsic::ppc_altivec_vrfin: // llvm.ppc.altivec.vrfin
+ case Intrinsic::ppc_altivec_vrfip: // llvm.ppc.altivec.vrfip
+ case Intrinsic::ppc_altivec_vrfiz: // llvm.ppc.altivec.vrfiz
+ case Intrinsic::ppc_altivec_vrsqrtefp: // llvm.ppc.altivec.vrsqrtefp
+ case Intrinsic::x86_sse_rcp_ps: // llvm.x86.sse.rcp.ps
+ case Intrinsic::x86_sse_rcp_ss: // llvm.x86.sse.rcp.ss
+ case Intrinsic::x86_sse_rsqrt_ps: // llvm.x86.sse.rsqrt.ps
+ case Intrinsic::x86_sse_rsqrt_ss: // llvm.x86.sse.rsqrt.ss
+ case Intrinsic::x86_sse_sqrt_ps: // llvm.x86.sse.sqrt.ps
+ case Intrinsic::x86_sse_sqrt_ss: // llvm.x86.sse.sqrt.ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse41_round_ps: // llvm.x86.sse41.round.ps
+ case Intrinsic::x86_sse_cvtsi2ss: // llvm.x86.sse.cvtsi2ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse_cvtsi642ss: // llvm.x86.sse.cvtsi642ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ break;
+ case Intrinsic::x86_sse2_cvtsd2ss: // llvm.x86.sse2.cvtsd2ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse_cvtpi2ps: // llvm.x86.sse.cvtpi2ps
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ break;
+ case Intrinsic::ppc_altivec_vmaxfp: // llvm.ppc.altivec.vmaxfp
+ case Intrinsic::ppc_altivec_vminfp: // llvm.ppc.altivec.vminfp
+ case Intrinsic::spu_si_fa: // llvm.spu.si.fa
+ case Intrinsic::spu_si_fceq: // llvm.spu.si.fceq
+ case Intrinsic::spu_si_fcgt: // llvm.spu.si.fcgt
+ case Intrinsic::spu_si_fcmeq: // llvm.spu.si.fcmeq
+ case Intrinsic::spu_si_fcmgt: // llvm.spu.si.fcmgt
+ case Intrinsic::spu_si_fm: // llvm.spu.si.fm
+ case Intrinsic::spu_si_fs: // llvm.spu.si.fs
+ case Intrinsic::x86_sse3_addsub_ps: // llvm.x86.sse3.addsub.ps
+ case Intrinsic::x86_sse3_hadd_ps: // llvm.x86.sse3.hadd.ps
+ case Intrinsic::x86_sse3_hsub_ps: // llvm.x86.sse3.hsub.ps
+ case Intrinsic::x86_sse_add_ss: // llvm.x86.sse.add.ss
+ case Intrinsic::x86_sse_div_ss: // llvm.x86.sse.div.ss
+ case Intrinsic::x86_sse_max_ps: // llvm.x86.sse.max.ps
+ case Intrinsic::x86_sse_max_ss: // llvm.x86.sse.max.ss
+ case Intrinsic::x86_sse_min_ps: // llvm.x86.sse.min.ps
+ case Intrinsic::x86_sse_min_ss: // llvm.x86.sse.min.ss
+ case Intrinsic::x86_sse_mul_ss: // llvm.x86.sse.mul.ss
+ case Intrinsic::x86_sse_sub_ss: // llvm.x86.sse.sub.ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse41_blendps: // llvm.x86.sse41.blendps
+ case Intrinsic::x86_sse41_dpps: // llvm.x86.sse41.dpps
+ case Intrinsic::x86_sse41_insertps: // llvm.x86.sse41.insertps
+ case Intrinsic::x86_sse41_round_ss: // llvm.x86.sse41.round.ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse_cmp_ps: // llvm.x86.sse.cmp.ps
+ case Intrinsic::x86_sse_cmp_ss: // llvm.x86.sse.cmp.ss
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::ppc_altivec_vmaddfp: // llvm.ppc.altivec.vmaddfp
+ case Intrinsic::ppc_altivec_vnmsubfp: // llvm.ppc.altivec.vnmsubfp
+ case Intrinsic::spu_si_fma: // llvm.spu.si.fma
+ case Intrinsic::spu_si_fms: // llvm.spu.si.fms
+ case Intrinsic::spu_si_fnms: // llvm.spu.si.fnms
+ case Intrinsic::x86_sse41_blendvps: // llvm.x86.sse41.blendvps
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse2_cvtdq2ps: // llvm.x86.sse2.cvtdq2ps
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_vcfsx: // llvm.ppc.altivec.vcfsx
+ case Intrinsic::ppc_altivec_vcfux: // llvm.ppc.altivec.vcfux
+ ResultTy = VectorType::get(Type::getFloatTy(Context), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_mmx_packssdw: // llvm.x86.mmx.packssdw
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 2));
+ break;
+ case Intrinsic::x86_ssse3_pabs_w: // llvm.x86.ssse3.pabs.w
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ break;
+ case Intrinsic::x86_mmx_pslli_w: // llvm.x86.mmx.pslli.w
+ case Intrinsic::x86_mmx_psrai_w: // llvm.x86.mmx.psrai.w
+ case Intrinsic::x86_mmx_psrli_w: // llvm.x86.mmx.psrli.w
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_mmx_psll_w: // llvm.x86.mmx.psll.w
+ case Intrinsic::x86_mmx_psra_w: // llvm.x86.mmx.psra.w
+ case Intrinsic::x86_mmx_psrl_w: // llvm.x86.mmx.psrl.w
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ break;
+ case Intrinsic::x86_mmx_padds_w: // llvm.x86.mmx.padds.w
+ case Intrinsic::x86_mmx_paddus_w: // llvm.x86.mmx.paddus.w
+ case Intrinsic::x86_mmx_pavg_w: // llvm.x86.mmx.pavg.w
+ case Intrinsic::x86_mmx_pcmpeq_w: // llvm.x86.mmx.pcmpeq.w
+ case Intrinsic::x86_mmx_pcmpgt_w: // llvm.x86.mmx.pcmpgt.w
+ case Intrinsic::x86_mmx_pmaxs_w: // llvm.x86.mmx.pmaxs.w
+ case Intrinsic::x86_mmx_pmins_w: // llvm.x86.mmx.pmins.w
+ case Intrinsic::x86_mmx_pmulh_w: // llvm.x86.mmx.pmulh.w
+ case Intrinsic::x86_mmx_pmulhu_w: // llvm.x86.mmx.pmulhu.w
+ case Intrinsic::x86_mmx_psubs_w: // llvm.x86.mmx.psubs.w
+ case Intrinsic::x86_mmx_psubus_w: // llvm.x86.mmx.psubus.w
+ case Intrinsic::x86_ssse3_phadd_sw: // llvm.x86.ssse3.phadd.sw
+ case Intrinsic::x86_ssse3_phadd_w: // llvm.x86.ssse3.phadd.w
+ case Intrinsic::x86_ssse3_phsub_sw: // llvm.x86.ssse3.phsub.sw
+ case Intrinsic::x86_ssse3_phsub_w: // llvm.x86.ssse3.phsub.w
+ case Intrinsic::x86_ssse3_pmadd_ub_sw: // llvm.x86.ssse3.pmadd.ub.sw
+ case Intrinsic::x86_ssse3_pmul_hr_sw: // llvm.x86.ssse3.pmul.hr.sw
+ case Intrinsic::x86_ssse3_psign_w: // llvm.x86.ssse3.psign.w
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ break;
+ case Intrinsic::x86_mmx_psad_bw: // llvm.x86.mmx.psad.bw
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::ppc_altivec_lvewx: // llvm.ppc.altivec.lvewx
+ case Intrinsic::ppc_altivec_lvx: // llvm.ppc.altivec.lvx
+ case Intrinsic::ppc_altivec_lvxl: // llvm.ppc.altivec.lvxl
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_sse41_pmovsxbd: // llvm.x86.sse41.pmovsxbd
+ case Intrinsic::x86_sse41_pmovzxbd: // llvm.x86.sse41.pmovzxbd
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::ppc_altivec_vmsummbm: // llvm.ppc.altivec.vmsummbm
+ case Intrinsic::ppc_altivec_vmsumubm: // llvm.ppc.altivec.vmsumubm
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_vsum4sbs: // llvm.ppc.altivec.vsum4sbs
+ case Intrinsic::ppc_altivec_vsum4ubs: // llvm.ppc.altivec.vsum4ubs
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::x86_sse2_cvtpd2dq: // llvm.x86.sse2.cvtpd2dq
+ case Intrinsic::x86_sse2_cvttpd2dq: // llvm.x86.sse2.cvttpd2dq
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse2_cvtps2dq: // llvm.x86.sse2.cvtps2dq
+ case Intrinsic::x86_sse2_cvttps2dq: // llvm.x86.sse2.cvttps2dq
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::ppc_altivec_vctsxs: // llvm.ppc.altivec.vctsxs
+ case Intrinsic::ppc_altivec_vctuxs: // llvm.ppc.altivec.vctuxs
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::arm_neon_vacgeq: // llvm.arm.neon.vacgeq
+ case Intrinsic::arm_neon_vacgtq: // llvm.arm.neon.vacgtq
+ case Intrinsic::ppc_altivec_vcmpbfp: // llvm.ppc.altivec.vcmpbfp
+ case Intrinsic::ppc_altivec_vcmpeqfp: // llvm.ppc.altivec.vcmpeqfp
+ case Intrinsic::ppc_altivec_vcmpgefp: // llvm.ppc.altivec.vcmpgefp
+ case Intrinsic::ppc_altivec_vcmpgtfp: // llvm.ppc.altivec.vcmpgtfp
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_ssse3_pabs_d_128: // llvm.x86.ssse3.pabs.d.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::spu_si_shli: // llvm.spu.si.shli
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ break;
+ case Intrinsic::spu_si_ai: // llvm.spu.si.ai
+ case Intrinsic::spu_si_andi: // llvm.spu.si.andi
+ case Intrinsic::spu_si_ceqi: // llvm.spu.si.ceqi
+ case Intrinsic::spu_si_cgti: // llvm.spu.si.cgti
+ case Intrinsic::spu_si_clgti: // llvm.spu.si.clgti
+ case Intrinsic::spu_si_ori: // llvm.spu.si.ori
+ case Intrinsic::spu_si_sfi: // llvm.spu.si.sfi
+ case Intrinsic::spu_si_xori: // llvm.spu.si.xori
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(IntegerType::get(Context, 16));
+ break;
+ case Intrinsic::x86_sse2_pslli_d: // llvm.x86.sse2.pslli.d
+ case Intrinsic::x86_sse2_psrai_d: // llvm.x86.sse2.psrai.d
+ case Intrinsic::x86_sse2_psrli_d: // llvm.x86.sse2.psrli.d
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::ppc_altivec_vaddcuw: // llvm.ppc.altivec.vaddcuw
+ case Intrinsic::ppc_altivec_vaddsws: // llvm.ppc.altivec.vaddsws
+ case Intrinsic::ppc_altivec_vadduws: // llvm.ppc.altivec.vadduws
+ case Intrinsic::ppc_altivec_vavgsw: // llvm.ppc.altivec.vavgsw
+ case Intrinsic::ppc_altivec_vavguw: // llvm.ppc.altivec.vavguw
+ case Intrinsic::ppc_altivec_vcmpequw: // llvm.ppc.altivec.vcmpequw
+ case Intrinsic::ppc_altivec_vcmpgtsw: // llvm.ppc.altivec.vcmpgtsw
+ case Intrinsic::ppc_altivec_vcmpgtuw: // llvm.ppc.altivec.vcmpgtuw
+ case Intrinsic::ppc_altivec_vmaxsw: // llvm.ppc.altivec.vmaxsw
+ case Intrinsic::ppc_altivec_vmaxuw: // llvm.ppc.altivec.vmaxuw
+ case Intrinsic::ppc_altivec_vminsw: // llvm.ppc.altivec.vminsw
+ case Intrinsic::ppc_altivec_vminuw: // llvm.ppc.altivec.vminuw
+ case Intrinsic::ppc_altivec_vrlw: // llvm.ppc.altivec.vrlw
+ case Intrinsic::ppc_altivec_vsl: // llvm.ppc.altivec.vsl
+ case Intrinsic::ppc_altivec_vslo: // llvm.ppc.altivec.vslo
+ case Intrinsic::ppc_altivec_vslw: // llvm.ppc.altivec.vslw
+ case Intrinsic::ppc_altivec_vsr: // llvm.ppc.altivec.vsr
+ case Intrinsic::ppc_altivec_vsraw: // llvm.ppc.altivec.vsraw
+ case Intrinsic::ppc_altivec_vsro: // llvm.ppc.altivec.vsro
+ case Intrinsic::ppc_altivec_vsrw: // llvm.ppc.altivec.vsrw
+ case Intrinsic::ppc_altivec_vsubcuw: // llvm.ppc.altivec.vsubcuw
+ case Intrinsic::ppc_altivec_vsubsws: // llvm.ppc.altivec.vsubsws
+ case Intrinsic::ppc_altivec_vsubuws: // llvm.ppc.altivec.vsubuws
+ case Intrinsic::ppc_altivec_vsum2sws: // llvm.ppc.altivec.vsum2sws
+ case Intrinsic::ppc_altivec_vsumsws: // llvm.ppc.altivec.vsumsws
+ case Intrinsic::spu_si_a: // llvm.spu.si.a
+ case Intrinsic::spu_si_addx: // llvm.spu.si.addx
+ case Intrinsic::spu_si_and: // llvm.spu.si.and
+ case Intrinsic::spu_si_andc: // llvm.spu.si.andc
+ case Intrinsic::spu_si_bg: // llvm.spu.si.bg
+ case Intrinsic::spu_si_bgx: // llvm.spu.si.bgx
+ case Intrinsic::spu_si_ceq: // llvm.spu.si.ceq
+ case Intrinsic::spu_si_cg: // llvm.spu.si.cg
+ case Intrinsic::spu_si_cgt: // llvm.spu.si.cgt
+ case Intrinsic::spu_si_cgx: // llvm.spu.si.cgx
+ case Intrinsic::spu_si_clgt: // llvm.spu.si.clgt
+ case Intrinsic::spu_si_nand: // llvm.spu.si.nand
+ case Intrinsic::spu_si_nor: // llvm.spu.si.nor
+ case Intrinsic::spu_si_or: // llvm.spu.si.or
+ case Intrinsic::spu_si_orc: // llvm.spu.si.orc
+ case Intrinsic::spu_si_sf: // llvm.spu.si.sf
+ case Intrinsic::spu_si_sfx: // llvm.spu.si.sfx
+ case Intrinsic::spu_si_xor: // llvm.spu.si.xor
+ case Intrinsic::x86_sse2_pcmpeq_d: // llvm.x86.sse2.pcmpeq.d
+ case Intrinsic::x86_sse2_pcmpgt_d: // llvm.x86.sse2.pcmpgt.d
+ case Intrinsic::x86_sse2_psll_d: // llvm.x86.sse2.psll.d
+ case Intrinsic::x86_sse2_psra_d: // llvm.x86.sse2.psra.d
+ case Intrinsic::x86_sse2_psrl_d: // llvm.x86.sse2.psrl.d
+ case Intrinsic::x86_sse41_pmaxsd: // llvm.x86.sse41.pmaxsd
+ case Intrinsic::x86_sse41_pmaxud: // llvm.x86.sse41.pmaxud
+ case Intrinsic::x86_sse41_pminsd: // llvm.x86.sse41.pminsd
+ case Intrinsic::x86_sse41_pminud: // llvm.x86.sse41.pminud
+ case Intrinsic::x86_sse41_pmulld: // llvm.x86.sse41.pmulld
+ case Intrinsic::x86_ssse3_phadd_d_128: // llvm.x86.ssse3.phadd.d.128
+ case Intrinsic::x86_ssse3_phadd_sw_128: // llvm.x86.ssse3.phadd.sw.128
+ case Intrinsic::x86_ssse3_phsub_d_128: // llvm.x86.ssse3.phsub.d.128
+ case Intrinsic::x86_ssse3_psign_d_128: // llvm.x86.ssse3.psign.d.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_vperm: // llvm.ppc.altivec.vperm
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::ppc_altivec_vsel: // llvm.ppc.altivec.vsel
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::spu_si_mpyh: // llvm.spu.si.mpyh
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::ppc_altivec_vupkhpx: // llvm.ppc.altivec.vupkhpx
+ case Intrinsic::ppc_altivec_vupkhsh: // llvm.ppc.altivec.vupkhsh
+ case Intrinsic::ppc_altivec_vupklpx: // llvm.ppc.altivec.vupklpx
+ case Intrinsic::ppc_altivec_vupklsh: // llvm.ppc.altivec.vupklsh
+ case Intrinsic::x86_sse41_pmovsxwd: // llvm.x86.sse41.pmovsxwd
+ case Intrinsic::x86_sse41_pmovzxwd: // llvm.x86.sse41.pmovzxwd
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::spu_si_mpyi: // llvm.spu.si.mpyi
+ case Intrinsic::spu_si_mpyui: // llvm.spu.si.mpyui
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(IntegerType::get(Context, 16));
+ break;
+ case Intrinsic::ppc_altivec_vsum4shs: // llvm.ppc.altivec.vsum4shs
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_vmulesh: // llvm.ppc.altivec.vmulesh
+ case Intrinsic::ppc_altivec_vmuleuh: // llvm.ppc.altivec.vmuleuh
+ case Intrinsic::ppc_altivec_vmulosh: // llvm.ppc.altivec.vmulosh
+ case Intrinsic::ppc_altivec_vmulouh: // llvm.ppc.altivec.vmulouh
+ case Intrinsic::spu_si_mpy: // llvm.spu.si.mpy
+ case Intrinsic::spu_si_mpyhh: // llvm.spu.si.mpyhh
+ case Intrinsic::spu_si_mpyhha: // llvm.spu.si.mpyhha
+ case Intrinsic::spu_si_mpyhhau: // llvm.spu.si.mpyhhau
+ case Intrinsic::spu_si_mpyhhu: // llvm.spu.si.mpyhhu
+ case Intrinsic::spu_si_mpys: // llvm.spu.si.mpys
+ case Intrinsic::spu_si_mpyu: // llvm.spu.si.mpyu
+ case Intrinsic::x86_sse2_pmadd_wd: // llvm.x86.sse2.pmadd.wd
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::ppc_altivec_vmsumshm: // llvm.ppc.altivec.vmsumshm
+ case Intrinsic::ppc_altivec_vmsumshs: // llvm.ppc.altivec.vmsumshs
+ case Intrinsic::ppc_altivec_vmsumuhm: // llvm.ppc.altivec.vmsumuhm
+ case Intrinsic::ppc_altivec_vmsumuhs: // llvm.ppc.altivec.vmsumuhs
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::spu_si_mpya: // llvm.spu.si.mpya
+ ResultTy = VectorType::get(IntegerType::get(Context, 32), 4);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::ppc_altivec_mfvscr: // llvm.ppc.altivec.mfvscr
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ break;
+ case Intrinsic::ppc_altivec_lvehx: // llvm.ppc.altivec.lvehx
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::ppc_altivec_vupkhsb: // llvm.ppc.altivec.vupkhsb
+ case Intrinsic::ppc_altivec_vupklsb: // llvm.ppc.altivec.vupklsb
+ case Intrinsic::x86_sse41_pmovsxbw: // llvm.x86.sse41.pmovsxbw
+ case Intrinsic::x86_sse41_pmovzxbw: // llvm.x86.sse41.pmovzxbw
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::ppc_altivec_vmulesb: // llvm.ppc.altivec.vmulesb
+ case Intrinsic::ppc_altivec_vmuleub: // llvm.ppc.altivec.vmuleub
+ case Intrinsic::ppc_altivec_vmulosb: // llvm.ppc.altivec.vmulosb
+ case Intrinsic::ppc_altivec_vmuloub: // llvm.ppc.altivec.vmuloub
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::ppc_altivec_vpkpx: // llvm.ppc.altivec.vpkpx
+ case Intrinsic::ppc_altivec_vpkswus: // llvm.ppc.altivec.vpkswus
+ case Intrinsic::ppc_altivec_vpkuwus: // llvm.ppc.altivec.vpkuwus
+ case Intrinsic::x86_sse2_packssdw_128: // llvm.x86.sse2.packssdw.128
+ case Intrinsic::x86_sse41_packusdw: // llvm.x86.sse41.packusdw
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::x86_sse41_phminposuw: // llvm.x86.sse41.phminposuw
+ case Intrinsic::x86_ssse3_pabs_w_128: // llvm.x86.ssse3.pabs.w.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::spu_si_ahi: // llvm.spu.si.ahi
+ case Intrinsic::spu_si_andhi: // llvm.spu.si.andhi
+ case Intrinsic::spu_si_ceqhi: // llvm.spu.si.ceqhi
+ case Intrinsic::spu_si_cgthi: // llvm.spu.si.cgthi
+ case Intrinsic::spu_si_clgthi: // llvm.spu.si.clgthi
+ case Intrinsic::spu_si_fsmbi: // llvm.spu.si.fsmbi
+ case Intrinsic::spu_si_orhi: // llvm.spu.si.orhi
+ case Intrinsic::spu_si_sfhi: // llvm.spu.si.sfhi
+ case Intrinsic::spu_si_xorhi: // llvm.spu.si.xorhi
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(IntegerType::get(Context, 16));
+ break;
+ case Intrinsic::spu_si_shlqbi: // llvm.spu.si.shlqbi
+ case Intrinsic::spu_si_shlqby: // llvm.spu.si.shlqby
+ case Intrinsic::x86_sse2_pslli_w: // llvm.x86.sse2.pslli.w
+ case Intrinsic::x86_sse2_psrai_w: // llvm.x86.sse2.psrai.w
+ case Intrinsic::x86_sse2_psrli_w: // llvm.x86.sse2.psrli.w
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::ppc_altivec_vaddshs: // llvm.ppc.altivec.vaddshs
+ case Intrinsic::ppc_altivec_vadduhs: // llvm.ppc.altivec.vadduhs
+ case Intrinsic::ppc_altivec_vavgsh: // llvm.ppc.altivec.vavgsh
+ case Intrinsic::ppc_altivec_vavguh: // llvm.ppc.altivec.vavguh
+ case Intrinsic::ppc_altivec_vcmpequh: // llvm.ppc.altivec.vcmpequh
+ case Intrinsic::ppc_altivec_vcmpgtsh: // llvm.ppc.altivec.vcmpgtsh
+ case Intrinsic::ppc_altivec_vcmpgtuh: // llvm.ppc.altivec.vcmpgtuh
+ case Intrinsic::ppc_altivec_vmaxsh: // llvm.ppc.altivec.vmaxsh
+ case Intrinsic::ppc_altivec_vmaxuh: // llvm.ppc.altivec.vmaxuh
+ case Intrinsic::ppc_altivec_vminsh: // llvm.ppc.altivec.vminsh
+ case Intrinsic::ppc_altivec_vminuh: // llvm.ppc.altivec.vminuh
+ case Intrinsic::ppc_altivec_vrlh: // llvm.ppc.altivec.vrlh
+ case Intrinsic::ppc_altivec_vslh: // llvm.ppc.altivec.vslh
+ case Intrinsic::ppc_altivec_vsrah: // llvm.ppc.altivec.vsrah
+ case Intrinsic::ppc_altivec_vsrh: // llvm.ppc.altivec.vsrh
+ case Intrinsic::ppc_altivec_vsubshs: // llvm.ppc.altivec.vsubshs
+ case Intrinsic::ppc_altivec_vsubuhs: // llvm.ppc.altivec.vsubuhs
+ case Intrinsic::spu_si_ah: // llvm.spu.si.ah
+ case Intrinsic::spu_si_ceqh: // llvm.spu.si.ceqh
+ case Intrinsic::spu_si_cgth: // llvm.spu.si.cgth
+ case Intrinsic::spu_si_clgth: // llvm.spu.si.clgth
+ case Intrinsic::spu_si_sfh: // llvm.spu.si.sfh
+ case Intrinsic::x86_sse2_padds_w: // llvm.x86.sse2.padds.w
+ case Intrinsic::x86_sse2_paddus_w: // llvm.x86.sse2.paddus.w
+ case Intrinsic::x86_sse2_pavg_w: // llvm.x86.sse2.pavg.w
+ case Intrinsic::x86_sse2_pcmpeq_w: // llvm.x86.sse2.pcmpeq.w
+ case Intrinsic::x86_sse2_pcmpgt_w: // llvm.x86.sse2.pcmpgt.w
+ case Intrinsic::x86_sse2_pmaxs_w: // llvm.x86.sse2.pmaxs.w
+ case Intrinsic::x86_sse2_pmins_w: // llvm.x86.sse2.pmins.w
+ case Intrinsic::x86_sse2_pmulh_w: // llvm.x86.sse2.pmulh.w
+ case Intrinsic::x86_sse2_pmulhu_w: // llvm.x86.sse2.pmulhu.w
+ case Intrinsic::x86_sse2_psll_w: // llvm.x86.sse2.psll.w
+ case Intrinsic::x86_sse2_psra_w: // llvm.x86.sse2.psra.w
+ case Intrinsic::x86_sse2_psrl_w: // llvm.x86.sse2.psrl.w
+ case Intrinsic::x86_sse2_psubs_w: // llvm.x86.sse2.psubs.w
+ case Intrinsic::x86_sse2_psubus_w: // llvm.x86.sse2.psubus.w
+ case Intrinsic::x86_sse41_pmaxuw: // llvm.x86.sse41.pmaxuw
+ case Intrinsic::x86_sse41_pminuw: // llvm.x86.sse41.pminuw
+ case Intrinsic::x86_ssse3_phadd_w_128: // llvm.x86.ssse3.phadd.w.128
+ case Intrinsic::x86_ssse3_phsub_sw_128: // llvm.x86.ssse3.phsub.sw.128
+ case Intrinsic::x86_ssse3_phsub_w_128: // llvm.x86.ssse3.phsub.w.128
+ case Intrinsic::x86_ssse3_pmadd_ub_sw_128: // llvm.x86.ssse3.pmadd.ub.sw.128
+ case Intrinsic::x86_ssse3_pmul_hr_sw_128: // llvm.x86.ssse3.pmul.hr.sw.128
+ case Intrinsic::x86_ssse3_psign_w_128: // llvm.x86.ssse3.psign.w.128
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::x86_sse41_pblendw: // llvm.x86.sse41.pblendw
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::ppc_altivec_vmhaddshs: // llvm.ppc.altivec.vmhaddshs
+ case Intrinsic::ppc_altivec_vmhraddshs: // llvm.ppc.altivec.vmhraddshs
+ case Intrinsic::ppc_altivec_vmladduhm: // llvm.ppc.altivec.vmladduhm
+ ResultTy = VectorType::get(IntegerType::get(Context, 16), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ break;
+ case Intrinsic::x86_mmx_packsswb: // llvm.x86.mmx.packsswb
+ case Intrinsic::x86_mmx_packuswb: // llvm.x86.mmx.packuswb
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 4));
+ break;
+ case Intrinsic::x86_ssse3_pabs_b: // llvm.x86.ssse3.pabs.b
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::arm_neon_vtbl1: // llvm.arm.neon.vtbl1
+ case Intrinsic::x86_mmx_padds_b: // llvm.x86.mmx.padds.b
+ case Intrinsic::x86_mmx_paddus_b: // llvm.x86.mmx.paddus.b
+ case Intrinsic::x86_mmx_pavg_b: // llvm.x86.mmx.pavg.b
+ case Intrinsic::x86_mmx_pcmpeq_b: // llvm.x86.mmx.pcmpeq.b
+ case Intrinsic::x86_mmx_pcmpgt_b: // llvm.x86.mmx.pcmpgt.b
+ case Intrinsic::x86_mmx_pmaxu_b: // llvm.x86.mmx.pmaxu.b
+ case Intrinsic::x86_mmx_pminu_b: // llvm.x86.mmx.pminu.b
+ case Intrinsic::x86_mmx_psubs_b: // llvm.x86.mmx.psubs.b
+ case Intrinsic::x86_mmx_psubus_b: // llvm.x86.mmx.psubus.b
+ case Intrinsic::x86_ssse3_pshuf_b: // llvm.x86.ssse3.pshuf.b
+ case Intrinsic::x86_ssse3_psign_b: // llvm.x86.ssse3.psign.b
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::arm_neon_vtbl2: // llvm.arm.neon.vtbl2
+ case Intrinsic::arm_neon_vtbx1: // llvm.arm.neon.vtbx1
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::arm_neon_vtbl3: // llvm.arm.neon.vtbl3
+ case Intrinsic::arm_neon_vtbx2: // llvm.arm.neon.vtbx2
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::arm_neon_vtbl4: // llvm.arm.neon.vtbl4
+ case Intrinsic::arm_neon_vtbx3: // llvm.arm.neon.vtbx3
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::arm_neon_vtbx4: // llvm.arm.neon.vtbx4
+ ResultTy = VectorType::get(IntegerType::get(Context, 8), 8);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ break;
+ case Intrinsic::eh_unwind_init: // llvm.eh.unwind.init
+ case Intrinsic::ppc_altivec_dssall: // llvm.ppc.altivec.dssall
+ case Intrinsic::ppc_sync: // llvm.ppc.sync
+ case Intrinsic::trap: // llvm.trap
+ case Intrinsic::x86_mmx_emms: // llvm.x86.mmx.emms
+ case Intrinsic::x86_mmx_femms: // llvm.x86.mmx.femms
+ case Intrinsic::x86_sse2_lfence: // llvm.x86.sse2.lfence
+ case Intrinsic::x86_sse2_mfence: // llvm.x86.sse2.mfence
+ case Intrinsic::x86_sse_sfence: // llvm.x86.sse.sfence
+ ResultTy = Type::getVoidTy(Context);
+ break;
+ case Intrinsic::invariant_end: // llvm.invariant.end
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(StructType::get(Context)));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::dbg_declare: // llvm.dbg.declare
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(StructType::get(Context)));
+ ArgTys.push_back(Type::getMetadataTy(Context));
+ break;
+ case Intrinsic::memory_barrier: // llvm.memory.barrier
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(IntegerType::get(Context, 1));
+ ArgTys.push_back(IntegerType::get(Context, 1));
+ ArgTys.push_back(IntegerType::get(Context, 1));
+ ArgTys.push_back(IntegerType::get(Context, 1));
+ ArgTys.push_back(IntegerType::get(Context, 1));
+ break;
+ case Intrinsic::pcmarker: // llvm.pcmarker
+ case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::dbg_stoppoint: // llvm.dbg.stoppoint
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(Type::getMetadataTy(Context));
+ break;
+ case Intrinsic::eh_return_i32: // llvm.eh.return.i32
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::eh_return_i64: // llvm.eh.return.i64
+ case Intrinsic::lifetime_end: // llvm.lifetime.end
+ case Intrinsic::lifetime_start: // llvm.lifetime.start
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::dbg_func_start: // llvm.dbg.func.start
+ case Intrinsic::dbg_region_end: // llvm.dbg.region.end
+ case Intrinsic::dbg_region_start: // llvm.dbg.region.start
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(Type::getMetadataTy(Context));
+ break;
+ case Intrinsic::dbg_value: // llvm.dbg.value
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(Type::getMetadataTy(Context));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ ArgTys.push_back(Type::getMetadataTy(Context));
+ break;
+ case Intrinsic::eh_sjlj_longjmp: // llvm.eh.sjlj.longjmp
+ case Intrinsic::ppc_dcba: // llvm.ppc.dcba
+ case Intrinsic::ppc_dcbf: // llvm.ppc.dcbf
+ case Intrinsic::ppc_dcbi: // llvm.ppc.dcbi
+ case Intrinsic::ppc_dcbst: // llvm.ppc.dcbst
+ case Intrinsic::ppc_dcbt: // llvm.ppc.dcbt
+ case Intrinsic::ppc_dcbtst: // llvm.ppc.dcbtst
+ case Intrinsic::ppc_dcbz: // llvm.ppc.dcbz
+ case Intrinsic::ppc_dcbzl: // llvm.ppc.dcbzl
+ case Intrinsic::stackrestore: // llvm.stackrestore
+ case Intrinsic::vaend: // llvm.va_end
+ case Intrinsic::vastart: // llvm.va_start
+ case Intrinsic::x86_sse2_clflush: // llvm.x86.sse2.clflush
+ case Intrinsic::x86_sse_ldmxcsr: // llvm.x86.sse.ldmxcsr
+ case Intrinsic::x86_sse_stmxcsr: // llvm.x86.sse.stmxcsr
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::arm_neon_vst1: // llvm.arm.neon.vst1
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vst2: // llvm.arm.neon.vst2
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vst3: // llvm.arm.neon.vst3
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vst4: // llvm.arm.neon.vst4
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ break;
+ case Intrinsic::arm_neon_vst2lane: // llvm.arm.neon.vst2lane
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::arm_neon_vst3lane: // llvm.arm.neon.vst3lane
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::arm_neon_vst4lane: // llvm.arm.neon.vst4lane
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::longjmp: // llvm.longjmp
+ case Intrinsic::siglongjmp: // llvm.siglongjmp
+ case Intrinsic::x86_sse2_movnt_i: // llvm.x86.sse2.movnt.i
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::ppc_altivec_dst: // llvm.ppc.altivec.dst
+ case Intrinsic::ppc_altivec_dstst: // llvm.ppc.altivec.dstst
+ case Intrinsic::ppc_altivec_dststt: // llvm.ppc.altivec.dststt
+ case Intrinsic::ppc_altivec_dstt: // llvm.ppc.altivec.dstt
+ case Intrinsic::prefetch: // llvm.prefetch
+ case Intrinsic::x86_sse3_monitor: // llvm.x86.sse3.monitor
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::memset: // llvm.memset
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 8));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::vacopy: // llvm.va_copy
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::memcpy: // llvm.memcpy
+ case Intrinsic::memmove: // llvm.memmove
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(Tys[0]);
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::var_annotation: // llvm.var.annotation
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(IntegerType::get(Context, 32));
+ break;
+ case Intrinsic::gcwrite: // llvm.gcwrite
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerType::get(Context, 8))));
+ break;
+ case Intrinsic::stackprotector: // llvm.stackprotector
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerType::get(Context, 8))));
+ break;
+ case Intrinsic::x86_sse2_storeu_dq: // llvm.x86.sse2.storeu.dq
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ break;
+ case Intrinsic::x86_mmx_movnt_dq: // llvm.x86.mmx.movnt.dq
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 1));
+ break;
+ case Intrinsic::x86_sse2_movnt_pd: // llvm.x86.sse2.movnt.pd
+ case Intrinsic::x86_sse2_storeu_pd: // llvm.x86.sse2.storeu.pd
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(VectorType::get(Type::getDoubleTy(Context), 2));
+ break;
+ case Intrinsic::x86_sse2_movnt_dq: // llvm.x86.sse2.movnt.dq
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 64), 2));
+ break;
+ case Intrinsic::x86_sse_movnt_ps: // llvm.x86.sse.movnt.ps
+ case Intrinsic::x86_sse_storeu_ps: // llvm.x86.sse.storeu.ps
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(VectorType::get(Type::getFloatTy(Context), 4));
+ break;
+ case Intrinsic::x86_sse2_storel_dq: // llvm.x86.sse2.storel.dq
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::gcroot: // llvm.gcroot
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(PointerType::getUnqual(PointerType::getUnqual(IntegerType::get(Context, 8))));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::ppc_altivec_stvebx: // llvm.ppc.altivec.stvebx
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_sse2_maskmov_dqu: // llvm.x86.sse2.maskmov.dqu
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 16));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::ppc_altivec_mtvscr: // llvm.ppc.altivec.mtvscr
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ break;
+ case Intrinsic::ppc_altivec_stvewx: // llvm.ppc.altivec.stvewx
+ case Intrinsic::ppc_altivec_stvx: // llvm.ppc.altivec.stvx
+ case Intrinsic::ppc_altivec_stvxl: // llvm.ppc.altivec.stvxl
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 32), 4));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::ppc_altivec_stvehx: // llvm.ppc.altivec.stvehx
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 16), 8));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ case Intrinsic::x86_mmx_maskmovq: // llvm.x86.mmx.maskmovq
+ ResultTy = Type::getVoidTy(Context);
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(VectorType::get(IntegerType::get(Context, 8), 8));
+ ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
+ break;
+ }
+#endif
+
+// Add parameter attributes that are not common to all intrinsics.
+#ifdef GET_INTRINSIC_ATTRIBUTES
+AttrListPtr Intrinsic::getAttributes(ID id) { // No intrinsic can throw exceptions.
+ Attributes Attr = Attribute::NoUnwind;
+ switch (id) {
+ default: break;
+ case Intrinsic::alpha_umulh:
+ case Intrinsic::arm_neon_vabals:
+ case Intrinsic::arm_neon_vabalu:
+ case Intrinsic::arm_neon_vabas:
+ case Intrinsic::arm_neon_vabau:
+ case Intrinsic::arm_neon_vabdls:
+ case Intrinsic::arm_neon_vabdlu:
+ case Intrinsic::arm_neon_vabds:
+ case Intrinsic::arm_neon_vabdu:
+ case Intrinsic::arm_neon_vabs:
+ case Intrinsic::arm_neon_vacged:
+ case Intrinsic::arm_neon_vacgeq:
+ case Intrinsic::arm_neon_vacgtd:
+ case Intrinsic::arm_neon_vacgtq:
+ case Intrinsic::arm_neon_vaddhn:
+ case Intrinsic::arm_neon_vaddls:
+ case Intrinsic::arm_neon_vaddlu:
+ case Intrinsic::arm_neon_vaddws:
+ case Intrinsic::arm_neon_vaddwu:
+ case Intrinsic::arm_neon_vcls:
+ case Intrinsic::arm_neon_vclz:
+ case Intrinsic::arm_neon_vcnt:
+ case Intrinsic::arm_neon_vcvtfp2fxs:
+ case Intrinsic::arm_neon_vcvtfp2fxu:
+ case Intrinsic::arm_neon_vcvtfxs2fp:
+ case Intrinsic::arm_neon_vcvtfxu2fp:
+ case Intrinsic::arm_neon_vhadds:
+ case Intrinsic::arm_neon_vhaddu:
+ case Intrinsic::arm_neon_vhsubs:
+ case Intrinsic::arm_neon_vhsubu:
+ case Intrinsic::arm_neon_vmaxs:
+ case Intrinsic::arm_neon_vmaxu:
+ case Intrinsic::arm_neon_vmins:
+ case Intrinsic::arm_neon_vminu:
+ case Intrinsic::arm_neon_vmlals:
+ case Intrinsic::arm_neon_vmlalu:
+ case Intrinsic::arm_neon_vmlsls:
+ case Intrinsic::arm_neon_vmlslu:
+ case Intrinsic::arm_neon_vmovls:
+ case Intrinsic::arm_neon_vmovlu:
+ case Intrinsic::arm_neon_vmovn:
+ case Intrinsic::arm_neon_vmullp:
+ case Intrinsic::arm_neon_vmulls:
+ case Intrinsic::arm_neon_vmullu:
+ case Intrinsic::arm_neon_vmulp:
+ case Intrinsic::arm_neon_vpadals:
+ case Intrinsic::arm_neon_vpadalu:
+ case Intrinsic::arm_neon_vpadd:
+ case Intrinsic::arm_neon_vpaddls:
+ case Intrinsic::arm_neon_vpaddlu:
+ case Intrinsic::arm_neon_vpmaxs:
+ case Intrinsic::arm_neon_vpmaxu:
+ case Intrinsic::arm_neon_vpmins:
+ case Intrinsic::arm_neon_vpminu:
+ case Intrinsic::arm_neon_vqabs:
+ case Intrinsic::arm_neon_vqadds:
+ case Intrinsic::arm_neon_vqaddu:
+ case Intrinsic::arm_neon_vqdmlal:
+ case Intrinsic::arm_neon_vqdmlsl:
+ case Intrinsic::arm_neon_vqdmulh:
+ case Intrinsic::arm_neon_vqdmull:
+ case Intrinsic::arm_neon_vqmovns:
+ case Intrinsic::arm_neon_vqmovnsu:
+ case Intrinsic::arm_neon_vqmovnu:
+ case Intrinsic::arm_neon_vqneg:
+ case Intrinsic::arm_neon_vqrdmulh:
+ case Intrinsic::arm_neon_vqrshiftns:
+ case Intrinsic::arm_neon_vqrshiftnsu:
+ case Intrinsic::arm_neon_vqrshiftnu:
+ case Intrinsic::arm_neon_vqrshifts:
+ case Intrinsic::arm_neon_vqrshiftu:
+ case Intrinsic::arm_neon_vqshiftns:
+ case Intrinsic::arm_neon_vqshiftnsu:
+ case Intrinsic::arm_neon_vqshiftnu:
+ case Intrinsic::arm_neon_vqshifts:
+ case Intrinsic::arm_neon_vqshiftsu:
+ case Intrinsic::arm_neon_vqshiftu:
+ case Intrinsic::arm_neon_vqsubs:
+ case Intrinsic::arm_neon_vqsubu:
+ case Intrinsic::arm_neon_vraddhn:
+ case Intrinsic::arm_neon_vrecpe:
+ case Intrinsic::arm_neon_vrecps:
+ case Intrinsic::arm_neon_vrhadds:
+ case Intrinsic::arm_neon_vrhaddu:
+ case Intrinsic::arm_neon_vrshiftn:
+ case Intrinsic::arm_neon_vrshifts:
+ case Intrinsic::arm_neon_vrshiftu:
+ case Intrinsic::arm_neon_vrsqrte:
+ case Intrinsic::arm_neon_vrsqrts:
+ case Intrinsic::arm_neon_vrsubhn:
+ case Intrinsic::arm_neon_vshiftins:
+ case Intrinsic::arm_neon_vshiftls:
+ case Intrinsic::arm_neon_vshiftlu:
+ case Intrinsic::arm_neon_vshiftn:
+ case Intrinsic::arm_neon_vshifts:
+ case Intrinsic::arm_neon_vshiftu:
+ case Intrinsic::arm_neon_vsubhn:
+ case Intrinsic::arm_neon_vsubls:
+ case Intrinsic::arm_neon_vsublu:
+ case Intrinsic::arm_neon_vsubws:
+ case Intrinsic::arm_neon_vsubwu:
+ case Intrinsic::arm_neon_vtbl1:
+ case Intrinsic::arm_neon_vtbl2:
+ case Intrinsic::arm_neon_vtbl3:
+ case Intrinsic::arm_neon_vtbl4:
+ case Intrinsic::arm_neon_vtbx1:
+ case Intrinsic::arm_neon_vtbx2:
+ case Intrinsic::arm_neon_vtbx3:
+ case Intrinsic::arm_neon_vtbx4:
+ case Intrinsic::arm_thread_pointer:
+ case Intrinsic::bswap:
+ case Intrinsic::ctlz:
+ case Intrinsic::ctpop:
+ case Intrinsic::cttz:
+ case Intrinsic::dbg_declare:
+ case Intrinsic::dbg_func_start:
+ case Intrinsic::dbg_region_end:
+ case Intrinsic::dbg_region_start:
+ case Intrinsic::dbg_stoppoint:
+ case Intrinsic::dbg_value:
+ case Intrinsic::eh_sjlj_longjmp:
+ case Intrinsic::eh_sjlj_lsda:
+ case Intrinsic::eh_sjlj_setjmp:
+ case Intrinsic::frameaddress:
+ case Intrinsic::ppc_altivec_lvsl:
+ case Intrinsic::ppc_altivec_lvsr:
+ case Intrinsic::ppc_altivec_vaddcuw:
+ case Intrinsic::ppc_altivec_vaddsbs:
+ case Intrinsic::ppc_altivec_vaddshs:
+ case Intrinsic::ppc_altivec_vaddsws:
+ case Intrinsic::ppc_altivec_vaddubs:
+ case Intrinsic::ppc_altivec_vadduhs:
+ case Intrinsic::ppc_altivec_vadduws:
+ case Intrinsic::ppc_altivec_vavgsb:
+ case Intrinsic::ppc_altivec_vavgsh:
+ case Intrinsic::ppc_altivec_vavgsw:
+ case Intrinsic::ppc_altivec_vavgub:
+ case Intrinsic::ppc_altivec_vavguh:
+ case Intrinsic::ppc_altivec_vavguw:
+ case Intrinsic::ppc_altivec_vcfsx:
+ case Intrinsic::ppc_altivec_vcfux:
+ case Intrinsic::ppc_altivec_vcmpbfp:
+ case Intrinsic::ppc_altivec_vcmpbfp_p:
+ case Intrinsic::ppc_altivec_vcmpeqfp:
+ case Intrinsic::ppc_altivec_vcmpeqfp_p:
+ case Intrinsic::ppc_altivec_vcmpequb:
+ case Intrinsic::ppc_altivec_vcmpequb_p:
+ case Intrinsic::ppc_altivec_vcmpequh:
+ case Intrinsic::ppc_altivec_vcmpequh_p:
+ case Intrinsic::ppc_altivec_vcmpequw:
+ case Intrinsic::ppc_altivec_vcmpequw_p:
+ case Intrinsic::ppc_altivec_vcmpgefp:
+ case Intrinsic::ppc_altivec_vcmpgefp_p:
+ case Intrinsic::ppc_altivec_vcmpgtfp:
+ case Intrinsic::ppc_altivec_vcmpgtfp_p:
+ case Intrinsic::ppc_altivec_vcmpgtsb:
+ case Intrinsic::ppc_altivec_vcmpgtsb_p:
+ case Intrinsic::ppc_altivec_vcmpgtsh:
+ case Intrinsic::ppc_altivec_vcmpgtsh_p:
+ case Intrinsic::ppc_altivec_vcmpgtsw:
+ case Intrinsic::ppc_altivec_vcmpgtsw_p:
+ case Intrinsic::ppc_altivec_vcmpgtub:
+ case Intrinsic::ppc_altivec_vcmpgtub_p:
+ case Intrinsic::ppc_altivec_vcmpgtuh:
+ case Intrinsic::ppc_altivec_vcmpgtuh_p:
+ case Intrinsic::ppc_altivec_vcmpgtuw:
+ case Intrinsic::ppc_altivec_vcmpgtuw_p:
+ case Intrinsic::ppc_altivec_vctsxs:
+ case Intrinsic::ppc_altivec_vctuxs:
+ case Intrinsic::ppc_altivec_vexptefp:
+ case Intrinsic::ppc_altivec_vlogefp:
+ case Intrinsic::ppc_altivec_vmaddfp:
+ case Intrinsic::ppc_altivec_vmaxfp:
+ case Intrinsic::ppc_altivec_vmaxsb:
+ case Intrinsic::ppc_altivec_vmaxsh:
+ case Intrinsic::ppc_altivec_vmaxsw:
+ case Intrinsic::ppc_altivec_vmaxub:
+ case Intrinsic::ppc_altivec_vmaxuh:
+ case Intrinsic::ppc_altivec_vmaxuw:
+ case Intrinsic::ppc_altivec_vmhaddshs:
+ case Intrinsic::ppc_altivec_vmhraddshs:
+ case Intrinsic::ppc_altivec_vminfp:
+ case Intrinsic::ppc_altivec_vminsb:
+ case Intrinsic::ppc_altivec_vminsh:
+ case Intrinsic::ppc_altivec_vminsw:
+ case Intrinsic::ppc_altivec_vminub:
+ case Intrinsic::ppc_altivec_vminuh:
+ case Intrinsic::ppc_altivec_vminuw:
+ case Intrinsic::ppc_altivec_vmladduhm:
+ case Intrinsic::ppc_altivec_vmsummbm:
+ case Intrinsic::ppc_altivec_vmsumshm:
+ case Intrinsic::ppc_altivec_vmsumshs:
+ case Intrinsic::ppc_altivec_vmsumubm:
+ case Intrinsic::ppc_altivec_vmsumuhm:
+ case Intrinsic::ppc_altivec_vmsumuhs:
+ case Intrinsic::ppc_altivec_vmulesb:
+ case Intrinsic::ppc_altivec_vmulesh:
+ case Intrinsic::ppc_altivec_vmuleub:
+ case Intrinsic::ppc_altivec_vmuleuh:
+ case Intrinsic::ppc_altivec_vmulosb:
+ case Intrinsic::ppc_altivec_vmulosh:
+ case Intrinsic::ppc_altivec_vmuloub:
+ case Intrinsic::ppc_altivec_vmulouh:
+ case Intrinsic::ppc_altivec_vnmsubfp:
+ case Intrinsic::ppc_altivec_vperm:
+ case Intrinsic::ppc_altivec_vpkpx:
+ case Intrinsic::ppc_altivec_vpkshss:
+ case Intrinsic::ppc_altivec_vpkshus:
+ case Intrinsic::ppc_altivec_vpkswss:
+ case Intrinsic::ppc_altivec_vpkswus:
+ case Intrinsic::ppc_altivec_vpkuhus:
+ case Intrinsic::ppc_altivec_vpkuwus:
+ case Intrinsic::ppc_altivec_vrefp:
+ case Intrinsic::ppc_altivec_vrfim:
+ case Intrinsic::ppc_altivec_vrfin:
+ case Intrinsic::ppc_altivec_vrfip:
+ case Intrinsic::ppc_altivec_vrfiz:
+ case Intrinsic::ppc_altivec_vrlb:
+ case Intrinsic::ppc_altivec_vrlh:
+ case Intrinsic::ppc_altivec_vrlw:
+ case Intrinsic::ppc_altivec_vrsqrtefp:
+ case Intrinsic::ppc_altivec_vsel:
+ case Intrinsic::ppc_altivec_vsl:
+ case Intrinsic::ppc_altivec_vslb:
+ case Intrinsic::ppc_altivec_vslh:
+ case Intrinsic::ppc_altivec_vslo:
+ case Intrinsic::ppc_altivec_vslw:
+ case Intrinsic::ppc_altivec_vsr:
+ case Intrinsic::ppc_altivec_vsrab:
+ case Intrinsic::ppc_altivec_vsrah:
+ case Intrinsic::ppc_altivec_vsraw:
+ case Intrinsic::ppc_altivec_vsrb:
+ case Intrinsic::ppc_altivec_vsrh:
+ case Intrinsic::ppc_altivec_vsro:
+ case Intrinsic::ppc_altivec_vsrw:
+ case Intrinsic::ppc_altivec_vsubcuw:
+ case Intrinsic::ppc_altivec_vsubsbs:
+ case Intrinsic::ppc_altivec_vsubshs:
+ case Intrinsic::ppc_altivec_vsubsws:
+ case Intrinsic::ppc_altivec_vsububs:
+ case Intrinsic::ppc_altivec_vsubuhs:
+ case Intrinsic::ppc_altivec_vsubuws:
+ case Intrinsic::ppc_altivec_vsum2sws:
+ case Intrinsic::ppc_altivec_vsum4sbs:
+ case Intrinsic::ppc_altivec_vsum4shs:
+ case Intrinsic::ppc_altivec_vsum4ubs:
+ case Intrinsic::ppc_altivec_vsumsws:
+ case Intrinsic::ppc_altivec_vupkhpx:
+ case Intrinsic::ppc_altivec_vupkhsb:
+ case Intrinsic::ppc_altivec_vupkhsh:
+ case Intrinsic::ppc_altivec_vupklpx:
+ case Intrinsic::ppc_altivec_vupklsb:
+ case Intrinsic::ppc_altivec_vupklsh:
+ case Intrinsic::returnaddress:
+ case Intrinsic::sadd_with_overflow:
+ case Intrinsic::smul_with_overflow:
+ case Intrinsic::spu_si_a:
+ case Intrinsic::spu_si_addx:
+ case Intrinsic::spu_si_ah:
+ case Intrinsic::spu_si_ahi:
+ case Intrinsic::spu_si_ai:
+ case Intrinsic::spu_si_and:
+ case Intrinsic::spu_si_andbi:
+ case Intrinsic::spu_si_andc:
+ case Intrinsic::spu_si_andhi:
+ case Intrinsic::spu_si_andi:
+ case Intrinsic::spu_si_bg:
+ case Intrinsic::spu_si_bgx:
+ case Intrinsic::spu_si_ceq:
+ case Intrinsic::spu_si_ceqb:
+ case Intrinsic::spu_si_ceqbi:
+ case Intrinsic::spu_si_ceqh:
+ case Intrinsic::spu_si_ceqhi:
+ case Intrinsic::spu_si_ceqi:
+ case Intrinsic::spu_si_cg:
+ case Intrinsic::spu_si_cgt:
+ case Intrinsic::spu_si_cgtb:
+ case Intrinsic::spu_si_cgtbi:
+ case Intrinsic::spu_si_cgth:
+ case Intrinsic::spu_si_cgthi:
+ case Intrinsic::spu_si_cgti:
+ case Intrinsic::spu_si_cgx:
+ case Intrinsic::spu_si_clgt:
+ case Intrinsic::spu_si_clgtb:
+ case Intrinsic::spu_si_clgtbi:
+ case Intrinsic::spu_si_clgth:
+ case Intrinsic::spu_si_clgthi:
+ case Intrinsic::spu_si_clgti:
+ case Intrinsic::spu_si_dfa:
+ case Intrinsic::spu_si_dfm:
+ case Intrinsic::spu_si_dfma:
+ case Intrinsic::spu_si_dfms:
+ case Intrinsic::spu_si_dfnma:
+ case Intrinsic::spu_si_dfnms:
+ case Intrinsic::spu_si_dfs:
+ case Intrinsic::spu_si_fa:
+ case Intrinsic::spu_si_fceq:
+ case Intrinsic::spu_si_fcgt:
+ case Intrinsic::spu_si_fcmeq:
+ case Intrinsic::spu_si_fcmgt:
+ case Intrinsic::spu_si_fm:
+ case Intrinsic::spu_si_fma:
+ case Intrinsic::spu_si_fms:
+ case Intrinsic::spu_si_fnms:
+ case Intrinsic::spu_si_fs:
+ case Intrinsic::spu_si_fsmbi:
+ case Intrinsic::spu_si_mpy:
+ case Intrinsic::spu_si_mpya:
+ case Intrinsic::spu_si_mpyh:
+ case Intrinsic::spu_si_mpyhh:
+ case Intrinsic::spu_si_mpyhha:
+ case Intrinsic::spu_si_mpyhhau:
+ case Intrinsic::spu_si_mpyhhu:
+ case Intrinsic::spu_si_mpyi:
+ case Intrinsic::spu_si_mpys:
+ case Intrinsic::spu_si_mpyu:
+ case Intrinsic::spu_si_mpyui:
+ case Intrinsic::spu_si_nand:
+ case Intrinsic::spu_si_nor:
+ case Intrinsic::spu_si_or:
+ case Intrinsic::spu_si_orbi:
+ case Intrinsic::spu_si_orc:
+ case Intrinsic::spu_si_orhi:
+ case Intrinsic::spu_si_ori:
+ case Intrinsic::spu_si_sf:
+ case Intrinsic::spu_si_sfh:
+ case Intrinsic::spu_si_sfhi:
+ case Intrinsic::spu_si_sfi:
+ case Intrinsic::spu_si_sfx:
+ case Intrinsic::spu_si_shli:
+ case Intrinsic::spu_si_shlqbi:
+ case Intrinsic::spu_si_shlqbii:
+ case Intrinsic::spu_si_shlqby:
+ case Intrinsic::spu_si_shlqbyi:
+ case Intrinsic::spu_si_xor:
+ case Intrinsic::spu_si_xorbi:
+ case Intrinsic::spu_si_xorhi:
+ case Intrinsic::spu_si_xori:
+ case Intrinsic::ssub_with_overflow:
+ case Intrinsic::uadd_with_overflow:
+ case Intrinsic::umul_with_overflow:
+ case Intrinsic::usub_with_overflow:
+ case Intrinsic::x86_mmx_packssdw:
+ case Intrinsic::x86_mmx_packsswb:
+ case Intrinsic::x86_mmx_packuswb:
+ case Intrinsic::x86_mmx_padds_b:
+ case Intrinsic::x86_mmx_padds_w:
+ case Intrinsic::x86_mmx_paddus_b:
+ case Intrinsic::x86_mmx_paddus_w:
+ case Intrinsic::x86_mmx_pavg_b:
+ case Intrinsic::x86_mmx_pavg_w:
+ case Intrinsic::x86_mmx_pcmpeq_b:
+ case Intrinsic::x86_mmx_pcmpeq_d:
+ case Intrinsic::x86_mmx_pcmpeq_w:
+ case Intrinsic::x86_mmx_pcmpgt_b:
+ case Intrinsic::x86_mmx_pcmpgt_d:
+ case Intrinsic::x86_mmx_pcmpgt_w:
+ case Intrinsic::x86_mmx_pmadd_wd:
+ case Intrinsic::x86_mmx_pmaxs_w:
+ case Intrinsic::x86_mmx_pmaxu_b:
+ case Intrinsic::x86_mmx_pmins_w:
+ case Intrinsic::x86_mmx_pminu_b:
+ case Intrinsic::x86_mmx_pmovmskb:
+ case Intrinsic::x86_mmx_pmulh_w:
+ case Intrinsic::x86_mmx_pmulhu_w:
+ case Intrinsic::x86_mmx_pmulu_dq:
+ case Intrinsic::x86_mmx_psad_bw:
+ case Intrinsic::x86_mmx_psll_d:
+ case Intrinsic::x86_mmx_psll_q:
+ case Intrinsic::x86_mmx_psll_w:
+ case Intrinsic::x86_mmx_pslli_d:
+ case Intrinsic::x86_mmx_pslli_q:
+ case Intrinsic::x86_mmx_pslli_w:
+ case Intrinsic::x86_mmx_psra_d:
+ case Intrinsic::x86_mmx_psra_w:
+ case Intrinsic::x86_mmx_psrai_d:
+ case Intrinsic::x86_mmx_psrai_w:
+ case Intrinsic::x86_mmx_psrl_d:
+ case Intrinsic::x86_mmx_psrl_q:
+ case Intrinsic::x86_mmx_psrl_w:
+ case Intrinsic::x86_mmx_psrli_d:
+ case Intrinsic::x86_mmx_psrli_q:
+ case Intrinsic::x86_mmx_psrli_w:
+ case Intrinsic::x86_mmx_psubs_b:
+ case Intrinsic::x86_mmx_psubs_w:
+ case Intrinsic::x86_mmx_psubus_b:
+ case Intrinsic::x86_mmx_psubus_w:
+ case Intrinsic::x86_sse2_add_sd:
+ case Intrinsic::x86_sse2_cmp_pd:
+ case Intrinsic::x86_sse2_cmp_sd:
+ case Intrinsic::x86_sse2_comieq_sd:
+ case Intrinsic::x86_sse2_comige_sd:
+ case Intrinsic::x86_sse2_comigt_sd:
+ case Intrinsic::x86_sse2_comile_sd:
+ case Intrinsic::x86_sse2_comilt_sd:
+ case Intrinsic::x86_sse2_comineq_sd:
+ case Intrinsic::x86_sse2_cvtdq2pd:
+ case Intrinsic::x86_sse2_cvtdq2ps:
+ case Intrinsic::x86_sse2_cvtpd2dq:
+ case Intrinsic::x86_sse2_cvtpd2ps:
+ case Intrinsic::x86_sse2_cvtps2dq:
+ case Intrinsic::x86_sse2_cvtps2pd:
+ case Intrinsic::x86_sse2_cvtsd2si:
+ case Intrinsic::x86_sse2_cvtsd2si64:
+ case Intrinsic::x86_sse2_cvtsd2ss:
+ case Intrinsic::x86_sse2_cvtsi2sd:
+ case Intrinsic::x86_sse2_cvtsi642sd:
+ case Intrinsic::x86_sse2_cvtss2sd:
+ case Intrinsic::x86_sse2_cvttpd2dq:
+ case Intrinsic::x86_sse2_cvttps2dq:
+ case Intrinsic::x86_sse2_cvttsd2si:
+ case Intrinsic::x86_sse2_cvttsd2si64:
+ case Intrinsic::x86_sse2_div_sd:
+ case Intrinsic::x86_sse2_max_pd:
+ case Intrinsic::x86_sse2_max_sd:
+ case Intrinsic::x86_sse2_min_pd:
+ case Intrinsic::x86_sse2_min_sd:
+ case Intrinsic::x86_sse2_movmsk_pd:
+ case Intrinsic::x86_sse2_mul_sd:
+ case Intrinsic::x86_sse2_packssdw_128:
+ case Intrinsic::x86_sse2_packsswb_128:
+ case Intrinsic::x86_sse2_packuswb_128:
+ case Intrinsic::x86_sse2_padds_b:
+ case Intrinsic::x86_sse2_padds_w:
+ case Intrinsic::x86_sse2_paddus_b:
+ case Intrinsic::x86_sse2_paddus_w:
+ case Intrinsic::x86_sse2_pavg_b:
+ case Intrinsic::x86_sse2_pavg_w:
+ case Intrinsic::x86_sse2_pcmpeq_b:
+ case Intrinsic::x86_sse2_pcmpeq_d:
+ case Intrinsic::x86_sse2_pcmpeq_w:
+ case Intrinsic::x86_sse2_pcmpgt_b:
+ case Intrinsic::x86_sse2_pcmpgt_d:
+ case Intrinsic::x86_sse2_pcmpgt_w:
+ case Intrinsic::x86_sse2_pmadd_wd:
+ case Intrinsic::x86_sse2_pmaxs_w:
+ case Intrinsic::x86_sse2_pmaxu_b:
+ case Intrinsic::x86_sse2_pmins_w:
+ case Intrinsic::x86_sse2_pminu_b:
+ case Intrinsic::x86_sse2_pmovmskb_128:
+ case Intrinsic::x86_sse2_pmulh_w:
+ case Intrinsic::x86_sse2_pmulhu_w:
+ case Intrinsic::x86_sse2_pmulu_dq:
+ case Intrinsic::x86_sse2_psad_bw:
+ case Intrinsic::x86_sse2_psll_d:
+ case Intrinsic::x86_sse2_psll_dq:
+ case Intrinsic::x86_sse2_psll_dq_bs:
+ case Intrinsic::x86_sse2_psll_q:
+ case Intrinsic::x86_sse2_psll_w:
+ case Intrinsic::x86_sse2_pslli_d:
+ case Intrinsic::x86_sse2_pslli_q:
+ case Intrinsic::x86_sse2_pslli_w:
+ case Intrinsic::x86_sse2_psra_d:
+ case Intrinsic::x86_sse2_psra_w:
+ case Intrinsic::x86_sse2_psrai_d:
+ case Intrinsic::x86_sse2_psrai_w:
+ case Intrinsic::x86_sse2_psrl_d:
+ case Intrinsic::x86_sse2_psrl_dq:
+ case Intrinsic::x86_sse2_psrl_dq_bs:
+ case Intrinsic::x86_sse2_psrl_q:
+ case Intrinsic::x86_sse2_psrl_w:
+ case Intrinsic::x86_sse2_psrli_d:
+ case Intrinsic::x86_sse2_psrli_q:
+ case Intrinsic::x86_sse2_psrli_w:
+ case Intrinsic::x86_sse2_psubs_b:
+ case Intrinsic::x86_sse2_psubs_w:
+ case Intrinsic::x86_sse2_psubus_b:
+ case Intrinsic::x86_sse2_psubus_w:
+ case Intrinsic::x86_sse2_sqrt_pd:
+ case Intrinsic::x86_sse2_sqrt_sd:
+ case Intrinsic::x86_sse2_sub_sd:
+ case Intrinsic::x86_sse2_ucomieq_sd:
+ case Intrinsic::x86_sse2_ucomige_sd:
+ case Intrinsic::x86_sse2_ucomigt_sd:
+ case Intrinsic::x86_sse2_ucomile_sd:
+ case Intrinsic::x86_sse2_ucomilt_sd:
+ case Intrinsic::x86_sse2_ucomineq_sd:
+ case Intrinsic::x86_sse3_addsub_pd:
+ case Intrinsic::x86_sse3_addsub_ps:
+ case Intrinsic::x86_sse3_hadd_pd:
+ case Intrinsic::x86_sse3_hadd_ps:
+ case Intrinsic::x86_sse3_hsub_pd:
+ case Intrinsic::x86_sse3_hsub_ps:
+ case Intrinsic::x86_sse41_blendpd:
+ case Intrinsic::x86_sse41_blendps:
+ case Intrinsic::x86_sse41_blendvpd:
+ case Intrinsic::x86_sse41_blendvps:
+ case Intrinsic::x86_sse41_dppd:
+ case Intrinsic::x86_sse41_dpps:
+ case Intrinsic::x86_sse41_extractps:
+ case Intrinsic::x86_sse41_insertps:
+ case Intrinsic::x86_sse41_mpsadbw:
+ case Intrinsic::x86_sse41_packusdw:
+ case Intrinsic::x86_sse41_pblendvb:
+ case Intrinsic::x86_sse41_pblendw:
+ case Intrinsic::x86_sse41_pcmpeqq:
+ case Intrinsic::x86_sse41_pextrb:
+ case Intrinsic::x86_sse41_pextrd:
+ case Intrinsic::x86_sse41_pextrq:
+ case Intrinsic::x86_sse41_phminposuw:
+ case Intrinsic::x86_sse41_pmaxsb:
+ case Intrinsic::x86_sse41_pmaxsd:
+ case Intrinsic::x86_sse41_pmaxud:
+ case Intrinsic::x86_sse41_pmaxuw:
+ case Intrinsic::x86_sse41_pminsb:
+ case Intrinsic::x86_sse41_pminsd:
+ case Intrinsic::x86_sse41_pminud:
+ case Intrinsic::x86_sse41_pminuw:
+ case Intrinsic::x86_sse41_pmovsxbd:
+ case Intrinsic::x86_sse41_pmovsxbq:
+ case Intrinsic::x86_sse41_pmovsxbw:
+ case Intrinsic::x86_sse41_pmovsxdq:
+ case Intrinsic::x86_sse41_pmovsxwd:
+ case Intrinsic::x86_sse41_pmovsxwq:
+ case Intrinsic::x86_sse41_pmovzxbd:
+ case Intrinsic::x86_sse41_pmovzxbq:
+ case Intrinsic::x86_sse41_pmovzxbw:
+ case Intrinsic::x86_sse41_pmovzxdq:
+ case Intrinsic::x86_sse41_pmovzxwd:
+ case Intrinsic::x86_sse41_pmovzxwq:
+ case Intrinsic::x86_sse41_pmuldq:
+ case Intrinsic::x86_sse41_pmulld:
+ case Intrinsic::x86_sse41_ptestc:
+ case Intrinsic::x86_sse41_ptestnzc:
+ case Intrinsic::x86_sse41_ptestz:
+ case Intrinsic::x86_sse41_round_pd:
+ case Intrinsic::x86_sse41_round_ps:
+ case Intrinsic::x86_sse41_round_sd:
+ case Intrinsic::x86_sse41_round_ss:
+ case Intrinsic::x86_sse42_crc32_16:
+ case Intrinsic::x86_sse42_crc32_32:
+ case Intrinsic::x86_sse42_crc32_64:
+ case Intrinsic::x86_sse42_crc32_8:
+ case Intrinsic::x86_sse42_pcmpestri128:
+ case Intrinsic::x86_sse42_pcmpestria128:
+ case Intrinsic::x86_sse42_pcmpestric128:
+ case Intrinsic::x86_sse42_pcmpestrio128:
+ case Intrinsic::x86_sse42_pcmpestris128:
+ case Intrinsic::x86_sse42_pcmpestriz128:
+ case Intrinsic::x86_sse42_pcmpestrm128:
+ case Intrinsic::x86_sse42_pcmpgtq:
+ case Intrinsic::x86_sse42_pcmpistri128:
+ case Intrinsic::x86_sse42_pcmpistria128:
+ case Intrinsic::x86_sse42_pcmpistric128:
+ case Intrinsic::x86_sse42_pcmpistrio128:
+ case Intrinsic::x86_sse42_pcmpistris128:
+ case Intrinsic::x86_sse42_pcmpistriz128:
+ case Intrinsic::x86_sse42_pcmpistrm128:
+ case Intrinsic::x86_sse_add_ss:
+ case Intrinsic::x86_sse_cmp_ps:
+ case Intrinsic::x86_sse_cmp_ss:
+ case Intrinsic::x86_sse_comieq_ss:
+ case Intrinsic::x86_sse_comige_ss:
+ case Intrinsic::x86_sse_comigt_ss:
+ case Intrinsic::x86_sse_comile_ss:
+ case Intrinsic::x86_sse_comilt_ss:
+ case Intrinsic::x86_sse_comineq_ss:
+ case Intrinsic::x86_sse_cvtpd2pi:
+ case Intrinsic::x86_sse_cvtpi2pd:
+ case Intrinsic::x86_sse_cvtpi2ps:
+ case Intrinsic::x86_sse_cvtps2pi:
+ case Intrinsic::x86_sse_cvtsi2ss:
+ case Intrinsic::x86_sse_cvtsi642ss:
+ case Intrinsic::x86_sse_cvtss2si:
+ case Intrinsic::x86_sse_cvtss2si64:
+ case Intrinsic::x86_sse_cvttpd2pi:
+ case Intrinsic::x86_sse_cvttps2pi:
+ case Intrinsic::x86_sse_cvttss2si:
+ case Intrinsic::x86_sse_cvttss2si64:
+ case Intrinsic::x86_sse_div_ss:
+ case Intrinsic::x86_sse_max_ps:
+ case Intrinsic::x86_sse_max_ss:
+ case Intrinsic::x86_sse_min_ps:
+ case Intrinsic::x86_sse_min_ss:
+ case Intrinsic::x86_sse_movmsk_ps:
+ case Intrinsic::x86_sse_mul_ss:
+ case Intrinsic::x86_sse_rcp_ps:
+ case Intrinsic::x86_sse_rcp_ss:
+ case Intrinsic::x86_sse_rsqrt_ps:
+ case Intrinsic::x86_sse_rsqrt_ss:
+ case Intrinsic::x86_sse_sqrt_ps:
+ case Intrinsic::x86_sse_sqrt_ss:
+ case Intrinsic::x86_sse_sub_ss:
+ case Intrinsic::x86_sse_ucomieq_ss:
+ case Intrinsic::x86_sse_ucomige_ss:
+ case Intrinsic::x86_sse_ucomigt_ss:
+ case Intrinsic::x86_sse_ucomile_ss:
+ case Intrinsic::x86_sse_ucomilt_ss:
+ case Intrinsic::x86_sse_ucomineq_ss:
+ case Intrinsic::x86_ssse3_pabs_b:
+ case Intrinsic::x86_ssse3_pabs_b_128:
+ case Intrinsic::x86_ssse3_pabs_d:
+ case Intrinsic::x86_ssse3_pabs_d_128:
+ case Intrinsic::x86_ssse3_pabs_w:
+ case Intrinsic::x86_ssse3_pabs_w_128:
+ case Intrinsic::x86_ssse3_palign_r:
+ case Intrinsic::x86_ssse3_palign_r_128:
+ case Intrinsic::x86_ssse3_phadd_d:
+ case Intrinsic::x86_ssse3_phadd_d_128:
+ case Intrinsic::x86_ssse3_phadd_sw:
+ case Intrinsic::x86_ssse3_phadd_sw_128:
+ case Intrinsic::x86_ssse3_phadd_w:
+ case Intrinsic::x86_ssse3_phadd_w_128:
+ case Intrinsic::x86_ssse3_phsub_d:
+ case Intrinsic::x86_ssse3_phsub_d_128:
+ case Intrinsic::x86_ssse3_phsub_sw:
+ case Intrinsic::x86_ssse3_phsub_sw_128:
+ case Intrinsic::x86_ssse3_phsub_w:
+ case Intrinsic::x86_ssse3_phsub_w_128:
+ case Intrinsic::x86_ssse3_pmadd_ub_sw:
+ case Intrinsic::x86_ssse3_pmadd_ub_sw_128:
+ case Intrinsic::x86_ssse3_pmul_hr_sw:
+ case Intrinsic::x86_ssse3_pmul_hr_sw_128:
+ case Intrinsic::x86_ssse3_pshuf_b:
+ case Intrinsic::x86_ssse3_pshuf_b_128:
+ case Intrinsic::x86_ssse3_psign_b:
+ case Intrinsic::x86_ssse3_psign_b_128:
+ case Intrinsic::x86_ssse3_psign_d:
+ case Intrinsic::x86_ssse3_psign_d_128:
+ case Intrinsic::x86_ssse3_psign_w:
+ case Intrinsic::x86_ssse3_psign_w_128:
+ case Intrinsic::xcore_bitrev:
+ case Intrinsic::xcore_getid:
+ Attr |= Attribute::ReadNone; // These do not access memory.
+ break;
+ case Intrinsic::arm_neon_vld1:
+ case Intrinsic::arm_neon_vld2:
+ case Intrinsic::arm_neon_vld2lane:
+ case Intrinsic::arm_neon_vld3:
+ case Intrinsic::arm_neon_vld3lane:
+ case Intrinsic::arm_neon_vld4:
+ case Intrinsic::arm_neon_vld4lane:
+ case Intrinsic::cos:
+ case Intrinsic::eh_exception:
+ case Intrinsic::exp:
+ case Intrinsic::exp2:
+ case Intrinsic::gcread:
+ case Intrinsic::invariant_start:
+ case Intrinsic::log:
+ case Intrinsic::log10:
+ case Intrinsic::log2:
+ case Intrinsic::objectsize:
+ case Intrinsic::pow:
+ case Intrinsic::powi:
+ case Intrinsic::ppc_altivec_lvebx:
+ case Intrinsic::ppc_altivec_lvehx:
+ case Intrinsic::ppc_altivec_lvewx:
+ case Intrinsic::ppc_altivec_lvx:
+ case Intrinsic::ppc_altivec_lvxl:
+ case Intrinsic::ppc_altivec_mfvscr:
+ case Intrinsic::sin:
+ case Intrinsic::sqrt:
+ case Intrinsic::x86_sse2_loadu_dq:
+ case Intrinsic::x86_sse2_loadu_pd:
+ case Intrinsic::x86_sse3_ldu_dq:
+ case Intrinsic::x86_sse41_movntdqa:
+ case Intrinsic::x86_sse_loadu_ps:
+ Attr |= Attribute::ReadOnly; // These do not write memory.
+ break;
+ }
+ AttributeWithIndex AWI[3];
+ unsigned NumAttrs = 0;
+ switch (id) {
+ default: break;
+ case Intrinsic::atomic_cmp_swap:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_add:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_and:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_max:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_min:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_nand:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_or:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_sub:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_umax:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_umin:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_load_xor:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::atomic_swap:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::gcwrite:
+ AWI[0] = AttributeWithIndex::get(2, 0|Attribute::NoCapture);
+ AWI[1] = AttributeWithIndex::get(3, 0|Attribute::NoCapture);
+ NumAttrs = 2;
+ break;
+ case Intrinsic::invariant_end:
+ AWI[0] = AttributeWithIndex::get(3, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::invariant_start:
+ AWI[0] = AttributeWithIndex::get(2, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::lifetime_end:
+ AWI[0] = AttributeWithIndex::get(2, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::lifetime_start:
+ AWI[0] = AttributeWithIndex::get(2, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::memcpy:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ AWI[1] = AttributeWithIndex::get(2, 0|Attribute::NoCapture);
+ NumAttrs = 2;
+ break;
+ case Intrinsic::memmove:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ AWI[1] = AttributeWithIndex::get(2, 0|Attribute::NoCapture);
+ NumAttrs = 2;
+ break;
+ case Intrinsic::memset:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ case Intrinsic::prefetch:
+ AWI[0] = AttributeWithIndex::get(1, 0|Attribute::NoCapture);
+ NumAttrs = 1;
+ break;
+ }
+ AWI[NumAttrs] = AttributeWithIndex::get(~0, Attr);
+ return AttrListPtr::get(AWI, NumAttrs+1);
+}
+#endif // GET_INTRINSIC_ATTRIBUTES
+
+// Determine intrinsic alias analysis mod/ref behavior.
+#ifdef GET_INTRINSIC_MODREF_BEHAVIOR
+switch (id) {
+default:
+ return UnknownModRefBehavior;
+case Intrinsic::alpha_umulh:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabals:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabalu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabas:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabau:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabdls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabdlu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabds:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabdu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vabs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vacged:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vacgeq:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vacgtd:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vacgtq:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vaddhn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vaddls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vaddlu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vaddws:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vaddwu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vcls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vclz:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vcnt:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vcvtfp2fxs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vcvtfp2fxu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vcvtfxs2fp:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vcvtfxu2fp:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vhadds:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vhaddu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vhsubs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vhsubu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vld1:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vld2:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vld2lane:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vld3:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vld3lane:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vld4:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vld4lane:
+ return OnlyReadsMemory;
+case Intrinsic::arm_neon_vmaxs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmaxu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmins:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vminu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmlals:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmlalu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmlsls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmlslu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmovls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmovlu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmovn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmullp:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmulls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmullu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vmulp:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpadals:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpadalu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpadd:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpaddls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpaddlu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpmaxs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpmaxu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpmins:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vpminu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqabs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqadds:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqaddu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqdmlal:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqdmlsl:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqdmulh:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqdmull:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqmovns:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqmovnsu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqmovnu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqneg:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqrdmulh:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqrshiftns:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqrshiftnsu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqrshiftnu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqrshifts:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqrshiftu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqshiftns:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqshiftnsu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqshiftnu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqshifts:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqshiftsu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqshiftu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqsubs:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vqsubu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vraddhn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrecpe:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrecps:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrhadds:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrhaddu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrshiftn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrshifts:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrshiftu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrsqrte:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrsqrts:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vrsubhn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vshiftins:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vshiftls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vshiftlu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vshiftn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vshifts:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vshiftu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vst1:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vst2:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vst2lane:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vst3:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vst3lane:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vst4:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vst4lane:
+ return AccessesArguments;
+case Intrinsic::arm_neon_vsubhn:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vsubls:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vsublu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vsubws:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vsubwu:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbl1:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbl2:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbl3:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbl4:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbx1:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbx2:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbx3:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_neon_vtbx4:
+ return DoesNotAccessMemory;
+case Intrinsic::arm_thread_pointer:
+ return DoesNotAccessMemory;
+case Intrinsic::atomic_cmp_swap:
+ return AccessesArguments;
+case Intrinsic::atomic_load_add:
+ return AccessesArguments;
+case Intrinsic::atomic_load_and:
+ return AccessesArguments;
+case Intrinsic::atomic_load_max:
+ return AccessesArguments;
+case Intrinsic::atomic_load_min:
+ return AccessesArguments;
+case Intrinsic::atomic_load_nand:
+ return AccessesArguments;
+case Intrinsic::atomic_load_or:
+ return AccessesArguments;
+case Intrinsic::atomic_load_sub:
+ return AccessesArguments;
+case Intrinsic::atomic_load_umax:
+ return AccessesArguments;
+case Intrinsic::atomic_load_umin:
+ return AccessesArguments;
+case Intrinsic::atomic_load_xor:
+ return AccessesArguments;
+case Intrinsic::atomic_swap:
+ return AccessesArguments;
+case Intrinsic::bswap:
+ return DoesNotAccessMemory;
+case Intrinsic::cos:
+ return OnlyReadsMemory;
+case Intrinsic::ctlz:
+ return DoesNotAccessMemory;
+case Intrinsic::ctpop:
+ return DoesNotAccessMemory;
+case Intrinsic::cttz:
+ return DoesNotAccessMemory;
+case Intrinsic::dbg_declare:
+ return DoesNotAccessMemory;
+case Intrinsic::dbg_func_start:
+ return DoesNotAccessMemory;
+case Intrinsic::dbg_region_end:
+ return DoesNotAccessMemory;
+case Intrinsic::dbg_region_start:
+ return DoesNotAccessMemory;
+case Intrinsic::dbg_stoppoint:
+ return DoesNotAccessMemory;
+case Intrinsic::dbg_value:
+ return DoesNotAccessMemory;
+case Intrinsic::eh_exception:
+ return OnlyReadsMemory;
+case Intrinsic::eh_sjlj_longjmp:
+ return DoesNotAccessMemory;
+case Intrinsic::eh_sjlj_lsda:
+ return DoesNotAccessMemory;
+case Intrinsic::eh_sjlj_setjmp:
+ return DoesNotAccessMemory;
+case Intrinsic::exp:
+ return OnlyReadsMemory;
+case Intrinsic::exp2:
+ return OnlyReadsMemory;
+case Intrinsic::frameaddress:
+ return DoesNotAccessMemory;
+case Intrinsic::gcread:
+ return OnlyReadsMemory;
+case Intrinsic::gcwrite:
+ return AccessesArguments;
+case Intrinsic::init_trampoline:
+ return AccessesArguments;
+case Intrinsic::invariant_end:
+ return AccessesArguments;
+case Intrinsic::invariant_start:
+ return OnlyReadsMemory;
+case Intrinsic::lifetime_end:
+ return AccessesArguments;
+case Intrinsic::lifetime_start:
+ return AccessesArguments;
+case Intrinsic::log:
+ return OnlyReadsMemory;
+case Intrinsic::log10:
+ return OnlyReadsMemory;
+case Intrinsic::log2:
+ return OnlyReadsMemory;
+case Intrinsic::memcpy:
+ return AccessesArguments;
+case Intrinsic::memmove:
+ return AccessesArguments;
+case Intrinsic::memset:
+ return AccessesArguments;
+case Intrinsic::objectsize:
+ return OnlyReadsMemory;
+case Intrinsic::pow:
+ return OnlyReadsMemory;
+case Intrinsic::powi:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_lvebx:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_lvehx:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_lvewx:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_lvsl:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_lvsr:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_lvx:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_lvxl:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_mfvscr:
+ return OnlyReadsMemory;
+case Intrinsic::ppc_altivec_vaddcuw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vaddsbs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vaddshs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vaddsws:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vaddubs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vadduhs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vadduws:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vavgsb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vavgsh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vavgsw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vavgub:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vavguh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vavguw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcfsx:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcfux:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpbfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpbfp_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpeqfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpeqfp_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpequb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpequb_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpequh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpequh_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpequw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpequw_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgefp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgefp_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtfp_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtsb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtsb_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtsh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtsh_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtsw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtsw_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtub:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtub_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtuh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtuh_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtuw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vcmpgtuw_p:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vctsxs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vctuxs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vexptefp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vlogefp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaddfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxsb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxsh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxsw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxub:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxuh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmaxuw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmhaddshs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmhraddshs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminsb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminsh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminsw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminub:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminuh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vminuw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmladduhm:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmsummbm:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmsumshm:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmsumshs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmsumubm:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmsumuhm:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmsumuhs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmulesb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmulesh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmuleub:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmuleuh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmulosb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmulosh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmuloub:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vmulouh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vnmsubfp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vperm:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkpx:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkshss:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkshus:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkswss:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkswus:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkuhus:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vpkuwus:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrefp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrfim:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrfin:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrfip:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrfiz:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrlb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrlh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrlw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vrsqrtefp:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsel:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsl:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vslb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vslh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vslo:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vslw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsr:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsrab:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsrah:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsraw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsrb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsrh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsro:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsrw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsubcuw:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsubsbs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsubshs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsubsws:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsububs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsubuhs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsubuws:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsum2sws:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsum4sbs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsum4shs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsum4ubs:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vsumsws:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vupkhpx:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vupkhsb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vupkhsh:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vupklpx:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vupklsb:
+ return DoesNotAccessMemory;
+case Intrinsic::ppc_altivec_vupklsh:
+ return DoesNotAccessMemory;
+case Intrinsic::prefetch:
+ return AccessesArguments;
+case Intrinsic::returnaddress:
+ return DoesNotAccessMemory;
+case Intrinsic::sadd_with_overflow:
+ return DoesNotAccessMemory;
+case Intrinsic::sin:
+ return OnlyReadsMemory;
+case Intrinsic::smul_with_overflow:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_a:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_addx:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ah:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ahi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ai:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_and:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_andbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_andc:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_andhi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_andi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_bg:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_bgx:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ceq:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ceqb:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ceqbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ceqh:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ceqhi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ceqi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cg:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgt:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgtb:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgtbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgth:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgthi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgti:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_cgx:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_clgt:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_clgtb:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_clgtbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_clgth:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_clgthi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_clgti:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfa:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfm:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfma:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfms:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfnma:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfnms:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_dfs:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fa:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fceq:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fcgt:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fcmeq:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fcmgt:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fm:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fma:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fms:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fnms:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fs:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_fsmbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpy:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpya:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyh:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyhh:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyhha:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyhhau:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyhhu:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpys:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyu:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_mpyui:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_nand:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_nor:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_or:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_orbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_orc:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_orhi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_ori:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_sf:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_sfh:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_sfhi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_sfi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_sfx:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_shli:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_shlqbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_shlqbii:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_shlqby:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_shlqbyi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_xor:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_xorbi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_xorhi:
+ return DoesNotAccessMemory;
+case Intrinsic::spu_si_xori:
+ return DoesNotAccessMemory;
+case Intrinsic::sqrt:
+ return OnlyReadsMemory;
+case Intrinsic::ssub_with_overflow:
+ return DoesNotAccessMemory;
+case Intrinsic::uadd_with_overflow:
+ return DoesNotAccessMemory;
+case Intrinsic::umul_with_overflow:
+ return DoesNotAccessMemory;
+case Intrinsic::usub_with_overflow:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_packssdw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_packsswb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_packuswb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_padds_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_padds_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_paddus_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_paddus_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pavg_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pavg_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pcmpeq_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pcmpeq_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pcmpeq_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pcmpgt_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pcmpgt_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pcmpgt_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmadd_wd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmaxs_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmaxu_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmins_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pminu_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmovmskb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmulh_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmulhu_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pmulu_dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psad_bw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psll_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psll_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psll_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pslli_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pslli_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_pslli_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psra_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psra_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrai_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrai_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrl_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrl_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrl_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrli_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrli_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psrli_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psubs_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psubs_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psubus_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_mmx_psubus_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_add_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cmp_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cmp_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_comieq_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_comige_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_comigt_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_comile_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_comilt_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_comineq_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtdq2pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtdq2ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtpd2dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtpd2ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtps2dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtps2pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtsd2si:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtsd2si64:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtsd2ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtsi2sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtsi642sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvtss2sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvttpd2dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvttps2dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvttsd2si:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_cvttsd2si64:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_div_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_loadu_dq:
+ return OnlyReadsMemory;
+case Intrinsic::x86_sse2_loadu_pd:
+ return OnlyReadsMemory;
+case Intrinsic::x86_sse2_max_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_max_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_min_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_min_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_movmsk_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_mul_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_packssdw_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_packsswb_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_packuswb_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_padds_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_padds_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_paddus_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_paddus_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pavg_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pavg_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pcmpeq_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pcmpeq_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pcmpeq_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pcmpgt_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pcmpgt_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pcmpgt_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmadd_wd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmaxs_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmaxu_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmins_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pminu_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmovmskb_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmulh_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmulhu_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pmulu_dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psad_bw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psll_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psll_dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psll_dq_bs:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psll_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psll_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pslli_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pslli_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_pslli_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psra_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psra_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrai_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrai_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrl_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrl_dq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrl_dq_bs:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrl_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrl_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrli_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrli_q:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psrli_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psubs_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psubs_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psubus_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_psubus_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_sqrt_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_sqrt_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_sub_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_ucomieq_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_ucomige_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_ucomigt_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_ucomile_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_ucomilt_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse2_ucomineq_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_addsub_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_addsub_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_hadd_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_hadd_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_hsub_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_hsub_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse3_ldu_dq:
+ return OnlyReadsMemory;
+case Intrinsic::x86_sse41_blendpd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_blendps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_blendvpd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_blendvps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_dppd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_dpps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_extractps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_insertps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_movntdqa:
+ return OnlyReadsMemory;
+case Intrinsic::x86_sse41_mpsadbw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_packusdw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pblendvb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pblendw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pcmpeqq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pextrb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pextrd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pextrq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_phminposuw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmaxsb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmaxsd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmaxud:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmaxuw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pminsb:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pminsd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pminud:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pminuw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovsxbd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovsxbq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovsxbw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovsxdq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovsxwd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovsxwq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovzxbd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovzxbq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovzxbw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovzxdq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovzxwd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmovzxwq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmuldq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_pmulld:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_ptestc:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_ptestnzc:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_ptestz:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_round_pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_round_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_round_sd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse41_round_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_crc32_16:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_crc32_32:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_crc32_64:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_crc32_8:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestri128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestria128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestric128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestrio128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestris128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestriz128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpestrm128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpgtq:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistri128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistria128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistric128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistrio128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistris128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistriz128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse42_pcmpistrm128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_add_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cmp_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cmp_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_comieq_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_comige_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_comigt_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_comile_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_comilt_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_comineq_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtpd2pi:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtpi2pd:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtpi2ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtps2pi:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtsi2ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtsi642ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtss2si:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvtss2si64:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvttpd2pi:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvttps2pi:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvttss2si:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_cvttss2si64:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_div_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_loadu_ps:
+ return OnlyReadsMemory;
+case Intrinsic::x86_sse_max_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_max_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_min_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_min_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_movmsk_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_mul_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_rcp_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_rcp_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_rsqrt_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_rsqrt_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_sqrt_ps:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_sqrt_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_sub_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_ucomieq_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_ucomige_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_ucomigt_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_ucomile_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_ucomilt_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_sse_ucomineq_ss:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pabs_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pabs_b_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pabs_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pabs_d_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pabs_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pabs_w_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_palign_r:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_palign_r_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phadd_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phadd_d_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phadd_sw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phadd_sw_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phadd_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phadd_w_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phsub_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phsub_d_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phsub_sw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phsub_sw_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phsub_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_phsub_w_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pmadd_ub_sw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pmadd_ub_sw_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pmul_hr_sw:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pmul_hr_sw_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pshuf_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_pshuf_b_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_psign_b:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_psign_b_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_psign_d:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_psign_d_128:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_psign_w:
+ return DoesNotAccessMemory;
+case Intrinsic::x86_ssse3_psign_w_128:
+ return DoesNotAccessMemory;
+case Intrinsic::xcore_bitrev:
+ return DoesNotAccessMemory;
+case Intrinsic::xcore_getid:
+ return DoesNotAccessMemory;
+}
+#endif // GET_INTRINSIC_MODREF_BEHAVIOR
+
+// Get the GCC builtin that corresponds to an LLVM intrinsic.
+#ifdef GET_GCC_BUILTIN_NAME
+ switch (F->getIntrinsicID()) {
+ default: BuiltinName = ""; break;
+ case Intrinsic::alpha_umulh: BuiltinName = "__builtin_alpha_umulh"; break;
+ case Intrinsic::arm_thread_pointer: BuiltinName = "__builtin_thread_pointer"; break;
+ case Intrinsic::atomic_cmp_swap: BuiltinName = "__sync_val_compare_and_swap"; break;
+ case Intrinsic::atomic_load_add: BuiltinName = "__sync_fetch_and_add"; break;
+ case Intrinsic::atomic_load_and: BuiltinName = "__sync_fetch_and_and"; break;
+ case Intrinsic::atomic_load_max: BuiltinName = "__sync_fetch_and_max"; break;
+ case Intrinsic::atomic_load_min: BuiltinName = "__sync_fetch_and_min"; break;
+ case Intrinsic::atomic_load_nand: BuiltinName = "__sync_fetch_and_nand"; break;
+ case Intrinsic::atomic_load_or: BuiltinName = "__sync_fetch_and_or"; break;
+ case Intrinsic::atomic_load_sub: BuiltinName = "__sync_fetch_and_sub"; break;
+ case Intrinsic::atomic_load_umax: BuiltinName = "__sync_fetch_and_umax"; break;
+ case Intrinsic::atomic_load_umin: BuiltinName = "__sync_fetch_and_umin"; break;
+ case Intrinsic::atomic_load_xor: BuiltinName = "__sync_fetch_and_xor"; break;
+ case Intrinsic::atomic_swap: BuiltinName = "__sync_lock_test_and_set"; break;
+ case Intrinsic::eh_unwind_init: BuiltinName = "__builtin_unwind_init"; break;
+ case Intrinsic::flt_rounds: BuiltinName = "__builtin_flt_rounds"; break;
+ case Intrinsic::init_trampoline: BuiltinName = "__builtin_init_trampoline"; break;
+ case Intrinsic::memory_barrier: BuiltinName = "__builtin_llvm_memory_barrier"; break;
+ case Intrinsic::objectsize: BuiltinName = "__builtin_object_size"; break;
+ case Intrinsic::ppc_altivec_dss: BuiltinName = "__builtin_altivec_dss"; break;
+ case Intrinsic::ppc_altivec_dssall: BuiltinName = "__builtin_altivec_dssall"; break;
+ case Intrinsic::ppc_altivec_dst: BuiltinName = "__builtin_altivec_dst"; break;
+ case Intrinsic::ppc_altivec_dstst: BuiltinName = "__builtin_altivec_dstst"; break;
+ case Intrinsic::ppc_altivec_dststt: BuiltinName = "__builtin_altivec_dststt"; break;
+ case Intrinsic::ppc_altivec_dstt: BuiltinName = "__builtin_altivec_dstt"; break;
+ case Intrinsic::ppc_altivec_mfvscr: BuiltinName = "__builtin_altivec_mfvscr"; break;
+ case Intrinsic::ppc_altivec_mtvscr: BuiltinName = "__builtin_altivec_mtvscr"; break;
+ case Intrinsic::ppc_altivec_vaddcuw: BuiltinName = "__builtin_altivec_vaddcuw"; break;
+ case Intrinsic::ppc_altivec_vaddsbs: BuiltinName = "__builtin_altivec_vaddsbs"; break;
+ case Intrinsic::ppc_altivec_vaddshs: BuiltinName = "__builtin_altivec_vaddshs"; break;
+ case Intrinsic::ppc_altivec_vaddsws: BuiltinName = "__builtin_altivec_vaddsws"; break;
+ case Intrinsic::ppc_altivec_vaddubs: BuiltinName = "__builtin_altivec_vaddubs"; break;
+ case Intrinsic::ppc_altivec_vadduhs: BuiltinName = "__builtin_altivec_vadduhs"; break;
+ case Intrinsic::ppc_altivec_vadduws: BuiltinName = "__builtin_altivec_vadduws"; break;
+ case Intrinsic::ppc_altivec_vavgsb: BuiltinName = "__builtin_altivec_vavgsb"; break;
+ case Intrinsic::ppc_altivec_vavgsh: BuiltinName = "__builtin_altivec_vavgsh"; break;
+ case Intrinsic::ppc_altivec_vavgsw: BuiltinName = "__builtin_altivec_vavgsw"; break;
+ case Intrinsic::ppc_altivec_vavgub: BuiltinName = "__builtin_altivec_vavgub"; break;
+ case Intrinsic::ppc_altivec_vavguh: BuiltinName = "__builtin_altivec_vavguh"; break;
+ case Intrinsic::ppc_altivec_vavguw: BuiltinName = "__builtin_altivec_vavguw"; break;
+ case Intrinsic::ppc_altivec_vcfsx: BuiltinName = "__builtin_altivec_vcfsx"; break;
+ case Intrinsic::ppc_altivec_vcfux: BuiltinName = "__builtin_altivec_vcfux"; break;
+ case Intrinsic::ppc_altivec_vcmpbfp: BuiltinName = "__builtin_altivec_vcmpbfp"; break;
+ case Intrinsic::ppc_altivec_vcmpbfp_p: BuiltinName = "__builtin_altivec_vcmpbfp_p"; break;
+ case Intrinsic::ppc_altivec_vcmpeqfp: BuiltinName = "__builtin_altivec_vcmpeqfp"; break;
+ case Intrinsic::ppc_altivec_vcmpeqfp_p: BuiltinName = "__builtin_altivec_vcmpeqfp_p"; break;
+ case Intrinsic::ppc_altivec_vcmpequb: BuiltinName = "__builtin_altivec_vcmpequb"; break;
+ case Intrinsic::ppc_altivec_vcmpequb_p: BuiltinName = "__builtin_altivec_vcmpequb_p"; break;
+ case Intrinsic::ppc_altivec_vcmpequh: BuiltinName = "__builtin_altivec_vcmpequh"; break;
+ case Intrinsic::ppc_altivec_vcmpequh_p: BuiltinName = "__builtin_altivec_vcmpequh_p"; break;
+ case Intrinsic::ppc_altivec_vcmpequw: BuiltinName = "__builtin_altivec_vcmpequw"; break;
+ case Intrinsic::ppc_altivec_vcmpequw_p: BuiltinName = "__builtin_altivec_vcmpequw_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgefp: BuiltinName = "__builtin_altivec_vcmpgefp"; break;
+ case Intrinsic::ppc_altivec_vcmpgefp_p: BuiltinName = "__builtin_altivec_vcmpgefp_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtfp: BuiltinName = "__builtin_altivec_vcmpgtfp"; break;
+ case Intrinsic::ppc_altivec_vcmpgtfp_p: BuiltinName = "__builtin_altivec_vcmpgtfp_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtsb: BuiltinName = "__builtin_altivec_vcmpgtsb"; break;
+ case Intrinsic::ppc_altivec_vcmpgtsb_p: BuiltinName = "__builtin_altivec_vcmpgtsb_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtsh: BuiltinName = "__builtin_altivec_vcmpgtsh"; break;
+ case Intrinsic::ppc_altivec_vcmpgtsh_p: BuiltinName = "__builtin_altivec_vcmpgtsh_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtsw: BuiltinName = "__builtin_altivec_vcmpgtsw"; break;
+ case Intrinsic::ppc_altivec_vcmpgtsw_p: BuiltinName = "__builtin_altivec_vcmpgtsw_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtub: BuiltinName = "__builtin_altivec_vcmpgtub"; break;
+ case Intrinsic::ppc_altivec_vcmpgtub_p: BuiltinName = "__builtin_altivec_vcmpgtub_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtuh: BuiltinName = "__builtin_altivec_vcmpgtuh"; break;
+ case Intrinsic::ppc_altivec_vcmpgtuh_p: BuiltinName = "__builtin_altivec_vcmpgtuh_p"; break;
+ case Intrinsic::ppc_altivec_vcmpgtuw: BuiltinName = "__builtin_altivec_vcmpgtuw"; break;
+ case Intrinsic::ppc_altivec_vcmpgtuw_p: BuiltinName = "__builtin_altivec_vcmpgtuw_p"; break;
+ case Intrinsic::ppc_altivec_vctsxs: BuiltinName = "__builtin_altivec_vctsxs"; break;
+ case Intrinsic::ppc_altivec_vctuxs: BuiltinName = "__builtin_altivec_vctuxs"; break;
+ case Intrinsic::ppc_altivec_vexptefp: BuiltinName = "__builtin_altivec_vexptefp"; break;
+ case Intrinsic::ppc_altivec_vlogefp: BuiltinName = "__builtin_altivec_vlogefp"; break;
+ case Intrinsic::ppc_altivec_vmaddfp: BuiltinName = "__builtin_altivec_vmaddfp"; break;
+ case Intrinsic::ppc_altivec_vmaxfp: BuiltinName = "__builtin_altivec_vmaxfp"; break;
+ case Intrinsic::ppc_altivec_vmaxsb: BuiltinName = "__builtin_altivec_vmaxsb"; break;
+ case Intrinsic::ppc_altivec_vmaxsh: BuiltinName = "__builtin_altivec_vmaxsh"; break;
+ case Intrinsic::ppc_altivec_vmaxsw: BuiltinName = "__builtin_altivec_vmaxsw"; break;
+ case Intrinsic::ppc_altivec_vmaxub: BuiltinName = "__builtin_altivec_vmaxub"; break;
+ case Intrinsic::ppc_altivec_vmaxuh: BuiltinName = "__builtin_altivec_vmaxuh"; break;
+ case Intrinsic::ppc_altivec_vmaxuw: BuiltinName = "__builtin_altivec_vmaxuw"; break;
+ case Intrinsic::ppc_altivec_vmhaddshs: BuiltinName = "__builtin_altivec_vmhaddshs"; break;
+ case Intrinsic::ppc_altivec_vmhraddshs: BuiltinName = "__builtin_altivec_vmhraddshs"; break;
+ case Intrinsic::ppc_altivec_vminfp: BuiltinName = "__builtin_altivec_vminfp"; break;
+ case Intrinsic::ppc_altivec_vminsb: BuiltinName = "__builtin_altivec_vminsb"; break;
+ case Intrinsic::ppc_altivec_vminsh: BuiltinName = "__builtin_altivec_vminsh"; break;
+ case Intrinsic::ppc_altivec_vminsw: BuiltinName = "__builtin_altivec_vminsw"; break;
+ case Intrinsic::ppc_altivec_vminub: BuiltinName = "__builtin_altivec_vminub"; break;
+ case Intrinsic::ppc_altivec_vminuh: BuiltinName = "__builtin_altivec_vminuh"; break;
+ case Intrinsic::ppc_altivec_vminuw: BuiltinName = "__builtin_altivec_vminuw"; break;
+ case Intrinsic::ppc_altivec_vmladduhm: BuiltinName = "__builtin_altivec_vmladduhm"; break;
+ case Intrinsic::ppc_altivec_vmsummbm: BuiltinName = "__builtin_altivec_vmsummbm"; break;
+ case Intrinsic::ppc_altivec_vmsumshm: BuiltinName = "__builtin_altivec_vmsumshm"; break;
+ case Intrinsic::ppc_altivec_vmsumshs: BuiltinName = "__builtin_altivec_vmsumshs"; break;
+ case Intrinsic::ppc_altivec_vmsumubm: BuiltinName = "__builtin_altivec_vmsumubm"; break;
+ case Intrinsic::ppc_altivec_vmsumuhm: BuiltinName = "__builtin_altivec_vmsumuhm"; break;
+ case Intrinsic::ppc_altivec_vmsumuhs: BuiltinName = "__builtin_altivec_vmsumuhs"; break;
+ case Intrinsic::ppc_altivec_vmulesb: BuiltinName = "__builtin_altivec_vmulesb"; break;
+ case Intrinsic::ppc_altivec_vmulesh: BuiltinName = "__builtin_altivec_vmulesh"; break;
+ case Intrinsic::ppc_altivec_vmuleub: BuiltinName = "__builtin_altivec_vmuleub"; break;
+ case Intrinsic::ppc_altivec_vmuleuh: BuiltinName = "__builtin_altivec_vmuleuh"; break;
+ case Intrinsic::ppc_altivec_vmulosb: BuiltinName = "__builtin_altivec_vmulosb"; break;
+ case Intrinsic::ppc_altivec_vmulosh: BuiltinName = "__builtin_altivec_vmulosh"; break;
+ case Intrinsic::ppc_altivec_vmuloub: BuiltinName = "__builtin_altivec_vmuloub"; break;
+ case Intrinsic::ppc_altivec_vmulouh: BuiltinName = "__builtin_altivec_vmulouh"; break;
+ case Intrinsic::ppc_altivec_vnmsubfp: BuiltinName = "__builtin_altivec_vnmsubfp"; break;
+ case Intrinsic::ppc_altivec_vperm: BuiltinName = "__builtin_altivec_vperm_4si"; break;
+ case Intrinsic::ppc_altivec_vpkpx: BuiltinName = "__builtin_altivec_vpkpx"; break;
+ case Intrinsic::ppc_altivec_vpkshss: BuiltinName = "__builtin_altivec_vpkshss"; break;
+ case Intrinsic::ppc_altivec_vpkshus: BuiltinName = "__builtin_altivec_vpkshus"; break;
+ case Intrinsic::ppc_altivec_vpkswss: BuiltinName = "__builtin_altivec_vpkswss"; break;
+ case Intrinsic::ppc_altivec_vpkswus: BuiltinName = "__builtin_altivec_vpkswus"; break;
+ case Intrinsic::ppc_altivec_vpkuhus: BuiltinName = "__builtin_altivec_vpkuhus"; break;
+ case Intrinsic::ppc_altivec_vpkuwus: BuiltinName = "__builtin_altivec_vpkuwus"; break;
+ case Intrinsic::ppc_altivec_vrefp: BuiltinName = "__builtin_altivec_vrefp"; break;
+ case Intrinsic::ppc_altivec_vrfim: BuiltinName = "__builtin_altivec_vrfim"; break;
+ case Intrinsic::ppc_altivec_vrfin: BuiltinName = "__builtin_altivec_vrfin"; break;
+ case Intrinsic::ppc_altivec_vrfip: BuiltinName = "__builtin_altivec_vrfip"; break;
+ case Intrinsic::ppc_altivec_vrfiz: BuiltinName = "__builtin_altivec_vrfiz"; break;
+ case Intrinsic::ppc_altivec_vrlb: BuiltinName = "__builtin_altivec_vrlb"; break;
+ case Intrinsic::ppc_altivec_vrlh: BuiltinName = "__builtin_altivec_vrlh"; break;
+ case Intrinsic::ppc_altivec_vrlw: BuiltinName = "__builtin_altivec_vrlw"; break;
+ case Intrinsic::ppc_altivec_vrsqrtefp: BuiltinName = "__builtin_altivec_vrsqrtefp"; break;
+ case Intrinsic::ppc_altivec_vsel: BuiltinName = "__builtin_altivec_vsel_4si"; break;
+ case Intrinsic::ppc_altivec_vsl: BuiltinName = "__builtin_altivec_vsl"; break;
+ case Intrinsic::ppc_altivec_vslb: BuiltinName = "__builtin_altivec_vslb"; break;
+ case Intrinsic::ppc_altivec_vslh: BuiltinName = "__builtin_altivec_vslh"; break;
+ case Intrinsic::ppc_altivec_vslo: BuiltinName = "__builtin_altivec_vslo"; break;
+ case Intrinsic::ppc_altivec_vslw: BuiltinName = "__builtin_altivec_vslw"; break;
+ case Intrinsic::ppc_altivec_vsr: BuiltinName = "__builtin_altivec_vsr"; break;
+ case Intrinsic::ppc_altivec_vsrab: BuiltinName = "__builtin_altivec_vsrab"; break;
+ case Intrinsic::ppc_altivec_vsrah: BuiltinName = "__builtin_altivec_vsrah"; break;
+ case Intrinsic::ppc_altivec_vsraw: BuiltinName = "__builtin_altivec_vsraw"; break;
+ case Intrinsic::ppc_altivec_vsrb: BuiltinName = "__builtin_altivec_vsrb"; break;
+ case Intrinsic::ppc_altivec_vsrh: BuiltinName = "__builtin_altivec_vsrh"; break;
+ case Intrinsic::ppc_altivec_vsro: BuiltinName = "__builtin_altivec_vsro"; break;
+ case Intrinsic::ppc_altivec_vsrw: BuiltinName = "__builtin_altivec_vsrw"; break;
+ case Intrinsic::ppc_altivec_vsubcuw: BuiltinName = "__builtin_altivec_vsubcuw"; break;
+ case Intrinsic::ppc_altivec_vsubsbs: BuiltinName = "__builtin_altivec_vsubsbs"; break;
+ case Intrinsic::ppc_altivec_vsubshs: BuiltinName = "__builtin_altivec_vsubshs"; break;
+ case Intrinsic::ppc_altivec_vsubsws: BuiltinName = "__builtin_altivec_vsubsws"; break;
+ case Intrinsic::ppc_altivec_vsububs: BuiltinName = "__builtin_altivec_vsububs"; break;
+ case Intrinsic::ppc_altivec_vsubuhs: BuiltinName = "__builtin_altivec_vsubuhs"; break;
+ case Intrinsic::ppc_altivec_vsubuws: BuiltinName = "__builtin_altivec_vsubuws"; break;
+ case Intrinsic::ppc_altivec_vsum2sws: BuiltinName = "__builtin_altivec_vsum2sws"; break;
+ case Intrinsic::ppc_altivec_vsum4sbs: BuiltinName = "__builtin_altivec_vsum4sbs"; break;
+ case Intrinsic::ppc_altivec_vsum4shs: BuiltinName = "__builtin_altivec_vsum4shs"; break;
+ case Intrinsic::ppc_altivec_vsum4ubs: BuiltinName = "__builtin_altivec_vsum4ubs"; break;
+ case Intrinsic::ppc_altivec_vsumsws: BuiltinName = "__builtin_altivec_vsumsws"; break;
+ case Intrinsic::ppc_altivec_vupkhpx: BuiltinName = "__builtin_altivec_vupkhpx"; break;
+ case Intrinsic::ppc_altivec_vupkhsb: BuiltinName = "__builtin_altivec_vupkhsb"; break;
+ case Intrinsic::ppc_altivec_vupkhsh: BuiltinName = "__builtin_altivec_vupkhsh"; break;
+ case Intrinsic::ppc_altivec_vupklpx: BuiltinName = "__builtin_altivec_vupklpx"; break;
+ case Intrinsic::ppc_altivec_vupklsb: BuiltinName = "__builtin_altivec_vupklsb"; break;
+ case Intrinsic::ppc_altivec_vupklsh: BuiltinName = "__builtin_altivec_vupklsh"; break;
+ case Intrinsic::spu_si_a: BuiltinName = "__builtin_si_a"; break;
+ case Intrinsic::spu_si_addx: BuiltinName = "__builtin_si_addx"; break;
+ case Intrinsic::spu_si_ah: BuiltinName = "__builtin_si_ah"; break;
+ case Intrinsic::spu_si_ahi: BuiltinName = "__builtin_si_ahi"; break;
+ case Intrinsic::spu_si_ai: BuiltinName = "__builtin_si_ai"; break;
+ case Intrinsic::spu_si_and: BuiltinName = "__builtin_si_and"; break;
+ case Intrinsic::spu_si_andbi: BuiltinName = "__builtin_si_andbi"; break;
+ case Intrinsic::spu_si_andc: BuiltinName = "__builtin_si_andc"; break;
+ case Intrinsic::spu_si_andhi: BuiltinName = "__builtin_si_andhi"; break;
+ case Intrinsic::spu_si_andi: BuiltinName = "__builtin_si_andi"; break;
+ case Intrinsic::spu_si_bg: BuiltinName = "__builtin_si_bg"; break;
+ case Intrinsic::spu_si_bgx: BuiltinName = "__builtin_si_bgx"; break;
+ case Intrinsic::spu_si_ceq: BuiltinName = "__builtin_si_ceq"; break;
+ case Intrinsic::spu_si_ceqb: BuiltinName = "__builtin_si_ceqb"; break;
+ case Intrinsic::spu_si_ceqbi: BuiltinName = "__builtin_si_ceqbi"; break;
+ case Intrinsic::spu_si_ceqh: BuiltinName = "__builtin_si_ceqh"; break;
+ case Intrinsic::spu_si_ceqhi: BuiltinName = "__builtin_si_ceqhi"; break;
+ case Intrinsic::spu_si_ceqi: BuiltinName = "__builtin_si_ceqi"; break;
+ case Intrinsic::spu_si_cg: BuiltinName = "__builtin_si_cg"; break;
+ case Intrinsic::spu_si_cgt: BuiltinName = "__builtin_si_cgt"; break;
+ case Intrinsic::spu_si_cgtb: BuiltinName = "__builtin_si_cgtb"; break;
+ case Intrinsic::spu_si_cgtbi: BuiltinName = "__builtin_si_cgtbi"; break;
+ case Intrinsic::spu_si_cgth: BuiltinName = "__builtin_si_cgth"; break;
+ case Intrinsic::spu_si_cgthi: BuiltinName = "__builtin_si_cgthi"; break;
+ case Intrinsic::spu_si_cgti: BuiltinName = "__builtin_si_cgti"; break;
+ case Intrinsic::spu_si_cgx: BuiltinName = "__builtin_si_cgx"; break;
+ case Intrinsic::spu_si_clgt: BuiltinName = "__builtin_si_clgt"; break;
+ case Intrinsic::spu_si_clgtb: BuiltinName = "__builtin_si_clgtb"; break;
+ case Intrinsic::spu_si_clgtbi: BuiltinName = "__builtin_si_clgtbi"; break;
+ case Intrinsic::spu_si_clgth: BuiltinName = "__builtin_si_clgth"; break;
+ case Intrinsic::spu_si_clgthi: BuiltinName = "__builtin_si_clgthi"; break;
+ case Intrinsic::spu_si_clgti: BuiltinName = "__builtin_si_clgti"; break;
+ case Intrinsic::spu_si_dfa: BuiltinName = "__builtin_si_dfa"; break;
+ case Intrinsic::spu_si_dfm: BuiltinName = "__builtin_si_dfm"; break;
+ case Intrinsic::spu_si_dfma: BuiltinName = "__builtin_si_dfma"; break;
+ case Intrinsic::spu_si_dfms: BuiltinName = "__builtin_si_dfms"; break;
+ case Intrinsic::spu_si_dfnma: BuiltinName = "__builtin_si_dfnma"; break;
+ case Intrinsic::spu_si_dfnms: BuiltinName = "__builtin_si_dfnms"; break;
+ case Intrinsic::spu_si_dfs: BuiltinName = "__builtin_si_dfs"; break;
+ case Intrinsic::spu_si_fa: BuiltinName = "__builtin_si_fa"; break;
+ case Intrinsic::spu_si_fceq: BuiltinName = "__builtin_si_fceq"; break;
+ case Intrinsic::spu_si_fcgt: BuiltinName = "__builtin_si_fcgt"; break;
+ case Intrinsic::spu_si_fcmeq: BuiltinName = "__builtin_si_fcmeq"; break;
+ case Intrinsic::spu_si_fcmgt: BuiltinName = "__builtin_si_fcmgt"; break;
+ case Intrinsic::spu_si_fm: BuiltinName = "__builtin_si_fm"; break;
+ case Intrinsic::spu_si_fma: BuiltinName = "__builtin_si_fma"; break;
+ case Intrinsic::spu_si_fms: BuiltinName = "__builtin_si_fms"; break;
+ case Intrinsic::spu_si_fnms: BuiltinName = "__builtin_si_fnms"; break;
+ case Intrinsic::spu_si_fs: BuiltinName = "__builtin_si_fs"; break;
+ case Intrinsic::spu_si_fsmbi: BuiltinName = "__builtin_si_fsmbi"; break;
+ case Intrinsic::spu_si_mpy: BuiltinName = "__builtin_si_mpy"; break;
+ case Intrinsic::spu_si_mpya: BuiltinName = "__builtin_si_mpya"; break;
+ case Intrinsic::spu_si_mpyh: BuiltinName = "__builtin_si_mpyh"; break;
+ case Intrinsic::spu_si_mpyhh: BuiltinName = "__builtin_si_mpyhh"; break;
+ case Intrinsic::spu_si_mpyhha: BuiltinName = "__builtin_si_mpyhha"; break;
+ case Intrinsic::spu_si_mpyhhau: BuiltinName = "__builtin_si_mpyhhau"; break;
+ case Intrinsic::spu_si_mpyhhu: BuiltinName = "__builtin_si_mpyhhu"; break;
+ case Intrinsic::spu_si_mpyi: BuiltinName = "__builtin_si_mpyi"; break;
+ case Intrinsic::spu_si_mpys: BuiltinName = "__builtin_si_mpys"; break;
+ case Intrinsic::spu_si_mpyu: BuiltinName = "__builtin_si_mpyu"; break;
+ case Intrinsic::spu_si_mpyui: BuiltinName = "__builtin_si_mpyui"; break;
+ case Intrinsic::spu_si_nand: BuiltinName = "__builtin_si_nand"; break;
+ case Intrinsic::spu_si_nor: BuiltinName = "__builtin_si_nor"; break;
+ case Intrinsic::spu_si_or: BuiltinName = "__builtin_si_or"; break;
+ case Intrinsic::spu_si_orbi: BuiltinName = "__builtin_si_orbi"; break;
+ case Intrinsic::spu_si_orc: BuiltinName = "__builtin_si_orc"; break;
+ case Intrinsic::spu_si_orhi: BuiltinName = "__builtin_si_orhi"; break;
+ case Intrinsic::spu_si_ori: BuiltinName = "__builtin_si_ori"; break;
+ case Intrinsic::spu_si_sf: BuiltinName = "__builtin_si_sf"; break;
+ case Intrinsic::spu_si_sfh: BuiltinName = "__builtin_si_sfh"; break;
+ case Intrinsic::spu_si_sfhi: BuiltinName = "__builtin_si_sfhi"; break;
+ case Intrinsic::spu_si_sfi: BuiltinName = "__builtin_si_sfi"; break;
+ case Intrinsic::spu_si_sfx: BuiltinName = "__builtin_si_sfx"; break;
+ case Intrinsic::spu_si_shli: BuiltinName = "__builtin_si_shli"; break;
+ case Intrinsic::spu_si_shlqbi: BuiltinName = "__builtin_si_shlqbi"; break;
+ case Intrinsic::spu_si_shlqbii: BuiltinName = "__builtin_si_shlqbii"; break;
+ case Intrinsic::spu_si_shlqby: BuiltinName = "__builtin_si_shlqby"; break;
+ case Intrinsic::spu_si_shlqbyi: BuiltinName = "__builtin_si_shlqbyi"; break;
+ case Intrinsic::spu_si_xor: BuiltinName = "__builtin_si_xor"; break;
+ case Intrinsic::spu_si_xorbi: BuiltinName = "__builtin_si_xorbi"; break;
+ case Intrinsic::spu_si_xorhi: BuiltinName = "__builtin_si_xorhi"; break;
+ case Intrinsic::spu_si_xori: BuiltinName = "__builtin_si_xori"; break;
+ case Intrinsic::stackrestore: BuiltinName = "__builtin_stack_restore"; break;
+ case Intrinsic::stacksave: BuiltinName = "__builtin_stack_save"; break;
+ case Intrinsic::trap: BuiltinName = "__builtin_trap"; break;
+ case Intrinsic::x86_mmx_emms: BuiltinName = "__builtin_ia32_emms"; break;
+ case Intrinsic::x86_mmx_femms: BuiltinName = "__builtin_ia32_femms"; break;
+ case Intrinsic::x86_mmx_maskmovq: BuiltinName = "__builtin_ia32_maskmovq"; break;
+ case Intrinsic::x86_mmx_movnt_dq: BuiltinName = "__builtin_ia32_movntq"; break;
+ case Intrinsic::x86_mmx_packssdw: BuiltinName = "__builtin_ia32_packssdw"; break;
+ case Intrinsic::x86_mmx_packsswb: BuiltinName = "__builtin_ia32_packsswb"; break;
+ case Intrinsic::x86_mmx_packuswb: BuiltinName = "__builtin_ia32_packuswb"; break;
+ case Intrinsic::x86_mmx_padds_b: BuiltinName = "__builtin_ia32_paddsb"; break;
+ case Intrinsic::x86_mmx_padds_w: BuiltinName = "__builtin_ia32_paddsw"; break;
+ case Intrinsic::x86_mmx_paddus_b: BuiltinName = "__builtin_ia32_paddusb"; break;
+ case Intrinsic::x86_mmx_paddus_w: BuiltinName = "__builtin_ia32_paddusw"; break;
+ case Intrinsic::x86_mmx_pavg_b: BuiltinName = "__builtin_ia32_pavgb"; break;
+ case Intrinsic::x86_mmx_pavg_w: BuiltinName = "__builtin_ia32_pavgw"; break;
+ case Intrinsic::x86_mmx_pcmpeq_b: BuiltinName = "__builtin_ia32_pcmpeqb"; break;
+ case Intrinsic::x86_mmx_pcmpeq_d: BuiltinName = "__builtin_ia32_pcmpeqd"; break;
+ case Intrinsic::x86_mmx_pcmpeq_w: BuiltinName = "__builtin_ia32_pcmpeqw"; break;
+ case Intrinsic::x86_mmx_pcmpgt_b: BuiltinName = "__builtin_ia32_pcmpgtb"; break;
+ case Intrinsic::x86_mmx_pcmpgt_d: BuiltinName = "__builtin_ia32_pcmpgtd"; break;
+ case Intrinsic::x86_mmx_pcmpgt_w: BuiltinName = "__builtin_ia32_pcmpgtw"; break;
+ case Intrinsic::x86_mmx_pmadd_wd: BuiltinName = "__builtin_ia32_pmaddwd"; break;
+ case Intrinsic::x86_mmx_pmaxs_w: BuiltinName = "__builtin_ia32_pmaxsw"; break;
+ case Intrinsic::x86_mmx_pmaxu_b: BuiltinName = "__builtin_ia32_pmaxub"; break;
+ case Intrinsic::x86_mmx_pmins_w: BuiltinName = "__builtin_ia32_pminsw"; break;
+ case Intrinsic::x86_mmx_pminu_b: BuiltinName = "__builtin_ia32_pminub"; break;
+ case Intrinsic::x86_mmx_pmovmskb: BuiltinName = "__builtin_ia32_pmovmskb"; break;
+ case Intrinsic::x86_mmx_pmulh_w: BuiltinName = "__builtin_ia32_pmulhw"; break;
+ case Intrinsic::x86_mmx_pmulhu_w: BuiltinName = "__builtin_ia32_pmulhuw"; break;
+ case Intrinsic::x86_mmx_pmulu_dq: BuiltinName = "__builtin_ia32_pmuludq"; break;
+ case Intrinsic::x86_mmx_psad_bw: BuiltinName = "__builtin_ia32_psadbw"; break;
+ case Intrinsic::x86_mmx_psll_d: BuiltinName = "__builtin_ia32_pslld"; break;
+ case Intrinsic::x86_mmx_psll_q: BuiltinName = "__builtin_ia32_psllq"; break;
+ case Intrinsic::x86_mmx_psll_w: BuiltinName = "__builtin_ia32_psllw"; break;
+ case Intrinsic::x86_mmx_pslli_d: BuiltinName = "__builtin_ia32_pslldi"; break;
+ case Intrinsic::x86_mmx_pslli_q: BuiltinName = "__builtin_ia32_psllqi"; break;
+ case Intrinsic::x86_mmx_pslli_w: BuiltinName = "__builtin_ia32_psllwi"; break;
+ case Intrinsic::x86_mmx_psra_d: BuiltinName = "__builtin_ia32_psrad"; break;
+ case Intrinsic::x86_mmx_psra_w: BuiltinName = "__builtin_ia32_psraw"; break;
+ case Intrinsic::x86_mmx_psrai_d: BuiltinName = "__builtin_ia32_psradi"; break;
+ case Intrinsic::x86_mmx_psrai_w: BuiltinName = "__builtin_ia32_psrawi"; break;
+ case Intrinsic::x86_mmx_psrl_d: BuiltinName = "__builtin_ia32_psrld"; break;
+ case Intrinsic::x86_mmx_psrl_q: BuiltinName = "__builtin_ia32_psrlq"; break;
+ case Intrinsic::x86_mmx_psrl_w: BuiltinName = "__builtin_ia32_psrlw"; break;
+ case Intrinsic::x86_mmx_psrli_d: BuiltinName = "__builtin_ia32_psrldi"; break;
+ case Intrinsic::x86_mmx_psrli_q: BuiltinName = "__builtin_ia32_psrlqi"; break;
+ case Intrinsic::x86_mmx_psrli_w: BuiltinName = "__builtin_ia32_psrlwi"; break;
+ case Intrinsic::x86_mmx_psubs_b: BuiltinName = "__builtin_ia32_psubsb"; break;
+ case Intrinsic::x86_mmx_psubs_w: BuiltinName = "__builtin_ia32_psubsw"; break;
+ case Intrinsic::x86_mmx_psubus_b: BuiltinName = "__builtin_ia32_psubusb"; break;
+ case Intrinsic::x86_mmx_psubus_w: BuiltinName = "__builtin_ia32_psubusw"; break;
+ case Intrinsic::x86_sse2_add_sd: BuiltinName = "__builtin_ia32_addsd"; break;
+ case Intrinsic::x86_sse2_clflush: BuiltinName = "__builtin_ia32_clflush"; break;
+ case Intrinsic::x86_sse2_comieq_sd: BuiltinName = "__builtin_ia32_comisdeq"; break;
+ case Intrinsic::x86_sse2_comige_sd: BuiltinName = "__builtin_ia32_comisdge"; break;
+ case Intrinsic::x86_sse2_comigt_sd: BuiltinName = "__builtin_ia32_comisdgt"; break;
+ case Intrinsic::x86_sse2_comile_sd: BuiltinName = "__builtin_ia32_comisdle"; break;
+ case Intrinsic::x86_sse2_comilt_sd: BuiltinName = "__builtin_ia32_comisdlt"; break;
+ case Intrinsic::x86_sse2_comineq_sd: BuiltinName = "__builtin_ia32_comisdneq"; break;
+ case Intrinsic::x86_sse2_cvtdq2pd: BuiltinName = "__builtin_ia32_cvtdq2pd"; break;
+ case Intrinsic::x86_sse2_cvtdq2ps: BuiltinName = "__builtin_ia32_cvtdq2ps"; break;
+ case Intrinsic::x86_sse2_cvtpd2dq: BuiltinName = "__builtin_ia32_cvtpd2dq"; break;
+ case Intrinsic::x86_sse2_cvtpd2ps: BuiltinName = "__builtin_ia32_cvtpd2ps"; break;
+ case Intrinsic::x86_sse2_cvtps2dq: BuiltinName = "__builtin_ia32_cvtps2dq"; break;
+ case Intrinsic::x86_sse2_cvtps2pd: BuiltinName = "__builtin_ia32_cvtps2pd"; break;
+ case Intrinsic::x86_sse2_cvtsd2si: BuiltinName = "__builtin_ia32_cvtsd2si"; break;
+ case Intrinsic::x86_sse2_cvtsd2si64: BuiltinName = "__builtin_ia32_cvtsd2si64"; break;
+ case Intrinsic::x86_sse2_cvtsd2ss: BuiltinName = "__builtin_ia32_cvtsd2ss"; break;
+ case Intrinsic::x86_sse2_cvtsi2sd: BuiltinName = "__builtin_ia32_cvtsi2sd"; break;
+ case Intrinsic::x86_sse2_cvtsi642sd: BuiltinName = "__builtin_ia32_cvtsi642sd"; break;
+ case Intrinsic::x86_sse2_cvtss2sd: BuiltinName = "__builtin_ia32_cvtss2sd"; break;
+ case Intrinsic::x86_sse2_cvttpd2dq: BuiltinName = "__builtin_ia32_cvttpd2dq"; break;
+ case Intrinsic::x86_sse2_cvttps2dq: BuiltinName = "__builtin_ia32_cvttps2dq"; break;
+ case Intrinsic::x86_sse2_cvttsd2si: BuiltinName = "__builtin_ia32_cvttsd2si"; break;
+ case Intrinsic::x86_sse2_cvttsd2si64: BuiltinName = "__builtin_ia32_cvttsd2si64"; break;
+ case Intrinsic::x86_sse2_div_sd: BuiltinName = "__builtin_ia32_divsd"; break;
+ case Intrinsic::x86_sse2_lfence: BuiltinName = "__builtin_ia32_lfence"; break;
+ case Intrinsic::x86_sse2_loadu_dq: BuiltinName = "__builtin_ia32_loaddqu"; break;
+ case Intrinsic::x86_sse2_loadu_pd: BuiltinName = "__builtin_ia32_loadupd"; break;
+ case Intrinsic::x86_sse2_maskmov_dqu: BuiltinName = "__builtin_ia32_maskmovdqu"; break;
+ case Intrinsic::x86_sse2_max_pd: BuiltinName = "__builtin_ia32_maxpd"; break;
+ case Intrinsic::x86_sse2_max_sd: BuiltinName = "__builtin_ia32_maxsd"; break;
+ case Intrinsic::x86_sse2_mfence: BuiltinName = "__builtin_ia32_mfence"; break;
+ case Intrinsic::x86_sse2_min_pd: BuiltinName = "__builtin_ia32_minpd"; break;
+ case Intrinsic::x86_sse2_min_sd: BuiltinName = "__builtin_ia32_minsd"; break;
+ case Intrinsic::x86_sse2_movmsk_pd: BuiltinName = "__builtin_ia32_movmskpd"; break;
+ case Intrinsic::x86_sse2_movnt_dq: BuiltinName = "__builtin_ia32_movntdq"; break;
+ case Intrinsic::x86_sse2_movnt_i: BuiltinName = "__builtin_ia32_movnti"; break;
+ case Intrinsic::x86_sse2_movnt_pd: BuiltinName = "__builtin_ia32_movntpd"; break;
+ case Intrinsic::x86_sse2_mul_sd: BuiltinName = "__builtin_ia32_mulsd"; break;
+ case Intrinsic::x86_sse2_packssdw_128: BuiltinName = "__builtin_ia32_packssdw128"; break;
+ case Intrinsic::x86_sse2_packsswb_128: BuiltinName = "__builtin_ia32_packsswb128"; break;
+ case Intrinsic::x86_sse2_packuswb_128: BuiltinName = "__builtin_ia32_packuswb128"; break;
+ case Intrinsic::x86_sse2_padds_b: BuiltinName = "__builtin_ia32_paddsb128"; break;
+ case Intrinsic::x86_sse2_padds_w: BuiltinName = "__builtin_ia32_paddsw128"; break;
+ case Intrinsic::x86_sse2_paddus_b: BuiltinName = "__builtin_ia32_paddusb128"; break;
+ case Intrinsic::x86_sse2_paddus_w: BuiltinName = "__builtin_ia32_paddusw128"; break;
+ case Intrinsic::x86_sse2_pavg_b: BuiltinName = "__builtin_ia32_pavgb128"; break;
+ case Intrinsic::x86_sse2_pavg_w: BuiltinName = "__builtin_ia32_pavgw128"; break;
+ case Intrinsic::x86_sse2_pcmpeq_b: BuiltinName = "__builtin_ia32_pcmpeqb128"; break;
+ case Intrinsic::x86_sse2_pcmpeq_d: BuiltinName = "__builtin_ia32_pcmpeqd128"; break;
+ case Intrinsic::x86_sse2_pcmpeq_w: BuiltinName = "__builtin_ia32_pcmpeqw128"; break;
+ case Intrinsic::x86_sse2_pcmpgt_b: BuiltinName = "__builtin_ia32_pcmpgtb128"; break;
+ case Intrinsic::x86_sse2_pcmpgt_d: BuiltinName = "__builtin_ia32_pcmpgtd128"; break;
+ case Intrinsic::x86_sse2_pcmpgt_w: BuiltinName = "__builtin_ia32_pcmpgtw128"; break;
+ case Intrinsic::x86_sse2_pmadd_wd: BuiltinName = "__builtin_ia32_pmaddwd128"; break;
+ case Intrinsic::x86_sse2_pmaxs_w: BuiltinName = "__builtin_ia32_pmaxsw128"; break;
+ case Intrinsic::x86_sse2_pmaxu_b: BuiltinName = "__builtin_ia32_pmaxub128"; break;
+ case Intrinsic::x86_sse2_pmins_w: BuiltinName = "__builtin_ia32_pminsw128"; break;
+ case Intrinsic::x86_sse2_pminu_b: BuiltinName = "__builtin_ia32_pminub128"; break;
+ case Intrinsic::x86_sse2_pmovmskb_128: BuiltinName = "__builtin_ia32_pmovmskb128"; break;
+ case Intrinsic::x86_sse2_pmulh_w: BuiltinName = "__builtin_ia32_pmulhw128"; break;
+ case Intrinsic::x86_sse2_pmulhu_w: BuiltinName = "__builtin_ia32_pmulhuw128"; break;
+ case Intrinsic::x86_sse2_pmulu_dq: BuiltinName = "__builtin_ia32_pmuludq128"; break;
+ case Intrinsic::x86_sse2_psad_bw: BuiltinName = "__builtin_ia32_psadbw128"; break;
+ case Intrinsic::x86_sse2_psll_d: BuiltinName = "__builtin_ia32_pslld128"; break;
+ case Intrinsic::x86_sse2_psll_dq: BuiltinName = "__builtin_ia32_pslldqi128"; break;
+ case Intrinsic::x86_sse2_psll_dq_bs: BuiltinName = "__builtin_ia32_pslldqi128_byteshift"; break;
+ case Intrinsic::x86_sse2_psll_q: BuiltinName = "__builtin_ia32_psllq128"; break;
+ case Intrinsic::x86_sse2_psll_w: BuiltinName = "__builtin_ia32_psllw128"; break;
+ case Intrinsic::x86_sse2_pslli_d: BuiltinName = "__builtin_ia32_pslldi128"; break;
+ case Intrinsic::x86_sse2_pslli_q: BuiltinName = "__builtin_ia32_psllqi128"; break;
+ case Intrinsic::x86_sse2_pslli_w: BuiltinName = "__builtin_ia32_psllwi128"; break;
+ case Intrinsic::x86_sse2_psra_d: BuiltinName = "__builtin_ia32_psrad128"; break;
+ case Intrinsic::x86_sse2_psra_w: BuiltinName = "__builtin_ia32_psraw128"; break;
+ case Intrinsic::x86_sse2_psrai_d: BuiltinName = "__builtin_ia32_psradi128"; break;
+ case Intrinsic::x86_sse2_psrai_w: BuiltinName = "__builtin_ia32_psrawi128"; break;
+ case Intrinsic::x86_sse2_psrl_d: BuiltinName = "__builtin_ia32_psrld128"; break;
+ case Intrinsic::x86_sse2_psrl_dq: BuiltinName = "__builtin_ia32_psrldqi128"; break;
+ case Intrinsic::x86_sse2_psrl_dq_bs: BuiltinName = "__builtin_ia32_psrldqi128_byteshift"; break;
+ case Intrinsic::x86_sse2_psrl_q: BuiltinName = "__builtin_ia32_psrlq128"; break;
+ case Intrinsic::x86_sse2_psrl_w: BuiltinName = "__builtin_ia32_psrlw128"; break;
+ case Intrinsic::x86_sse2_psrli_d: BuiltinName = "__builtin_ia32_psrldi128"; break;
+ case Intrinsic::x86_sse2_psrli_q: BuiltinName = "__builtin_ia32_psrlqi128"; break;
+ case Intrinsic::x86_sse2_psrli_w: BuiltinName = "__builtin_ia32_psrlwi128"; break;
+ case Intrinsic::x86_sse2_psubs_b: BuiltinName = "__builtin_ia32_psubsb128"; break;
+ case Intrinsic::x86_sse2_psubs_w: BuiltinName = "__builtin_ia32_psubsw128"; break;
+ case Intrinsic::x86_sse2_psubus_b: BuiltinName = "__builtin_ia32_psubusb128"; break;
+ case Intrinsic::x86_sse2_psubus_w: BuiltinName = "__builtin_ia32_psubusw128"; break;
+ case Intrinsic::x86_sse2_sqrt_pd: BuiltinName = "__builtin_ia32_sqrtpd"; break;
+ case Intrinsic::x86_sse2_sqrt_sd: BuiltinName = "__builtin_ia32_sqrtsd"; break;
+ case Intrinsic::x86_sse2_storel_dq: BuiltinName = "__builtin_ia32_storelv4si"; break;
+ case Intrinsic::x86_sse2_storeu_dq: BuiltinName = "__builtin_ia32_storedqu"; break;
+ case Intrinsic::x86_sse2_storeu_pd: BuiltinName = "__builtin_ia32_storeupd"; break;
+ case Intrinsic::x86_sse2_sub_sd: BuiltinName = "__builtin_ia32_subsd"; break;
+ case Intrinsic::x86_sse2_ucomieq_sd: BuiltinName = "__builtin_ia32_ucomisdeq"; break;
+ case Intrinsic::x86_sse2_ucomige_sd: BuiltinName = "__builtin_ia32_ucomisdge"; break;
+ case Intrinsic::x86_sse2_ucomigt_sd: BuiltinName = "__builtin_ia32_ucomisdgt"; break;
+ case Intrinsic::x86_sse2_ucomile_sd: BuiltinName = "__builtin_ia32_ucomisdle"; break;
+ case Intrinsic::x86_sse2_ucomilt_sd: BuiltinName = "__builtin_ia32_ucomisdlt"; break;
+ case Intrinsic::x86_sse2_ucomineq_sd: BuiltinName = "__builtin_ia32_ucomisdneq"; break;
+ case Intrinsic::x86_sse3_addsub_pd: BuiltinName = "__builtin_ia32_addsubpd"; break;
+ case Intrinsic::x86_sse3_addsub_ps: BuiltinName = "__builtin_ia32_addsubps"; break;
+ case Intrinsic::x86_sse3_hadd_pd: BuiltinName = "__builtin_ia32_haddpd"; break;
+ case Intrinsic::x86_sse3_hadd_ps: BuiltinName = "__builtin_ia32_haddps"; break;
+ case Intrinsic::x86_sse3_hsub_pd: BuiltinName = "__builtin_ia32_hsubpd"; break;
+ case Intrinsic::x86_sse3_hsub_ps: BuiltinName = "__builtin_ia32_hsubps"; break;
+ case Intrinsic::x86_sse3_ldu_dq: BuiltinName = "__builtin_ia32_lddqu"; break;
+ case Intrinsic::x86_sse3_monitor: BuiltinName = "__builtin_ia32_monitor"; break;
+ case Intrinsic::x86_sse3_mwait: BuiltinName = "__builtin_ia32_mwait"; break;
+ case Intrinsic::x86_sse41_blendpd: BuiltinName = "__builtin_ia32_blendpd"; break;
+ case Intrinsic::x86_sse41_blendps: BuiltinName = "__builtin_ia32_blendps"; break;
+ case Intrinsic::x86_sse41_blendvpd: BuiltinName = "__builtin_ia32_blendvpd"; break;
+ case Intrinsic::x86_sse41_blendvps: BuiltinName = "__builtin_ia32_blendvps"; break;
+ case Intrinsic::x86_sse41_dppd: BuiltinName = "__builtin_ia32_dppd"; break;
+ case Intrinsic::x86_sse41_dpps: BuiltinName = "__builtin_ia32_dpps"; break;
+ case Intrinsic::x86_sse41_extractps: BuiltinName = "__builtin_ia32_extractps128"; break;
+ case Intrinsic::x86_sse41_insertps: BuiltinName = "__builtin_ia32_insertps128"; break;
+ case Intrinsic::x86_sse41_movntdqa: BuiltinName = "__builtin_ia32_movntdqa"; break;
+ case Intrinsic::x86_sse41_mpsadbw: BuiltinName = "__builtin_ia32_mpsadbw128"; break;
+ case Intrinsic::x86_sse41_packusdw: BuiltinName = "__builtin_ia32_packusdw128"; break;
+ case Intrinsic::x86_sse41_pblendvb: BuiltinName = "__builtin_ia32_pblendvb128"; break;
+ case Intrinsic::x86_sse41_pblendw: BuiltinName = "__builtin_ia32_pblendw128"; break;
+ case Intrinsic::x86_sse41_pcmpeqq: BuiltinName = "__builtin_ia32_pcmpeqq"; break;
+ case Intrinsic::x86_sse41_phminposuw: BuiltinName = "__builtin_ia32_phminposuw128"; break;
+ case Intrinsic::x86_sse41_pmaxsb: BuiltinName = "__builtin_ia32_pmaxsb128"; break;
+ case Intrinsic::x86_sse41_pmaxsd: BuiltinName = "__builtin_ia32_pmaxsd128"; break;
+ case Intrinsic::x86_sse41_pmaxud: BuiltinName = "__builtin_ia32_pmaxud128"; break;
+ case Intrinsic::x86_sse41_pmaxuw: BuiltinName = "__builtin_ia32_pmaxuw128"; break;
+ case Intrinsic::x86_sse41_pminsb: BuiltinName = "__builtin_ia32_pminsb128"; break;
+ case Intrinsic::x86_sse41_pminsd: BuiltinName = "__builtin_ia32_pminsd128"; break;
+ case Intrinsic::x86_sse41_pminud: BuiltinName = "__builtin_ia32_pminud128"; break;
+ case Intrinsic::x86_sse41_pminuw: BuiltinName = "__builtin_ia32_pminuw128"; break;
+ case Intrinsic::x86_sse41_pmovsxbd: BuiltinName = "__builtin_ia32_pmovsxbd128"; break;
+ case Intrinsic::x86_sse41_pmovsxbq: BuiltinName = "__builtin_ia32_pmovsxbq128"; break;
+ case Intrinsic::x86_sse41_pmovsxbw: BuiltinName = "__builtin_ia32_pmovsxbw128"; break;
+ case Intrinsic::x86_sse41_pmovsxdq: BuiltinName = "__builtin_ia32_pmovsxdq128"; break;
+ case Intrinsic::x86_sse41_pmovsxwd: BuiltinName = "__builtin_ia32_pmovsxwd128"; break;
+ case Intrinsic::x86_sse41_pmovsxwq: BuiltinName = "__builtin_ia32_pmovsxwq128"; break;
+ case Intrinsic::x86_sse41_pmovzxbd: BuiltinName = "__builtin_ia32_pmovzxbd128"; break;
+ case Intrinsic::x86_sse41_pmovzxbq: BuiltinName = "__builtin_ia32_pmovzxbq128"; break;
+ case Intrinsic::x86_sse41_pmovzxbw: BuiltinName = "__builtin_ia32_pmovzxbw128"; break;
+ case Intrinsic::x86_sse41_pmovzxdq: BuiltinName = "__builtin_ia32_pmovzxdq128"; break;
+ case Intrinsic::x86_sse41_pmovzxwd: BuiltinName = "__builtin_ia32_pmovzxwd128"; break;
+ case Intrinsic::x86_sse41_pmovzxwq: BuiltinName = "__builtin_ia32_pmovzxwq128"; break;
+ case Intrinsic::x86_sse41_pmuldq: BuiltinName = "__builtin_ia32_pmuldq128"; break;
+ case Intrinsic::x86_sse41_pmulld: BuiltinName = "__builtin_ia32_pmulld128"; break;
+ case Intrinsic::x86_sse41_ptestc: BuiltinName = "__builtin_ia32_ptestc128"; break;
+ case Intrinsic::x86_sse41_ptestnzc: BuiltinName = "__builtin_ia32_ptestnzc128"; break;
+ case Intrinsic::x86_sse41_ptestz: BuiltinName = "__builtin_ia32_ptestz128"; break;
+ case Intrinsic::x86_sse41_round_pd: BuiltinName = "__builtin_ia32_roundpd"; break;
+ case Intrinsic::x86_sse41_round_ps: BuiltinName = "__builtin_ia32_roundps"; break;
+ case Intrinsic::x86_sse41_round_sd: BuiltinName = "__builtin_ia32_roundsd"; break;
+ case Intrinsic::x86_sse41_round_ss: BuiltinName = "__builtin_ia32_roundss"; break;
+ case Intrinsic::x86_sse42_crc32_16: BuiltinName = "__builtin_ia32_crc32hi"; break;
+ case Intrinsic::x86_sse42_crc32_32: BuiltinName = "__builtin_ia32_crc32si"; break;
+ case Intrinsic::x86_sse42_crc32_64: BuiltinName = "__builtin_ia32_crc32di"; break;
+ case Intrinsic::x86_sse42_crc32_8: BuiltinName = "__builtin_ia32_crc32qi"; break;
+ case Intrinsic::x86_sse42_pcmpestri128: BuiltinName = "__builtin_ia32_pcmpestri128"; break;
+ case Intrinsic::x86_sse42_pcmpestria128: BuiltinName = "__builtin_ia32_pcmpestria128"; break;
+ case Intrinsic::x86_sse42_pcmpestric128: BuiltinName = "__builtin_ia32_pcmpestric128"; break;
+ case Intrinsic::x86_sse42_pcmpestrio128: BuiltinName = "__builtin_ia32_pcmpestrio128"; break;
+ case Intrinsic::x86_sse42_pcmpestris128: BuiltinName = "__builtin_ia32_pcmpestris128"; break;
+ case Intrinsic::x86_sse42_pcmpestriz128: BuiltinName = "__builtin_ia32_pcmpestriz128"; break;
+ case Intrinsic::x86_sse42_pcmpestrm128: BuiltinName = "__builtin_ia32_pcmpestrm128"; break;
+ case Intrinsic::x86_sse42_pcmpgtq: BuiltinName = "__builtin_ia32_pcmpgtq"; break;
+ case Intrinsic::x86_sse42_pcmpistri128: BuiltinName = "__builtin_ia32_pcmpistri128"; break;
+ case Intrinsic::x86_sse42_pcmpistria128: BuiltinName = "__builtin_ia32_pcmpistria128"; break;
+ case Intrinsic::x86_sse42_pcmpistric128: BuiltinName = "__builtin_ia32_pcmpistric128"; break;
+ case Intrinsic::x86_sse42_pcmpistrio128: BuiltinName = "__builtin_ia32_pcmpistrio128"; break;
+ case Intrinsic::x86_sse42_pcmpistris128: BuiltinName = "__builtin_ia32_pcmpistris128"; break;
+ case Intrinsic::x86_sse42_pcmpistriz128: BuiltinName = "__builtin_ia32_pcmpistriz128"; break;
+ case Intrinsic::x86_sse42_pcmpistrm128: BuiltinName = "__builtin_ia32_pcmpistrm128"; break;
+ case Intrinsic::x86_sse_add_ss: BuiltinName = "__builtin_ia32_addss"; break;
+ case Intrinsic::x86_sse_comieq_ss: BuiltinName = "__builtin_ia32_comieq"; break;
+ case Intrinsic::x86_sse_comige_ss: BuiltinName = "__builtin_ia32_comige"; break;
+ case Intrinsic::x86_sse_comigt_ss: BuiltinName = "__builtin_ia32_comigt"; break;
+ case Intrinsic::x86_sse_comile_ss: BuiltinName = "__builtin_ia32_comile"; break;
+ case Intrinsic::x86_sse_comilt_ss: BuiltinName = "__builtin_ia32_comilt"; break;
+ case Intrinsic::x86_sse_comineq_ss: BuiltinName = "__builtin_ia32_comineq"; break;
+ case Intrinsic::x86_sse_cvtpd2pi: BuiltinName = "__builtin_ia32_cvtpd2pi"; break;
+ case Intrinsic::x86_sse_cvtpi2pd: BuiltinName = "__builtin_ia32_cvtpi2pd"; break;
+ case Intrinsic::x86_sse_cvtpi2ps: BuiltinName = "__builtin_ia32_cvtpi2ps"; break;
+ case Intrinsic::x86_sse_cvtps2pi: BuiltinName = "__builtin_ia32_cvtps2pi"; break;
+ case Intrinsic::x86_sse_cvtsi2ss: BuiltinName = "__builtin_ia32_cvtsi2ss"; break;
+ case Intrinsic::x86_sse_cvtsi642ss: BuiltinName = "__builtin_ia32_cvtsi642ss"; break;
+ case Intrinsic::x86_sse_cvtss2si: BuiltinName = "__builtin_ia32_cvtss2si"; break;
+ case Intrinsic::x86_sse_cvtss2si64: BuiltinName = "__builtin_ia32_cvtss2si64"; break;
+ case Intrinsic::x86_sse_cvttpd2pi: BuiltinName = "__builtin_ia32_cvttpd2pi"; break;
+ case Intrinsic::x86_sse_cvttps2pi: BuiltinName = "__builtin_ia32_cvttps2pi"; break;
+ case Intrinsic::x86_sse_cvttss2si: BuiltinName = "__builtin_ia32_cvttss2si"; break;
+ case Intrinsic::x86_sse_cvttss2si64: BuiltinName = "__builtin_ia32_cvttss2si64"; break;
+ case Intrinsic::x86_sse_div_ss: BuiltinName = "__builtin_ia32_divss"; break;
+ case Intrinsic::x86_sse_loadu_ps: BuiltinName = "__builtin_ia32_loadups"; break;
+ case Intrinsic::x86_sse_max_ps: BuiltinName = "__builtin_ia32_maxps"; break;
+ case Intrinsic::x86_sse_max_ss: BuiltinName = "__builtin_ia32_maxss"; break;
+ case Intrinsic::x86_sse_min_ps: BuiltinName = "__builtin_ia32_minps"; break;
+ case Intrinsic::x86_sse_min_ss: BuiltinName = "__builtin_ia32_minss"; break;
+ case Intrinsic::x86_sse_movmsk_ps: BuiltinName = "__builtin_ia32_movmskps"; break;
+ case Intrinsic::x86_sse_movnt_ps: BuiltinName = "__builtin_ia32_movntps"; break;
+ case Intrinsic::x86_sse_mul_ss: BuiltinName = "__builtin_ia32_mulss"; break;
+ case Intrinsic::x86_sse_rcp_ps: BuiltinName = "__builtin_ia32_rcpps"; break;
+ case Intrinsic::x86_sse_rcp_ss: BuiltinName = "__builtin_ia32_rcpss"; break;
+ case Intrinsic::x86_sse_rsqrt_ps: BuiltinName = "__builtin_ia32_rsqrtps"; break;
+ case Intrinsic::x86_sse_rsqrt_ss: BuiltinName = "__builtin_ia32_rsqrtss"; break;
+ case Intrinsic::x86_sse_sfence: BuiltinName = "__builtin_ia32_sfence"; break;
+ case Intrinsic::x86_sse_sqrt_ps: BuiltinName = "__builtin_ia32_sqrtps"; break;
+ case Intrinsic::x86_sse_sqrt_ss: BuiltinName = "__builtin_ia32_sqrtss"; break;
+ case Intrinsic::x86_sse_storeu_ps: BuiltinName = "__builtin_ia32_storeups"; break;
+ case Intrinsic::x86_sse_sub_ss: BuiltinName = "__builtin_ia32_subss"; break;
+ case Intrinsic::x86_sse_ucomieq_ss: BuiltinName = "__builtin_ia32_ucomieq"; break;
+ case Intrinsic::x86_sse_ucomige_ss: BuiltinName = "__builtin_ia32_ucomige"; break;
+ case Intrinsic::x86_sse_ucomigt_ss: BuiltinName = "__builtin_ia32_ucomigt"; break;
+ case Intrinsic::x86_sse_ucomile_ss: BuiltinName = "__builtin_ia32_ucomile"; break;
+ case Intrinsic::x86_sse_ucomilt_ss: BuiltinName = "__builtin_ia32_ucomilt"; break;
+ case Intrinsic::x86_sse_ucomineq_ss: BuiltinName = "__builtin_ia32_ucomineq"; break;
+ case Intrinsic::x86_ssse3_pabs_b: BuiltinName = "__builtin_ia32_pabsb"; break;
+ case Intrinsic::x86_ssse3_pabs_b_128: BuiltinName = "__builtin_ia32_pabsb128"; break;
+ case Intrinsic::x86_ssse3_pabs_d: BuiltinName = "__builtin_ia32_pabsd"; break;
+ case Intrinsic::x86_ssse3_pabs_d_128: BuiltinName = "__builtin_ia32_pabsd128"; break;
+ case Intrinsic::x86_ssse3_pabs_w: BuiltinName = "__builtin_ia32_pabsw"; break;
+ case Intrinsic::x86_ssse3_pabs_w_128: BuiltinName = "__builtin_ia32_pabsw128"; break;
+ case Intrinsic::x86_ssse3_phadd_d: BuiltinName = "__builtin_ia32_phaddd"; break;
+ case Intrinsic::x86_ssse3_phadd_d_128: BuiltinName = "__builtin_ia32_phaddd128"; break;
+ case Intrinsic::x86_ssse3_phadd_sw: BuiltinName = "__builtin_ia32_phaddsw"; break;
+ case Intrinsic::x86_ssse3_phadd_sw_128: BuiltinName = "__builtin_ia32_phaddsw128"; break;
+ case Intrinsic::x86_ssse3_phadd_w: BuiltinName = "__builtin_ia32_phaddw"; break;
+ case Intrinsic::x86_ssse3_phadd_w_128: BuiltinName = "__builtin_ia32_phaddw128"; break;
+ case Intrinsic::x86_ssse3_phsub_d: BuiltinName = "__builtin_ia32_phsubd"; break;
+ case Intrinsic::x86_ssse3_phsub_d_128: BuiltinName = "__builtin_ia32_phsubd128"; break;
+ case Intrinsic::x86_ssse3_phsub_sw: BuiltinName = "__builtin_ia32_phsubsw"; break;
+ case Intrinsic::x86_ssse3_phsub_sw_128: BuiltinName = "__builtin_ia32_phsubsw128"; break;
+ case Intrinsic::x86_ssse3_phsub_w: BuiltinName = "__builtin_ia32_phsubw"; break;
+ case Intrinsic::x86_ssse3_phsub_w_128: BuiltinName = "__builtin_ia32_phsubw128"; break;
+ case Intrinsic::x86_ssse3_pmadd_ub_sw: BuiltinName = "__builtin_ia32_pmaddubsw"; break;
+ case Intrinsic::x86_ssse3_pmadd_ub_sw_128: BuiltinName = "__builtin_ia32_pmaddubsw128"; break;
+ case Intrinsic::x86_ssse3_pmul_hr_sw: BuiltinName = "__builtin_ia32_pmulhrsw"; break;
+ case Intrinsic::x86_ssse3_pmul_hr_sw_128: BuiltinName = "__builtin_ia32_pmulhrsw128"; break;
+ case Intrinsic::x86_ssse3_pshuf_b: BuiltinName = "__builtin_ia32_pshufb"; break;
+ case Intrinsic::x86_ssse3_pshuf_b_128: BuiltinName = "__builtin_ia32_pshufb128"; break;
+ case Intrinsic::x86_ssse3_psign_b: BuiltinName = "__builtin_ia32_psignb"; break;
+ case Intrinsic::x86_ssse3_psign_b_128: BuiltinName = "__builtin_ia32_psignb128"; break;
+ case Intrinsic::x86_ssse3_psign_d: BuiltinName = "__builtin_ia32_psignd"; break;
+ case Intrinsic::x86_ssse3_psign_d_128: BuiltinName = "__builtin_ia32_psignd128"; break;
+ case Intrinsic::x86_ssse3_psign_w: BuiltinName = "__builtin_ia32_psignw"; break;
+ case Intrinsic::x86_ssse3_psign_w_128: BuiltinName = "__builtin_ia32_psignw128"; break;
+ }
+#endif
+
+// Get the LLVM intrinsic that corresponds to a GCC builtin.
+// This is used by the C front-end. The GCC builtin name is passed
+// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed
+// in as TargetPrefix. The result is assigned to 'IntrinsicID'.
+#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
+Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix, const char *BuiltinName) {
+ Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic;
+ /* Target Independent Builtins */ {
+ switch (strlen(BuiltinName)) {
+ default: break;
+ case 14:
+ if (!memcmp(BuiltinName, "__builtin_trap", 14))
+ IntrinsicID = Intrinsic::trap;
+ break;
+ case 19:
+ if (!memcmp(BuiltinName, "__sync_fetch_and_or", 19))
+ IntrinsicID = Intrinsic::atomic_load_or;
+ break;
+ case 20:
+ if (!memcmp(BuiltinName, "__", 2)) {
+ switch (BuiltinName[2]) { // "__"
+ case 'b':
+ if (!memcmp(BuiltinName+3, "uiltin_", 7)) {
+ switch (BuiltinName[10]) { // "__builtin_"
+ case 'f':
+ if (!memcmp(BuiltinName+11, "lt_rounds", 9))
+ IntrinsicID = Intrinsic::flt_rounds;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+11, "tack_save", 9))
+ IntrinsicID = Intrinsic::stacksave;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+3, "ync_fetch_and_", 14)) {
+ switch (BuiltinName[17]) { // "__sync_fetch_and_"
+ case 'a':
+ switch (BuiltinName[18]) { // "__sync_fetch_and_a"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "d", 1))
+ IntrinsicID = Intrinsic::atomic_load_add;
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+19, "d", 1))
+ IntrinsicID = Intrinsic::atomic_load_and;
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[18]) { // "__sync_fetch_and_m"
+ case 'a':
+ if (!memcmp(BuiltinName+19, "x", 1))
+ IntrinsicID = Intrinsic::atomic_load_max;
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+19, "n", 1))
+ IntrinsicID = Intrinsic::atomic_load_min;
+ break;
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+18, "ub", 2))
+ IntrinsicID = Intrinsic::atomic_load_sub;
+ break;
+ case 'x':
+ if (!memcmp(BuiltinName+18, "or", 2))
+ IntrinsicID = Intrinsic::atomic_load_xor;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 21:
+ if (!memcmp(BuiltinName, "__", 2)) {
+ switch (BuiltinName[2]) { // "__"
+ case 'b':
+ if (!memcmp(BuiltinName+3, "uiltin_", 7)) {
+ switch (BuiltinName[10]) { // "__builtin_"
+ case 'o':
+ if (!memcmp(BuiltinName+11, "bject_size", 10))
+ IntrinsicID = Intrinsic::objectsize;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+11, "nwind_init", 10))
+ IntrinsicID = Intrinsic::eh_unwind_init;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+3, "ync_fetch_and_", 14)) {
+ switch (BuiltinName[17]) { // "__sync_fetch_and_"
+ case 'n':
+ if (!memcmp(BuiltinName+18, "and", 3))
+ IntrinsicID = Intrinsic::atomic_load_nand;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "m", 1)) {
+ switch (BuiltinName[19]) { // "__sync_fetch_and_um"
+ case 'a':
+ if (!memcmp(BuiltinName+20, "x", 1))
+ IntrinsicID = Intrinsic::atomic_load_umax;
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+20, "n", 1))
+ IntrinsicID = Intrinsic::atomic_load_umin;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 23:
+ if (!memcmp(BuiltinName, "__builtin_stack_restore", 23))
+ IntrinsicID = Intrinsic::stackrestore;
+ break;
+ case 24:
+ if (!memcmp(BuiltinName, "__sync_lock_test_and_set", 24))
+ IntrinsicID = Intrinsic::atomic_swap;
+ break;
+ case 25:
+ if (!memcmp(BuiltinName, "__builtin_init_trampoline", 25))
+ IntrinsicID = Intrinsic::init_trampoline;
+ break;
+ case 27:
+ if (!memcmp(BuiltinName, "__sync_val_compare_and_swap", 27))
+ IntrinsicID = Intrinsic::atomic_cmp_swap;
+ break;
+ case 29:
+ if (!memcmp(BuiltinName, "__builtin_llvm_memory_barrier", 29))
+ IntrinsicID = Intrinsic::memory_barrier;
+ break;
+ }
+ }
+ if (!strcmp(TargetPrefix, "alpha")) {
+ switch (strlen(BuiltinName)) {
+ default: break;
+ case 21:
+ if (!memcmp(BuiltinName, "__builtin_alpha_umulh", 21))
+ IntrinsicID = Intrinsic::alpha_umulh;
+ break;
+ }
+ }
+ if (!strcmp(TargetPrefix, "arm")) {
+ switch (strlen(BuiltinName)) {
+ default: break;
+ case 24:
+ if (!memcmp(BuiltinName, "__builtin_thread_pointer", 24))
+ IntrinsicID = Intrinsic::arm_thread_pointer;
+ break;
+ }
+ }
+ if (!strcmp(TargetPrefix, "ppc")) {
+ switch (strlen(BuiltinName)) {
+ default: break;
+ case 21:
+ if (!memcmp(BuiltinName, "__builtin_altivec_", 18)) {
+ switch (BuiltinName[18]) { // "__builtin_altivec_"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "s", 1)) {
+ switch (BuiltinName[20]) { // "__builtin_altivec_ds"
+ case 's':
+ IntrinsicID = Intrinsic::ppc_altivec_dss;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::ppc_altivec_dst;
+ break;
+ }
+ }
+ break;
+ case 'v':
+ if (!memcmp(BuiltinName+19, "s", 1)) {
+ switch (BuiltinName[20]) { // "__builtin_altivec_vs"
+ case 'l':
+ IntrinsicID = Intrinsic::ppc_altivec_vsl;
+ break;
+ case 'r':
+ IntrinsicID = Intrinsic::ppc_altivec_vsr;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 22:
+ if (!memcmp(BuiltinName, "__builtin_altivec_", 18)) {
+ switch (BuiltinName[18]) { // "__builtin_altivec_"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "stt", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_dstt;
+ break;
+ case 'v':
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'r':
+ if (!memcmp(BuiltinName+20, "l", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_altivec_vrl"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vrlb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vrlh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vrlw;
+ break;
+ }
+ }
+ break;
+ case 's':
+ switch (BuiltinName[20]) { // "__builtin_altivec_vs"
+ case 'l':
+ switch (BuiltinName[21]) { // "__builtin_altivec_vsl"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vslb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vslh;
+ break;
+ case 'o':
+ IntrinsicID = Intrinsic::ppc_altivec_vslo;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vslw;
+ break;
+ }
+ break;
+ case 'r':
+ switch (BuiltinName[21]) { // "__builtin_altivec_vsr"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vsrb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vsrh;
+ break;
+ case 'o':
+ IntrinsicID = Intrinsic::ppc_altivec_vsro;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vsrw;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 23:
+ if (!memcmp(BuiltinName, "__builtin_altivec_", 18)) {
+ switch (BuiltinName[18]) { // "__builtin_altivec_"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "stst", 4))
+ IntrinsicID = Intrinsic::ppc_altivec_dstst;
+ break;
+ case 'v':
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'c':
+ if (!memcmp(BuiltinName+20, "f", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_altivec_vcf"
+ case 's':
+ if (!memcmp(BuiltinName+22, "x", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vcfsx;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+22, "x", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vcfux;
+ break;
+ }
+ }
+ break;
+ case 'p':
+ if (!memcmp(BuiltinName+20, "kpx", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkpx;
+ break;
+ case 'r':
+ switch (BuiltinName[20]) { // "__builtin_altivec_vr"
+ case 'e':
+ if (!memcmp(BuiltinName+21, "fp", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vrefp;
+ break;
+ case 'f':
+ if (!memcmp(BuiltinName+21, "i", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vrfi"
+ case 'm':
+ IntrinsicID = Intrinsic::ppc_altivec_vrfim;
+ break;
+ case 'n':
+ IntrinsicID = Intrinsic::ppc_altivec_vrfin;
+ break;
+ case 'p':
+ IntrinsicID = Intrinsic::ppc_altivec_vrfip;
+ break;
+ case 'z':
+ IntrinsicID = Intrinsic::ppc_altivec_vrfiz;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+20, "ra", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vsra"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vsrab;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vsrah;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vsraw;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 24:
+ if (!memcmp(BuiltinName, "__builtin_altivec_", 18)) {
+ switch (BuiltinName[18]) { // "__builtin_altivec_"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "s", 1)) {
+ switch (BuiltinName[20]) { // "__builtin_altivec_ds"
+ case 's':
+ if (!memcmp(BuiltinName+21, "all", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_dssall;
+ break;
+ case 't':
+ if (!memcmp(BuiltinName+21, "stt", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_dststt;
+ break;
+ }
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[19]) { // "__builtin_altivec_m"
+ case 'f':
+ if (!memcmp(BuiltinName+20, "vscr", 4))
+ IntrinsicID = Intrinsic::ppc_altivec_mfvscr;
+ break;
+ case 't':
+ if (!memcmp(BuiltinName+20, "vscr", 4))
+ IntrinsicID = Intrinsic::ppc_altivec_mtvscr;
+ break;
+ }
+ break;
+ case 'v':
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'a':
+ if (!memcmp(BuiltinName+20, "vg", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vavg"
+ case 's':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vavgs"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vavgsb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vavgsh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vavgsw;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vavgu"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vavgub;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vavguh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vavguw;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+20, "t", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_altivec_vct"
+ case 's':
+ if (!memcmp(BuiltinName+22, "xs", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vctsxs;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+22, "xs", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vctuxs;
+ break;
+ }
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[20]) { // "__builtin_altivec_vm"
+ case 'a':
+ if (!memcmp(BuiltinName+21, "x", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vmax"
+ case 'f':
+ if (!memcmp(BuiltinName+23, "p", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxfp;
+ break;
+ case 's':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vmaxs"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxsb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxsh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxsw;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vmaxu"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxub;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxuh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vmaxuw;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+21, "n", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vmin"
+ case 'f':
+ if (!memcmp(BuiltinName+23, "p", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vminfp;
+ break;
+ case 's':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vmins"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vminsb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vminsh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vminsw;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vminu"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vminub;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vminuh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vminuw;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 25:
+ if (!memcmp(BuiltinName, "__builtin_altivec_v", 19)) {
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'a':
+ if (!memcmp(BuiltinName+20, "dd", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vadd"
+ case 'c':
+ if (!memcmp(BuiltinName+23, "uw", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vaddcuw;
+ break;
+ case 's':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vadds"
+ case 'b':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vaddsbs;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vaddshs;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vaddsws;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vaddu"
+ case 'b':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vaddubs;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vadduhs;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vadduws;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+20, "mpbfp", 5))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpbfp;
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+20, "ogefp", 5))
+ IntrinsicID = Intrinsic::ppc_altivec_vlogefp;
+ break;
+ case 'm':
+ switch (BuiltinName[20]) { // "__builtin_altivec_vm"
+ case 'a':
+ if (!memcmp(BuiltinName+21, "ddfp", 4))
+ IntrinsicID = Intrinsic::ppc_altivec_vmaddfp;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+21, "l", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vmul"
+ case 'e':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vmule"
+ case 's':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vmules"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vmulesb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vmulesh;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vmuleu"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vmuleub;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vmuleuh;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'o':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vmulo"
+ case 's':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vmulos"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vmulosb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vmulosh;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vmulou"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vmuloub;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vmulouh;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'p':
+ if (!memcmp(BuiltinName+20, "k", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_altivec_vpk"
+ case 's':
+ switch (BuiltinName[22]) { // "__builtin_altivec_vpks"
+ case 'h':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vpksh"
+ case 's':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkshss;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkshus;
+ break;
+ }
+ break;
+ case 'w':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vpksw"
+ case 's':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkswss;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkswus;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[22]) { // "__builtin_altivec_vpku"
+ case 'h':
+ if (!memcmp(BuiltinName+23, "us", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkuhus;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+23, "us", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vpkuwus;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+20, "u", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_altivec_vsu"
+ case 'b':
+ switch (BuiltinName[22]) { // "__builtin_altivec_vsub"
+ case 'c':
+ if (!memcmp(BuiltinName+23, "uw", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vsubcuw;
+ break;
+ case 's':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vsubs"
+ case 'b':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsubsbs;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsubshs;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsubsws;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vsubu"
+ case 'b':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsububs;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsubuhs;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+24, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsubuws;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+22, "sws", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_vsumsws;
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "pk", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vupk"
+ case 'h':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vupkh"
+ case 'p':
+ if (!memcmp(BuiltinName+24, "x", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vupkhpx;
+ break;
+ case 's':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vupkhs"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vupkhsb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vupkhsh;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vupkl"
+ case 'p':
+ if (!memcmp(BuiltinName+24, "x", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vupklpx;
+ break;
+ case 's':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vupkls"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vupklsb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vupklsh;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 26:
+ if (!memcmp(BuiltinName, "__builtin_altivec_v", 19)) {
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'c':
+ if (!memcmp(BuiltinName+20, "mp", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vcmp"
+ case 'e':
+ if (!memcmp(BuiltinName+23, "q", 1)) {
+ switch (BuiltinName[24]) { // "__builtin_altivec_vcmpeq"
+ case 'f':
+ if (!memcmp(BuiltinName+25, "p", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpeqfp;
+ break;
+ case 'u':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vcmpequ"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpequb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpequh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpequw;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'g':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vcmpg"
+ case 'e':
+ if (!memcmp(BuiltinName+24, "fp", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgefp;
+ break;
+ case 't':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vcmpgt"
+ case 'f':
+ if (!memcmp(BuiltinName+25, "p", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtfp;
+ break;
+ case 's':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vcmpgts"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtsb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtsh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtsw;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vcmpgtu"
+ case 'b':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtub;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtuh;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtuw;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'e':
+ if (!memcmp(BuiltinName+20, "xptefp", 6))
+ IntrinsicID = Intrinsic::ppc_altivec_vexptefp;
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+20, "sum", 3)) {
+ switch (BuiltinName[23]) { // "__builtin_altivec_vmsum"
+ case 'm':
+ if (!memcmp(BuiltinName+24, "bm", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vmsummbm;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+24, "h", 1)) {
+ switch (BuiltinName[25]) { // "__builtin_altivec_vmsumsh"
+ case 'm':
+ IntrinsicID = Intrinsic::ppc_altivec_vmsumshm;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::ppc_altivec_vmsumshs;
+ break;
+ }
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vmsumu"
+ case 'b':
+ if (!memcmp(BuiltinName+25, "m", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vmsumubm;
+ break;
+ case 'h':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vmsumuh"
+ case 'm':
+ IntrinsicID = Intrinsic::ppc_altivec_vmsumuhm;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::ppc_altivec_vmsumuhs;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+20, "msubfp", 6))
+ IntrinsicID = Intrinsic::ppc_altivec_vnmsubfp;
+ break;
+ case 's':
+ switch (BuiltinName[20]) { // "__builtin_altivec_vs"
+ case 'e':
+ if (!memcmp(BuiltinName+21, "l_4si", 5))
+ IntrinsicID = Intrinsic::ppc_altivec_vsel;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+21, "m", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vsum"
+ case '2':
+ if (!memcmp(BuiltinName+23, "sws", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_vsum2sws;
+ break;
+ case '4':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vsum4"
+ case 's':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vsum4s"
+ case 'b':
+ if (!memcmp(BuiltinName+25, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsum4sbs;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+25, "s", 1))
+ IntrinsicID = Intrinsic::ppc_altivec_vsum4shs;
+ break;
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+24, "bs", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vsum4ubs;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 27:
+ if (!memcmp(BuiltinName, "__builtin_altivec_v", 19)) {
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'c':
+ if (!memcmp(BuiltinName+20, "mpbfp_p", 7))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpbfp_p;
+ break;
+ case 'm':
+ switch (BuiltinName[20]) { // "__builtin_altivec_vm"
+ case 'h':
+ if (!memcmp(BuiltinName+21, "addshs", 6))
+ IntrinsicID = Intrinsic::ppc_altivec_vmhaddshs;
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+21, "adduhm", 6))
+ IntrinsicID = Intrinsic::ppc_altivec_vmladduhm;
+ break;
+ }
+ break;
+ case 'p':
+ if (!memcmp(BuiltinName+20, "erm_4si", 7))
+ IntrinsicID = Intrinsic::ppc_altivec_vperm;
+ break;
+ case 'r':
+ if (!memcmp(BuiltinName+20, "sqrtefp", 7))
+ IntrinsicID = Intrinsic::ppc_altivec_vrsqrtefp;
+ break;
+ }
+ }
+ break;
+ case 28:
+ if (!memcmp(BuiltinName, "__builtin_altivec_v", 19)) {
+ switch (BuiltinName[19]) { // "__builtin_altivec_v"
+ case 'c':
+ if (!memcmp(BuiltinName+20, "mp", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_altivec_vcmp"
+ case 'e':
+ if (!memcmp(BuiltinName+23, "q", 1)) {
+ switch (BuiltinName[24]) { // "__builtin_altivec_vcmpeq"
+ case 'f':
+ if (!memcmp(BuiltinName+25, "p_p", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpeqfp_p;
+ break;
+ case 'u':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vcmpequ"
+ case 'b':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpequb_p;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpequh_p;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpequw_p;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'g':
+ switch (BuiltinName[23]) { // "__builtin_altivec_vcmpg"
+ case 'e':
+ if (!memcmp(BuiltinName+24, "fp_p", 4))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgefp_p;
+ break;
+ case 't':
+ switch (BuiltinName[24]) { // "__builtin_altivec_vcmpgt"
+ case 'f':
+ if (!memcmp(BuiltinName+25, "p_p", 3))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtfp_p;
+ break;
+ case 's':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vcmpgts"
+ case 'b':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtsb_p;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtsh_p;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtsw_p;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[25]) { // "__builtin_altivec_vcmpgtu"
+ case 'b':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtub_p;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtuh_p;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+26, "_p", 2))
+ IntrinsicID = Intrinsic::ppc_altivec_vcmpgtuw_p;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+20, "hraddshs", 8))
+ IntrinsicID = Intrinsic::ppc_altivec_vmhraddshs;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ if (!strcmp(TargetPrefix, "spu")) {
+ switch (strlen(BuiltinName)) {
+ default: break;
+ case 14:
+ if (!memcmp(BuiltinName, "__builtin_si_a", 14))
+ IntrinsicID = Intrinsic::spu_si_a;
+ break;
+ case 15:
+ if (!memcmp(BuiltinName, "__builtin_si_", 13)) {
+ switch (BuiltinName[13]) { // "__builtin_si_"
+ case 'a':
+ switch (BuiltinName[14]) { // "__builtin_si_a"
+ case 'h':
+ IntrinsicID = Intrinsic::spu_si_ah;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_ai;
+ break;
+ }
+ break;
+ case 'b':
+ if (!memcmp(BuiltinName+14, "g", 1))
+ IntrinsicID = Intrinsic::spu_si_bg;
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+14, "g", 1))
+ IntrinsicID = Intrinsic::spu_si_cg;
+ break;
+ case 'f':
+ switch (BuiltinName[14]) { // "__builtin_si_f"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_fa;
+ break;
+ case 'm':
+ IntrinsicID = Intrinsic::spu_si_fm;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::spu_si_fs;
+ break;
+ }
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+14, "r", 1))
+ IntrinsicID = Intrinsic::spu_si_or;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+14, "f", 1))
+ IntrinsicID = Intrinsic::spu_si_sf;
+ break;
+ }
+ }
+ break;
+ case 16:
+ if (!memcmp(BuiltinName, "__builtin_si_", 13)) {
+ switch (BuiltinName[13]) { // "__builtin_si_"
+ case 'a':
+ switch (BuiltinName[14]) { // "__builtin_si_a"
+ case 'h':
+ if (!memcmp(BuiltinName+15, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_ahi;
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+15, "d", 1))
+ IntrinsicID = Intrinsic::spu_si_and;
+ break;
+ }
+ break;
+ case 'b':
+ if (!memcmp(BuiltinName+14, "gx", 2))
+ IntrinsicID = Intrinsic::spu_si_bgx;
+ break;
+ case 'c':
+ switch (BuiltinName[14]) { // "__builtin_si_c"
+ case 'e':
+ if (!memcmp(BuiltinName+15, "q", 1))
+ IntrinsicID = Intrinsic::spu_si_ceq;
+ break;
+ case 'g':
+ switch (BuiltinName[15]) { // "__builtin_si_cg"
+ case 't':
+ IntrinsicID = Intrinsic::spu_si_cgt;
+ break;
+ case 'x':
+ IntrinsicID = Intrinsic::spu_si_cgx;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+14, "f", 1)) {
+ switch (BuiltinName[15]) { // "__builtin_si_df"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_dfa;
+ break;
+ case 'm':
+ IntrinsicID = Intrinsic::spu_si_dfm;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::spu_si_dfs;
+ break;
+ }
+ }
+ break;
+ case 'f':
+ if (!memcmp(BuiltinName+14, "m", 1)) {
+ switch (BuiltinName[15]) { // "__builtin_si_fm"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_fma;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::spu_si_fms;
+ break;
+ }
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+14, "py", 2))
+ IntrinsicID = Intrinsic::spu_si_mpy;
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+14, "or", 2))
+ IntrinsicID = Intrinsic::spu_si_nor;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+14, "r", 1)) {
+ switch (BuiltinName[15]) { // "__builtin_si_or"
+ case 'c':
+ IntrinsicID = Intrinsic::spu_si_orc;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_ori;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+14, "f", 1)) {
+ switch (BuiltinName[15]) { // "__builtin_si_sf"
+ case 'h':
+ IntrinsicID = Intrinsic::spu_si_sfh;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_sfi;
+ break;
+ case 'x':
+ IntrinsicID = Intrinsic::spu_si_sfx;
+ break;
+ }
+ }
+ break;
+ case 'x':
+ if (!memcmp(BuiltinName+14, "or", 2))
+ IntrinsicID = Intrinsic::spu_si_xor;
+ break;
+ }
+ }
+ break;
+ case 17:
+ if (!memcmp(BuiltinName, "__builtin_si_", 13)) {
+ switch (BuiltinName[13]) { // "__builtin_si_"
+ case 'a':
+ switch (BuiltinName[14]) { // "__builtin_si_a"
+ case 'd':
+ if (!memcmp(BuiltinName+15, "dx", 2))
+ IntrinsicID = Intrinsic::spu_si_addx;
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+15, "d", 1)) {
+ switch (BuiltinName[16]) { // "__builtin_si_and"
+ case 'c':
+ IntrinsicID = Intrinsic::spu_si_andc;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_andi;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'c':
+ switch (BuiltinName[14]) { // "__builtin_si_c"
+ case 'e':
+ if (!memcmp(BuiltinName+15, "q", 1)) {
+ switch (BuiltinName[16]) { // "__builtin_si_ceq"
+ case 'b':
+ IntrinsicID = Intrinsic::spu_si_ceqb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::spu_si_ceqh;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_ceqi;
+ break;
+ }
+ }
+ break;
+ case 'g':
+ if (!memcmp(BuiltinName+15, "t", 1)) {
+ switch (BuiltinName[16]) { // "__builtin_si_cgt"
+ case 'b':
+ IntrinsicID = Intrinsic::spu_si_cgtb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::spu_si_cgth;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_cgti;
+ break;
+ }
+ }
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+15, "gt", 2))
+ IntrinsicID = Intrinsic::spu_si_clgt;
+ break;
+ }
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+14, "fm", 2)) {
+ switch (BuiltinName[16]) { // "__builtin_si_dfm"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_dfma;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::spu_si_dfms;
+ break;
+ }
+ }
+ break;
+ case 'f':
+ switch (BuiltinName[14]) { // "__builtin_si_f"
+ case 'c':
+ switch (BuiltinName[15]) { // "__builtin_si_fc"
+ case 'e':
+ if (!memcmp(BuiltinName+16, "q", 1))
+ IntrinsicID = Intrinsic::spu_si_fceq;
+ break;
+ case 'g':
+ if (!memcmp(BuiltinName+16, "t", 1))
+ IntrinsicID = Intrinsic::spu_si_fcgt;
+ break;
+ }
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+15, "ms", 2))
+ IntrinsicID = Intrinsic::spu_si_fnms;
+ break;
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+14, "py", 2)) {
+ switch (BuiltinName[16]) { // "__builtin_si_mpy"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_mpya;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::spu_si_mpyh;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_mpyi;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::spu_si_mpys;
+ break;
+ case 'u':
+ IntrinsicID = Intrinsic::spu_si_mpyu;
+ break;
+ }
+ }
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+14, "and", 3))
+ IntrinsicID = Intrinsic::spu_si_nand;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+14, "r", 1)) {
+ switch (BuiltinName[15]) { // "__builtin_si_or"
+ case 'b':
+ if (!memcmp(BuiltinName+16, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_orbi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+16, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_orhi;
+ break;
+ }
+ }
+ break;
+ case 's':
+ switch (BuiltinName[14]) { // "__builtin_si_s"
+ case 'f':
+ if (!memcmp(BuiltinName+15, "hi", 2))
+ IntrinsicID = Intrinsic::spu_si_sfhi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+15, "li", 2))
+ IntrinsicID = Intrinsic::spu_si_shli;
+ break;
+ }
+ break;
+ case 'x':
+ if (!memcmp(BuiltinName+14, "ori", 3))
+ IntrinsicID = Intrinsic::spu_si_xori;
+ break;
+ }
+ }
+ break;
+ case 18:
+ if (!memcmp(BuiltinName, "__builtin_si_", 13)) {
+ switch (BuiltinName[13]) { // "__builtin_si_"
+ case 'a':
+ if (!memcmp(BuiltinName+14, "nd", 2)) {
+ switch (BuiltinName[16]) { // "__builtin_si_and"
+ case 'b':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_andbi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_andhi;
+ break;
+ }
+ }
+ break;
+ case 'c':
+ switch (BuiltinName[14]) { // "__builtin_si_c"
+ case 'e':
+ if (!memcmp(BuiltinName+15, "q", 1)) {
+ switch (BuiltinName[16]) { // "__builtin_si_ceq"
+ case 'b':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_ceqbi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_ceqhi;
+ break;
+ }
+ }
+ break;
+ case 'g':
+ if (!memcmp(BuiltinName+15, "t", 1)) {
+ switch (BuiltinName[16]) { // "__builtin_si_cgt"
+ case 'b':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_cgtbi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_cgthi;
+ break;
+ }
+ }
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+15, "gt", 2)) {
+ switch (BuiltinName[17]) { // "__builtin_si_clgt"
+ case 'b':
+ IntrinsicID = Intrinsic::spu_si_clgtb;
+ break;
+ case 'h':
+ IntrinsicID = Intrinsic::spu_si_clgth;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_clgti;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+14, "fnm", 3)) {
+ switch (BuiltinName[17]) { // "__builtin_si_dfnm"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_dfnma;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::spu_si_dfnms;
+ break;
+ }
+ }
+ break;
+ case 'f':
+ switch (BuiltinName[14]) { // "__builtin_si_f"
+ case 'c':
+ if (!memcmp(BuiltinName+15, "m", 1)) {
+ switch (BuiltinName[16]) { // "__builtin_si_fcm"
+ case 'e':
+ if (!memcmp(BuiltinName+17, "q", 1))
+ IntrinsicID = Intrinsic::spu_si_fcmeq;
+ break;
+ case 'g':
+ if (!memcmp(BuiltinName+17, "t", 1))
+ IntrinsicID = Intrinsic::spu_si_fcmgt;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+15, "mbi", 3))
+ IntrinsicID = Intrinsic::spu_si_fsmbi;
+ break;
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+14, "py", 2)) {
+ switch (BuiltinName[16]) { // "__builtin_si_mpy"
+ case 'h':
+ if (!memcmp(BuiltinName+17, "h", 1))
+ IntrinsicID = Intrinsic::spu_si_mpyhh;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_mpyui;
+ break;
+ }
+ }
+ break;
+ case 'x':
+ if (!memcmp(BuiltinName+14, "or", 2)) {
+ switch (BuiltinName[16]) { // "__builtin_si_xor"
+ case 'b':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_xorbi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+17, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_xorhi;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 19:
+ if (!memcmp(BuiltinName, "__builtin_si_", 13)) {
+ switch (BuiltinName[13]) { // "__builtin_si_"
+ case 'c':
+ if (!memcmp(BuiltinName+14, "lgt", 3)) {
+ switch (BuiltinName[17]) { // "__builtin_si_clgt"
+ case 'b':
+ if (!memcmp(BuiltinName+18, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_clgtbi;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+18, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_clgthi;
+ break;
+ }
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+14, "pyhh", 4)) {
+ switch (BuiltinName[18]) { // "__builtin_si_mpyhh"
+ case 'a':
+ IntrinsicID = Intrinsic::spu_si_mpyhha;
+ break;
+ case 'u':
+ IntrinsicID = Intrinsic::spu_si_mpyhhu;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+14, "hlqb", 4)) {
+ switch (BuiltinName[18]) { // "__builtin_si_shlqb"
+ case 'i':
+ IntrinsicID = Intrinsic::spu_si_shlqbi;
+ break;
+ case 'y':
+ IntrinsicID = Intrinsic::spu_si_shlqby;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 20:
+ if (!memcmp(BuiltinName, "__builtin_si_", 13)) {
+ switch (BuiltinName[13]) { // "__builtin_si_"
+ case 'm':
+ if (!memcmp(BuiltinName+14, "pyhhau", 6))
+ IntrinsicID = Intrinsic::spu_si_mpyhhau;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+14, "hlqb", 4)) {
+ switch (BuiltinName[18]) { // "__builtin_si_shlqb"
+ case 'i':
+ if (!memcmp(BuiltinName+19, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_shlqbii;
+ break;
+ case 'y':
+ if (!memcmp(BuiltinName+19, "i", 1))
+ IntrinsicID = Intrinsic::spu_si_shlqbyi;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ if (!strcmp(TargetPrefix, "x86")) {
+ switch (strlen(BuiltinName)) {
+ default: break;
+ case 19:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'd':
+ if (!memcmp(BuiltinName+16, "pp", 2)) {
+ switch (BuiltinName[18]) { // "__builtin_ia32_dpp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse41_dppd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse41_dpps;
+ break;
+ }
+ }
+ break;
+ case 'e':
+ if (!memcmp(BuiltinName+16, "mms", 3))
+ IntrinsicID = Intrinsic::x86_mmx_emms;
+ break;
+ }
+ }
+ break;
+ case 20:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'a':
+ if (!memcmp(BuiltinName+16, "dds", 3)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_adds"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_add_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_add_ss;
+ break;
+ }
+ }
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+16, "ivs", 3)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_divs"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_div_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_div_ss;
+ break;
+ }
+ }
+ break;
+ case 'f':
+ if (!memcmp(BuiltinName+16, "emms", 4))
+ IntrinsicID = Intrinsic::x86_mmx_femms;
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+16, "ddqu", 4))
+ IntrinsicID = Intrinsic::x86_sse3_ldu_dq;
+ break;
+ case 'm':
+ switch (BuiltinName[16]) { // "__builtin_ia32_m"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "x", 1)) {
+ switch (BuiltinName[18]) { // "__builtin_ia32_max"
+ case 'p':
+ switch (BuiltinName[19]) { // "__builtin_ia32_maxp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_max_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_max_ps;
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[19]) { // "__builtin_ia32_maxs"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_max_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_max_ss;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+17, "n", 1)) {
+ switch (BuiltinName[18]) { // "__builtin_ia32_min"
+ case 'p':
+ switch (BuiltinName[19]) { // "__builtin_ia32_minp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_min_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_min_ps;
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[19]) { // "__builtin_ia32_mins"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_min_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_min_ss;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+17, "ls", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_muls"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_mul_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_mul_ss;
+ break;
+ }
+ }
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+17, "ait", 3))
+ IntrinsicID = Intrinsic::x86_sse3_mwait;
+ break;
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pa"
+ case 'b':
+ if (!memcmp(BuiltinName+18, "s", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pabs"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_ssse3_pabs_b;
+ break;
+ case 'd':
+ IntrinsicID = Intrinsic::x86_ssse3_pabs_d;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_ssse3_pabs_w;
+ break;
+ }
+ }
+ break;
+ case 'v':
+ if (!memcmp(BuiltinName+18, "g", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pavg"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_pavg_b;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_pavg_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ps"
+ case 'l':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_psll"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_mmx_psll_d;
+ break;
+ case 'q':
+ IntrinsicID = Intrinsic::x86_mmx_psll_q;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_psll_w;
+ break;
+ }
+ }
+ break;
+ case 'r':
+ switch (BuiltinName[18]) { // "__builtin_ia32_psr"
+ case 'a':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psra"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_mmx_psra_d;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_psra_w;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psrl"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_mmx_psrl_d;
+ break;
+ case 'q':
+ IntrinsicID = Intrinsic::x86_mmx_psrl_q;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_psrl_w;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'r':
+ if (!memcmp(BuiltinName+16, "cp", 2)) {
+ switch (BuiltinName[18]) { // "__builtin_ia32_rcp"
+ case 'p':
+ if (!memcmp(BuiltinName+19, "s", 1))
+ IntrinsicID = Intrinsic::x86_sse_rcp_ps;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+19, "s", 1))
+ IntrinsicID = Intrinsic::x86_sse_rcp_ss;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+16, "ubs", 3)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_subs"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_sub_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_sub_ss;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 21:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'c':
+ if (!memcmp(BuiltinName+16, "omi", 3)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_comi"
+ case 'e':
+ if (!memcmp(BuiltinName+20, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse_comieq_ss;
+ break;
+ case 'g':
+ switch (BuiltinName[20]) { // "__builtin_ia32_comig"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse_comige_ss;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse_comigt_ss;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[20]) { // "__builtin_ia32_comil"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse_comile_ss;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse_comilt_ss;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'h':
+ switch (BuiltinName[16]) { // "__builtin_ia32_h"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "ddp", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_haddp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse3_hadd_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse3_hadd_ps;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+17, "ubp", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_hsubp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse3_hsub_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse3_hsub_ps;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+16, "fence", 5))
+ IntrinsicID = Intrinsic::x86_sse2_lfence;
+ break;
+ case 'm':
+ switch (BuiltinName[16]) { // "__builtin_ia32_m"
+ case 'f':
+ if (!memcmp(BuiltinName+17, "ence", 4))
+ IntrinsicID = Intrinsic::x86_sse2_mfence;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+17, "vnt", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_movnt"
+ case 'i':
+ IntrinsicID = Intrinsic::x86_sse2_movnt_i;
+ break;
+ case 'q':
+ IntrinsicID = Intrinsic::x86_mmx_movnt_dq;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "dds", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_padds"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_padds_b;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_padds_w;
+ break;
+ }
+ }
+ break;
+ case 'h':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ph"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "dd", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_phadd"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_ssse3_phadd_d;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_ssse3_phadd_w;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+18, "ub", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_phsub"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_ssse3_phsub_d;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_ssse3_phsub_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pm"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "x", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmax"
+ case 's':
+ if (!memcmp(BuiltinName+20, "w", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pmaxs_w;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "b", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pmaxu_b;
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+18, "n", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmin"
+ case 's':
+ if (!memcmp(BuiltinName+20, "w", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pmins_w;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "b", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pminu_b;
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "lhw", 3))
+ IntrinsicID = Intrinsic::x86_mmx_pmulh_w;
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ps"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "dbw", 3))
+ IntrinsicID = Intrinsic::x86_mmx_psad_bw;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+18, "ufb", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_pshuf_b;
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+18, "gn", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_psign"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_ssse3_psign_b;
+ break;
+ case 'd':
+ IntrinsicID = Intrinsic::x86_ssse3_psign_d;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_ssse3_psign_w;
+ break;
+ }
+ }
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_psll"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pslli_d;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pslli_q;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_pslli_w;
+ break;
+ }
+ }
+ break;
+ case 'r':
+ switch (BuiltinName[18]) { // "__builtin_ia32_psr"
+ case 'a':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psra"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_psrai_d;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_psrai_w;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psrl"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_psrli_d;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_psrli_q;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "i", 1))
+ IntrinsicID = Intrinsic::x86_mmx_psrli_w;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "bs", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_psubs"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_psubs_b;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_psubs_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[16]) { // "__builtin_ia32_s"
+ case 'f':
+ if (!memcmp(BuiltinName+17, "ence", 4))
+ IntrinsicID = Intrinsic::x86_sse_sfence;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+17, "rt", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_sqrt"
+ case 'p':
+ switch (BuiltinName[20]) { // "__builtin_ia32_sqrtp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_sqrt_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_sqrt_ps;
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[20]) { // "__builtin_ia32_sqrts"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_sqrt_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_sqrt_ss;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 22:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'b':
+ if (!memcmp(BuiltinName+16, "lendp", 5)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_blendp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse41_blendpd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse41_blendps;
+ break;
+ }
+ }
+ break;
+ case 'c':
+ switch (BuiltinName[16]) { // "__builtin_ia32_c"
+ case 'l':
+ if (!memcmp(BuiltinName+17, "flush", 5))
+ IntrinsicID = Intrinsic::x86_sse2_clflush;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+17, "mineq", 5))
+ IntrinsicID = Intrinsic::x86_sse_comineq_ss;
+ break;
+ case 'r':
+ if (!memcmp(BuiltinName+17, "c32", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_crc32"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "i", 1))
+ IntrinsicID = Intrinsic::x86_sse42_crc32_64;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+21, "i", 1))
+ IntrinsicID = Intrinsic::x86_sse42_crc32_16;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+21, "i", 1))
+ IntrinsicID = Intrinsic::x86_sse42_crc32_8;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+21, "i", 1))
+ IntrinsicID = Intrinsic::x86_sse42_crc32_32;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+16, "oad", 3)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_load"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "qu", 2))
+ IntrinsicID = Intrinsic::x86_sse2_loadu_dq;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "p", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_loadup"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_loadu_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_loadu_ps;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+16, "o", 1)) {
+ switch (BuiltinName[17]) { // "__builtin_ia32_mo"
+ case 'n':
+ if (!memcmp(BuiltinName+18, "itor", 4))
+ IntrinsicID = Intrinsic::x86_sse3_monitor;
+ break;
+ case 'v':
+ if (!memcmp(BuiltinName+18, "nt", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_movnt"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_movnt_dq;
+ break;
+ case 'p':
+ switch (BuiltinName[21]) { // "__builtin_ia32_movntp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_movnt_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_movnt_ps;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "ddus", 4)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_paddus"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_paddus_b;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_paddus_w;
+ break;
+ }
+ }
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+17, "mp", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pcmp"
+ case 'e':
+ if (!memcmp(BuiltinName+20, "q", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_pcmpeq"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_pcmpeq_b;
+ break;
+ case 'd':
+ IntrinsicID = Intrinsic::x86_mmx_pcmpeq_d;
+ break;
+ case 'q':
+ IntrinsicID = Intrinsic::x86_sse41_pcmpeqq;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_pcmpeq_w;
+ break;
+ }
+ }
+ break;
+ case 'g':
+ if (!memcmp(BuiltinName+20, "t", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_pcmpgt"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_pcmpgt_b;
+ break;
+ case 'd':
+ IntrinsicID = Intrinsic::x86_mmx_pcmpgt_d;
+ break;
+ case 'q':
+ IntrinsicID = Intrinsic::x86_sse42_pcmpgtq;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_pcmpgt_w;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'h':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ph"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "ddsw", 4))
+ IntrinsicID = Intrinsic::x86_ssse3_phadd_sw;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+18, "ubsw", 4))
+ IntrinsicID = Intrinsic::x86_ssse3_phsub_sw;
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pm"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "ddwd", 4))
+ IntrinsicID = Intrinsic::x86_mmx_pmadd_wd;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmul"
+ case 'h':
+ if (!memcmp(BuiltinName+20, "uw", 2))
+ IntrinsicID = Intrinsic::x86_mmx_pmulhu_w;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "dq", 2))
+ IntrinsicID = Intrinsic::x86_mmx_pmulu_dq;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+17, "ubus", 4)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_psubus"
+ case 'b':
+ IntrinsicID = Intrinsic::x86_mmx_psubus_b;
+ break;
+ case 'w':
+ IntrinsicID = Intrinsic::x86_mmx_psubus_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'r':
+ switch (BuiltinName[16]) { // "__builtin_ia32_r"
+ case 'o':
+ if (!memcmp(BuiltinName+17, "und", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_round"
+ case 'p':
+ switch (BuiltinName[21]) { // "__builtin_ia32_roundp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse41_round_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse41_round_ps;
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[21]) { // "__builtin_ia32_rounds"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse41_round_sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse41_round_ss;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+17, "qrt", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_rsqrt"
+ case 'p':
+ if (!memcmp(BuiltinName+21, "s", 1))
+ IntrinsicID = Intrinsic::x86_sse_rsqrt_ps;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+21, "s", 1))
+ IntrinsicID = Intrinsic::x86_sse_rsqrt_ss;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+16, "comi", 4)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_ucomi"
+ case 'e':
+ if (!memcmp(BuiltinName+21, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse_ucomieq_ss;
+ break;
+ case 'g':
+ switch (BuiltinName[21]) { // "__builtin_ia32_ucomig"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse_ucomige_ss;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse_ucomigt_ss;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[21]) { // "__builtin_ia32_ucomil"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse_ucomile_ss;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse_ucomilt_ss;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 23:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'a':
+ if (!memcmp(BuiltinName+16, "ddsubp", 6)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_addsubp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse3_addsub_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse3_addsub_ps;
+ break;
+ }
+ }
+ break;
+ case 'b':
+ if (!memcmp(BuiltinName+16, "lendvp", 6)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_blendvp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse41_blendvpd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse41_blendvps;
+ break;
+ }
+ }
+ break;
+ case 'c':
+ switch (BuiltinName[16]) { // "__builtin_ia32_c"
+ case 'o':
+ if (!memcmp(BuiltinName+17, "misd", 4)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_comisd"
+ case 'e':
+ if (!memcmp(BuiltinName+22, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_comieq_sd;
+ break;
+ case 'g':
+ switch (BuiltinName[22]) { // "__builtin_ia32_comisdg"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse2_comige_sd;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse2_comigt_sd;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[22]) { // "__builtin_ia32_comisdl"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse2_comile_sd;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse2_comilt_sd;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'v':
+ if (!memcmp(BuiltinName+17, "t", 1)) {
+ switch (BuiltinName[18]) { // "__builtin_ia32_cvt"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "q2p", 3)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtdq2p"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_cvtdq2pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse2_cvtdq2ps;
+ break;
+ }
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[19]) { // "__builtin_ia32_cvtp"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "2", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_cvtpd2"
+ case 'd':
+ if (!memcmp(BuiltinName+22, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_cvtpd2dq;
+ break;
+ case 'p':
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtpd2p"
+ case 'i':
+ IntrinsicID = Intrinsic::x86_sse_cvtpd2pi;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse2_cvtpd2ps;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+20, "2p", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtpi2p"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse_cvtpi2pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_cvtpi2ps;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+20, "2", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_cvtps2"
+ case 'd':
+ if (!memcmp(BuiltinName+22, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_cvtps2dq;
+ break;
+ case 'p':
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtps2p"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_cvtps2pd;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::x86_sse_cvtps2pi;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[19]) { // "__builtin_ia32_cvts"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "2s", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtsd2s"
+ case 'i':
+ IntrinsicID = Intrinsic::x86_sse2_cvtsd2si;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse2_cvtsd2ss;
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+20, "2s", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtsi2s"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_cvtsi2sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_cvtsi2ss;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+20, "2s", 2)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvtss2s"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_cvtss2sd;
+ break;
+ case 'i':
+ IntrinsicID = Intrinsic::x86_sse_cvtss2si;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[16]) { // "__builtin_ia32_m"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "skmovq", 6))
+ IntrinsicID = Intrinsic::x86_mmx_maskmovq;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+17, "v", 1)) {
+ switch (BuiltinName[18]) { // "__builtin_ia32_mov"
+ case 'm':
+ if (!memcmp(BuiltinName+19, "skp", 3)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_movmskp"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_movmsk_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_movmsk_ps;
+ break;
+ }
+ }
+ break;
+ case 'n':
+ if (!memcmp(BuiltinName+19, "tdqa", 4))
+ IntrinsicID = Intrinsic::x86_sse41_movntdqa;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pa"
+ case 'b':
+ if (!memcmp(BuiltinName+18, "s", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pabs"
+ case 'b':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_pabs_b_128;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_pabs_d_128;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_pabs_w_128;
+ break;
+ }
+ }
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+18, "k", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pack"
+ case 's':
+ if (!memcmp(BuiltinName+20, "s", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_packss"
+ case 'd':
+ if (!memcmp(BuiltinName+22, "w", 1))
+ IntrinsicID = Intrinsic::x86_mmx_packssdw;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "b", 1))
+ IntrinsicID = Intrinsic::x86_mmx_packsswb;
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "swb", 3))
+ IntrinsicID = Intrinsic::x86_mmx_packuswb;
+ break;
+ }
+ }
+ break;
+ case 'v':
+ if (!memcmp(BuiltinName+18, "g", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pavg"
+ case 'b':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pavg_b;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pavg_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pm"
+ case 'o':
+ if (!memcmp(BuiltinName+18, "vmskb", 5))
+ IntrinsicID = Intrinsic::x86_mmx_pmovmskb;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "lhrsw", 5))
+ IntrinsicID = Intrinsic::x86_ssse3_pmul_hr_sw;
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ps"
+ case 'l':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_psll"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psll_d;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psll_q;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psll_w;
+ break;
+ }
+ }
+ break;
+ case 'r':
+ switch (BuiltinName[18]) { // "__builtin_ia32_psr"
+ case 'a':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psra"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psra_d;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psra_w;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psrl"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psrl_d;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psrl_q;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psrl_w;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+16, "tore", 4)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_store"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "qu", 2))
+ IntrinsicID = Intrinsic::x86_sse2_storeu_dq;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+21, "p", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_storeup"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_storeu_pd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_storeu_ps;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+16, "comineq", 7))
+ IntrinsicID = Intrinsic::x86_sse_ucomineq_ss;
+ break;
+ }
+ }
+ break;
+ case 24:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'c':
+ switch (BuiltinName[16]) { // "__builtin_ia32_c"
+ case 'o':
+ if (!memcmp(BuiltinName+17, "misdneq", 7))
+ IntrinsicID = Intrinsic::x86_sse2_comineq_sd;
+ break;
+ case 'v':
+ if (!memcmp(BuiltinName+17, "tt", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_cvtt"
+ case 'p':
+ switch (BuiltinName[20]) { // "__builtin_ia32_cvttp"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "2", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvttpd2"
+ case 'd':
+ if (!memcmp(BuiltinName+23, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_cvttpd2dq;
+ break;
+ case 'p':
+ if (!memcmp(BuiltinName+23, "i", 1))
+ IntrinsicID = Intrinsic::x86_sse_cvttpd2pi;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+21, "2", 1)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_cvttps2"
+ case 'd':
+ if (!memcmp(BuiltinName+23, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_cvttps2dq;
+ break;
+ case 'p':
+ if (!memcmp(BuiltinName+23, "i", 1))
+ IntrinsicID = Intrinsic::x86_sse_cvttps2pi;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[20]) { // "__builtin_ia32_cvtts"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "2si", 3))
+ IntrinsicID = Intrinsic::x86_sse2_cvttsd2si;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+21, "2si", 3))
+ IntrinsicID = Intrinsic::x86_sse_cvttss2si;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "dds", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_padds"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_padds_b;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_padds_w;
+ break;
+ }
+ }
+ break;
+ case 'h':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ph"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "dd", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_phadd"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_phadd_d_128;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_phadd_w_128;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+18, "ub", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_phsub"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_phsub_d_128;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_phsub_w_128;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pm"
+ case 'a':
+ switch (BuiltinName[18]) { // "__builtin_ia32_pma"
+ case 'd':
+ if (!memcmp(BuiltinName+19, "dubsw", 5))
+ IntrinsicID = Intrinsic::x86_ssse3_pmadd_ub_sw;
+ break;
+ case 'x':
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmax"
+ case 's':
+ switch (BuiltinName[20]) { // "__builtin_ia32_pmaxs"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmaxsb;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmaxsd;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pmaxs_w;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[20]) { // "__builtin_ia32_pmaxu"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pmaxu_b;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmaxud;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmaxuw;
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+18, "n", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmin"
+ case 's':
+ switch (BuiltinName[20]) { // "__builtin_ia32_pmins"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pminsb;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pminsd;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pmins_w;
+ break;
+ }
+ break;
+ case 'u':
+ switch (BuiltinName[20]) { // "__builtin_ia32_pminu"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pminu_b;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pminud;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pminuw;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmul"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "q128", 4))
+ IntrinsicID = Intrinsic::x86_sse41_pmuldq;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+20, "w128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_pmulh_w;
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+20, "d128", 4))
+ IntrinsicID = Intrinsic::x86_sse41_pmulld;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ps"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "dbw128", 6))
+ IntrinsicID = Intrinsic::x86_sse2_psad_bw;
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+18, "ufb128", 6))
+ IntrinsicID = Intrinsic::x86_ssse3_pshuf_b_128;
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+18, "gn", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_psign"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_psign_b_128;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_psign_d_128;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_ssse3_psign_w_128;
+ break;
+ }
+ }
+ break;
+ case 'l':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_psll"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_pslli_d;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_pslli_q;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_pslli_w;
+ break;
+ }
+ }
+ break;
+ case 'r':
+ switch (BuiltinName[18]) { // "__builtin_ia32_psr"
+ case 'a':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psra"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_psrai_d;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_psrai_w;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[19]) { // "__builtin_ia32_psrl"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_psrli_d;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_psrli_q;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+20, "i128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_psrli_w;
+ break;
+ }
+ break;
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "bs", 2)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_psubs"
+ case 'b':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psubs_b;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psubs_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 't':
+ if (!memcmp(BuiltinName+17, "est", 3)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_ptest"
+ case 'c':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_ptestc;
+ break;
+ case 'z':
+ if (!memcmp(BuiltinName+21, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_ptestz;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+16, "comisd", 6)) {
+ switch (BuiltinName[22]) { // "__builtin_ia32_ucomisd"
+ case 'e':
+ if (!memcmp(BuiltinName+23, "q", 1))
+ IntrinsicID = Intrinsic::x86_sse2_ucomieq_sd;
+ break;
+ case 'g':
+ switch (BuiltinName[23]) { // "__builtin_ia32_ucomisdg"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse2_ucomige_sd;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse2_ucomigt_sd;
+ break;
+ }
+ break;
+ case 'l':
+ switch (BuiltinName[23]) { // "__builtin_ia32_ucomisdl"
+ case 'e':
+ IntrinsicID = Intrinsic::x86_sse2_ucomile_sd;
+ break;
+ case 't':
+ IntrinsicID = Intrinsic::x86_sse2_ucomilt_sd;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 25:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'c':
+ if (!memcmp(BuiltinName+16, "vts", 3)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_cvts"
+ case 'd':
+ if (!memcmp(BuiltinName+20, "2si64", 5))
+ IntrinsicID = Intrinsic::x86_sse2_cvtsd2si64;
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+20, "642s", 4)) {
+ switch (BuiltinName[24]) { // "__builtin_ia32_cvtsi642s"
+ case 'd':
+ IntrinsicID = Intrinsic::x86_sse2_cvtsi642sd;
+ break;
+ case 's':
+ IntrinsicID = Intrinsic::x86_sse_cvtsi642ss;
+ break;
+ }
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+20, "2si64", 5))
+ IntrinsicID = Intrinsic::x86_sse_cvtss2si64;
+ break;
+ }
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[16]) { // "__builtin_ia32_m"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "skmovdqu", 8))
+ IntrinsicID = Intrinsic::x86_sse2_maskmov_dqu;
+ break;
+ case 'p':
+ if (!memcmp(BuiltinName+17, "sadbw128", 8))
+ IntrinsicID = Intrinsic::x86_sse41_mpsadbw;
+ break;
+ }
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "ddus", 4)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_paddus"
+ case 'b':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_paddus_b;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_paddus_w;
+ break;
+ }
+ }
+ break;
+ case 'b':
+ if (!memcmp(BuiltinName+17, "lendw128", 8))
+ IntrinsicID = Intrinsic::x86_sse41_pblendw;
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+17, "mp", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pcmp"
+ case 'e':
+ if (!memcmp(BuiltinName+20, "q", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_pcmpeq"
+ case 'b':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pcmpeq_b;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pcmpeq_d;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pcmpeq_w;
+ break;
+ }
+ }
+ break;
+ case 'g':
+ if (!memcmp(BuiltinName+20, "t", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_pcmpgt"
+ case 'b':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pcmpgt_b;
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pcmpgt_d;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_pcmpgt_w;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'h':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ph"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "ddsw128", 7))
+ IntrinsicID = Intrinsic::x86_ssse3_phadd_sw_128;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+18, "ubsw128", 7))
+ IntrinsicID = Intrinsic::x86_ssse3_phsub_sw_128;
+ break;
+ }
+ break;
+ case 'm':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pm"
+ case 'a':
+ if (!memcmp(BuiltinName+18, "ddwd128", 7))
+ IntrinsicID = Intrinsic::x86_sse2_pmadd_wd;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "l", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmul"
+ case 'h':
+ if (!memcmp(BuiltinName+20, "uw128", 5))
+ IntrinsicID = Intrinsic::x86_sse2_pmulhu_w;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "dq128", 5))
+ IntrinsicID = Intrinsic::x86_sse2_pmulu_dq;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ case 's':
+ switch (BuiltinName[17]) { // "__builtin_ia32_ps"
+ case 'l':
+ if (!memcmp(BuiltinName+18, "ldqi128", 7))
+ IntrinsicID = Intrinsic::x86_sse2_psll_dq;
+ break;
+ case 'r':
+ if (!memcmp(BuiltinName+18, "ldqi128", 7))
+ IntrinsicID = Intrinsic::x86_sse2_psrl_dq;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "bus", 3)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_psubus"
+ case 'b':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psubus_b;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse2_psubus_w;
+ break;
+ }
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+16, "torelv4si", 9))
+ IntrinsicID = Intrinsic::x86_sse2_storel_dq;
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+16, "comisdneq", 9))
+ IntrinsicID = Intrinsic::x86_sse2_ucomineq_sd;
+ break;
+ }
+ }
+ break;
+ case 26:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'c':
+ if (!memcmp(BuiltinName+16, "vtts", 4)) {
+ switch (BuiltinName[20]) { // "__builtin_ia32_cvtts"
+ case 'd':
+ if (!memcmp(BuiltinName+21, "2si64", 5))
+ IntrinsicID = Intrinsic::x86_sse2_cvttsd2si64;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+21, "2si64", 5))
+ IntrinsicID = Intrinsic::x86_sse_cvttss2si64;
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+16, "nsertps128", 10))
+ IntrinsicID = Intrinsic::x86_sse41_insertps;
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'a':
+ if (!memcmp(BuiltinName+17, "ck", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pack"
+ case 's':
+ if (!memcmp(BuiltinName+20, "s", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_packss"
+ case 'd':
+ if (!memcmp(BuiltinName+22, "w128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_packssdw_128;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "b128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_packsswb_128;
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+20, "s", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_packus"
+ case 'd':
+ if (!memcmp(BuiltinName+22, "w128", 4))
+ IntrinsicID = Intrinsic::x86_sse41_packusdw;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+22, "b128", 4))
+ IntrinsicID = Intrinsic::x86_sse2_packuswb_128;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'b':
+ if (!memcmp(BuiltinName+17, "lendvb128", 9))
+ IntrinsicID = Intrinsic::x86_sse41_pblendvb;
+ break;
+ case 'm':
+ switch (BuiltinName[17]) { // "__builtin_ia32_pm"
+ case 'o':
+ if (!memcmp(BuiltinName+18, "v", 1)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pmov"
+ case 'm':
+ if (!memcmp(BuiltinName+20, "skb128", 6))
+ IntrinsicID = Intrinsic::x86_sse2_pmovmskb_128;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+20, "x", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_pmovsx"
+ case 'b':
+ switch (BuiltinName[22]) { // "__builtin_ia32_pmovsxb"
+ case 'd':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovsxbd;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovsxbq;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovsxbw;
+ break;
+ }
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+22, "q128", 4))
+ IntrinsicID = Intrinsic::x86_sse41_pmovsxdq;
+ break;
+ case 'w':
+ switch (BuiltinName[22]) { // "__builtin_ia32_pmovsxw"
+ case 'd':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovsxwd;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovsxwq;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 'z':
+ if (!memcmp(BuiltinName+20, "x", 1)) {
+ switch (BuiltinName[21]) { // "__builtin_ia32_pmovzx"
+ case 'b':
+ switch (BuiltinName[22]) { // "__builtin_ia32_pmovzxb"
+ case 'd':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovzxbd;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovzxbq;
+ break;
+ case 'w':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovzxbw;
+ break;
+ }
+ break;
+ case 'd':
+ if (!memcmp(BuiltinName+22, "q128", 4))
+ IntrinsicID = Intrinsic::x86_sse41_pmovzxdq;
+ break;
+ case 'w':
+ switch (BuiltinName[22]) { // "__builtin_ia32_pmovzxw"
+ case 'd':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovzxwd;
+ break;
+ case 'q':
+ if (!memcmp(BuiltinName+23, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse41_pmovzxwq;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'u':
+ if (!memcmp(BuiltinName+18, "lhrsw128", 8))
+ IntrinsicID = Intrinsic::x86_ssse3_pmul_hr_sw_128;
+ break;
+ }
+ break;
+ case 't':
+ if (!memcmp(BuiltinName+17, "estnzc128", 9))
+ IntrinsicID = Intrinsic::x86_sse41_ptestnzc;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 27:
+ if (!memcmp(BuiltinName, "__builtin_ia32_", 15)) {
+ switch (BuiltinName[15]) { // "__builtin_ia32_"
+ case 'e':
+ if (!memcmp(BuiltinName+16, "xtractps128", 11))
+ IntrinsicID = Intrinsic::x86_sse41_extractps;
+ break;
+ case 'p':
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'c':
+ if (!memcmp(BuiltinName+17, "mp", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pcmp"
+ case 'e':
+ if (!memcmp(BuiltinName+20, "str", 3)) {
+ switch (BuiltinName[23]) { // "__builtin_ia32_pcmpestr"
+ case 'i':
+ if (!memcmp(BuiltinName+24, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestri128;
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+24, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestrm128;
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+20, "str", 3)) {
+ switch (BuiltinName[23]) { // "__builtin_ia32_pcmpistr"
+ case 'i':
+ if (!memcmp(BuiltinName+24, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistri128;
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+24, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistrm128;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'm':
+ if (!memcmp(BuiltinName+17, "addubsw128", 10))
+ IntrinsicID = Intrinsic::x86_ssse3_pmadd_ub_sw_128;
+ break;
+ }
+ break;
+ }
+ }
+ break;
+ case 28:
+ if (!memcmp(BuiltinName, "__builtin_ia32_p", 16)) {
+ switch (BuiltinName[16]) { // "__builtin_ia32_p"
+ case 'c':
+ if (!memcmp(BuiltinName+17, "mp", 2)) {
+ switch (BuiltinName[19]) { // "__builtin_ia32_pcmp"
+ case 'e':
+ if (!memcmp(BuiltinName+20, "stri", 4)) {
+ switch (BuiltinName[24]) { // "__builtin_ia32_pcmpestri"
+ case 'a':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestria128;
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestric128;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestrio128;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestris128;
+ break;
+ case 'z':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpestriz128;
+ break;
+ }
+ }
+ break;
+ case 'i':
+ if (!memcmp(BuiltinName+20, "stri", 4)) {
+ switch (BuiltinName[24]) { // "__builtin_ia32_pcmpistri"
+ case 'a':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistria128;
+ break;
+ case 'c':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistric128;
+ break;
+ case 'o':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistrio128;
+ break;
+ case 's':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistris128;
+ break;
+ case 'z':
+ if (!memcmp(BuiltinName+25, "128", 3))
+ IntrinsicID = Intrinsic::x86_sse42_pcmpistriz128;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ break;
+ case 'h':
+ if (!memcmp(BuiltinName+17, "minposuw128", 11))
+ IntrinsicID = Intrinsic::x86_sse41_phminposuw;
+ break;
+ }
+ }
+ break;
+ case 35:
+ if (!memcmp(BuiltinName, "__builtin_ia32_ps", 17)) {
+ switch (BuiltinName[17]) { // "__builtin_ia32_ps"
+ case 'l':
+ if (!memcmp(BuiltinName+18, "ldqi128_byteshift", 17))
+ IntrinsicID = Intrinsic::x86_sse2_psll_dq_bs;
+ break;
+ case 'r':
+ if (!memcmp(BuiltinName+18, "ldqi128_byteshift", 17))
+ IntrinsicID = Intrinsic::x86_sse2_psrl_dq_bs;
+ break;
+ }
+ }
+ break;
+ }
+ }
+ return IntrinsicID;
+}
+#endif
+
--
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